arch/x86/events/intel/core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Per core/cpu state
   4  *
   5  * Used to coordinate shared registers between HT threads or
   6  * among events on a single PMU.
   7  */
   8
   9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10
  11 #include <linux/stddef.h>
  12 #include <linux/types.h>
  13 #include <linux/init.h>
  14 #include <linux/slab.h>
  15 #include <linux/export.h>
  16 #include <linux/nmi.h>
  17
  18 #include <asm/cpufeature.h>
  19 #include <asm/hardirq.h>
  20 #include <asm/intel-family.h>
  21 #include <asm/intel_pt.h>
  22 #include <asm/apic.h>
  23 #include <asm/cpu_device_id.h>
  24
  25 #include "../perf_event.h"
  26
  27 /*
  28  * Intel PerfMon, used on Core and later.
  29  */
  30 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
  31 {
  32         [PERF_COUNT_HW_CPU_CYCLES]              = 0x003c,
  33         [PERF_COUNT_HW_INSTRUCTIONS]            = 0x00c0,
  34         [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x4f2e,
  35         [PERF_COUNT_HW_CACHE_MISSES]            = 0x412e,
  36         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x00c4,
  37         [PERF_COUNT_HW_BRANCH_MISSES]           = 0x00c5,
  38         [PERF_COUNT_HW_BUS_CYCLES]              = 0x013c,
  39         [PERF_COUNT_HW_REF_CPU_CYCLES]          = 0x0300, /* pseudo-encoding */
  40 };
  41
  42 static struct event_constraint intel_core_event_constraints[] __read_mostly =
  43 {
  44         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  45         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  46         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  47         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  48         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  49         INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
  50         EVENT_CONSTRAINT_END
  51 };
  52
  53 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
  54 {
  55         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  56         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  57         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  58         INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
  59         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  60         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  61         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  62         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  63         INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
  64         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  65         INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
  66         INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
  67         INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
  68         EVENT_CONSTRAINT_END
  69 };
  70
  71 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
  72 {
  73         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  74         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  75         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  76         INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
  77         INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
  78         INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
  79         INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
  80         INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
  81         INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
  82         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  83         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  84         EVENT_CONSTRAINT_END
  85 };
  86
  87 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
  88 {
  89         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
  90         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
  91         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
  92         EVENT_EXTRA_END
  93 };
  94
  95 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
  96 {
  97         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  98         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  99         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 100         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
 101         INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
 102         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
 103         INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
 104         EVENT_CONSTRAINT_END
 105 };
 106
 107 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 108 {
 109         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 110         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 111         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 112         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 113         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 114         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 115         INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 116         INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
 117         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 118         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 119         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 120         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 121
 122         /*
 123          * When HT is off these events can only run on the bottom 4 counters
 124          * When HT is on, they are impacted by the HT bug and require EXCL access
 125          */
 126         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 127         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 128         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 129         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 130
 131         EVENT_CONSTRAINT_END
 132 };
 133
 134 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
 135 {
 136         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 137         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 138         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 139         INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
 140         INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */
 141         INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
 142         INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
 143         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 144         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 145         INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
 146         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 147         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 148         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 149
 150         /*
 151          * When HT is off these events can only run on the bottom 4 counters
 152          * When HT is on, they are impacted by the HT bug and require EXCL access
 153          */
 154         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 155         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 156         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 157         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 158
 159         EVENT_CONSTRAINT_END
 160 };
 161
 162 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
 163 {
 164         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 165         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
 166         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
 167         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
 168         EVENT_EXTRA_END
 169 };
 170
 171 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
 172 {
 173         EVENT_CONSTRAINT_END
 174 };
 175
 176 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
 177 {
 178         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 179         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 180         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 181         EVENT_CONSTRAINT_END
 182 };
 183
 184 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
 185 {
 186         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 187         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 188         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
 189         EVENT_CONSTRAINT_END
 190 };
 191
 192 static struct event_constraint intel_skl_event_constraints[] = {
 193         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 194         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 195         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 196         INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2),    /* INST_RETIRED.PREC_DIST */
 197
 198         /*
 199          * when HT is off, these can only run on the bottom 4 counters
 200          */
 201         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),      /* MEM_INST_RETIRED.* */
 202         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),      /* MEM_LOAD_RETIRED.* */
 203         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),      /* MEM_LOAD_L3_HIT_RETIRED.* */
 204         INTEL_EVENT_CONSTRAINT(0xcd, 0xf),      /* MEM_TRANS_RETIRED.* */
 205         INTEL_EVENT_CONSTRAINT(0xc6, 0xf),      /* FRONTEND_RETIRED.* */
 206
 207         EVENT_CONSTRAINT_END
 208 };
 209
 210 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
 211         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
 212         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
 213         EVENT_EXTRA_END
 214 };
 215
 216 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
 217         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 218         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
 219         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
 220         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 221         EVENT_EXTRA_END
 222 };
 223
 224 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
 225         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 226         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 227         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 228         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 229         EVENT_EXTRA_END
 230 };
 231
 232 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
 233         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 234         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 235         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 236         /*
 237          * Note the low 8 bits eventsel code is not a continuous field, containing
 238          * some #GPing bits. These are masked out.
 239          */
 240         INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
 241         EVENT_EXTRA_END
 242 };
 243
 244 static struct event_constraint intel_icl_event_constraints[] = {
 245         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 246         FIXED_EVENT_CONSTRAINT(0x01c0, 0),      /* INST_RETIRED.PREC_DIST */
 247         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 248         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 249         FIXED_EVENT_CONSTRAINT(0x0400, 3),      /* SLOTS */
 250         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
 251         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
 252         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
 253         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
 254         INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
 255         INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
 256         INTEL_EVENT_CONSTRAINT(0x32, 0xf),      /* SW_PREFETCH_ACCESS.* */
 257         INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf),
 258         INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
 259         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff),  /* CYCLE_ACTIVITY.STALLS_TOTAL */
 260         INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff),  /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */
 261         INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff),  /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
 262         INTEL_EVENT_CONSTRAINT(0xa3, 0xf),      /* CYCLE_ACTIVITY.* */
 263         INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
 264         INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
 265         INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
 266         INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
 267         EVENT_CONSTRAINT_END
 268 };
 269
 270 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
 271         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
 272         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
 273         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 274         INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
 275         EVENT_EXTRA_END
 276 };
 277
 278 static struct extra_reg intel_spr_extra_regs[] __read_mostly = {
 279         INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
 280         INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
 281         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 282         INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
 283         EVENT_EXTRA_END
 284 };
 285
 286 static struct event_constraint intel_spr_event_constraints[] = {
 287         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 288         FIXED_EVENT_CONSTRAINT(0x01c0, 0),      /* INST_RETIRED.PREC_DIST */
 289         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 290         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 291         FIXED_EVENT_CONSTRAINT(0x0400, 3),      /* SLOTS */
 292         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
 293         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
 294         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
 295         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
 296         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
 297         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
 298         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
 299         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
 300
 301         INTEL_EVENT_CONSTRAINT(0x2e, 0xff),
 302         INTEL_EVENT_CONSTRAINT(0x3c, 0xff),
 303         /*
 304          * Generally event codes < 0x90 are restricted to counters 0-3.
 305          * The 0x2E and 0x3C are exception, which has no restriction.
 306          */
 307         INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf),
 308
 309         INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
 310         INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
 311         INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
 312         INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
 313         INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
 314         INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
 315         INTEL_EVENT_CONSTRAINT(0xce, 0x1),
 316         INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
 317         /*
 318          * Generally event codes >= 0x90 are likely to have no restrictions.
 319          * The exception are defined as above.
 320          */
 321         INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff),
 322
 323         EVENT_CONSTRAINT_END
 324 };
 325
 326
 327 EVENT_ATTR_STR(mem-loads,       mem_ld_nhm,     "event=0x0b,umask=0x10,ldlat=3");
 328 EVENT_ATTR_STR(mem-loads,       mem_ld_snb,     "event=0xcd,umask=0x1,ldlat=3");
 329 EVENT_ATTR_STR(mem-stores,      mem_st_snb,     "event=0xcd,umask=0x2");
 330
 331 static struct attribute *nhm_mem_events_attrs[] = {
 332         EVENT_PTR(mem_ld_nhm),
 333         NULL,
 334 };
 335
 336 /*
 337  * topdown events for Intel Core CPUs.
 338  *
 339  * The events are all in slots, which is a free slot in a 4 wide
 340  * pipeline. Some events are already reported in slots, for cycle
 341  * events we multiply by the pipeline width (4).
 342  *
 343  * With Hyper Threading on, topdown metrics are either summed or averaged
 344  * between the threads of a core: (count_t0 + count_t1).
 345  *
 346  * For the average case the metric is always scaled to pipeline width,
 347  * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
 348  */
 349
 350 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
 351         "event=0x3c,umask=0x0",                 /* cpu_clk_unhalted.thread */
 352         "event=0x3c,umask=0x0,any=1");          /* cpu_clk_unhalted.thread_any */
 353 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
 354 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
 355         "event=0xe,umask=0x1");                 /* uops_issued.any */
 356 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
 357         "event=0xc2,umask=0x2");                /* uops_retired.retire_slots */
 358 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
 359         "event=0x9c,umask=0x1");                /* idq_uops_not_delivered_core */
 360 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
 361         "event=0xd,umask=0x3,cmask=1",          /* int_misc.recovery_cycles */
 362         "event=0xd,umask=0x3,cmask=1,any=1");   /* int_misc.recovery_cycles_any */
 363 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
 364         "4", "2");
 365
 366 EVENT_ATTR_STR(slots,                   slots,                  "event=0x00,umask=0x4");
 367 EVENT_ATTR_STR(topdown-retiring,        td_retiring,            "event=0x00,umask=0x80");
 368 EVENT_ATTR_STR(topdown-bad-spec,        td_bad_spec,            "event=0x00,umask=0x81");
 369 EVENT_ATTR_STR(topdown-fe-bound,        td_fe_bound,            "event=0x00,umask=0x82");
 370 EVENT_ATTR_STR(topdown-be-bound,        td_be_bound,            "event=0x00,umask=0x83");
 371 EVENT_ATTR_STR(topdown-heavy-ops,       td_heavy_ops,           "event=0x00,umask=0x84");
 372 EVENT_ATTR_STR(topdown-br-mispredict,   td_br_mispredict,       "event=0x00,umask=0x85");
 373 EVENT_ATTR_STR(topdown-fetch-lat,       td_fetch_lat,           "event=0x00,umask=0x86");
 374 EVENT_ATTR_STR(topdown-mem-bound,       td_mem_bound,           "event=0x00,umask=0x87");
 375
 376 static struct attribute *snb_events_attrs[] = {
 377         EVENT_PTR(td_slots_issued),
 378         EVENT_PTR(td_slots_retired),
 379         EVENT_PTR(td_fetch_bubbles),
 380         EVENT_PTR(td_total_slots),
 381         EVENT_PTR(td_total_slots_scale),
 382         EVENT_PTR(td_recovery_bubbles),
 383         EVENT_PTR(td_recovery_bubbles_scale),
 384         NULL,
 385 };
 386
 387 static struct attribute *snb_mem_events_attrs[] = {
 388         EVENT_PTR(mem_ld_snb),
 389         EVENT_PTR(mem_st_snb),
 390         NULL,
 391 };
 392
 393 static struct event_constraint intel_hsw_event_constraints[] = {
 394         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 395         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 396         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 397         INTEL_UEVENT_CONSTRAINT(0x148, 0x4),    /* L1D_PEND_MISS.PENDING */
 398         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 399         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 400         /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 401         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
 402         /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 403         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
 404         /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 405         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
 406
 407         /*
 408          * When HT is off these events can only run on the bottom 4 counters
 409          * When HT is on, they are impacted by the HT bug and require EXCL access
 410          */
 411         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 412         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 413         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 414         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 415
 416         EVENT_CONSTRAINT_END
 417 };
 418
 419 static struct event_constraint intel_bdw_event_constraints[] = {
 420         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 421         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 422         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 423         INTEL_UEVENT_CONSTRAINT(0x148, 0x4),    /* L1D_PEND_MISS.PENDING */
 424         INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4),        /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
 425         /*
 426          * when HT is off, these can only run on the bottom 4 counters
 427          */
 428         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),      /* MEM_INST_RETIRED.* */
 429         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),      /* MEM_LOAD_RETIRED.* */
 430         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),      /* MEM_LOAD_L3_HIT_RETIRED.* */
 431         INTEL_EVENT_CONSTRAINT(0xcd, 0xf),      /* MEM_TRANS_RETIRED.* */
 432         EVENT_CONSTRAINT_END
 433 };
 434
 435 static u64 intel_pmu_event_map(int hw_event)
 436 {
 437         return intel_perfmon_event_map[hw_event];
 438 }
 439
 440 static __initconst const u64 spr_hw_cache_event_ids
 441                                 [PERF_COUNT_HW_CACHE_MAX]
 442                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 443                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 444 {
 445  [ C(L1D ) ] = {
 446         [ C(OP_READ) ] = {
 447                 [ C(RESULT_ACCESS) ] = 0x81d0,
 448                 [ C(RESULT_MISS)   ] = 0xe124,
 449         },
 450         [ C(OP_WRITE) ] = {
 451                 [ C(RESULT_ACCESS) ] = 0x82d0,
 452         },
 453  },
 454  [ C(L1I ) ] = {
 455         [ C(OP_READ) ] = {
 456                 [ C(RESULT_MISS)   ] = 0xe424,
 457         },
 458         [ C(OP_WRITE) ] = {
 459                 [ C(RESULT_ACCESS) ] = -1,
 460                 [ C(RESULT_MISS)   ] = -1,
 461         },
 462  },
 463  [ C(LL  ) ] = {
 464         [ C(OP_READ) ] = {
 465                 [ C(RESULT_ACCESS) ] = 0x12a,
 466                 [ C(RESULT_MISS)   ] = 0x12a,
 467         },
 468         [ C(OP_WRITE) ] = {
 469                 [ C(RESULT_ACCESS) ] = 0x12a,
 470                 [ C(RESULT_MISS)   ] = 0x12a,
 471         },
 472  },
 473  [ C(DTLB) ] = {
 474         [ C(OP_READ) ] = {
 475                 [ C(RESULT_ACCESS) ] = 0x81d0,
 476                 [ C(RESULT_MISS)   ] = 0xe12,
 477         },
 478         [ C(OP_WRITE) ] = {
 479                 [ C(RESULT_ACCESS) ] = 0x82d0,
 480                 [ C(RESULT_MISS)   ] = 0xe13,
 481         },
 482  },
 483  [ C(ITLB) ] = {
 484         [ C(OP_READ) ] = {
 485                 [ C(RESULT_ACCESS) ] = -1,
 486                 [ C(RESULT_MISS)   ] = 0xe11,
 487         },
 488         [ C(OP_WRITE) ] = {
 489                 [ C(RESULT_ACCESS) ] = -1,
 490                 [ C(RESULT_MISS)   ] = -1,
 491         },
 492         [ C(OP_PREFETCH) ] = {
 493                 [ C(RESULT_ACCESS) ] = -1,
 494                 [ C(RESULT_MISS)   ] = -1,
 495         },
 496  },
 497  [ C(BPU ) ] = {
 498         [ C(OP_READ) ] = {
 499                 [ C(RESULT_ACCESS) ] = 0x4c4,
 500                 [ C(RESULT_MISS)   ] = 0x4c5,
 501         },
 502         [ C(OP_WRITE) ] = {
 503                 [ C(RESULT_ACCESS) ] = -1,
 504                 [ C(RESULT_MISS)   ] = -1,
 505         },
 506         [ C(OP_PREFETCH) ] = {
 507                 [ C(RESULT_ACCESS) ] = -1,
 508                 [ C(RESULT_MISS)   ] = -1,
 509         },
 510  },
 511  [ C(NODE) ] = {
 512         [ C(OP_READ) ] = {
 513                 [ C(RESULT_ACCESS) ] = 0x12a,
 514                 [ C(RESULT_MISS)   ] = 0x12a,
 515         },
 516  },
 517 };
 518
 519 static __initconst const u64 spr_hw_cache_extra_regs
 520                                 [PERF_COUNT_HW_CACHE_MAX]
 521                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 522                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 523 {
 524  [ C(LL  ) ] = {
 525         [ C(OP_READ) ] = {
 526                 [ C(RESULT_ACCESS) ] = 0x10001,
 527                 [ C(RESULT_MISS)   ] = 0x3fbfc00001,
 528         },
 529         [ C(OP_WRITE) ] = {
 530                 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
 531                 [ C(RESULT_MISS)   ] = 0x3f3fc00002,
 532         },
 533  },
 534  [ C(NODE) ] = {
 535         [ C(OP_READ) ] = {
 536                 [ C(RESULT_ACCESS) ] = 0x10c000001,
 537                 [ C(RESULT_MISS)   ] = 0x3fb3000001,
 538         },
 539  },
 540 };
 541
 542 /*
 543  * Notes on the events:
 544  * - data reads do not include code reads (comparable to earlier tables)
 545  * - data counts include speculative execution (except L1 write, dtlb, bpu)
 546  * - remote node access includes remote memory, remote cache, remote mmio.
 547  * - prefetches are not included in the counts.
 548  * - icache miss does not include decoded icache
 549  */
 550
 551 #define SKL_DEMAND_DATA_RD              BIT_ULL(0)
 552 #define SKL_DEMAND_RFO                  BIT_ULL(1)
 553 #define SKL_ANY_RESPONSE                BIT_ULL(16)
 554 #define SKL_SUPPLIER_NONE               BIT_ULL(17)
 555 #define SKL_L3_MISS_LOCAL_DRAM          BIT_ULL(26)
 556 #define SKL_L3_MISS_REMOTE_HOP0_DRAM    BIT_ULL(27)
 557 #define SKL_L3_MISS_REMOTE_HOP1_DRAM    BIT_ULL(28)
 558 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM   BIT_ULL(29)
 559 #define SKL_L3_MISS                     (SKL_L3_MISS_LOCAL_DRAM| \
 560                                          SKL_L3_MISS_REMOTE_HOP0_DRAM| \
 561                                          SKL_L3_MISS_REMOTE_HOP1_DRAM| \
 562                                          SKL_L3_MISS_REMOTE_HOP2P_DRAM)
 563 #define SKL_SPL_HIT                     BIT_ULL(30)
 564 #define SKL_SNOOP_NONE                  BIT_ULL(31)
 565 #define SKL_SNOOP_NOT_NEEDED            BIT_ULL(32)
 566 #define SKL_SNOOP_MISS                  BIT_ULL(33)
 567 #define SKL_SNOOP_HIT_NO_FWD            BIT_ULL(34)
 568 #define SKL_SNOOP_HIT_WITH_FWD          BIT_ULL(35)
 569 #define SKL_SNOOP_HITM                  BIT_ULL(36)
 570 #define SKL_SNOOP_NON_DRAM              BIT_ULL(37)
 571 #define SKL_ANY_SNOOP                   (SKL_SPL_HIT|SKL_SNOOP_NONE| \
 572                                          SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
 573                                          SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
 574                                          SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
 575 #define SKL_DEMAND_READ                 SKL_DEMAND_DATA_RD
 576 #define SKL_SNOOP_DRAM                  (SKL_SNOOP_NONE| \
 577                                          SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
 578                                          SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
 579                                          SKL_SNOOP_HITM|SKL_SPL_HIT)
 580 #define SKL_DEMAND_WRITE                SKL_DEMAND_RFO
 581 #define SKL_LLC_ACCESS                  SKL_ANY_RESPONSE
 582 #define SKL_L3_MISS_REMOTE              (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
 583                                          SKL_L3_MISS_REMOTE_HOP1_DRAM| \
 584                                          SKL_L3_MISS_REMOTE_HOP2P_DRAM)
 585
 586 static __initconst const u64 skl_hw_cache_event_ids
 587                                 [PERF_COUNT_HW_CACHE_MAX]
 588                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 589                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 590 {
 591  [ C(L1D ) ] = {
 592         [ C(OP_READ) ] = {
 593                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_INST_RETIRED.ALL_LOADS */
 594                 [ C(RESULT_MISS)   ] = 0x151,   /* L1D.REPLACEMENT */
 595         },
 596         [ C(OP_WRITE) ] = {
 597                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_INST_RETIRED.ALL_STORES */
 598                 [ C(RESULT_MISS)   ] = 0x0,
 599         },
 600         [ C(OP_PREFETCH) ] = {
 601                 [ C(RESULT_ACCESS) ] = 0x0,
 602                 [ C(RESULT_MISS)   ] = 0x0,
 603         },
 604  },
 605  [ C(L1I ) ] = {
 606         [ C(OP_READ) ] = {
 607                 [ C(RESULT_ACCESS) ] = 0x0,
 608                 [ C(RESULT_MISS)   ] = 0x283,   /* ICACHE_64B.MISS */
 609         },
 610         [ C(OP_WRITE) ] = {
 611                 [ C(RESULT_ACCESS) ] = -1,
 612                 [ C(RESULT_MISS)   ] = -1,
 613         },
 614         [ C(OP_PREFETCH) ] = {
 615                 [ C(RESULT_ACCESS) ] = 0x0,
 616                 [ C(RESULT_MISS)   ] = 0x0,
 617         },
 618  },
 619  [ C(LL  ) ] = {
 620         [ C(OP_READ) ] = {
 621                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 622                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 623         },
 624         [ C(OP_WRITE) ] = {
 625                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 626                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 627         },
 628         [ C(OP_PREFETCH) ] = {
 629                 [ C(RESULT_ACCESS) ] = 0x0,
 630                 [ C(RESULT_MISS)   ] = 0x0,
 631         },
 632  },
 633  [ C(DTLB) ] = {
 634         [ C(OP_READ) ] = {
 635                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_INST_RETIRED.ALL_LOADS */
 636                 [ C(RESULT_MISS)   ] = 0xe08,   /* DTLB_LOAD_MISSES.WALK_COMPLETED */
 637         },
 638         [ C(OP_WRITE) ] = {
 639                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_INST_RETIRED.ALL_STORES */
 640                 [ C(RESULT_MISS)   ] = 0xe49,   /* DTLB_STORE_MISSES.WALK_COMPLETED */
 641         },
 642         [ C(OP_PREFETCH) ] = {
 643                 [ C(RESULT_ACCESS) ] = 0x0,
 644                 [ C(RESULT_MISS)   ] = 0x0,
 645         },
 646  },
 647  [ C(ITLB) ] = {
 648         [ C(OP_READ) ] = {
 649                 [ C(RESULT_ACCESS) ] = 0x2085,  /* ITLB_MISSES.STLB_HIT */
 650                 [ C(RESULT_MISS)   ] = 0xe85,   /* ITLB_MISSES.WALK_COMPLETED */
 651         },
 652         [ C(OP_WRITE) ] = {
 653                 [ C(RESULT_ACCESS) ] = -1,
 654                 [ C(RESULT_MISS)   ] = -1,
 655         },
 656         [ C(OP_PREFETCH) ] = {
 657                 [ C(RESULT_ACCESS) ] = -1,
 658                 [ C(RESULT_MISS)   ] = -1,
 659         },
 660  },
 661  [ C(BPU ) ] = {
 662         [ C(OP_READ) ] = {
 663                 [ C(RESULT_ACCESS) ] = 0xc4,    /* BR_INST_RETIRED.ALL_BRANCHES */
 664                 [ C(RESULT_MISS)   ] = 0xc5,    /* BR_MISP_RETIRED.ALL_BRANCHES */
 665         },
 666         [ C(OP_WRITE) ] = {
 667                 [ C(RESULT_ACCESS) ] = -1,
 668                 [ C(RESULT_MISS)   ] = -1,
 669         },
 670         [ C(OP_PREFETCH) ] = {
 671                 [ C(RESULT_ACCESS) ] = -1,
 672                 [ C(RESULT_MISS)   ] = -1,
 673         },
 674  },
 675  [ C(NODE) ] = {
 676         [ C(OP_READ) ] = {
 677                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 678                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 679         },
 680         [ C(OP_WRITE) ] = {
 681                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 682                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 683         },
 684         [ C(OP_PREFETCH) ] = {
 685                 [ C(RESULT_ACCESS) ] = 0x0,
 686                 [ C(RESULT_MISS)   ] = 0x0,
 687         },
 688  },
 689 };
 690
 691 static __initconst const u64 skl_hw_cache_extra_regs
 692                                 [PERF_COUNT_HW_CACHE_MAX]
 693                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 694                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 695 {
 696  [ C(LL  ) ] = {
 697         [ C(OP_READ) ] = {
 698                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
 699                                        SKL_LLC_ACCESS|SKL_ANY_SNOOP,
 700                 [ C(RESULT_MISS)   ] = SKL_DEMAND_READ|
 701                                        SKL_L3_MISS|SKL_ANY_SNOOP|
 702                                        SKL_SUPPLIER_NONE,
 703         },
 704         [ C(OP_WRITE) ] = {
 705                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
 706                                        SKL_LLC_ACCESS|SKL_ANY_SNOOP,
 707                 [ C(RESULT_MISS)   ] = SKL_DEMAND_WRITE|
 708                                        SKL_L3_MISS|SKL_ANY_SNOOP|
 709                                        SKL_SUPPLIER_NONE,
 710         },
 711         [ C(OP_PREFETCH) ] = {
 712                 [ C(RESULT_ACCESS) ] = 0x0,
 713                 [ C(RESULT_MISS)   ] = 0x0,
 714         },
 715  },
 716  [ C(NODE) ] = {
 717         [ C(OP_READ) ] = {
 718                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
 719                                        SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
 720                 [ C(RESULT_MISS)   ] = SKL_DEMAND_READ|
 721                                        SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
 722         },
 723         [ C(OP_WRITE) ] = {
 724                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
 725                                        SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
 726                 [ C(RESULT_MISS)   ] = SKL_DEMAND_WRITE|
 727                                        SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
 728         },
 729         [ C(OP_PREFETCH) ] = {
 730                 [ C(RESULT_ACCESS) ] = 0x0,
 731                 [ C(RESULT_MISS)   ] = 0x0,
 732         },
 733  },
 734 };
 735
 736 #define SNB_DMND_DATA_RD        (1ULL << 0)
 737 #define SNB_DMND_RFO            (1ULL << 1)
 738 #define SNB_DMND_IFETCH         (1ULL << 2)
 739 #define SNB_DMND_WB             (1ULL << 3)
 740 #define SNB_PF_DATA_RD          (1ULL << 4)
 741 #define SNB_PF_RFO              (1ULL << 5)
 742 #define SNB_PF_IFETCH           (1ULL << 6)
 743 #define SNB_LLC_DATA_RD         (1ULL << 7)
 744 #define SNB_LLC_RFO             (1ULL << 8)
 745 #define SNB_LLC_IFETCH          (1ULL << 9)
 746 #define SNB_BUS_LOCKS           (1ULL << 10)
 747 #define SNB_STRM_ST             (1ULL << 11)
 748 #define SNB_OTHER               (1ULL << 15)
 749 #define SNB_RESP_ANY            (1ULL << 16)
 750 #define SNB_NO_SUPP             (1ULL << 17)
 751 #define SNB_LLC_HITM            (1ULL << 18)
 752 #define SNB_LLC_HITE            (1ULL << 19)
 753 #define SNB_LLC_HITS            (1ULL << 20)
 754 #define SNB_LLC_HITF            (1ULL << 21)
 755 #define SNB_LOCAL               (1ULL << 22)
 756 #define SNB_REMOTE              (0xffULL << 23)
 757 #define SNB_SNP_NONE            (1ULL << 31)
 758 #define SNB_SNP_NOT_NEEDED      (1ULL << 32)
 759 #define SNB_SNP_MISS            (1ULL << 33)
 760 #define SNB_NO_FWD              (1ULL << 34)
 761 #define SNB_SNP_FWD             (1ULL << 35)
 762 #define SNB_HITM                (1ULL << 36)
 763 #define SNB_NON_DRAM            (1ULL << 37)
 764
 765 #define SNB_DMND_READ           (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
 766 #define SNB_DMND_WRITE          (SNB_DMND_RFO|SNB_LLC_RFO)
 767 #define SNB_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
 768
 769 #define SNB_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
 770                                  SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
 771                                  SNB_HITM)
 772
 773 #define SNB_DRAM_ANY            (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
 774 #define SNB_DRAM_REMOTE         (SNB_REMOTE|SNB_SNP_ANY)
 775
 776 #define SNB_L3_ACCESS           SNB_RESP_ANY
 777 #define SNB_L3_MISS             (SNB_DRAM_ANY|SNB_NON_DRAM)
 778
 779 static __initconst const u64 snb_hw_cache_extra_regs
 780                                 [PERF_COUNT_HW_CACHE_MAX]
 781                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 782                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 783 {
 784  [ C(LL  ) ] = {
 785         [ C(OP_READ) ] = {
 786                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
 787                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_L3_MISS,
 788         },
 789         [ C(OP_WRITE) ] = {
 790                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
 791                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_L3_MISS,
 792         },
 793         [ C(OP_PREFETCH) ] = {
 794                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
 795                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
 796         },
 797  },
 798  [ C(NODE) ] = {
 799         [ C(OP_READ) ] = {
 800                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
 801                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
 802         },
 803         [ C(OP_WRITE) ] = {
 804                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
 805                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
 806         },
 807         [ C(OP_PREFETCH) ] = {
 808                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
 809                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
 810         },
 811  },
 812 };
 813
 814 static __initconst const u64 snb_hw_cache_event_ids
 815                                 [PERF_COUNT_HW_CACHE_MAX]
 816                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 817                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 818 {
 819  [ C(L1D) ] = {
 820         [ C(OP_READ) ] = {
 821                 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS        */
 822                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPLACEMENT              */
 823         },
 824         [ C(OP_WRITE) ] = {
 825                 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES       */
 826                 [ C(RESULT_MISS)   ] = 0x0851, /* L1D.ALL_M_REPLACEMENT        */
 827         },
 828         [ C(OP_PREFETCH) ] = {
 829                 [ C(RESULT_ACCESS) ] = 0x0,
 830                 [ C(RESULT_MISS)   ] = 0x024e, /* HW_PRE_REQ.DL1_MISS          */
 831         },
 832  },
 833  [ C(L1I ) ] = {
 834         [ C(OP_READ) ] = {
 835                 [ C(RESULT_ACCESS) ] = 0x0,
 836                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACHE.MISSES */
 837         },
 838         [ C(OP_WRITE) ] = {
 839                 [ C(RESULT_ACCESS) ] = -1,
 840                 [ C(RESULT_MISS)   ] = -1,
 841         },
 842         [ C(OP_PREFETCH) ] = {
 843                 [ C(RESULT_ACCESS) ] = 0x0,
 844                 [ C(RESULT_MISS)   ] = 0x0,
 845         },
 846  },
 847  [ C(LL  ) ] = {
 848         [ C(OP_READ) ] = {
 849                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 850                 [ C(RESULT_ACCESS) ] = 0x01b7,
 851                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 852                 [ C(RESULT_MISS)   ] = 0x01b7,
 853         },
 854         [ C(OP_WRITE) ] = {
 855                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 856                 [ C(RESULT_ACCESS) ] = 0x01b7,
 857                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 858                 [ C(RESULT_MISS)   ] = 0x01b7,
 859         },
 860         [ C(OP_PREFETCH) ] = {
 861                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 862                 [ C(RESULT_ACCESS) ] = 0x01b7,
 863                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 864                 [ C(RESULT_MISS)   ] = 0x01b7,
 865         },
 866  },
 867  [ C(DTLB) ] = {
 868         [ C(OP_READ) ] = {
 869                 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
 870                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
 871         },
 872         [ C(OP_WRITE) ] = {
 873                 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
 874                 [ C(RESULT_MISS)   ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
 875         },
 876         [ C(OP_PREFETCH) ] = {
 877                 [ C(RESULT_ACCESS) ] = 0x0,
 878                 [ C(RESULT_MISS)   ] = 0x0,
 879         },
 880  },
 881  [ C(ITLB) ] = {
 882         [ C(OP_READ) ] = {
 883                 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT         */
 884                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK    */
 885         },
 886         [ C(OP_WRITE) ] = {
 887                 [ C(RESULT_ACCESS) ] = -1,
 888                 [ C(RESULT_MISS)   ] = -1,
 889         },
 890         [ C(OP_PREFETCH) ] = {
 891                 [ C(RESULT_ACCESS) ] = -1,
 892                 [ C(RESULT_MISS)   ] = -1,
 893         },
 894  },
 895  [ C(BPU ) ] = {
 896         [ C(OP_READ) ] = {
 897                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 898                 [ C(RESULT_MISS)   ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
 899         },
 900         [ C(OP_WRITE) ] = {
 901                 [ C(RESULT_ACCESS) ] = -1,
 902                 [ C(RESULT_MISS)   ] = -1,
 903         },
 904         [ C(OP_PREFETCH) ] = {
 905                 [ C(RESULT_ACCESS) ] = -1,
 906                 [ C(RESULT_MISS)   ] = -1,
 907         },
 908  },
 909  [ C(NODE) ] = {
 910         [ C(OP_READ) ] = {
 911                 [ C(RESULT_ACCESS) ] = 0x01b7,
 912                 [ C(RESULT_MISS)   ] = 0x01b7,
 913         },
 914         [ C(OP_WRITE) ] = {
 915                 [ C(RESULT_ACCESS) ] = 0x01b7,
 916                 [ C(RESULT_MISS)   ] = 0x01b7,
 917         },
 918         [ C(OP_PREFETCH) ] = {
 919                 [ C(RESULT_ACCESS) ] = 0x01b7,
 920                 [ C(RESULT_MISS)   ] = 0x01b7,
 921         },
 922  },
 923
 924 };
 925
 926 /*
 927  * Notes on the events:
 928  * - data reads do not include code reads (comparable to earlier tables)
 929  * - data counts include speculative execution (except L1 write, dtlb, bpu)
 930  * - remote node access includes remote memory, remote cache, remote mmio.
 931  * - prefetches are not included in the counts because they are not
 932  *   reliably counted.
 933  */
 934
 935 #define HSW_DEMAND_DATA_RD              BIT_ULL(0)
 936 #define HSW_DEMAND_RFO                  BIT_ULL(1)
 937 #define HSW_ANY_RESPONSE                BIT_ULL(16)
 938 #define HSW_SUPPLIER_NONE               BIT_ULL(17)
 939 #define HSW_L3_MISS_LOCAL_DRAM          BIT_ULL(22)
 940 #define HSW_L3_MISS_REMOTE_HOP0         BIT_ULL(27)
 941 #define HSW_L3_MISS_REMOTE_HOP1         BIT_ULL(28)
 942 #define HSW_L3_MISS_REMOTE_HOP2P        BIT_ULL(29)
 943 #define HSW_L3_MISS                     (HSW_L3_MISS_LOCAL_DRAM| \
 944                                          HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
 945                                          HSW_L3_MISS_REMOTE_HOP2P)
 946 #define HSW_SNOOP_NONE                  BIT_ULL(31)
 947 #define HSW_SNOOP_NOT_NEEDED            BIT_ULL(32)
 948 #define HSW_SNOOP_MISS                  BIT_ULL(33)
 949 #define HSW_SNOOP_HIT_NO_FWD            BIT_ULL(34)
 950 #define HSW_SNOOP_HIT_WITH_FWD          BIT_ULL(35)
 951 #define HSW_SNOOP_HITM                  BIT_ULL(36)
 952 #define HSW_SNOOP_NON_DRAM              BIT_ULL(37)
 953 #define HSW_ANY_SNOOP                   (HSW_SNOOP_NONE| \
 954                                          HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
 955                                          HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
 956                                          HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
 957 #define HSW_SNOOP_DRAM                  (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
 958 #define HSW_DEMAND_READ                 HSW_DEMAND_DATA_RD
 959 #define HSW_DEMAND_WRITE                HSW_DEMAND_RFO
 960 #define HSW_L3_MISS_REMOTE              (HSW_L3_MISS_REMOTE_HOP0|\
 961                                          HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
 962 #define HSW_LLC_ACCESS                  HSW_ANY_RESPONSE
 963
 964 #define BDW_L3_MISS_LOCAL               BIT(26)
 965 #define BDW_L3_MISS                     (BDW_L3_MISS_LOCAL| \
 966                                          HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
 967                                          HSW_L3_MISS_REMOTE_HOP2P)
 968
 969
 970 static __initconst const u64 hsw_hw_cache_event_ids
 971                                 [PERF_COUNT_HW_CACHE_MAX]
 972                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 973                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 974 {
 975  [ C(L1D ) ] = {
 976         [ C(OP_READ) ] = {
 977                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
 978                 [ C(RESULT_MISS)   ] = 0x151,   /* L1D.REPLACEMENT */
 979         },
 980         [ C(OP_WRITE) ] = {
 981                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
 982                 [ C(RESULT_MISS)   ] = 0x0,
 983         },
 984         [ C(OP_PREFETCH) ] = {
 985                 [ C(RESULT_ACCESS) ] = 0x0,
 986                 [ C(RESULT_MISS)   ] = 0x0,
 987         },
 988  },
 989  [ C(L1I ) ] = {
 990         [ C(OP_READ) ] = {
 991                 [ C(RESULT_ACCESS) ] = 0x0,
 992                 [ C(RESULT_MISS)   ] = 0x280,   /* ICACHE.MISSES */
 993         },
 994         [ C(OP_WRITE) ] = {
 995                 [ C(RESULT_ACCESS) ] = -1,
 996                 [ C(RESULT_MISS)   ] = -1,
 997         },
 998         [ C(OP_PREFETCH) ] = {
 999                 [ C(RESULT_ACCESS) ] = 0x0,
1000                 [ C(RESULT_MISS)   ] = 0x0,
1001         },
1002  },
1003  [ C(LL  ) ] = {
1004         [ C(OP_READ) ] = {
1005                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
1006                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
1007         },
1008         [ C(OP_WRITE) ] = {
1009                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
1010                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
1011         },
1012         [ C(OP_PREFETCH) ] = {
1013                 [ C(RESULT_ACCESS) ] = 0x0,
1014                 [ C(RESULT_MISS)   ] = 0x0,
1015         },
1016  },
1017  [ C(DTLB) ] = {
1018         [ C(OP_READ) ] = {
1019                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
1020                 [ C(RESULT_MISS)   ] = 0x108,   /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1021         },
1022         [ C(OP_WRITE) ] = {
1023                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
1024                 [ C(RESULT_MISS)   ] = 0x149,   /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1025         },
1026         [ C(OP_PREFETCH) ] = {
1027                 [ C(RESULT_ACCESS) ] = 0x0,
1028                 [ C(RESULT_MISS)   ] = 0x0,
1029         },
1030  },
1031  [ C(ITLB) ] = {
1032         [ C(OP_READ) ] = {
1033                 [ C(RESULT_ACCESS) ] = 0x6085,  /* ITLB_MISSES.STLB_HIT */
1034                 [ C(RESULT_MISS)   ] = 0x185,   /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1035         },
1036         [ C(OP_WRITE) ] = {
1037                 [ C(RESULT_ACCESS) ] = -1,
1038                 [ C(RESULT_MISS)   ] = -1,
1039         },
1040         [ C(OP_PREFETCH) ] = {
1041                 [ C(RESULT_ACCESS) ] = -1,
1042                 [ C(RESULT_MISS)   ] = -1,
1043         },
1044  },
1045  [ C(BPU ) ] = {
1046         [ C(OP_READ) ] = {
1047                 [ C(RESULT_ACCESS) ] = 0xc4,    /* BR_INST_RETIRED.ALL_BRANCHES */
1048                 [ C(RESULT_MISS)   ] = 0xc5,    /* BR_MISP_RETIRED.ALL_BRANCHES */
1049         },
1050         [ C(OP_WRITE) ] = {
1051                 [ C(RESULT_ACCESS) ] = -1,
1052                 [ C(RESULT_MISS)   ] = -1,
1053         },
1054         [ C(OP_PREFETCH) ] = {
1055                 [ C(RESULT_ACCESS) ] = -1,
1056                 [ C(RESULT_MISS)   ] = -1,
1057         },
1058  },
1059  [ C(NODE) ] = {
1060         [ C(OP_READ) ] = {
1061                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
1062                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
1063         },
1064         [ C(OP_WRITE) ] = {
1065                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
1066                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
1067         },
1068         [ C(OP_PREFETCH) ] = {
1069                 [ C(RESULT_ACCESS) ] = 0x0,
1070                 [ C(RESULT_MISS)   ] = 0x0,
1071         },
1072  },
1073 };
1074
1075 static __initconst const u64 hsw_hw_cache_extra_regs
1076                                 [PERF_COUNT_HW_CACHE_MAX]
1077                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1078                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1079 {
1080  [ C(LL  ) ] = {
1081         [ C(OP_READ) ] = {
1082                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1083                                        HSW_LLC_ACCESS,
1084                 [ C(RESULT_MISS)   ] = HSW_DEMAND_READ|
1085                                        HSW_L3_MISS|HSW_ANY_SNOOP,
1086         },
1087         [ C(OP_WRITE) ] = {
1088                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1089                                        HSW_LLC_ACCESS,
1090                 [ C(RESULT_MISS)   ] = HSW_DEMAND_WRITE|
1091                                        HSW_L3_MISS|HSW_ANY_SNOOP,
1092         },
1093         [ C(OP_PREFETCH) ] = {
1094                 [ C(RESULT_ACCESS) ] = 0x0,
1095                 [ C(RESULT_MISS)   ] = 0x0,
1096         },
1097  },
1098  [ C(NODE) ] = {
1099         [ C(OP_READ) ] = {
1100                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1101                                        HSW_L3_MISS_LOCAL_DRAM|
1102                                        HSW_SNOOP_DRAM,
1103                 [ C(RESULT_MISS)   ] = HSW_DEMAND_READ|
1104                                        HSW_L3_MISS_REMOTE|
1105                                        HSW_SNOOP_DRAM,
1106         },
1107         [ C(OP_WRITE) ] = {
1108                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1109                                        HSW_L3_MISS_LOCAL_DRAM|
1110                                        HSW_SNOOP_DRAM,
1111                 [ C(RESULT_MISS)   ] = HSW_DEMAND_WRITE|
1112                                        HSW_L3_MISS_REMOTE|
1113                                        HSW_SNOOP_DRAM,
1114         },
1115         [ C(OP_PREFETCH) ] = {
1116                 [ C(RESULT_ACCESS) ] = 0x0,
1117                 [ C(RESULT_MISS)   ] = 0x0,
1118         },
1119  },
1120 };
1121
1122 static __initconst const u64 westmere_hw_cache_event_ids
1123                                 [PERF_COUNT_HW_CACHE_MAX]
1124                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1125                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1126 {
1127  [ C(L1D) ] = {
1128         [ C(OP_READ) ] = {
1129                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
1130                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
1131         },
1132         [ C(OP_WRITE) ] = {
1133                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
1134                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
1135         },
1136         [ C(OP_PREFETCH) ] = {
1137                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
1138                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
1139         },
1140  },
1141  [ C(L1I ) ] = {
1142         [ C(OP_READ) ] = {
1143                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
1144                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
1145         },
1146         [ C(OP_WRITE) ] = {
1147                 [ C(RESULT_ACCESS) ] = -1,
1148                 [ C(RESULT_MISS)   ] = -1,
1149         },
1150         [ C(OP_PREFETCH) ] = {
1151                 [ C(RESULT_ACCESS) ] = 0x0,
1152                 [ C(RESULT_MISS)   ] = 0x0,
1153         },
1154  },
1155  [ C(LL  ) ] = {
1156         [ C(OP_READ) ] = {
1157                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1158                 [ C(RESULT_ACCESS) ] = 0x01b7,
1159                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1160                 [ C(RESULT_MISS)   ] = 0x01b7,
1161         },
1162         /*
1163          * Use RFO, not WRITEBACK, because a write miss would typically occur
1164          * on RFO.
1165          */
1166         [ C(OP_WRITE) ] = {
1167                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1168                 [ C(RESULT_ACCESS) ] = 0x01b7,
1169                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1170                 [ C(RESULT_MISS)   ] = 0x01b7,
1171         },
1172         [ C(OP_PREFETCH) ] = {
1173                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1174                 [ C(RESULT_ACCESS) ] = 0x01b7,
1175                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1176                 [ C(RESULT_MISS)   ] = 0x01b7,
1177         },
1178  },
1179  [ C(DTLB) ] = {
1180         [ C(OP_READ) ] = {
1181                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
1182                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
1183         },
1184         [ C(OP_WRITE) ] = {
1185                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
1186                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
1187         },
1188         [ C(OP_PREFETCH) ] = {
1189                 [ C(RESULT_ACCESS) ] = 0x0,
1190                 [ C(RESULT_MISS)   ] = 0x0,
1191         },
1192  },
1193  [ C(ITLB) ] = {
1194         [ C(OP_READ) ] = {
1195                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
1196                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.ANY              */
1197         },
1198         [ C(OP_WRITE) ] = {
1199                 [ C(RESULT_ACCESS) ] = -1,
1200                 [ C(RESULT_MISS)   ] = -1,
1201         },
1202         [ C(OP_PREFETCH) ] = {
1203                 [ C(RESULT_ACCESS) ] = -1,
1204                 [ C(RESULT_MISS)   ] = -1,
1205         },
1206  },
1207  [ C(BPU ) ] = {
1208         [ C(OP_READ) ] = {
1209                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1210                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
1211         },
1212         [ C(OP_WRITE) ] = {
1213                 [ C(RESULT_ACCESS) ] = -1,
1214                 [ C(RESULT_MISS)   ] = -1,
1215         },
1216         [ C(OP_PREFETCH) ] = {
1217                 [ C(RESULT_ACCESS) ] = -1,
1218                 [ C(RESULT_MISS)   ] = -1,
1219         },
1220  },
1221  [ C(NODE) ] = {
1222         [ C(OP_READ) ] = {
1223                 [ C(RESULT_ACCESS) ] = 0x01b7,
1224                 [ C(RESULT_MISS)   ] = 0x01b7,
1225         },
1226         [ C(OP_WRITE) ] = {
1227                 [ C(RESULT_ACCESS) ] = 0x01b7,
1228                 [ C(RESULT_MISS)   ] = 0x01b7,
1229         },
1230         [ C(OP_PREFETCH) ] = {
1231                 [ C(RESULT_ACCESS) ] = 0x01b7,
1232                 [ C(RESULT_MISS)   ] = 0x01b7,
1233         },
1234  },
1235 };
1236
1237 /*
1238  * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1239  * See IA32 SDM Vol 3B 30.6.1.3
1240  */
1241
1242 #define NHM_DMND_DATA_RD        (1 << 0)
1243 #define NHM_DMND_RFO            (1 << 1)
1244 #define NHM_DMND_IFETCH         (1 << 2)
1245 #define NHM_DMND_WB             (1 << 3)
1246 #define NHM_PF_DATA_RD          (1 << 4)
1247 #define NHM_PF_DATA_RFO         (1 << 5)
1248 #define NHM_PF_IFETCH           (1 << 6)
1249 #define NHM_OFFCORE_OTHER       (1 << 7)
1250 #define NHM_UNCORE_HIT          (1 << 8)
1251 #define NHM_OTHER_CORE_HIT_SNP  (1 << 9)
1252 #define NHM_OTHER_CORE_HITM     (1 << 10)
1253                                 /* reserved */
1254 #define NHM_REMOTE_CACHE_FWD    (1 << 12)
1255 #define NHM_REMOTE_DRAM         (1 << 13)
1256 #define NHM_LOCAL_DRAM          (1 << 14)
1257 #define NHM_NON_DRAM            (1 << 15)
1258
1259 #define NHM_LOCAL               (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1260 #define NHM_REMOTE              (NHM_REMOTE_DRAM)
1261
1262 #define NHM_DMND_READ           (NHM_DMND_DATA_RD)
1263 #define NHM_DMND_WRITE          (NHM_DMND_RFO|NHM_DMND_WB)
1264 #define NHM_DMND_PREFETCH       (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1265
1266 #define NHM_L3_HIT      (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1267 #define NHM_L3_MISS     (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1268 #define NHM_L3_ACCESS   (NHM_L3_HIT|NHM_L3_MISS)
1269
1270 static __initconst const u64 nehalem_hw_cache_extra_regs
1271                                 [PERF_COUNT_HW_CACHE_MAX]
1272                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1273                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1274 {
1275  [ C(LL  ) ] = {
1276         [ C(OP_READ) ] = {
1277                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1278                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_L3_MISS,
1279         },
1280         [ C(OP_WRITE) ] = {
1281                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1282                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_L3_MISS,
1283         },
1284         [ C(OP_PREFETCH) ] = {
1285                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1286                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1287         },
1288  },
1289  [ C(NODE) ] = {
1290         [ C(OP_READ) ] = {
1291                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1292                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_REMOTE,
1293         },
1294         [ C(OP_WRITE) ] = {
1295                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1296                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_REMOTE,
1297         },
1298         [ C(OP_PREFETCH) ] = {
1299                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1300                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1301         },
1302  },
1303 };
1304
1305 static __initconst const u64 nehalem_hw_cache_event_ids
1306                                 [PERF_COUNT_HW_CACHE_MAX]
1307                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1308                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1309 {
1310  [ C(L1D) ] = {
1311         [ C(OP_READ) ] = {
1312                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
1313                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
1314         },
1315         [ C(OP_WRITE) ] = {
1316                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
1317                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
1318         },
1319         [ C(OP_PREFETCH) ] = {
1320                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
1321                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
1322         },
1323  },
1324  [ C(L1I ) ] = {
1325         [ C(OP_READ) ] = {
1326                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
1327                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
1328         },
1329         [ C(OP_WRITE) ] = {
1330                 [ C(RESULT_ACCESS) ] = -1,
1331                 [ C(RESULT_MISS)   ] = -1,
1332         },
1333         [ C(OP_PREFETCH) ] = {
1334                 [ C(RESULT_ACCESS) ] = 0x0,
1335                 [ C(RESULT_MISS)   ] = 0x0,
1336         },
1337  },
1338  [ C(LL  ) ] = {
1339         [ C(OP_READ) ] = {
1340                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1341                 [ C(RESULT_ACCESS) ] = 0x01b7,
1342                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1343                 [ C(RESULT_MISS)   ] = 0x01b7,
1344         },
1345         /*
1346          * Use RFO, not WRITEBACK, because a write miss would typically occur
1347          * on RFO.
1348          */
1349         [ C(OP_WRITE) ] = {
1350                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1351                 [ C(RESULT_ACCESS) ] = 0x01b7,
1352                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1353                 [ C(RESULT_MISS)   ] = 0x01b7,
1354         },
1355         [ C(OP_PREFETCH) ] = {
1356                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1357                 [ C(RESULT_ACCESS) ] = 0x01b7,
1358                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1359                 [ C(RESULT_MISS)   ] = 0x01b7,
1360         },
1361  },
1362  [ C(DTLB) ] = {
1363         [ C(OP_READ) ] = {
1364                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
1365                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
1366         },
1367         [ C(OP_WRITE) ] = {
1368                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
1369                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
1370         },
1371         [ C(OP_PREFETCH) ] = {
1372                 [ C(RESULT_ACCESS) ] = 0x0,
1373                 [ C(RESULT_MISS)   ] = 0x0,
1374         },
1375  },
1376  [ C(ITLB) ] = {
1377         [ C(OP_READ) ] = {
1378                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
1379                 [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
1380         },
1381         [ C(OP_WRITE) ] = {
1382                 [ C(RESULT_ACCESS) ] = -1,
1383                 [ C(RESULT_MISS)   ] = -1,
1384         },
1385         [ C(OP_PREFETCH) ] = {
1386                 [ C(RESULT_ACCESS) ] = -1,
1387                 [ C(RESULT_MISS)   ] = -1,
1388         },
1389  },
1390  [ C(BPU ) ] = {
1391         [ C(OP_READ) ] = {
1392                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1393                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
1394         },
1395         [ C(OP_WRITE) ] = {
1396                 [ C(RESULT_ACCESS) ] = -1,
1397                 [ C(RESULT_MISS)   ] = -1,
1398         },
1399         [ C(OP_PREFETCH) ] = {
1400                 [ C(RESULT_ACCESS) ] = -1,
1401                 [ C(RESULT_MISS)   ] = -1,
1402         },
1403  },
1404  [ C(NODE) ] = {
1405         [ C(OP_READ) ] = {
1406                 [ C(RESULT_ACCESS) ] = 0x01b7,
1407                 [ C(RESULT_MISS)   ] = 0x01b7,
1408         },
1409         [ C(OP_WRITE) ] = {
1410                 [ C(RESULT_ACCESS) ] = 0x01b7,
1411                 [ C(RESULT_MISS)   ] = 0x01b7,
1412         },
1413         [ C(OP_PREFETCH) ] = {
1414                 [ C(RESULT_ACCESS) ] = 0x01b7,
1415                 [ C(RESULT_MISS)   ] = 0x01b7,
1416         },
1417  },
1418 };
1419
1420 static __initconst const u64 core2_hw_cache_event_ids
1421                                 [PERF_COUNT_HW_CACHE_MAX]
1422                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1423                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1424 {
1425  [ C(L1D) ] = {
1426         [ C(OP_READ) ] = {
1427                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
1428                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
1429         },
1430         [ C(OP_WRITE) ] = {
1431                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
1432                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
1433         },
1434         [ C(OP_PREFETCH) ] = {
1435                 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
1436                 [ C(RESULT_MISS)   ] = 0,
1437         },
1438  },
1439  [ C(L1I ) ] = {
1440         [ C(OP_READ) ] = {
1441                 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
1442                 [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
1443         },
1444         [ C(OP_WRITE) ] = {
1445                 [ C(RESULT_ACCESS) ] = -1,
1446                 [ C(RESULT_MISS)   ] = -1,
1447         },
1448         [ C(OP_PREFETCH) ] = {
1449                 [ C(RESULT_ACCESS) ] = 0,
1450                 [ C(RESULT_MISS)   ] = 0,
1451         },
1452  },
1453  [ C(LL  ) ] = {
1454         [ C(OP_READ) ] = {
1455                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
1456                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
1457         },
1458         [ C(OP_WRITE) ] = {
1459                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
1460                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
1461         },
1462         [ C(OP_PREFETCH) ] = {
1463                 [ C(RESULT_ACCESS) ] = 0,
1464                 [ C(RESULT_MISS)   ] = 0,
1465         },
1466  },
1467  [ C(DTLB) ] = {
1468         [ C(OP_READ) ] = {
1469                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
1470                 [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
1471         },
1472         [ C(OP_WRITE) ] = {
1473                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
1474                 [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
1475         },
1476         [ C(OP_PREFETCH) ] = {
1477                 [ C(RESULT_ACCESS) ] = 0,
1478                 [ C(RESULT_MISS)   ] = 0,
1479         },
1480  },
1481  [ C(ITLB) ] = {
1482         [ C(OP_READ) ] = {
1483                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
1484                 [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
1485         },
1486         [ C(OP_WRITE) ] = {
1487                 [ C(RESULT_ACCESS) ] = -1,
1488                 [ C(RESULT_MISS)   ] = -1,
1489         },
1490         [ C(OP_PREFETCH) ] = {
1491                 [ C(RESULT_ACCESS) ] = -1,
1492                 [ C(RESULT_MISS)   ] = -1,
1493         },
1494  },
1495  [ C(BPU ) ] = {
1496         [ C(OP_READ) ] = {
1497                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
1498                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
1499         },
1500         [ C(OP_WRITE) ] = {
1501                 [ C(RESULT_ACCESS) ] = -1,
1502                 [ C(RESULT_MISS)   ] = -1,
1503         },
1504         [ C(OP_PREFETCH) ] = {
1505                 [ C(RESULT_ACCESS) ] = -1,
1506                 [ C(RESULT_MISS)   ] = -1,
1507         },
1508  },
1509 };
1510
1511 static __initconst const u64 atom_hw_cache_event_ids
1512                                 [PERF_COUNT_HW_CACHE_MAX]
1513                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1514                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1515 {
1516  [ C(L1D) ] = {
1517         [ C(OP_READ) ] = {
1518                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
1519                 [ C(RESULT_MISS)   ] = 0,
1520         },
1521         [ C(OP_WRITE) ] = {
1522                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
1523                 [ C(RESULT_MISS)   ] = 0,
1524         },
1525         [ C(OP_PREFETCH) ] = {
1526                 [ C(RESULT_ACCESS) ] = 0x0,
1527                 [ C(RESULT_MISS)   ] = 0,
1528         },
1529  },
1530  [ C(L1I ) ] = {
1531         [ C(OP_READ) ] = {
1532                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
1533                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
1534         },
1535         [ C(OP_WRITE) ] = {
1536                 [ C(RESULT_ACCESS) ] = -1,
1537                 [ C(RESULT_MISS)   ] = -1,
1538         },
1539         [ C(OP_PREFETCH) ] = {
1540                 [ C(RESULT_ACCESS) ] = 0,
1541                 [ C(RESULT_MISS)   ] = 0,
1542         },
1543  },
1544  [ C(LL  ) ] = {
1545         [ C(OP_READ) ] = {
1546                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
1547                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
1548         },
1549         [ C(OP_WRITE) ] = {
1550                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
1551                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
1552         },
1553         [ C(OP_PREFETCH) ] = {
1554                 [ C(RESULT_ACCESS) ] = 0,
1555                 [ C(RESULT_MISS)   ] = 0,
1556         },
1557  },
1558  [ C(DTLB) ] = {
1559         [ C(OP_READ) ] = {
1560                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
1561                 [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
1562         },
1563         [ C(OP_WRITE) ] = {
1564                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
1565                 [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
1566         },
1567         [ C(OP_PREFETCH) ] = {
1568                 [ C(RESULT_ACCESS) ] = 0,
1569                 [ C(RESULT_MISS)   ] = 0,
1570         },
1571  },
1572  [ C(ITLB) ] = {
1573         [ C(OP_READ) ] = {
1574                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
1575                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
1576         },
1577         [ C(OP_WRITE) ] = {
1578                 [ C(RESULT_ACCESS) ] = -1,
1579                 [ C(RESULT_MISS)   ] = -1,
1580         },
1581         [ C(OP_PREFETCH) ] = {
1582                 [ C(RESULT_ACCESS) ] = -1,
1583                 [ C(RESULT_MISS)   ] = -1,
1584         },
1585  },
1586  [ C(BPU ) ] = {
1587         [ C(OP_READ) ] = {
1588                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
1589                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
1590         },
1591         [ C(OP_WRITE) ] = {
1592                 [ C(RESULT_ACCESS) ] = -1,
1593                 [ C(RESULT_MISS)   ] = -1,
1594         },
1595         [ C(OP_PREFETCH) ] = {
1596                 [ C(RESULT_ACCESS) ] = -1,
1597                 [ C(RESULT_MISS)   ] = -1,
1598         },
1599  },
1600 };
1601
1602 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1603 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1604 /* no_alloc_cycles.not_delivered */
1605 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1606                "event=0xca,umask=0x50");
1607 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1608 /* uops_retired.all */
1609 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1610                "event=0xc2,umask=0x10");
1611 /* uops_retired.all */
1612 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1613                "event=0xc2,umask=0x10");
1614
1615 static struct attribute *slm_events_attrs[] = {
1616         EVENT_PTR(td_total_slots_slm),
1617         EVENT_PTR(td_total_slots_scale_slm),
1618         EVENT_PTR(td_fetch_bubbles_slm),
1619         EVENT_PTR(td_fetch_bubbles_scale_slm),
1620         EVENT_PTR(td_slots_issued_slm),
1621         EVENT_PTR(td_slots_retired_slm),
1622         NULL
1623 };
1624
1625 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1626 {
1627         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1628         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1629         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1630         EVENT_EXTRA_END
1631 };
1632
1633 #define SLM_DMND_READ           SNB_DMND_DATA_RD
1634 #define SLM_DMND_WRITE          SNB_DMND_RFO
1635 #define SLM_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
1636
1637 #define SLM_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1638 #define SLM_LLC_ACCESS          SNB_RESP_ANY
1639 #define SLM_LLC_MISS            (SLM_SNP_ANY|SNB_NON_DRAM)
1640
1641 static __initconst const u64 slm_hw_cache_extra_regs
1642                                 [PERF_COUNT_HW_CACHE_MAX]
1643                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1644                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1645 {
1646  [ C(LL  ) ] = {
1647         [ C(OP_READ) ] = {
1648                 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1649                 [ C(RESULT_MISS)   ] = 0,
1650         },
1651         [ C(OP_WRITE) ] = {
1652                 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1653                 [ C(RESULT_MISS)   ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1654         },
1655         [ C(OP_PREFETCH) ] = {
1656                 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1657                 [ C(RESULT_MISS)   ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1658         },
1659  },
1660 };
1661
1662 static __initconst const u64 slm_hw_cache_event_ids
1663                                 [PERF_COUNT_HW_CACHE_MAX]
1664                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1665                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1666 {
1667  [ C(L1D) ] = {
1668         [ C(OP_READ) ] = {
1669                 [ C(RESULT_ACCESS) ] = 0,
1670                 [ C(RESULT_MISS)   ] = 0x0104, /* LD_DCU_MISS */
1671         },
1672         [ C(OP_WRITE) ] = {
1673                 [ C(RESULT_ACCESS) ] = 0,
1674                 [ C(RESULT_MISS)   ] = 0,
1675         },
1676         [ C(OP_PREFETCH) ] = {
1677                 [ C(RESULT_ACCESS) ] = 0,
1678                 [ C(RESULT_MISS)   ] = 0,
1679         },
1680  },
1681  [ C(L1I ) ] = {
1682         [ C(OP_READ) ] = {
1683                 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1684                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACGE.MISSES */
1685         },
1686         [ C(OP_WRITE) ] = {
1687                 [ C(RESULT_ACCESS) ] = -1,
1688                 [ C(RESULT_MISS)   ] = -1,
1689         },
1690         [ C(OP_PREFETCH) ] = {
1691                 [ C(RESULT_ACCESS) ] = 0,
1692                 [ C(RESULT_MISS)   ] = 0,
1693         },
1694  },
1695  [ C(LL  ) ] = {
1696         [ C(OP_READ) ] = {
1697                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1698                 [ C(RESULT_ACCESS) ] = 0x01b7,
1699                 [ C(RESULT_MISS)   ] = 0,
1700         },
1701         [ C(OP_WRITE) ] = {
1702                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1703                 [ C(RESULT_ACCESS) ] = 0x01b7,
1704                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1705                 [ C(RESULT_MISS)   ] = 0x01b7,
1706         },
1707         [ C(OP_PREFETCH) ] = {
1708                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1709                 [ C(RESULT_ACCESS) ] = 0x01b7,
1710                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1711                 [ C(RESULT_MISS)   ] = 0x01b7,
1712         },
1713  },
1714  [ C(DTLB) ] = {
1715         [ C(OP_READ) ] = {
1716                 [ C(RESULT_ACCESS) ] = 0,
1717                 [ C(RESULT_MISS)   ] = 0x0804, /* LD_DTLB_MISS */
1718         },
1719         [ C(OP_WRITE) ] = {
1720                 [ C(RESULT_ACCESS) ] = 0,
1721                 [ C(RESULT_MISS)   ] = 0,
1722         },
1723         [ C(OP_PREFETCH) ] = {
1724                 [ C(RESULT_ACCESS) ] = 0,
1725                 [ C(RESULT_MISS)   ] = 0,
1726         },
1727  },
1728  [ C(ITLB) ] = {
1729         [ C(OP_READ) ] = {
1730                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1731                 [ C(RESULT_MISS)   ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1732         },
1733         [ C(OP_WRITE) ] = {
1734                 [ C(RESULT_ACCESS) ] = -1,
1735                 [ C(RESULT_MISS)   ] = -1,
1736         },
1737         [ C(OP_PREFETCH) ] = {
1738                 [ C(RESULT_ACCESS) ] = -1,
1739                 [ C(RESULT_MISS)   ] = -1,
1740         },
1741  },
1742  [ C(BPU ) ] = {
1743         [ C(OP_READ) ] = {
1744                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1745                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1746         },
1747         [ C(OP_WRITE) ] = {
1748                 [ C(RESULT_ACCESS) ] = -1,
1749                 [ C(RESULT_MISS)   ] = -1,
1750         },
1751         [ C(OP_PREFETCH) ] = {
1752                 [ C(RESULT_ACCESS) ] = -1,
1753                 [ C(RESULT_MISS)   ] = -1,
1754         },
1755  },
1756 };
1757
1758 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1759 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1760 /* UOPS_NOT_DELIVERED.ANY */
1761 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1762 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1763 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1764 /* UOPS_RETIRED.ANY */
1765 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1766 /* UOPS_ISSUED.ANY */
1767 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1768
1769 static struct attribute *glm_events_attrs[] = {
1770         EVENT_PTR(td_total_slots_glm),
1771         EVENT_PTR(td_total_slots_scale_glm),
1772         EVENT_PTR(td_fetch_bubbles_glm),
1773         EVENT_PTR(td_recovery_bubbles_glm),
1774         EVENT_PTR(td_slots_issued_glm),
1775         EVENT_PTR(td_slots_retired_glm),
1776         NULL
1777 };
1778
1779 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1780         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1781         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1782         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1783         EVENT_EXTRA_END
1784 };
1785
1786 #define GLM_DEMAND_DATA_RD              BIT_ULL(0)
1787 #define GLM_DEMAND_RFO                  BIT_ULL(1)
1788 #define GLM_ANY_RESPONSE                BIT_ULL(16)
1789 #define GLM_SNP_NONE_OR_MISS            BIT_ULL(33)
1790 #define GLM_DEMAND_READ                 GLM_DEMAND_DATA_RD
1791 #define GLM_DEMAND_WRITE                GLM_DEMAND_RFO
1792 #define GLM_DEMAND_PREFETCH             (SNB_PF_DATA_RD|SNB_PF_RFO)
1793 #define GLM_LLC_ACCESS                  GLM_ANY_RESPONSE
1794 #define GLM_SNP_ANY                     (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1795 #define GLM_LLC_MISS                    (GLM_SNP_ANY|SNB_NON_DRAM)
1796
1797 static __initconst const u64 glm_hw_cache_event_ids
1798                                 [PERF_COUNT_HW_CACHE_MAX]
1799                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1800                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1801         [C(L1D)] = {
1802                 [C(OP_READ)] = {
1803                         [C(RESULT_ACCESS)]      = 0x81d0,       /* MEM_UOPS_RETIRED.ALL_LOADS */
1804                         [C(RESULT_MISS)]        = 0x0,
1805                 },
1806                 [C(OP_WRITE)] = {
1807                         [C(RESULT_ACCESS)]      = 0x82d0,       /* MEM_UOPS_RETIRED.ALL_STORES */
1808                         [C(RESULT_MISS)]        = 0x0,
1809                 },
1810                 [C(OP_PREFETCH)] = {
1811                         [C(RESULT_ACCESS)]      = 0x0,
1812                         [C(RESULT_MISS)]        = 0x0,
1813                 },
1814         },
1815         [C(L1I)] = {
1816                 [C(OP_READ)] = {
1817                         [C(RESULT_ACCESS)]      = 0x0380,       /* ICACHE.ACCESSES */
1818                         [C(RESULT_MISS)]        = 0x0280,       /* ICACHE.MISSES */
1819                 },
1820                 [C(OP_WRITE)] = {
1821                         [C(RESULT_ACCESS)]      = -1,
1822                         [C(RESULT_MISS)]        = -1,
1823                 },
1824                 [C(OP_PREFETCH)] = {
1825                         [C(RESULT_ACCESS)]      = 0x0,
1826                         [C(RESULT_MISS)]        = 0x0,
1827                 },
1828         },
1829         [C(LL)] = {
1830                 [C(OP_READ)] = {
1831                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1832                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1833                 },
1834                 [C(OP_WRITE)] = {
1835                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1836                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1837                 },
1838                 [C(OP_PREFETCH)] = {
1839                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1840                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1841                 },
1842         },
1843         [C(DTLB)] = {
1844                 [C(OP_READ)] = {
1845                         [C(RESULT_ACCESS)]      = 0x81d0,       /* MEM_UOPS_RETIRED.ALL_LOADS */
1846                         [C(RESULT_MISS)]        = 0x0,
1847                 },
1848                 [C(OP_WRITE)] = {
1849                         [C(RESULT_ACCESS)]      = 0x82d0,       /* MEM_UOPS_RETIRED.ALL_STORES */
1850                         [C(RESULT_MISS)]        = 0x0,
1851                 },
1852                 [C(OP_PREFETCH)] = {
1853                         [C(RESULT_ACCESS)]      = 0x0,
1854                         [C(RESULT_MISS)]        = 0x0,
1855                 },
1856         },
1857         [C(ITLB)] = {
1858                 [C(OP_READ)] = {
1859                         [C(RESULT_ACCESS)]      = 0x00c0,       /* INST_RETIRED.ANY_P */
1860                         [C(RESULT_MISS)]        = 0x0481,       /* ITLB.MISS */
1861                 },
1862                 [C(OP_WRITE)] = {
1863                         [C(RESULT_ACCESS)]      = -1,
1864                         [C(RESULT_MISS)]        = -1,
1865                 },
1866                 [C(OP_PREFETCH)] = {
1867                         [C(RESULT_ACCESS)]      = -1,
1868                         [C(RESULT_MISS)]        = -1,
1869                 },
1870         },
1871         [C(BPU)] = {
1872                 [C(OP_READ)] = {
1873                         [C(RESULT_ACCESS)]      = 0x00c4,       /* BR_INST_RETIRED.ALL_BRANCHES */
1874                         [C(RESULT_MISS)]        = 0x00c5,       /* BR_MISP_RETIRED.ALL_BRANCHES */
1875                 },
1876                 [C(OP_WRITE)] = {
1877                         [C(RESULT_ACCESS)]      = -1,
1878                         [C(RESULT_MISS)]        = -1,
1879                 },
1880                 [C(OP_PREFETCH)] = {
1881                         [C(RESULT_ACCESS)]      = -1,
1882                         [C(RESULT_MISS)]        = -1,
1883                 },
1884         },
1885 };
1886
1887 static __initconst const u64 glm_hw_cache_extra_regs
1888                                 [PERF_COUNT_HW_CACHE_MAX]
1889                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1890                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1891         [C(LL)] = {
1892                 [C(OP_READ)] = {
1893                         [C(RESULT_ACCESS)]      = GLM_DEMAND_READ|
1894                                                   GLM_LLC_ACCESS,
1895                         [C(RESULT_MISS)]        = GLM_DEMAND_READ|
1896                                                   GLM_LLC_MISS,
1897                 },
1898                 [C(OP_WRITE)] = {
1899                         [C(RESULT_ACCESS)]      = GLM_DEMAND_WRITE|
1900                                                   GLM_LLC_ACCESS,
1901                         [C(RESULT_MISS)]        = GLM_DEMAND_WRITE|
1902                                                   GLM_LLC_MISS,
1903                 },
1904                 [C(OP_PREFETCH)] = {
1905                         [C(RESULT_ACCESS)]      = GLM_DEMAND_PREFETCH|
1906                                                   GLM_LLC_ACCESS,
1907                         [C(RESULT_MISS)]        = GLM_DEMAND_PREFETCH|
1908                                                   GLM_LLC_MISS,
1909                 },
1910         },
1911 };
1912
1913 static __initconst const u64 glp_hw_cache_event_ids
1914                                 [PERF_COUNT_HW_CACHE_MAX]
1915                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1916                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1917         [C(L1D)] = {
1918                 [C(OP_READ)] = {
1919                         [C(RESULT_ACCESS)]      = 0x81d0,       /* MEM_UOPS_RETIRED.ALL_LOADS */
1920                         [C(RESULT_MISS)]        = 0x0,
1921                 },
1922                 [C(OP_WRITE)] = {
1923                         [C(RESULT_ACCESS)]      = 0x82d0,       /* MEM_UOPS_RETIRED.ALL_STORES */
1924                         [C(RESULT_MISS)]        = 0x0,
1925                 },
1926                 [C(OP_PREFETCH)] = {
1927                         [C(RESULT_ACCESS)]      = 0x0,
1928                         [C(RESULT_MISS)]        = 0x0,
1929                 },
1930         },
1931         [C(L1I)] = {
1932                 [C(OP_READ)] = {
1933                         [C(RESULT_ACCESS)]      = 0x0380,       /* ICACHE.ACCESSES */
1934                         [C(RESULT_MISS)]        = 0x0280,       /* ICACHE.MISSES */
1935                 },
1936                 [C(OP_WRITE)] = {
1937                         [C(RESULT_ACCESS)]      = -1,
1938                         [C(RESULT_MISS)]        = -1,
1939                 },
1940                 [C(OP_PREFETCH)] = {
1941                         [C(RESULT_ACCESS)]      = 0x0,
1942                         [C(RESULT_MISS)]        = 0x0,
1943                 },
1944         },
1945         [C(LL)] = {
1946                 [C(OP_READ)] = {
1947                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1948                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1949                 },
1950                 [C(OP_WRITE)] = {
1951                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1952                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1953                 },
1954                 [C(OP_PREFETCH)] = {
1955                         [C(RESULT_ACCESS)]      = 0x0,
1956                         [C(RESULT_MISS)]        = 0x0,
1957                 },
1958         },
1959         [C(DTLB)] = {
1960                 [C(OP_READ)] = {
1961                         [C(RESULT_ACCESS)]      = 0x81d0,       /* MEM_UOPS_RETIRED.ALL_LOADS */
1962                         [C(RESULT_MISS)]        = 0xe08,        /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1963                 },
1964                 [C(OP_WRITE)] = {
1965                         [C(RESULT_ACCESS)]      = 0x82d0,       /* MEM_UOPS_RETIRED.ALL_STORES */
1966                         [C(RESULT_MISS)]        = 0xe49,        /* DTLB_STORE_MISSES.WALK_COMPLETED */
1967                 },
1968                 [C(OP_PREFETCH)] = {
1969                         [C(RESULT_ACCESS)]      = 0x0,
1970                         [C(RESULT_MISS)]        = 0x0,
1971                 },
1972         },
1973         [C(ITLB)] = {
1974                 [C(OP_READ)] = {
1975                         [C(RESULT_ACCESS)]      = 0x00c0,       /* INST_RETIRED.ANY_P */
1976                         [C(RESULT_MISS)]        = 0x0481,       /* ITLB.MISS */
1977                 },
1978                 [C(OP_WRITE)] = {
1979                         [C(RESULT_ACCESS)]      = -1,
1980                         [C(RESULT_MISS)]        = -1,
1981                 },
1982                 [C(OP_PREFETCH)] = {
1983                         [C(RESULT_ACCESS)]      = -1,
1984                         [C(RESULT_MISS)]        = -1,
1985                 },
1986         },
1987         [C(BPU)] = {
1988                 [C(OP_READ)] = {
1989                         [C(RESULT_ACCESS)]      = 0x00c4,       /* BR_INST_RETIRED.ALL_BRANCHES */
1990                         [C(RESULT_MISS)]        = 0x00c5,       /* BR_MISP_RETIRED.ALL_BRANCHES */
1991                 },
1992                 [C(OP_WRITE)] = {
1993                         [C(RESULT_ACCESS)]      = -1,
1994                         [C(RESULT_MISS)]        = -1,
1995                 },
1996                 [C(OP_PREFETCH)] = {
1997                         [C(RESULT_ACCESS)]      = -1,
1998                         [C(RESULT_MISS)]        = -1,
1999                 },
2000         },
2001 };
2002
2003 static __initconst const u64 glp_hw_cache_extra_regs
2004                                 [PERF_COUNT_HW_CACHE_MAX]
2005                                 [PERF_COUNT_HW_CACHE_OP_MAX]
2006                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2007         [C(LL)] = {
2008                 [C(OP_READ)] = {
2009                         [C(RESULT_ACCESS)]      = GLM_DEMAND_READ|
2010                                                   GLM_LLC_ACCESS,
2011                         [C(RESULT_MISS)]        = GLM_DEMAND_READ|
2012                                                   GLM_LLC_MISS,
2013                 },
2014                 [C(OP_WRITE)] = {
2015                         [C(RESULT_ACCESS)]      = GLM_DEMAND_WRITE|
2016                                                   GLM_LLC_ACCESS,
2017                         [C(RESULT_MISS)]        = GLM_DEMAND_WRITE|
2018                                                   GLM_LLC_MISS,
2019                 },
2020                 [C(OP_PREFETCH)] = {
2021                         [C(RESULT_ACCESS)]      = 0x0,
2022                         [C(RESULT_MISS)]        = 0x0,
2023                 },
2024         },
2025 };
2026
2027 #define TNT_LOCAL_DRAM                  BIT_ULL(26)
2028 #define TNT_DEMAND_READ                 GLM_DEMAND_DATA_RD
2029 #define TNT_DEMAND_WRITE                GLM_DEMAND_RFO
2030 #define TNT_LLC_ACCESS                  GLM_ANY_RESPONSE
2031 #define TNT_SNP_ANY                     (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
2032                                          SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
2033 #define TNT_LLC_MISS                    (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
2034
2035 static __initconst const u64 tnt_hw_cache_extra_regs
2036                                 [PERF_COUNT_HW_CACHE_MAX]
2037                                 [PERF_COUNT_HW_CACHE_OP_MAX]
2038                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2039         [C(LL)] = {
2040                 [C(OP_READ)] = {
2041                         [C(RESULT_ACCESS)]      = TNT_DEMAND_READ|
2042                                                   TNT_LLC_ACCESS,
2043                         [C(RESULT_MISS)]        = TNT_DEMAND_READ|
2044                                                   TNT_LLC_MISS,
2045                 },
2046                 [C(OP_WRITE)] = {
2047                         [C(RESULT_ACCESS)]      = TNT_DEMAND_WRITE|
2048                                                   TNT_LLC_ACCESS,
2049                         [C(RESULT_MISS)]        = TNT_DEMAND_WRITE|
2050                                                   TNT_LLC_MISS,
2051                 },
2052                 [C(OP_PREFETCH)] = {
2053                         [C(RESULT_ACCESS)]      = 0x0,
2054                         [C(RESULT_MISS)]        = 0x0,
2055                 },
2056         },
2057 };
2058
2059 EVENT_ATTR_STR(topdown-fe-bound,       td_fe_bound_tnt,        "event=0x71,umask=0x0");
2060 EVENT_ATTR_STR(topdown-retiring,       td_retiring_tnt,        "event=0xc2,umask=0x0");
2061 EVENT_ATTR_STR(topdown-bad-spec,       td_bad_spec_tnt,        "event=0x73,umask=0x6");
2062 EVENT_ATTR_STR(topdown-be-bound,       td_be_bound_tnt,        "event=0x74,umask=0x0");
2063
2064 static struct attribute *tnt_events_attrs[] = {
2065         EVENT_PTR(td_fe_bound_tnt),
2066         EVENT_PTR(td_retiring_tnt),
2067         EVENT_PTR(td_bad_spec_tnt),
2068         EVENT_PTR(td_be_bound_tnt),
2069         NULL,
2070 };
2071
2072 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
2073         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2074         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
2075         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
2076         EVENT_EXTRA_END
2077 };
2078
2079 #define KNL_OT_L2_HITE          BIT_ULL(19) /* Other Tile L2 Hit */
2080 #define KNL_OT_L2_HITF          BIT_ULL(20) /* Other Tile L2 Hit */
2081 #define KNL_MCDRAM_LOCAL        BIT_ULL(21)
2082 #define KNL_MCDRAM_FAR          BIT_ULL(22)
2083 #define KNL_DDR_LOCAL           BIT_ULL(23)
2084 #define KNL_DDR_FAR             BIT_ULL(24)
2085 #define KNL_DRAM_ANY            (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
2086                                     KNL_DDR_LOCAL | KNL_DDR_FAR)
2087 #define KNL_L2_READ             SLM_DMND_READ
2088 #define KNL_L2_WRITE            SLM_DMND_WRITE
2089 #define KNL_L2_PREFETCH         SLM_DMND_PREFETCH
2090 #define KNL_L2_ACCESS           SLM_LLC_ACCESS
2091 #define KNL_L2_MISS             (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
2092                                    KNL_DRAM_ANY | SNB_SNP_ANY | \
2093                                                   SNB_NON_DRAM)
2094
2095 static __initconst const u64 knl_hw_cache_extra_regs
2096                                 [PERF_COUNT_HW_CACHE_MAX]
2097                                 [PERF_COUNT_HW_CACHE_OP_MAX]
2098                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2099         [C(LL)] = {
2100                 [C(OP_READ)] = {
2101                         [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2102                         [C(RESULT_MISS)]   = 0,
2103                 },
2104                 [C(OP_WRITE)] = {
2105                         [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2106                         [C(RESULT_MISS)]   = KNL_L2_WRITE | KNL_L2_MISS,
2107                 },
2108                 [C(OP_PREFETCH)] = {
2109                         [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2110                         [C(RESULT_MISS)]   = KNL_L2_PREFETCH | KNL_L2_MISS,
2111                 },
2112         },
2113 };
2114
2115 /*
2116  * Used from PMIs where the LBRs are already disabled.
2117  *
2118  * This function could be called consecutively. It is required to remain in
2119  * disabled state if called consecutively.
2120  *
2121  * During consecutive calls, the same disable value will be written to related
2122  * registers, so the PMU state remains unchanged.
2123  *
2124  * intel_bts events don't coexist with intel PMU's BTS events because of
2125  * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
2126  * disabled around intel PMU's event batching etc, only inside the PMI handler.
2127  *
2128  * Avoid PEBS_ENABLE MSR access in PMIs.
2129  * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
2130  * It doesn't matter if the PEBS is enabled or not.
2131  * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
2132  * access PEBS_ENABLE MSR in disable_all()/enable_all().
2133  * However, there are some cases which may change PEBS status, e.g. PMI
2134  * throttle. The PEBS_ENABLE should be updated where the status changes.
2135  */
2136 static void __intel_pmu_disable_all(void)
2137 {
2138         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2139
2140         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2141
2142         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
2143                 intel_pmu_disable_bts();
2144 }
2145
2146 static void intel_pmu_disable_all(void)
2147 {
2148         __intel_pmu_disable_all();
2149         intel_pmu_pebs_disable_all();
2150         intel_pmu_lbr_disable_all();
2151 }
2152
2153 static void __intel_pmu_enable_all(int added, bool pmi)
2154 {
2155         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2156
2157         intel_pmu_lbr_enable_all(pmi);
2158         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
2159                         x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
2160
2161         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2162                 struct perf_event *event =
2163                         cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
2164
2165                 if (WARN_ON_ONCE(!event))
2166                         return;
2167
2168                 intel_pmu_enable_bts(event->hw.config);
2169         }
2170 }
2171
2172 static void intel_pmu_enable_all(int added)
2173 {
2174         intel_pmu_pebs_enable_all();
2175         __intel_pmu_enable_all(added, false);
2176 }
2177
2178 /*
2179  * Workaround for:
2180  *   Intel Errata AAK100 (model 26)
2181  *   Intel Errata AAP53  (model 30)
2182  *   Intel Errata BD53   (model 44)
2183  *
2184  * The official story:
2185  *   These chips need to be 'reset' when adding counters by programming the
2186  *   magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2187  *   in sequence on the same PMC or on different PMCs.
2188  *
2189  * In practice it appears some of these events do in fact count, and
2190  * we need to program all 4 events.
2191  */
2192 static void intel_pmu_nhm_workaround(void)
2193 {
2194         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2195         static const unsigned long nhm_magic[4] = {
2196                 0x4300B5,
2197                 0x4300D2,
2198                 0x4300B1,
2199                 0x4300B1
2200         };
2201         struct perf_event *event;
2202         int i;
2203
2204         /*
2205          * The Errata requires below steps:
2206          * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2207          * 2) Configure 4 PERFEVTSELx with the magic events and clear
2208          *    the corresponding PMCx;
2209          * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2210          * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2211          * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2212          */
2213
2214         /*
2215          * The real steps we choose are a little different from above.
2216          * A) To reduce MSR operations, we don't run step 1) as they
2217          *    are already cleared before this function is called;
2218          * B) Call x86_perf_event_update to save PMCx before configuring
2219          *    PERFEVTSELx with magic number;
2220          * C) With step 5), we do clear only when the PERFEVTSELx is
2221          *    not used currently.
2222          * D) Call x86_perf_event_set_period to restore PMCx;
2223          */
2224
2225         /* We always operate 4 pairs of PERF Counters */
2226         for (i = 0; i < 4; i++) {
2227                 event = cpuc->events[i];
2228                 if (event)
2229                         x86_perf_event_update(event);
2230         }
2231
2232         for (i = 0; i < 4; i++) {
2233                 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2234                 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2235         }
2236
2237         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2238         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2239
2240         for (i = 0; i < 4; i++) {
2241                 event = cpuc->events[i];
2242
2243                 if (event) {
2244                         x86_perf_event_set_period(event);
2245                         __x86_pmu_enable_event(&event->hw,
2246                                         ARCH_PERFMON_EVENTSEL_ENABLE);
2247                 } else
2248                         wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2249         }
2250 }
2251
2252 static void intel_pmu_nhm_enable_all(int added)
2253 {
2254         if (added)
2255                 intel_pmu_nhm_workaround();
2256         intel_pmu_enable_all(added);
2257 }
2258
2259 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2260 {
2261         u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2262
2263         if (cpuc->tfa_shadow != val) {
2264                 cpuc->tfa_shadow = val;
2265                 wrmsrl(MSR_TSX_FORCE_ABORT, val);
2266         }
2267 }
2268
2269 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2270 {
2271         /*
2272          * We're going to use PMC3, make sure TFA is set before we touch it.
2273          */
2274         if (cntr == 3)
2275                 intel_set_tfa(cpuc, true);
2276 }
2277
2278 static void intel_tfa_pmu_enable_all(int added)
2279 {
2280         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2281
2282         /*
2283          * If we find PMC3 is no longer used when we enable the PMU, we can
2284          * clear TFA.
2285          */
2286         if (!test_bit(3, cpuc->active_mask))
2287                 intel_set_tfa(cpuc, false);
2288
2289         intel_pmu_enable_all(added);
2290 }
2291
2292 static inline u64 intel_pmu_get_status(void)
2293 {
2294         u64 status;
2295
2296         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2297
2298         return status;
2299 }
2300
2301 static inline void intel_pmu_ack_status(u64 ack)
2302 {
2303         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2304 }
2305
2306 static inline bool event_is_checkpointed(struct perf_event *event)
2307 {
2308         return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2309 }
2310
2311 static inline void intel_set_masks(struct perf_event *event, int idx)
2312 {
2313         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2314
2315         if (event->attr.exclude_host)
2316                 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2317         if (event->attr.exclude_guest)
2318                 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2319         if (event_is_checkpointed(event))
2320                 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2321 }
2322
2323 static inline void intel_clear_masks(struct perf_event *event, int idx)
2324 {
2325         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2326
2327         __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2328         __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2329         __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2330 }
2331
2332 static void intel_pmu_disable_fixed(struct perf_event *event)
2333 {
2334         struct hw_perf_event *hwc = &event->hw;
2335         u64 ctrl_val, mask;
2336         int idx = hwc->idx;
2337
2338         if (is_topdown_idx(idx)) {
2339                 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2340
2341                 /*
2342                  * When there are other active TopDown events,
2343                  * don't disable the fixed counter 3.
2344                  */
2345                 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2346                         return;
2347                 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2348         }
2349
2350         intel_clear_masks(event, idx);
2351
2352         mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4);
2353         rdmsrl(hwc->config_base, ctrl_val);
2354         ctrl_val &= ~mask;
2355         wrmsrl(hwc->config_base, ctrl_val);
2356 }
2357
2358 static void intel_pmu_disable_event(struct perf_event *event)
2359 {
2360         struct hw_perf_event *hwc = &event->hw;
2361         int idx = hwc->idx;
2362
2363         switch (idx) {
2364         case 0 ... INTEL_PMC_IDX_FIXED - 1:
2365                 intel_clear_masks(event, idx);
2366                 x86_pmu_disable_event(event);
2367                 break;
2368         case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2369         case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2370                 intel_pmu_disable_fixed(event);
2371                 break;
2372         case INTEL_PMC_IDX_FIXED_BTS:
2373                 intel_pmu_disable_bts();
2374                 intel_pmu_drain_bts_buffer();
2375                 return;
2376         case INTEL_PMC_IDX_FIXED_VLBR:
2377                 intel_clear_masks(event, idx);
2378                 break;
2379         default:
2380                 intel_clear_masks(event, idx);
2381                 pr_warn("Failed to disable the event with invalid index %d\n",
2382                         idx);
2383                 return;
2384         }
2385
2386         /*
2387          * Needs to be called after x86_pmu_disable_event,
2388          * so we don't trigger the event without PEBS bit set.
2389          */
2390         if (unlikely(event->attr.precise_ip))
2391                 intel_pmu_pebs_disable(event);
2392 }
2393
2394 static void intel_pmu_del_event(struct perf_event *event)
2395 {
2396         if (needs_branch_stack(event))
2397                 intel_pmu_lbr_del(event);
2398         if (event->attr.precise_ip)
2399                 intel_pmu_pebs_del(event);
2400 }
2401
2402 static int icl_set_topdown_event_period(struct perf_event *event)
2403 {
2404         struct hw_perf_event *hwc = &event->hw;
2405         s64 left = local64_read(&hwc->period_left);
2406
2407         /*
2408          * The values in PERF_METRICS MSR are derived from fixed counter 3.
2409          * Software should start both registers, PERF_METRICS and fixed
2410          * counter 3, from zero.
2411          * Clear PERF_METRICS and Fixed counter 3 in initialization.
2412          * After that, both MSRs will be cleared for each read.
2413          * Don't need to clear them again.
2414          */
2415         if (left == x86_pmu.max_period) {
2416                 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2417                 wrmsrl(MSR_PERF_METRICS, 0);
2418                 hwc->saved_slots = 0;
2419                 hwc->saved_metric = 0;
2420         }
2421
2422         if ((hwc->saved_slots) && is_slots_event(event)) {
2423                 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots);
2424                 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric);
2425         }
2426
2427         perf_event_update_userpage(event);
2428
2429         return 0;
2430 }
2431
2432 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
2433 {
2434         u32 val;
2435
2436         /*
2437          * The metric is reported as an 8bit integer fraction
2438          * summing up to 0xff.
2439          * slots-in-metric = (Metric / 0xff) * slots
2440          */
2441         val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff;
2442         return  mul_u64_u32_div(slots, val, 0xff);
2443 }
2444
2445 static u64 icl_get_topdown_value(struct perf_event *event,
2446                                        u64 slots, u64 metrics)
2447 {
2448         int idx = event->hw.idx;
2449         u64 delta;
2450
2451         if (is_metric_idx(idx))
2452                 delta = icl_get_metrics_event_value(metrics, slots, idx);
2453         else
2454                 delta = slots;
2455
2456         return delta;
2457 }
2458
2459 static void __icl_update_topdown_event(struct perf_event *event,
2460                                        u64 slots, u64 metrics,
2461                                        u64 last_slots, u64 last_metrics)
2462 {
2463         u64 delta, last = 0;
2464
2465         delta = icl_get_topdown_value(event, slots, metrics);
2466         if (last_slots)
2467                 last = icl_get_topdown_value(event, last_slots, last_metrics);
2468
2469         /*
2470          * The 8bit integer fraction of metric may be not accurate,
2471          * especially when the changes is very small.
2472          * For example, if only a few bad_spec happens, the fraction
2473          * may be reduced from 1 to 0. If so, the bad_spec event value
2474          * will be 0 which is definitely less than the last value.
2475          * Avoid update event->count for this case.
2476          */
2477         if (delta > last) {
2478                 delta -= last;
2479                 local64_add(delta, &event->count);
2480         }
2481 }
2482
2483 static void update_saved_topdown_regs(struct perf_event *event, u64 slots,
2484                                       u64 metrics, int metric_end)
2485 {
2486         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2487         struct perf_event *other;
2488         int idx;
2489
2490         event->hw.saved_slots = slots;
2491         event->hw.saved_metric = metrics;
2492
2493         for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2494                 if (!is_topdown_idx(idx))
2495                         continue;
2496                 other = cpuc->events[idx];
2497                 other->hw.saved_slots = slots;
2498                 other->hw.saved_metric = metrics;
2499         }
2500 }
2501
2502 /*
2503  * Update all active Topdown events.
2504  *
2505  * The PERF_METRICS and Fixed counter 3 are read separately. The values may be
2506  * modify by a NMI. PMU has to be disabled before calling this function.
2507  */
2508
2509 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end)
2510 {
2511         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2512         struct perf_event *other;
2513         u64 slots, metrics;
2514         bool reset = true;
2515         int idx;
2516
2517         /* read Fixed counter 3 */
2518         rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots);
2519         if (!slots)
2520                 return 0;
2521
2522         /* read PERF_METRICS */
2523         rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics);
2524
2525         for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2526                 if (!is_topdown_idx(idx))
2527                         continue;
2528                 other = cpuc->events[idx];
2529                 __icl_update_topdown_event(other, slots, metrics,
2530                                            event ? event->hw.saved_slots : 0,
2531                                            event ? event->hw.saved_metric : 0);
2532         }
2533
2534         /*
2535          * Check and update this event, which may have been cleared
2536          * in active_mask e.g. x86_pmu_stop()
2537          */
2538         if (event && !test_bit(event->hw.idx, cpuc->active_mask)) {
2539                 __icl_update_topdown_event(event, slots, metrics,
2540                                            event->hw.saved_slots,
2541                                            event->hw.saved_metric);
2542
2543                 /*
2544                  * In x86_pmu_stop(), the event is cleared in active_mask first,
2545                  * then drain the delta, which indicates context switch for
2546                  * counting.
2547                  * Save metric and slots for context switch.
2548                  * Don't need to reset the PERF_METRICS and Fixed counter 3.
2549                  * Because the values will be restored in next schedule in.
2550                  */
2551                 update_saved_topdown_regs(event, slots, metrics, metric_end);
2552                 reset = false;
2553         }
2554
2555         if (reset) {
2556                 /* The fixed counter 3 has to be written before the PERF_METRICS. */
2557                 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2558                 wrmsrl(MSR_PERF_METRICS, 0);
2559                 if (event)
2560                         update_saved_topdown_regs(event, 0, 0, metric_end);
2561         }
2562
2563         return slots;
2564 }
2565
2566 static u64 icl_update_topdown_event(struct perf_event *event)
2567 {
2568         return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE +
2569                                                  x86_pmu.num_topdown_events - 1);
2570 }
2571
2572 static void intel_pmu_read_topdown_event(struct perf_event *event)
2573 {
2574         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2575
2576         /* Only need to call update_topdown_event() once for group read. */
2577         if ((cpuc->txn_flags & PERF_PMU_TXN_READ) &&
2578             !is_slots_event(event))
2579                 return;
2580
2581         perf_pmu_disable(event->pmu);
2582         x86_pmu.update_topdown_event(event);
2583         perf_pmu_enable(event->pmu);
2584 }
2585
2586 static void intel_pmu_read_event(struct perf_event *event)
2587 {
2588         if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2589                 intel_pmu_auto_reload_read(event);
2590         else if (is_topdown_count(event) && x86_pmu.update_topdown_event)
2591                 intel_pmu_read_topdown_event(event);
2592         else
2593                 x86_perf_event_update(event);
2594 }
2595
2596 static void intel_pmu_enable_fixed(struct perf_event *event)
2597 {
2598         struct hw_perf_event *hwc = &event->hw;
2599         u64 ctrl_val, mask, bits = 0;
2600         int idx = hwc->idx;
2601
2602         if (is_topdown_idx(idx)) {
2603                 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2604                 /*
2605                  * When there are other active TopDown events,
2606                  * don't enable the fixed counter 3 again.
2607                  */
2608                 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2609                         return;
2610
2611                 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2612         }
2613
2614         intel_set_masks(event, idx);
2615
2616         /*
2617          * Enable IRQ generation (0x8), if not PEBS,
2618          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2619          * if requested:
2620          */
2621         if (!event->attr.precise_ip)
2622                 bits |= 0x8;
2623         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2624                 bits |= 0x2;
2625         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2626                 bits |= 0x1;
2627
2628         /*
2629          * ANY bit is supported in v3 and up
2630          */
2631         if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2632                 bits |= 0x4;
2633
2634         idx -= INTEL_PMC_IDX_FIXED;
2635         bits <<= (idx * 4);
2636         mask = 0xfULL << (idx * 4);
2637
2638         if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {
2639                 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2640                 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2641         }
2642
2643         rdmsrl(hwc->config_base, ctrl_val);
2644         ctrl_val &= ~mask;
2645         ctrl_val |= bits;
2646         wrmsrl(hwc->config_base, ctrl_val);
2647 }
2648
2649 static void intel_pmu_enable_event(struct perf_event *event)
2650 {
2651         struct hw_perf_event *hwc = &event->hw;
2652         int idx = hwc->idx;
2653
2654         if (unlikely(event->attr.precise_ip))
2655                 intel_pmu_pebs_enable(event);
2656
2657         switch (idx) {
2658         case 0 ... INTEL_PMC_IDX_FIXED - 1:
2659                 intel_set_masks(event, idx);
2660                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2661                 break;
2662         case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2663         case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2664                 intel_pmu_enable_fixed(event);
2665                 break;
2666         case INTEL_PMC_IDX_FIXED_BTS:
2667                 if (!__this_cpu_read(cpu_hw_events.enabled))
2668                         return;
2669                 intel_pmu_enable_bts(hwc->config);
2670                 break;
2671         case INTEL_PMC_IDX_FIXED_VLBR:
2672                 intel_set_masks(event, idx);
2673                 break;
2674         default:
2675                 pr_warn("Failed to enable the event with invalid index %d\n",
2676                         idx);
2677         }
2678 }
2679
2680 static void intel_pmu_add_event(struct perf_event *event)
2681 {
2682         if (event->attr.precise_ip)
2683                 intel_pmu_pebs_add(event);
2684         if (needs_branch_stack(event))
2685                 intel_pmu_lbr_add(event);
2686 }
2687
2688 /*
2689  * Save and restart an expired event. Called by NMI contexts,
2690  * so it has to be careful about preempting normal event ops:
2691  */
2692 int intel_pmu_save_and_restart(struct perf_event *event)
2693 {
2694         x86_perf_event_update(event);
2695         /*
2696          * For a checkpointed counter always reset back to 0.  This
2697          * avoids a situation where the counter overflows, aborts the
2698          * transaction and is then set back to shortly before the
2699          * overflow, and overflows and aborts again.
2700          */
2701         if (unlikely(event_is_checkpointed(event))) {
2702                 /* No race with NMIs because the counter should not be armed */
2703                 wrmsrl(event->hw.event_base, 0);
2704                 local64_set(&event->hw.prev_count, 0);
2705         }
2706         return x86_perf_event_set_period(event);
2707 }
2708
2709 static void intel_pmu_reset(void)
2710 {
2711         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2712         unsigned long flags;
2713         int idx;
2714
2715         if (!x86_pmu.num_counters)
2716                 return;
2717
2718         local_irq_save(flags);
2719
2720         pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2721
2722         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2723                 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2724                 wrmsrl_safe(x86_pmu_event_addr(idx),  0ull);
2725         }
2726         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
2727                 if (fixed_counter_disabled(idx))
2728                         continue;
2729                 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
2730         }
2731
2732         if (ds)
2733                 ds->bts_index = ds->bts_buffer_base;
2734
2735         /* Ack all overflows and disable fixed counters */
2736         if (x86_pmu.version >= 2) {
2737                 intel_pmu_ack_status(intel_pmu_get_status());
2738                 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2739         }
2740
2741         /* Reset LBRs and LBR freezing */
2742         if (x86_pmu.lbr_nr) {
2743                 update_debugctlmsr(get_debugctlmsr() &
2744                         ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2745         }
2746
2747         local_irq_restore(flags);
2748 }
2749
2750 static int handle_pmi_common(struct pt_regs *regs, u64 status)
2751 {
2752         struct perf_sample_data data;
2753         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2754         int bit;
2755         int handled = 0;
2756
2757         inc_irq_stat(apic_perf_irqs);
2758
2759         /*
2760          * Ignore a range of extra bits in status that do not indicate
2761          * overflow by themselves.
2762          */
2763         status &= ~(GLOBAL_STATUS_COND_CHG |
2764                     GLOBAL_STATUS_ASIF |
2765                     GLOBAL_STATUS_LBRS_FROZEN);
2766         if (!status)
2767                 return 0;
2768         /*
2769          * In case multiple PEBS events are sampled at the same time,
2770          * it is possible to have GLOBAL_STATUS bit 62 set indicating
2771          * PEBS buffer overflow and also seeing at most 3 PEBS counters
2772          * having their bits set in the status register. This is a sign
2773          * that there was at least one PEBS record pending at the time
2774          * of the PMU interrupt. PEBS counters must only be processed
2775          * via the drain_pebs() calls and not via the regular sample
2776          * processing loop coming after that the function, otherwise
2777          * phony regular samples may be generated in the sampling buffer
2778          * not marked with the EXACT tag. Another possibility is to have
2779          * one PEBS event and at least one non-PEBS event which overflows
2780          * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
2781          * not be set, yet the overflow status bit for the PEBS counter will
2782          * be on Skylake.
2783          *
2784          * To avoid this problem, we systematically ignore the PEBS-enabled
2785          * counters from the GLOBAL_STATUS mask and we always process PEBS
2786          * events via drain_pebs().
2787          */
2788         if (x86_pmu.flags & PMU_FL_PEBS_ALL)
2789                 status &= ~cpuc->pebs_enabled;
2790         else
2791                 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
2792
2793         /*
2794          * PEBS overflow sets bit 62 in the global status register
2795          */
2796         if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
2797                 u64 pebs_enabled = cpuc->pebs_enabled;
2798
2799                 handled++;
2800                 x86_pmu.drain_pebs(regs, &data);
2801                 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
2802
2803                 /*
2804                  * PMI throttle may be triggered, which stops the PEBS event.
2805                  * Although cpuc->pebs_enabled is updated accordingly, the
2806                  * MSR_IA32_PEBS_ENABLE is not updated. Because the
2807                  * cpuc->enabled has been forced to 0 in PMI.
2808                  * Update the MSR if pebs_enabled is changed.
2809                  */
2810                 if (pebs_enabled != cpuc->pebs_enabled)
2811                         wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
2812         }
2813
2814         /*
2815          * Intel PT
2816          */
2817         if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
2818                 handled++;
2819                 if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() &&
2820                         perf_guest_cbs->handle_intel_pt_intr))
2821                         perf_guest_cbs->handle_intel_pt_intr();
2822                 else
2823                         intel_pt_interrupt();
2824         }
2825
2826         /*
2827          * Intel Perf metrics
2828          */
2829         if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) {
2830                 handled++;
2831                 if (x86_pmu.update_topdown_event)
2832                         x86_pmu.update_topdown_event(NULL);
2833         }
2834
2835         /*
2836          * Checkpointed counters can lead to 'spurious' PMIs because the
2837          * rollback caused by the PMI will have cleared the overflow status
2838          * bit. Therefore always force probe these counters.
2839          */
2840         status |= cpuc->intel_cp_status;
2841
2842         for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
2843                 struct perf_event *event = cpuc->events[bit];
2844
2845                 handled++;
2846
2847                 if (!test_bit(bit, cpuc->active_mask))
2848                         continue;
2849
2850                 if (!intel_pmu_save_and_restart(event))
2851                         continue;
2852
2853                 perf_sample_data_init(&data, 0, event->hw.last_period);
2854
2855                 if (has_branch_stack(event))
2856                         data.br_stack = &cpuc->lbr_stack;
2857
2858                 if (perf_event_overflow(event, &data, regs))
2859                         x86_pmu_stop(event, 0);
2860         }
2861
2862         return handled;
2863 }
2864
2865 /*
2866  * This handler is triggered by the local APIC, so the APIC IRQ handling
2867  * rules apply:
2868  */
2869 static int intel_pmu_handle_irq(struct pt_regs *regs)
2870 {
2871         struct cpu_hw_events *cpuc;
2872         int loops;
2873         u64 status;
2874         int handled;
2875         int pmu_enabled;
2876
2877         cpuc = this_cpu_ptr(&cpu_hw_events);
2878
2879         /*
2880          * Save the PMU state.
2881          * It needs to be restored when leaving the handler.
2882          */
2883         pmu_enabled = cpuc->enabled;
2884         /*
2885          * No known reason to not always do late ACK,
2886          * but just in case do it opt-in.
2887          */
2888         if (!x86_pmu.late_ack)
2889                 apic_write(APIC_LVTPC, APIC_DM_NMI);
2890         intel_bts_disable_local();
2891         cpuc->enabled = 0;
2892         __intel_pmu_disable_all();
2893         handled = intel_pmu_drain_bts_buffer();
2894         handled += intel_bts_interrupt();
2895         status = intel_pmu_get_status();
2896         if (!status)
2897                 goto done;
2898
2899         loops = 0;
2900 again:
2901         intel_pmu_lbr_read();
2902         intel_pmu_ack_status(status);
2903         if (++loops > 100) {
2904                 static bool warned;
2905
2906                 if (!warned) {
2907                         WARN(1, "perfevents: irq loop stuck!\n");
2908                         perf_event_print_debug();
2909                         warned = true;
2910                 }
2911                 intel_pmu_reset();
2912                 goto done;
2913         }
2914
2915         handled += handle_pmi_common(regs, status);
2916
2917         /*
2918          * Repeat if there is more work to be done:
2919          */
2920         status = intel_pmu_get_status();
2921         if (status)
2922                 goto again;
2923
2924 done:
2925         /* Only restore PMU state when it's active. See x86_pmu_disable(). */
2926         cpuc->enabled = pmu_enabled;
2927         if (pmu_enabled)
2928                 __intel_pmu_enable_all(0, true);
2929         intel_bts_enable_local();
2930
2931         /*
2932          * Only unmask the NMI after the overflow counters
2933          * have been reset. This avoids spurious NMIs on
2934          * Haswell CPUs.
2935          */
2936         if (x86_pmu.late_ack)
2937                 apic_write(APIC_LVTPC, APIC_DM_NMI);
2938         return handled;
2939 }
2940
2941 static struct event_constraint *
2942 intel_bts_constraints(struct perf_event *event)
2943 {
2944         if (unlikely(intel_pmu_has_bts(event)))
2945                 return &bts_constraint;
2946
2947         return NULL;
2948 }
2949
2950 /*
2951  * Note: matches a fake event, like Fixed2.
2952  */
2953 static struct event_constraint *
2954 intel_vlbr_constraints(struct perf_event *event)
2955 {
2956         struct event_constraint *c = &vlbr_constraint;
2957
2958         if (unlikely(constraint_match(c, event->hw.config)))
2959                 return c;
2960
2961         return NULL;
2962 }
2963
2964 static int intel_alt_er(int idx, u64 config)
2965 {
2966         int alt_idx = idx;
2967
2968         if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
2969                 return idx;
2970
2971         if (idx == EXTRA_REG_RSP_0)
2972                 alt_idx = EXTRA_REG_RSP_1;
2973
2974         if (idx == EXTRA_REG_RSP_1)
2975                 alt_idx = EXTRA_REG_RSP_0;
2976
2977         if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
2978                 return idx;
2979
2980         return alt_idx;
2981 }
2982
2983 static void intel_fixup_er(struct perf_event *event, int idx)
2984 {
2985         event->hw.extra_reg.idx = idx;
2986
2987         if (idx == EXTRA_REG_RSP_0) {
2988                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2989                 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
2990                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
2991         } else if (idx == EXTRA_REG_RSP_1) {
2992                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2993                 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
2994                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
2995         }
2996 }
2997
2998 /*
2999  * manage allocation of shared extra msr for certain events
3000  *
3001  * sharing can be:
3002  * per-cpu: to be shared between the various events on a single PMU
3003  * per-core: per-cpu + shared by HT threads
3004  */
3005 static struct event_constraint *
3006 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
3007                                    struct perf_event *event,
3008                                    struct hw_perf_event_extra *reg)
3009 {
3010         struct event_constraint *c = &emptyconstraint;
3011         struct er_account *era;
3012         unsigned long flags;
3013         int idx = reg->idx;
3014
3015         /*
3016          * reg->alloc can be set due to existing state, so for fake cpuc we
3017          * need to ignore this, otherwise we might fail to allocate proper fake
3018          * state for this extra reg constraint. Also see the comment below.
3019          */
3020         if (reg->alloc && !cpuc->is_fake)
3021                 return NULL; /* call x86_get_event_constraint() */
3022
3023 again:
3024         era = &cpuc->shared_regs->regs[idx];
3025         /*
3026          * we use spin_lock_irqsave() to avoid lockdep issues when
3027          * passing a fake cpuc
3028          */
3029         raw_spin_lock_irqsave(&era->lock, flags);
3030
3031         if (!atomic_read(&era->ref) || era->config == reg->config) {
3032
3033                 /*
3034                  * If its a fake cpuc -- as per validate_{group,event}() we
3035                  * shouldn't touch event state and we can avoid doing so
3036                  * since both will only call get_event_constraints() once
3037                  * on each event, this avoids the need for reg->alloc.
3038                  *
3039                  * Not doing the ER fixup will only result in era->reg being
3040                  * wrong, but since we won't actually try and program hardware
3041                  * this isn't a problem either.
3042                  */
3043                 if (!cpuc->is_fake) {
3044                         if (idx != reg->idx)
3045                                 intel_fixup_er(event, idx);
3046
3047                         /*
3048                          * x86_schedule_events() can call get_event_constraints()
3049                          * multiple times on events in the case of incremental
3050                          * scheduling(). reg->alloc ensures we only do the ER
3051                          * allocation once.
3052                          */
3053                         reg->alloc = 1;
3054                 }
3055
3056                 /* lock in msr value */
3057                 era->config = reg->config;
3058                 era->reg = reg->reg;
3059
3060                 /* one more user */
3061                 atomic_inc(&era->ref);
3062
3063                 /*
3064                  * need to call x86_get_event_constraint()
3065                  * to check if associated event has constraints
3066                  */
3067                 c = NULL;
3068         } else {
3069                 idx = intel_alt_er(idx, reg->config);
3070                 if (idx != reg->idx) {
3071                         raw_spin_unlock_irqrestore(&era->lock, flags);
3072                         goto again;
3073                 }
3074         }
3075         raw_spin_unlock_irqrestore(&era->lock, flags);
3076
3077         return c;
3078 }
3079
3080 static void
3081 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
3082                                    struct hw_perf_event_extra *reg)
3083 {
3084         struct er_account *era;
3085
3086         /*
3087          * Only put constraint if extra reg was actually allocated. Also takes
3088          * care of event which do not use an extra shared reg.
3089          *
3090          * Also, if this is a fake cpuc we shouldn't touch any event state
3091          * (reg->alloc) and we don't care about leaving inconsistent cpuc state
3092          * either since it'll be thrown out.
3093          */
3094         if (!reg->alloc || cpuc->is_fake)
3095                 return;
3096
3097         era = &cpuc->shared_regs->regs[reg->idx];
3098
3099         /* one fewer user */
3100         atomic_dec(&era->ref);
3101
3102         /* allocate again next time */
3103         reg->alloc = 0;
3104 }
3105
3106 static struct event_constraint *
3107 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
3108                               struct perf_event *event)
3109 {
3110         struct event_constraint *c = NULL, *d;
3111         struct hw_perf_event_extra *xreg, *breg;
3112
3113         xreg = &event->hw.extra_reg;
3114         if (xreg->idx != EXTRA_REG_NONE) {
3115                 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
3116                 if (c == &emptyconstraint)
3117                         return c;
3118         }
3119         breg = &event->hw.branch_reg;
3120         if (breg->idx != EXTRA_REG_NONE) {
3121                 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
3122                 if (d == &emptyconstraint) {
3123                         __intel_shared_reg_put_constraints(cpuc, xreg);
3124                         c = d;
3125                 }
3126         }
3127         return c;
3128 }
3129
3130 struct event_constraint *
3131 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3132                           struct perf_event *event)
3133 {
3134         struct event_constraint *c;
3135
3136         if (x86_pmu.event_constraints) {
3137                 for_each_event_constraint(c, x86_pmu.event_constraints) {
3138                         if (constraint_match(c, event->hw.config)) {
3139                                 event->hw.flags |= c->flags;
3140                                 return c;
3141                         }
3142                 }
3143         }
3144
3145         return &unconstrained;
3146 }
3147
3148 static struct event_constraint *
3149 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3150                             struct perf_event *event)
3151 {
3152         struct event_constraint *c;
3153
3154         c = intel_vlbr_constraints(event);
3155         if (c)
3156                 return c;
3157
3158         c = intel_bts_constraints(event);
3159         if (c)
3160                 return c;
3161
3162         c = intel_shared_regs_constraints(cpuc, event);
3163         if (c)
3164                 return c;
3165
3166         c = intel_pebs_constraints(event);
3167         if (c)
3168                 return c;
3169
3170         return x86_get_event_constraints(cpuc, idx, event);
3171 }
3172
3173 static void
3174 intel_start_scheduling(struct cpu_hw_events *cpuc)
3175 {
3176         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3177         struct intel_excl_states *xl;
3178         int tid = cpuc->excl_thread_id;
3179
3180         /*
3181          * nothing needed if in group validation mode
3182          */
3183         if (cpuc->is_fake || !is_ht_workaround_enabled())
3184                 return;
3185
3186         /*
3187          * no exclusion needed
3188          */
3189         if (WARN_ON_ONCE(!excl_cntrs))
3190                 return;
3191
3192         xl = &excl_cntrs->states[tid];
3193
3194         xl->sched_started = true;
3195         /*
3196          * lock shared state until we are done scheduling
3197          * in stop_event_scheduling()
3198          * makes scheduling appear as a transaction
3199          */
3200         raw_spin_lock(&excl_cntrs->lock);
3201 }
3202
3203 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
3204 {
3205         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3206         struct event_constraint *c = cpuc->event_constraint[idx];
3207         struct intel_excl_states *xl;
3208         int tid = cpuc->excl_thread_id;
3209
3210         if (cpuc->is_fake || !is_ht_workaround_enabled())
3211                 return;
3212
3213         if (WARN_ON_ONCE(!excl_cntrs))
3214                 return;
3215
3216         if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
3217                 return;
3218
3219         xl = &excl_cntrs->states[tid];
3220
3221         lockdep_assert_held(&excl_cntrs->lock);
3222
3223         if (c->flags & PERF_X86_EVENT_EXCL)
3224                 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
3225         else
3226                 xl->state[cntr] = INTEL_EXCL_SHARED;
3227 }
3228
3229 static void
3230 intel_stop_scheduling(struct cpu_hw_events *cpuc)
3231 {
3232         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3233         struct intel_excl_states *xl;
3234         int tid = cpuc->excl_thread_id;
3235
3236         /*
3237          * nothing needed if in group validation mode
3238          */
3239         if (cpuc->is_fake || !is_ht_workaround_enabled())
3240                 return;
3241         /*
3242          * no exclusion needed
3243          */
3244         if (WARN_ON_ONCE(!excl_cntrs))
3245                 return;
3246
3247         xl = &excl_cntrs->states[tid];
3248
3249         xl->sched_started = false;
3250         /*
3251          * release shared state lock (acquired in intel_start_scheduling())
3252          */
3253         raw_spin_unlock(&excl_cntrs->lock);
3254 }
3255
3256 static struct event_constraint *
3257 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
3258 {
3259         WARN_ON_ONCE(!cpuc->constraint_list);
3260
3261         if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
3262                 struct event_constraint *cx;
3263
3264                 /*
3265                  * grab pre-allocated constraint entry
3266                  */
3267                 cx = &cpuc->constraint_list[idx];
3268
3269                 /*
3270                  * initialize dynamic constraint
3271                  * with static constraint
3272                  */
3273                 *cx = *c;
3274
3275                 /*
3276                  * mark constraint as dynamic
3277                  */
3278                 cx->flags |= PERF_X86_EVENT_DYNAMIC;
3279                 c = cx;
3280         }
3281
3282         return c;
3283 }
3284
3285 static struct event_constraint *
3286 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
3287                            int idx, struct event_constraint *c)
3288 {
3289         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3290         struct intel_excl_states *xlo;
3291         int tid = cpuc->excl_thread_id;
3292         int is_excl, i, w;
3293
3294         /*
3295          * validating a group does not require
3296          * enforcing cross-thread  exclusion
3297          */
3298         if (cpuc->is_fake || !is_ht_workaround_enabled())
3299                 return c;
3300
3301         /*
3302          * no exclusion needed
3303          */
3304         if (WARN_ON_ONCE(!excl_cntrs))
3305                 return c;
3306
3307         /*
3308          * because we modify the constraint, we need
3309          * to make a copy. Static constraints come
3310          * from static const tables.
3311          *
3312          * only needed when constraint has not yet
3313          * been cloned (marked dynamic)
3314          */
3315         c = dyn_constraint(cpuc, c, idx);
3316
3317         /*
3318          * From here on, the constraint is dynamic.
3319          * Either it was just allocated above, or it
3320          * was allocated during a earlier invocation
3321          * of this function
3322          */
3323
3324         /*
3325          * state of sibling HT
3326          */
3327         xlo = &excl_cntrs->states[tid ^ 1];
3328
3329         /*
3330          * event requires exclusive counter access
3331          * across HT threads
3332          */
3333         is_excl = c->flags & PERF_X86_EVENT_EXCL;
3334         if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
3335                 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
3336                 if (!cpuc->n_excl++)
3337                         WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
3338         }
3339
3340         /*
3341          * Modify static constraint with current dynamic
3342          * state of thread
3343          *
3344          * EXCLUSIVE: sibling counter measuring exclusive event
3345          * SHARED   : sibling counter measuring non-exclusive event
3346          * UNUSED   : sibling counter unused
3347          */
3348         w = c->weight;
3349         for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
3350                 /*
3351                  * exclusive event in sibling counter
3352                  * our corresponding counter cannot be used
3353                  * regardless of our event
3354                  */
3355                 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
3356                         __clear_bit(i, c->idxmsk);
3357                         w--;
3358                         continue;
3359                 }
3360                 /*
3361                  * if measuring an exclusive event, sibling
3362                  * measuring non-exclusive, then counter cannot
3363                  * be used
3364                  */
3365                 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
3366                         __clear_bit(i, c->idxmsk);
3367                         w--;
3368                         continue;
3369                 }
3370         }
3371
3372         /*
3373          * if we return an empty mask, then switch
3374          * back to static empty constraint to avoid
3375          * the cost of freeing later on
3376          */
3377         if (!w)
3378                 c = &emptyconstraint;
3379
3380         c->weight = w;
3381
3382         return c;
3383 }
3384
3385 static struct event_constraint *
3386 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3387                             struct perf_event *event)
3388 {
3389         struct event_constraint *c1, *c2;
3390
3391         c1 = cpuc->event_constraint[idx];
3392
3393         /*
3394          * first time only
3395          * - static constraint: no change across incremental scheduling calls
3396          * - dynamic constraint: handled by intel_get_excl_constraints()
3397          */
3398         c2 = __intel_get_event_constraints(cpuc, idx, event);
3399         if (c1) {
3400                 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
3401                 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
3402                 c1->weight = c2->weight;
3403                 c2 = c1;
3404         }
3405
3406         if (cpuc->excl_cntrs)
3407                 return intel_get_excl_constraints(cpuc, event, idx, c2);
3408
3409         return c2;
3410 }
3411
3412 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
3413                 struct perf_event *event)
3414 {
3415         struct hw_perf_event *hwc = &event->hw;
3416         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3417         int tid = cpuc->excl_thread_id;
3418         struct intel_excl_states *xl;
3419
3420         /*
3421          * nothing needed if in group validation mode
3422          */
3423         if (cpuc->is_fake)
3424                 return;
3425
3426         if (WARN_ON_ONCE(!excl_cntrs))
3427                 return;
3428
3429         if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
3430                 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
3431                 if (!--cpuc->n_excl)
3432                         WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
3433         }
3434
3435         /*
3436          * If event was actually assigned, then mark the counter state as
3437          * unused now.
3438          */
3439         if (hwc->idx >= 0) {
3440                 xl = &excl_cntrs->states[tid];
3441
3442                 /*
3443                  * put_constraint may be called from x86_schedule_events()
3444                  * which already has the lock held so here make locking
3445                  * conditional.
3446                  */
3447                 if (!xl->sched_started)
3448                         raw_spin_lock(&excl_cntrs->lock);
3449
3450                 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
3451
3452                 if (!xl->sched_started)
3453                         raw_spin_unlock(&excl_cntrs->lock);
3454         }
3455 }
3456
3457 static void
3458 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
3459                                         struct perf_event *event)
3460 {
3461         struct hw_perf_event_extra *reg;
3462
3463         reg = &event->hw.extra_reg;
3464         if (reg->idx != EXTRA_REG_NONE)
3465                 __intel_shared_reg_put_constraints(cpuc, reg);
3466
3467         reg = &event->hw.branch_reg;
3468         if (reg->idx != EXTRA_REG_NONE)
3469                 __intel_shared_reg_put_constraints(cpuc, reg);
3470 }
3471
3472 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
3473                                         struct perf_event *event)
3474 {
3475         intel_put_shared_regs_event_constraints(cpuc, event);
3476
3477         /*
3478          * is PMU has exclusive counter restrictions, then
3479          * all events are subject to and must call the
3480          * put_excl_constraints() routine
3481          */
3482         if (cpuc->excl_cntrs)
3483                 intel_put_excl_constraints(cpuc, event);
3484 }
3485
3486 static void intel_pebs_aliases_core2(struct perf_event *event)
3487 {
3488         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3489                 /*
3490                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3491                  * (0x003c) so that we can use it with PEBS.
3492                  *
3493                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3494                  * PEBS capable. However we can use INST_RETIRED.ANY_P
3495                  * (0x00c0), which is a PEBS capable event, to get the same
3496                  * count.
3497                  *
3498                  * INST_RETIRED.ANY_P counts the number of cycles that retires
3499                  * CNTMASK instructions. By setting CNTMASK to a value (16)
3500                  * larger than the maximum number of instructions that can be
3501                  * retired per cycle (4) and then inverting the condition, we
3502                  * count all cycles that retire 16 or less instructions, which
3503                  * is every cycle.
3504                  *
3505                  * Thereby we gain a PEBS capable cycle counter.
3506                  */
3507                 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3508
3509                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3510                 event->hw.config = alt_config;
3511         }
3512 }
3513
3514 static void intel_pebs_aliases_snb(struct perf_event *event)
3515 {
3516         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3517                 /*
3518                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3519                  * (0x003c) so that we can use it with PEBS.
3520                  *
3521                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3522                  * PEBS capable. However we can use UOPS_RETIRED.ALL
3523                  * (0x01c2), which is a PEBS capable event, to get the same
3524                  * count.
3525                  *
3526                  * UOPS_RETIRED.ALL counts the number of cycles that retires
3527                  * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3528                  * larger than the maximum number of micro-ops that can be
3529                  * retired per cycle (4) and then inverting the condition, we
3530                  * count all cycles that retire 16 or less micro-ops, which
3531                  * is every cycle.
3532                  *
3533                  * Thereby we gain a PEBS capable cycle counter.
3534                  */
3535                 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
3536
3537                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3538                 event->hw.config = alt_config;
3539         }
3540 }
3541
3542 static void intel_pebs_aliases_precdist(struct perf_event *event)
3543 {
3544         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3545                 /*
3546                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3547                  * (0x003c) so that we can use it with PEBS.
3548                  *
3549                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3550                  * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3551                  * (0x01c0), which is a PEBS capable event, to get the same
3552                  * count.
3553                  *
3554                  * The PREC_DIST event has special support to minimize sample
3555                  * shadowing effects. One drawback is that it can be
3556                  * only programmed on counter 1, but that seems like an
3557                  * acceptable trade off.
3558                  */
3559                 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3560
3561                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3562                 event->hw.config = alt_config;
3563         }
3564 }
3565
3566 static void intel_pebs_aliases_ivb(struct perf_event *event)
3567 {
3568         if (event->attr.precise_ip < 3)
3569                 return intel_pebs_aliases_snb(event);
3570         return intel_pebs_aliases_precdist(event);
3571 }
3572
3573 static void intel_pebs_aliases_skl(struct perf_event *event)
3574 {
3575         if (event->attr.precise_ip < 3)
3576                 return intel_pebs_aliases_core2(event);
3577         return intel_pebs_aliases_precdist(event);
3578 }
3579
3580 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
3581 {
3582         unsigned long flags = x86_pmu.large_pebs_flags;
3583
3584         if (event->attr.use_clockid)
3585                 flags &= ~PERF_SAMPLE_TIME;
3586         if (!event->attr.exclude_kernel)
3587                 flags &= ~PERF_SAMPLE_REGS_USER;
3588         if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
3589                 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
3590         return flags;
3591 }
3592
3593 static int intel_pmu_bts_config(struct perf_event *event)
3594 {
3595         struct perf_event_attr *attr = &event->attr;
3596
3597         if (unlikely(intel_pmu_has_bts(event))) {
3598                 /* BTS is not supported by this architecture. */
3599                 if (!x86_pmu.bts_active)
3600                         return -EOPNOTSUPP;
3601
3602                 /* BTS is currently only allowed for user-mode. */
3603                 if (!attr->exclude_kernel)
3604                         return -EOPNOTSUPP;
3605
3606                 /* BTS is not allowed for precise events. */
3607                 if (attr->precise_ip)
3608                         return -EOPNOTSUPP;
3609
3610                 /* disallow bts if conflicting events are present */
3611                 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3612                         return -EBUSY;
3613
3614                 event->destroy = hw_perf_lbr_event_destroy;
3615         }
3616
3617         return 0;
3618 }
3619
3620 static int core_pmu_hw_config(struct perf_event *event)
3621 {
3622         int ret = x86_pmu_hw_config(event);
3623
3624         if (ret)
3625                 return ret;
3626
3627         return intel_pmu_bts_config(event);
3628 }
3629
3630 #define INTEL_TD_METRIC_AVAILABLE_MAX   (INTEL_TD_METRIC_RETIRING + \
3631                                          ((x86_pmu.num_topdown_events - 1) << 8))
3632
3633 static bool is_available_metric_event(struct perf_event *event)
3634 {
3635         return is_metric_event(event) &&
3636                 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX;
3637 }
3638
3639 static inline bool is_mem_loads_event(struct perf_event *event)
3640 {
3641         return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01);
3642 }
3643
3644 static inline bool is_mem_loads_aux_event(struct perf_event *event)
3645 {
3646         return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82);
3647 }
3648
3649
3650 static int intel_pmu_hw_config(struct perf_event *event)
3651 {
3652         int ret = x86_pmu_hw_config(event);
3653
3654         if (ret)
3655                 return ret;
3656
3657         ret = intel_pmu_bts_config(event);
3658         if (ret)
3659                 return ret;
3660
3661         if (event->attr.precise_ip) {
3662                 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
3663                         return -EINVAL;
3664
3665                 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
3666                         event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
3667                         if (!(event->attr.sample_type &
3668                               ~intel_pmu_large_pebs_flags(event))) {
3669                                 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
3670                                 event->attach_state |= PERF_ATTACH_SCHED_CB;
3671                         }
3672                 }
3673                 if (x86_pmu.pebs_aliases)
3674                         x86_pmu.pebs_aliases(event);
3675
3676                 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN)
3677                         event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY;
3678         }
3679
3680         if (needs_branch_stack(event)) {
3681                 ret = intel_pmu_setup_lbr_filter(event);
3682                 if (ret)
3683                         return ret;
3684                 event->attach_state |= PERF_ATTACH_SCHED_CB;
3685
3686                 /*
3687                  * BTS is set up earlier in this path, so don't account twice
3688                  */
3689                 if (!unlikely(intel_pmu_has_bts(event))) {
3690                         /* disallow lbr if conflicting events are present */
3691                         if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3692                                 return -EBUSY;
3693
3694                         event->destroy = hw_perf_lbr_event_destroy;
3695                 }
3696         }
3697
3698         if (event->attr.aux_output) {
3699                 if (!event->attr.precise_ip)
3700                         return -EINVAL;
3701
3702                 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
3703         }
3704
3705         if (event->attr.type != PERF_TYPE_RAW)
3706                 return 0;
3707
3708         /*
3709          * Config Topdown slots and metric events
3710          *
3711          * The slots event on Fixed Counter 3 can support sampling,
3712          * which will be handled normally in x86_perf_event_update().
3713          *
3714          * Metric events don't support sampling and require being paired
3715          * with a slots event as group leader. When the slots event
3716          * is used in a metrics group, it too cannot support sampling.
3717          */
3718         if (x86_pmu.intel_cap.perf_metrics && is_topdown_event(event)) {
3719                 if (event->attr.config1 || event->attr.config2)
3720                         return -EINVAL;
3721
3722                 /*
3723                  * The TopDown metrics events and slots event don't
3724                  * support any filters.
3725                  */
3726                 if (event->attr.config & X86_ALL_EVENT_FLAGS)
3727                         return -EINVAL;
3728
3729                 if (is_available_metric_event(event)) {
3730                         struct perf_event *leader = event->group_leader;
3731
3732                         /* The metric events don't support sampling. */
3733                         if (is_sampling_event(event))
3734                                 return -EINVAL;
3735
3736                         /* The metric events require a slots group leader. */
3737                         if (!is_slots_event(leader))
3738                                 return -EINVAL;
3739
3740                         /*
3741                          * The leader/SLOTS must not be a sampling event for
3742                          * metric use; hardware requires it starts at 0 when used
3743                          * in conjunction with MSR_PERF_METRICS.
3744                          */
3745                         if (is_sampling_event(leader))
3746                                 return -EINVAL;
3747
3748                         event->event_caps |= PERF_EV_CAP_SIBLING;
3749                         /*
3750                          * Only once we have a METRICs sibling do we
3751                          * need TopDown magic.
3752                          */
3753                         leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
3754                         event->hw.flags  |= PERF_X86_EVENT_TOPDOWN;
3755                 }
3756         }
3757
3758         /*
3759          * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR
3760          * doesn't function quite right. As a work-around it needs to always be
3761          * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82).
3762          * The actual count of this second event is irrelevant it just needs
3763          * to be active to make the first event function correctly.
3764          *
3765          * In a group, the auxiliary event must be in front of the load latency
3766          * event. The rule is to simplify the implementation of the check.
3767          * That's because perf cannot have a complete group at the moment.
3768          */
3769         if (x86_pmu.flags & PMU_FL_MEM_LOADS_AUX &&
3770             (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) &&
3771             is_mem_loads_event(event)) {
3772                 struct perf_event *leader = event->group_leader;
3773                 struct perf_event *sibling = NULL;
3774
3775                 if (!is_mem_loads_aux_event(leader)) {
3776                         for_each_sibling_event(sibling, leader) {
3777                                 if (is_mem_loads_aux_event(sibling))
3778                                         break;
3779                         }
3780                         if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list))
3781                                 return -ENODATA;
3782                 }
3783         }
3784
3785         if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
3786                 return 0;
3787
3788         if (x86_pmu.version < 3)
3789                 return -EINVAL;
3790
3791         ret = perf_allow_cpu(&event->attr);
3792         if (ret)
3793                 return ret;
3794
3795         event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
3796
3797         return 0;
3798 }
3799
3800 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
3801 {
3802         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3803         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3804
3805         arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
3806         arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
3807         arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
3808         if (x86_pmu.flags & PMU_FL_PEBS_ALL)
3809                 arr[0].guest &= ~cpuc->pebs_enabled;
3810         else
3811                 arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
3812         *nr = 1;
3813
3814         if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) {
3815                 /*
3816                  * If PMU counter has PEBS enabled it is not enough to
3817                  * disable counter on a guest entry since PEBS memory
3818                  * write can overshoot guest entry and corrupt guest
3819                  * memory. Disabling PEBS solves the problem.
3820                  *
3821                  * Don't do this if the CPU already enforces it.
3822                  */
3823                 arr[1].msr = MSR_IA32_PEBS_ENABLE;
3824                 arr[1].host = cpuc->pebs_enabled;
3825                 arr[1].guest = 0;
3826                 *nr = 2;
3827         }
3828
3829         return arr;
3830 }
3831
3832 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
3833 {
3834         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3835         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3836         int idx;
3837
3838         for (idx = 0; idx < x86_pmu.num_counters; idx++)  {
3839                 struct perf_event *event = cpuc->events[idx];
3840
3841                 arr[idx].msr = x86_pmu_config_addr(idx);
3842                 arr[idx].host = arr[idx].guest = 0;
3843
3844                 if (!test_bit(idx, cpuc->active_mask))
3845                         continue;
3846
3847                 arr[idx].host = arr[idx].guest =
3848                         event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
3849
3850                 if (event->attr.exclude_host)
3851                         arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3852                 else if (event->attr.exclude_guest)
3853                         arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3854         }
3855
3856         *nr = x86_pmu.num_counters;
3857         return arr;
3858 }
3859
3860 static void core_pmu_enable_event(struct perf_event *event)
3861 {
3862         if (!event->attr.exclude_host)
3863                 x86_pmu_enable_event(event);
3864 }
3865
3866 static void core_pmu_enable_all(int added)
3867 {
3868         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3869         int idx;
3870
3871         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3872                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
3873
3874                 if (!test_bit(idx, cpuc->active_mask) ||
3875                                 cpuc->events[idx]->attr.exclude_host)
3876                         continue;
3877
3878                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
3879         }
3880 }
3881
3882 static int hsw_hw_config(struct perf_event *event)
3883 {
3884         int ret = intel_pmu_hw_config(event);
3885
3886         if (ret)
3887                 return ret;
3888         if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
3889                 return 0;
3890         event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
3891
3892         /*
3893          * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
3894          * PEBS or in ANY thread mode. Since the results are non-sensical forbid
3895          * this combination.
3896          */
3897         if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
3898              ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
3899               event->attr.precise_ip > 0))
3900                 return -EOPNOTSUPP;
3901
3902         if (event_is_checkpointed(event)) {
3903                 /*
3904                  * Sampling of checkpointed events can cause situations where
3905                  * the CPU constantly aborts because of a overflow, which is
3906                  * then checkpointed back and ignored. Forbid checkpointing
3907                  * for sampling.
3908                  *
3909                  * But still allow a long sampling period, so that perf stat
3910                  * from KVM works.
3911                  */
3912                 if (event->attr.sample_period > 0 &&
3913                     event->attr.sample_period < 0x7fffffff)
3914                         return -EOPNOTSUPP;
3915         }
3916         return 0;
3917 }
3918
3919 static struct event_constraint counter0_constraint =
3920                         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
3921
3922 static struct event_constraint counter2_constraint =
3923                         EVENT_CONSTRAINT(0, 0x4, 0);
3924
3925 static struct event_constraint fixed0_constraint =
3926                         FIXED_EVENT_CONSTRAINT(0x00c0, 0);
3927
3928 static struct event_constraint fixed0_counter0_constraint =
3929                         INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
3930
3931 static struct event_constraint *
3932 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3933                           struct perf_event *event)
3934 {
3935         struct event_constraint *c;
3936
3937         c = intel_get_event_constraints(cpuc, idx, event);
3938
3939         /* Handle special quirk on in_tx_checkpointed only in counter 2 */
3940         if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
3941                 if (c->idxmsk64 & (1U << 2))
3942                         return &counter2_constraint;
3943                 return &emptyconstraint;
3944         }
3945
3946         return c;
3947 }
3948
3949 static struct event_constraint *
3950 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3951                           struct perf_event *event)
3952 {
3953         /*
3954          * Fixed counter 0 has less skid.
3955          * Force instruction:ppp in Fixed counter 0
3956          */
3957         if ((event->attr.precise_ip == 3) &&
3958             constraint_match(&fixed0_constraint, event->hw.config))
3959                 return &fixed0_constraint;
3960
3961         return hsw_get_event_constraints(cpuc, idx, event);
3962 }
3963
3964 static struct event_constraint *
3965 spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3966                           struct perf_event *event)
3967 {
3968         struct event_constraint *c;
3969
3970         c = icl_get_event_constraints(cpuc, idx, event);
3971
3972         /*
3973          * The :ppp indicates the Precise Distribution (PDist) facility, which
3974          * is only supported on the GP counter 0. If a :ppp event which is not
3975          * available on the GP counter 0, error out.
3976          */
3977         if (event->attr.precise_ip == 3) {
3978                 if (c->idxmsk64 & BIT_ULL(0))
3979                         return &counter0_constraint;
3980
3981                 return &emptyconstraint;
3982         }
3983
3984         return c;
3985 }
3986
3987 static struct event_constraint *
3988 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3989                           struct perf_event *event)
3990 {
3991         struct event_constraint *c;
3992
3993         /* :ppp means to do reduced skid PEBS which is PMC0 only. */
3994         if (event->attr.precise_ip == 3)
3995                 return &counter0_constraint;
3996
3997         c = intel_get_event_constraints(cpuc, idx, event);
3998
3999         return c;
4000 }
4001
4002 static struct event_constraint *
4003 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4004                           struct perf_event *event)
4005 {
4006         struct event_constraint *c;
4007
4008         /*
4009          * :ppp means to do reduced skid PEBS,
4010          * which is available on PMC0 and fixed counter 0.
4011          */
4012         if (event->attr.precise_ip == 3) {
4013                 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
4014                 if (constraint_match(&fixed0_constraint, event->hw.config))
4015                         return &fixed0_counter0_constraint;
4016
4017                 return &counter0_constraint;
4018         }
4019
4020         c = intel_get_event_constraints(cpuc, idx, event);
4021
4022         return c;
4023 }
4024
4025 static bool allow_tsx_force_abort = true;
4026
4027 static struct event_constraint *
4028 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4029                           struct perf_event *event)
4030 {
4031         struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
4032
4033         /*
4034          * Without TFA we must not use PMC3.
4035          */
4036         if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
4037                 c = dyn_constraint(cpuc, c, idx);
4038                 c->idxmsk64 &= ~(1ULL << 3);
4039                 c->weight--;
4040         }
4041
4042         return c;
4043 }
4044
4045 /*
4046  * Broadwell:
4047  *
4048  * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
4049  * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
4050  * the two to enforce a minimum period of 128 (the smallest value that has bits
4051  * 0-5 cleared and >= 100).
4052  *
4053  * Because of how the code in x86_perf_event_set_period() works, the truncation
4054  * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
4055  * to make up for the 'lost' events due to carrying the 'error' in period_left.
4056  *
4057  * Therefore the effective (average) period matches the requested period,
4058  * despite coarser hardware granularity.
4059  */
4060 static u64 bdw_limit_period(struct perf_event *event, u64 left)
4061 {
4062         if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
4063                         X86_CONFIG(.event=0xc0, .umask=0x01)) {
4064                 if (left < 128)
4065                         left = 128;
4066                 left &= ~0x3fULL;
4067         }
4068         return left;
4069 }
4070
4071 static u64 nhm_limit_period(struct perf_event *event, u64 left)
4072 {
4073         return max(left, 32ULL);
4074 }
4075
4076 static u64 spr_limit_period(struct perf_event *event, u64 left)
4077 {
4078         if (event->attr.precise_ip == 3)
4079                 return max(left, 128ULL);
4080
4081         return left;
4082 }
4083
4084 PMU_FORMAT_ATTR(event,  "config:0-7"    );
4085 PMU_FORMAT_ATTR(umask,  "config:8-15"   );
4086 PMU_FORMAT_ATTR(edge,   "config:18"     );
4087 PMU_FORMAT_ATTR(pc,     "config:19"     );
4088 PMU_FORMAT_ATTR(any,    "config:21"     ); /* v3 + */
4089 PMU_FORMAT_ATTR(inv,    "config:23"     );
4090 PMU_FORMAT_ATTR(cmask,  "config:24-31"  );
4091 PMU_FORMAT_ATTR(in_tx,  "config:32");
4092 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
4093
4094 static struct attribute *intel_arch_formats_attr[] = {
4095         &format_attr_event.attr,
4096         &format_attr_umask.attr,
4097         &format_attr_edge.attr,
4098         &format_attr_pc.attr,
4099         &format_attr_inv.attr,
4100         &format_attr_cmask.attr,
4101         NULL,
4102 };
4103
4104 ssize_t intel_event_sysfs_show(char *page, u64 config)
4105 {
4106         u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
4107
4108         return x86_event_sysfs_show(page, config, event);
4109 }
4110
4111 static struct intel_shared_regs *allocate_shared_regs(int cpu)
4112 {
4113         struct intel_shared_regs *regs;
4114         int i;
4115
4116         regs = kzalloc_node(sizeof(struct intel_shared_regs),
4117                             GFP_KERNEL, cpu_to_node(cpu));
4118         if (regs) {
4119                 /*
4120                  * initialize the locks to keep lockdep happy
4121                  */
4122                 for (i = 0; i < EXTRA_REG_MAX; i++)
4123                         raw_spin_lock_init(&regs->regs[i].lock);
4124
4125                 regs->core_id = -1;
4126         }
4127         return regs;
4128 }
4129
4130 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
4131 {
4132         struct intel_excl_cntrs *c;
4133
4134         c = kzalloc_node(sizeof(struct intel_excl_cntrs),
4135                          GFP_KERNEL, cpu_to_node(cpu));
4136         if (c) {
4137                 raw_spin_lock_init(&c->lock);
4138                 c->core_id = -1;
4139         }
4140         return c;
4141 }
4142
4143
4144 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
4145 {
4146         cpuc->pebs_record_size = x86_pmu.pebs_record_size;
4147
4148         if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
4149                 cpuc->shared_regs = allocate_shared_regs(cpu);
4150                 if (!cpuc->shared_regs)
4151                         goto err;
4152         }
4153
4154         if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) {
4155                 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
4156
4157                 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
4158                 if (!cpuc->constraint_list)
4159                         goto err_shared_regs;
4160         }
4161
4162         if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4163                 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
4164                 if (!cpuc->excl_cntrs)
4165                         goto err_constraint_list;
4166
4167                 cpuc->excl_thread_id = 0;
4168         }
4169
4170         return 0;
4171
4172 err_constraint_list:
4173         kfree(cpuc->constraint_list);
4174         cpuc->constraint_list = NULL;
4175
4176 err_shared_regs:
4177         kfree(cpuc->shared_regs);
4178         cpuc->shared_regs = NULL;
4179
4180 err:
4181         return -ENOMEM;
4182 }
4183
4184 static int intel_pmu_cpu_prepare(int cpu)
4185 {
4186         return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
4187 }
4188
4189 static void flip_smm_bit(void *data)
4190 {
4191         unsigned long set = *(unsigned long *)data;
4192
4193         if (set > 0) {
4194                 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
4195                             DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4196         } else {
4197                 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
4198                               DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4199         }
4200 }
4201
4202 static void intel_pmu_cpu_starting(int cpu)
4203 {
4204         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4205         int core_id = topology_core_id(cpu);
4206         int i;
4207
4208         init_debug_store_on_cpu(cpu);
4209         /*
4210          * Deal with CPUs that don't clear their LBRs on power-up.
4211          */
4212         intel_pmu_lbr_reset();
4213
4214         cpuc->lbr_sel = NULL;
4215
4216         if (x86_pmu.flags & PMU_FL_TFA) {
4217                 WARN_ON_ONCE(cpuc->tfa_shadow);
4218                 cpuc->tfa_shadow = ~0ULL;
4219                 intel_set_tfa(cpuc, false);
4220         }
4221
4222         if (x86_pmu.version > 1)
4223                 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
4224
4225         /* Disable perf metrics if any added CPU doesn't support it. */
4226         if (x86_pmu.intel_cap.perf_metrics) {
4227                 union perf_capabilities perf_cap;
4228
4229                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
4230                 if (!perf_cap.perf_metrics) {
4231                         x86_pmu.intel_cap.perf_metrics = 0;
4232                         x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
4233                 }
4234         }
4235
4236         if (!cpuc->shared_regs)
4237                 return;
4238
4239         if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
4240                 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4241                         struct intel_shared_regs *pc;
4242
4243                         pc = per_cpu(cpu_hw_events, i).shared_regs;
4244                         if (pc && pc->core_id == core_id) {
4245                                 cpuc->kfree_on_online[0] = cpuc->shared_regs;
4246                                 cpuc->shared_regs = pc;
4247                                 break;
4248                         }
4249                 }
4250                 cpuc->shared_regs->core_id = core_id;
4251                 cpuc->shared_regs->refcnt++;
4252         }
4253
4254         if (x86_pmu.lbr_sel_map)
4255                 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
4256
4257         if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4258                 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4259                         struct cpu_hw_events *sibling;
4260                         struct intel_excl_cntrs *c;
4261
4262                         sibling = &per_cpu(cpu_hw_events, i);
4263                         c = sibling->excl_cntrs;
4264                         if (c && c->core_id == core_id) {
4265                                 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
4266                                 cpuc->excl_cntrs = c;
4267                                 if (!sibling->excl_thread_id)
4268                                         cpuc->excl_thread_id = 1;
4269                                 break;
4270                         }
4271                 }
4272                 cpuc->excl_cntrs->core_id = core_id;
4273                 cpuc->excl_cntrs->refcnt++;
4274         }
4275 }
4276
4277 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
4278 {
4279         struct intel_excl_cntrs *c;
4280
4281         c = cpuc->excl_cntrs;
4282         if (c) {
4283                 if (c->core_id == -1 || --c->refcnt == 0)
4284                         kfree(c);
4285                 cpuc->excl_cntrs = NULL;
4286         }
4287
4288         kfree(cpuc->constraint_list);
4289         cpuc->constraint_list = NULL;
4290 }
4291
4292 static void intel_pmu_cpu_dying(int cpu)
4293 {
4294         fini_debug_store_on_cpu(cpu);
4295 }
4296
4297 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
4298 {
4299         struct intel_shared_regs *pc;
4300
4301         pc = cpuc->shared_regs;
4302         if (pc) {
4303                 if (pc->core_id == -1 || --pc->refcnt == 0)
4304                         kfree(pc);
4305                 cpuc->shared_regs = NULL;
4306         }
4307
4308         free_excl_cntrs(cpuc);
4309 }
4310
4311 static void intel_pmu_cpu_dead(int cpu)
4312 {
4313         intel_cpuc_finish(&per_cpu(cpu_hw_events, cpu));
4314 }
4315
4316 static void intel_pmu_sched_task(struct perf_event_context *ctx,
4317                                  bool sched_in)
4318 {
4319         intel_pmu_pebs_sched_task(ctx, sched_in);
4320         intel_pmu_lbr_sched_task(ctx, sched_in);
4321 }
4322
4323 static void intel_pmu_swap_task_ctx(struct perf_event_context *prev,
4324                                     struct perf_event_context *next)
4325 {
4326         intel_pmu_lbr_swap_task_ctx(prev, next);
4327 }
4328
4329 static int intel_pmu_check_period(struct perf_event *event, u64 value)
4330 {
4331         return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
4332 }
4333
4334 static int intel_pmu_aux_output_match(struct perf_event *event)
4335 {
4336         if (!x86_pmu.intel_cap.pebs_output_pt_available)
4337                 return 0;
4338
4339         return is_intel_pt_event(event);
4340 }
4341
4342 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
4343
4344 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
4345
4346 PMU_FORMAT_ATTR(frontend, "config1:0-23");
4347
4348 static struct attribute *intel_arch3_formats_attr[] = {
4349         &format_attr_event.attr,
4350         &format_attr_umask.attr,
4351         &format_attr_edge.attr,
4352         &format_attr_pc.attr,
4353         &format_attr_any.attr,
4354         &format_attr_inv.attr,
4355         &format_attr_cmask.attr,
4356         NULL,
4357 };
4358
4359 static struct attribute *hsw_format_attr[] = {
4360         &format_attr_in_tx.attr,
4361         &format_attr_in_tx_cp.attr,
4362         &format_attr_offcore_rsp.attr,
4363         &format_attr_ldlat.attr,
4364         NULL
4365 };
4366
4367 static struct attribute *nhm_format_attr[] = {
4368         &format_attr_offcore_rsp.attr,
4369         &format_attr_ldlat.attr,
4370         NULL
4371 };
4372
4373 static struct attribute *slm_format_attr[] = {
4374         &format_attr_offcore_rsp.attr,
4375         NULL
4376 };
4377
4378 static struct attribute *skl_format_attr[] = {
4379         &format_attr_frontend.attr,
4380         NULL,
4381 };
4382
4383 static __initconst const struct x86_pmu core_pmu = {
4384         .name                   = "core",
4385         .handle_irq             = x86_pmu_handle_irq,
4386         .disable_all            = x86_pmu_disable_all,
4387         .enable_all             = core_pmu_enable_all,
4388         .enable                 = core_pmu_enable_event,
4389         .disable                = x86_pmu_disable_event,
4390         .hw_config              = core_pmu_hw_config,
4391         .schedule_events        = x86_schedule_events,
4392         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
4393         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
4394         .event_map              = intel_pmu_event_map,
4395         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
4396         .apic                   = 1,
4397         .large_pebs_flags       = LARGE_PEBS_FLAGS,
4398
4399         /*
4400          * Intel PMCs cannot be accessed sanely above 32-bit width,
4401          * so we install an artificial 1<<31 period regardless of
4402          * the generic event period:
4403          */
4404         .max_period             = (1ULL<<31) - 1,
4405         .get_event_constraints  = intel_get_event_constraints,
4406         .put_event_constraints  = intel_put_event_constraints,
4407         .event_constraints      = intel_core_event_constraints,
4408         .guest_get_msrs         = core_guest_get_msrs,
4409         .format_attrs           = intel_arch_formats_attr,
4410         .events_sysfs_show      = intel_event_sysfs_show,
4411
4412         /*
4413          * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
4414          * together with PMU version 1 and thus be using core_pmu with
4415          * shared_regs. We need following callbacks here to allocate
4416          * it properly.
4417          */
4418         .cpu_prepare            = intel_pmu_cpu_prepare,
4419         .cpu_starting           = intel_pmu_cpu_starting,
4420         .cpu_dying              = intel_pmu_cpu_dying,
4421         .cpu_dead               = intel_pmu_cpu_dead,
4422
4423         .check_period           = intel_pmu_check_period,
4424
4425         .lbr_reset              = intel_pmu_lbr_reset_64,
4426         .lbr_read               = intel_pmu_lbr_read_64,
4427         .lbr_save               = intel_pmu_lbr_save,
4428         .lbr_restore            = intel_pmu_lbr_restore,
4429 };
4430
4431 static __initconst const struct x86_pmu intel_pmu = {
4432         .name                   = "Intel",
4433         .handle_irq             = intel_pmu_handle_irq,
4434         .disable_all            = intel_pmu_disable_all,
4435         .enable_all             = intel_pmu_enable_all,
4436         .enable                 = intel_pmu_enable_event,
4437         .disable                = intel_pmu_disable_event,
4438         .add                    = intel_pmu_add_event,
4439         .del                    = intel_pmu_del_event,
4440         .read                   = intel_pmu_read_event,
4441         .hw_config              = intel_pmu_hw_config,
4442         .schedule_events        = x86_schedule_events,
4443         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
4444         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
4445         .event_map              = intel_pmu_event_map,
4446         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
4447         .apic                   = 1,
4448         .large_pebs_flags       = LARGE_PEBS_FLAGS,
4449         /*
4450          * Intel PMCs cannot be accessed sanely above 32 bit width,
4451          * so we install an artificial 1<<31 period regardless of
4452          * the generic event period:
4453          */
4454         .max_period             = (1ULL << 31) - 1,
4455         .get_event_constraints  = intel_get_event_constraints,
4456         .put_event_constraints  = intel_put_event_constraints,
4457         .pebs_aliases           = intel_pebs_aliases_core2,
4458
4459         .format_attrs           = intel_arch3_formats_attr,
4460         .events_sysfs_show      = intel_event_sysfs_show,
4461
4462         .cpu_prepare            = intel_pmu_cpu_prepare,
4463         .cpu_starting           = intel_pmu_cpu_starting,
4464         .cpu_dying              = intel_pmu_cpu_dying,
4465         .cpu_dead               = intel_pmu_cpu_dead,
4466
4467         .guest_get_msrs         = intel_guest_get_msrs,
4468         .sched_task             = intel_pmu_sched_task,
4469         .swap_task_ctx          = intel_pmu_swap_task_ctx,
4470
4471         .check_period           = intel_pmu_check_period,
4472
4473         .aux_output_match       = intel_pmu_aux_output_match,
4474
4475         .lbr_reset              = intel_pmu_lbr_reset_64,
4476         .lbr_read               = intel_pmu_lbr_read_64,
4477         .lbr_save               = intel_pmu_lbr_save,
4478         .lbr_restore            = intel_pmu_lbr_restore,
4479 };
4480
4481 static __init void intel_clovertown_quirk(void)
4482 {
4483         /*
4484          * PEBS is unreliable due to:
4485          *
4486          *   AJ67  - PEBS may experience CPL leaks
4487          *   AJ68  - PEBS PMI may be delayed by one event
4488          *   AJ69  - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
4489          *   AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
4490          *
4491          * AJ67 could be worked around by restricting the OS/USR flags.
4492          * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
4493          *
4494          * AJ106 could possibly be worked around by not allowing LBR
4495          *       usage from PEBS, including the fixup.
4496          * AJ68  could possibly be worked around by always programming
4497          *       a pebs_event_reset[0] value and coping with the lost events.
4498          *
4499          * But taken together it might just make sense to not enable PEBS on
4500          * these chips.
4501          */
4502         pr_warn("PEBS disabled due to CPU errata\n");
4503         x86_pmu.pebs = 0;
4504         x86_pmu.pebs_constraints = NULL;
4505 }
4506
4507 static const struct x86_cpu_desc isolation_ucodes[] = {
4508         INTEL_CPU_DESC(INTEL_FAM6_HASWELL,               3, 0x0000001f),
4509         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L,             1, 0x0000001e),
4510         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G,             1, 0x00000015),
4511         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X,             2, 0x00000037),
4512         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X,             4, 0x0000000a),
4513         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL,             4, 0x00000023),
4514         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G,           1, 0x00000014),
4515         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,           2, 0x00000010),
4516         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,           3, 0x07000009),
4517         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,           4, 0x0f000009),
4518         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,           5, 0x0e000002),
4519         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X,           1, 0x0b000014),
4520         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             3, 0x00000021),
4521         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             4, 0x00000000),
4522         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             5, 0x00000000),
4523         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             6, 0x00000000),
4524         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             7, 0x00000000),
4525         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L,             3, 0x0000007c),
4526         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE,               3, 0x0000007c),
4527         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,              9, 0x0000004e),
4528         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,            9, 0x0000004e),
4529         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,           10, 0x0000004e),
4530         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,           11, 0x0000004e),
4531         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,           12, 0x0000004e),
4532         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,             10, 0x0000004e),
4533         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,             11, 0x0000004e),
4534         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,             12, 0x0000004e),
4535         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,             13, 0x0000004e),
4536         {}
4537 };
4538
4539 static void intel_check_pebs_isolation(void)
4540 {
4541         x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes);
4542 }
4543
4544 static __init void intel_pebs_isolation_quirk(void)
4545 {
4546         WARN_ON_ONCE(x86_pmu.check_microcode);
4547         x86_pmu.check_microcode = intel_check_pebs_isolation;
4548         intel_check_pebs_isolation();
4549 }
4550
4551 static const struct x86_cpu_desc pebs_ucodes[] = {
4552         INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE,          7, 0x00000028),
4553         INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X,        6, 0x00000618),
4554         INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X,        7, 0x0000070c),
4555         {}
4556 };
4557
4558 static bool intel_snb_pebs_broken(void)
4559 {
4560         return !x86_cpu_has_min_microcode_rev(pebs_ucodes);
4561 }
4562
4563 static void intel_snb_check_microcode(void)
4564 {
4565         if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
4566                 return;
4567
4568         /*
4569          * Serialized by the microcode lock..
4570          */
4571         if (x86_pmu.pebs_broken) {
4572                 pr_info("PEBS enabled due to microcode update\n");
4573                 x86_pmu.pebs_broken = 0;
4574         } else {
4575                 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
4576                 x86_pmu.pebs_broken = 1;
4577         }
4578 }
4579
4580 static bool is_lbr_from(unsigned long msr)
4581 {
4582         unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
4583
4584         return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
4585 }
4586
4587 /*
4588  * Under certain circumstances, access certain MSR may cause #GP.
4589  * The function tests if the input MSR can be safely accessed.
4590  */
4591 static bool check_msr(unsigned long msr, u64 mask)
4592 {
4593         u64 val_old, val_new, val_tmp;
4594
4595         /*
4596          * Disable the check for real HW, so we don't
4597          * mess with potentially enabled registers:
4598          */
4599         if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
4600                 return true;
4601
4602         /*
4603          * Read the current value, change it and read it back to see if it
4604          * matches, this is needed to detect certain hardware emulators
4605          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
4606          */
4607         if (rdmsrl_safe(msr, &val_old))
4608                 return false;
4609
4610         /*
4611          * Only change the bits which can be updated by wrmsrl.
4612          */
4613         val_tmp = val_old ^ mask;
4614
4615         if (is_lbr_from(msr))
4616                 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
4617
4618         if (wrmsrl_safe(msr, val_tmp) ||
4619             rdmsrl_safe(msr, &val_new))
4620                 return false;
4621
4622         /*
4623          * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
4624          * should equal rdmsrl()'s even with the quirk.
4625          */
4626         if (val_new != val_tmp)
4627                 return false;
4628
4629         if (is_lbr_from(msr))
4630                 val_old = lbr_from_signext_quirk_wr(val_old);
4631
4632         /* Here it's sure that the MSR can be safely accessed.
4633          * Restore the old value and return.
4634          */
4635         wrmsrl(msr, val_old);
4636
4637         return true;
4638 }
4639
4640 static __init void intel_sandybridge_quirk(void)
4641 {
4642         x86_pmu.check_microcode = intel_snb_check_microcode;
4643         cpus_read_lock();
4644         intel_snb_check_microcode();
4645         cpus_read_unlock();
4646 }
4647
4648 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
4649         { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
4650         { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
4651         { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
4652         { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
4653         { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
4654         { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
4655         { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
4656 };
4657
4658 static __init void intel_arch_events_quirk(void)
4659 {
4660         int bit;
4661
4662         /* disable event that reported as not present by cpuid */
4663         for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
4664                 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
4665                 pr_warn("CPUID marked event: \'%s\' unavailable\n",
4666                         intel_arch_events_map[bit].name);
4667         }
4668 }
4669
4670 static __init void intel_nehalem_quirk(void)
4671 {
4672         union cpuid10_ebx ebx;
4673
4674         ebx.full = x86_pmu.events_maskl;
4675         if (ebx.split.no_branch_misses_retired) {
4676                 /*
4677                  * Erratum AAJ80 detected, we work it around by using
4678                  * the BR_MISP_EXEC.ANY event. This will over-count
4679                  * branch-misses, but it's still much better than the
4680                  * architectural event which is often completely bogus:
4681                  */
4682                 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
4683                 ebx.split.no_branch_misses_retired = 0;
4684                 x86_pmu.events_maskl = ebx.full;
4685                 pr_info("CPU erratum AAJ80 worked around\n");
4686         }
4687 }
4688
4689 /*
4690  * enable software workaround for errata:
4691  * SNB: BJ122
4692  * IVB: BV98
4693  * HSW: HSD29
4694  *
4695  * Only needed when HT is enabled. However detecting
4696  * if HT is enabled is difficult (model specific). So instead,
4697  * we enable the workaround in the early boot, and verify if
4698  * it is needed in a later initcall phase once we have valid
4699  * topology information to check if HT is actually enabled
4700  */
4701 static __init void intel_ht_bug(void)
4702 {
4703         x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
4704
4705         x86_pmu.start_scheduling = intel_start_scheduling;
4706         x86_pmu.commit_scheduling = intel_commit_scheduling;
4707         x86_pmu.stop_scheduling = intel_stop_scheduling;
4708 }
4709
4710 EVENT_ATTR_STR(mem-loads,       mem_ld_hsw,     "event=0xcd,umask=0x1,ldlat=3");
4711 EVENT_ATTR_STR(mem-stores,      mem_st_hsw,     "event=0xd0,umask=0x82")
4712
4713 /* Haswell special events */
4714 EVENT_ATTR_STR(tx-start,        tx_start,       "event=0xc9,umask=0x1");
4715 EVENT_ATTR_STR(tx-commit,       tx_commit,      "event=0xc9,umask=0x2");
4716 EVENT_ATTR_STR(tx-abort,        tx_abort,       "event=0xc9,umask=0x4");
4717 EVENT_ATTR_STR(tx-capacity,     tx_capacity,    "event=0x54,umask=0x2");
4718 EVENT_ATTR_STR(tx-conflict,     tx_conflict,    "event=0x54,umask=0x1");
4719 EVENT_ATTR_STR(el-start,        el_start,       "event=0xc8,umask=0x1");
4720 EVENT_ATTR_STR(el-commit,       el_commit,      "event=0xc8,umask=0x2");
4721 EVENT_ATTR_STR(el-abort,        el_abort,       "event=0xc8,umask=0x4");
4722 EVENT_ATTR_STR(el-capacity,     el_capacity,    "event=0x54,umask=0x2");
4723 EVENT_ATTR_STR(el-conflict,     el_conflict,    "event=0x54,umask=0x1");
4724 EVENT_ATTR_STR(cycles-t,        cycles_t,       "event=0x3c,in_tx=1");
4725 EVENT_ATTR_STR(cycles-ct,       cycles_ct,      "event=0x3c,in_tx=1,in_tx_cp=1");
4726
4727 static struct attribute *hsw_events_attrs[] = {
4728         EVENT_PTR(td_slots_issued),
4729         EVENT_PTR(td_slots_retired),
4730         EVENT_PTR(td_fetch_bubbles),
4731         EVENT_PTR(td_total_slots),
4732         EVENT_PTR(td_total_slots_scale),
4733         EVENT_PTR(td_recovery_bubbles),
4734         EVENT_PTR(td_recovery_bubbles_scale),
4735         NULL
4736 };
4737
4738 static struct attribute *hsw_mem_events_attrs[] = {
4739         EVENT_PTR(mem_ld_hsw),
4740         EVENT_PTR(mem_st_hsw),
4741         NULL,
4742 };
4743
4744 static struct attribute *hsw_tsx_events_attrs[] = {
4745         EVENT_PTR(tx_start),
4746         EVENT_PTR(tx_commit),
4747         EVENT_PTR(tx_abort),
4748         EVENT_PTR(tx_capacity),
4749         EVENT_PTR(tx_conflict),
4750         EVENT_PTR(el_start),
4751         EVENT_PTR(el_commit),
4752         EVENT_PTR(el_abort),
4753         EVENT_PTR(el_capacity),
4754         EVENT_PTR(el_conflict),
4755         EVENT_PTR(cycles_t),
4756         EVENT_PTR(cycles_ct),
4757         NULL
4758 };
4759
4760 EVENT_ATTR_STR(tx-capacity-read,  tx_capacity_read,  "event=0x54,umask=0x80");
4761 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
4762 EVENT_ATTR_STR(el-capacity-read,  el_capacity_read,  "event=0x54,umask=0x80");
4763 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
4764
4765 static struct attribute *icl_events_attrs[] = {
4766         EVENT_PTR(mem_ld_hsw),
4767         EVENT_PTR(mem_st_hsw),
4768         NULL,
4769 };
4770
4771 static struct attribute *icl_td_events_attrs[] = {
4772         EVENT_PTR(slots),
4773         EVENT_PTR(td_retiring),
4774         EVENT_PTR(td_bad_spec),
4775         EVENT_PTR(td_fe_bound),
4776         EVENT_PTR(td_be_bound),
4777         NULL,
4778 };
4779
4780 static struct attribute *icl_tsx_events_attrs[] = {
4781         EVENT_PTR(tx_start),
4782         EVENT_PTR(tx_abort),
4783         EVENT_PTR(tx_commit),
4784         EVENT_PTR(tx_capacity_read),
4785         EVENT_PTR(tx_capacity_write),
4786         EVENT_PTR(tx_conflict),
4787         EVENT_PTR(el_start),
4788         EVENT_PTR(el_abort),
4789         EVENT_PTR(el_commit),
4790         EVENT_PTR(el_capacity_read),
4791         EVENT_PTR(el_capacity_write),
4792         EVENT_PTR(el_conflict),
4793         EVENT_PTR(cycles_t),
4794         EVENT_PTR(cycles_ct),
4795         NULL,
4796 };
4797
4798
4799 EVENT_ATTR_STR(mem-stores,      mem_st_spr,     "event=0xcd,umask=0x2");
4800 EVENT_ATTR_STR(mem-loads-aux,   mem_ld_aux,     "event=0x03,umask=0x82");
4801
4802 static struct attribute *spr_events_attrs[] = {
4803         EVENT_PTR(mem_ld_hsw),
4804         EVENT_PTR(mem_st_spr),
4805         EVENT_PTR(mem_ld_aux),
4806         NULL,
4807 };
4808
4809 static struct attribute *spr_td_events_attrs[] = {
4810         EVENT_PTR(slots),
4811         EVENT_PTR(td_retiring),
4812         EVENT_PTR(td_bad_spec),
4813         EVENT_PTR(td_fe_bound),
4814         EVENT_PTR(td_be_bound),
4815         EVENT_PTR(td_heavy_ops),
4816         EVENT_PTR(td_br_mispredict),
4817         EVENT_PTR(td_fetch_lat),
4818         EVENT_PTR(td_mem_bound),
4819         NULL,
4820 };
4821
4822 static struct attribute *spr_tsx_events_attrs[] = {
4823         EVENT_PTR(tx_start),
4824         EVENT_PTR(tx_abort),
4825         EVENT_PTR(tx_commit),
4826         EVENT_PTR(tx_capacity_read),
4827         EVENT_PTR(tx_capacity_write),
4828         EVENT_PTR(tx_conflict),
4829         EVENT_PTR(cycles_t),
4830         EVENT_PTR(cycles_ct),
4831         NULL,
4832 };
4833
4834 static ssize_t freeze_on_smi_show(struct device *cdev,
4835                                   struct device_attribute *attr,
4836                                   char *buf)
4837 {
4838         return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
4839 }
4840
4841 static DEFINE_MUTEX(freeze_on_smi_mutex);
4842
4843 static ssize_t freeze_on_smi_store(struct device *cdev,
4844                                    struct device_attribute *attr,
4845                                    const char *buf, size_t count)
4846 {
4847         unsigned long val;
4848         ssize_t ret;
4849
4850         ret = kstrtoul(buf, 0, &val);
4851         if (ret)
4852                 return ret;
4853
4854         if (val > 1)
4855                 return -EINVAL;
4856
4857         mutex_lock(&freeze_on_smi_mutex);
4858
4859         if (x86_pmu.attr_freeze_on_smi == val)
4860                 goto done;
4861
4862         x86_pmu.attr_freeze_on_smi = val;
4863
4864         get_online_cpus();
4865         on_each_cpu(flip_smm_bit, &val, 1);
4866         put_online_cpus();
4867 done:
4868         mutex_unlock(&freeze_on_smi_mutex);
4869
4870         return count;
4871 }
4872
4873 static void update_tfa_sched(void *ignored)
4874 {
4875         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4876
4877         /*
4878          * check if PMC3 is used
4879          * and if so force schedule out for all event types all contexts
4880          */
4881         if (test_bit(3, cpuc->active_mask))
4882                 perf_pmu_resched(x86_get_pmu());
4883 }
4884
4885 static ssize_t show_sysctl_tfa(struct device *cdev,
4886                               struct device_attribute *attr,
4887                               char *buf)
4888 {
4889         return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
4890 }
4891
4892 static ssize_t set_sysctl_tfa(struct device *cdev,
4893                               struct device_attribute *attr,
4894                               const char *buf, size_t count)
4895 {
4896         bool val;
4897         ssize_t ret;
4898
4899         ret = kstrtobool(buf, &val);
4900         if (ret)
4901                 return ret;
4902
4903         /* no change */
4904         if (val == allow_tsx_force_abort)
4905                 return count;
4906
4907         allow_tsx_force_abort = val;
4908
4909         get_online_cpus();
4910         on_each_cpu(update_tfa_sched, NULL, 1);
4911         put_online_cpus();
4912
4913         return count;
4914 }
4915
4916
4917 static DEVICE_ATTR_RW(freeze_on_smi);
4918
4919 static ssize_t branches_show(struct device *cdev,
4920                              struct device_attribute *attr,
4921                              char *buf)
4922 {
4923         return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
4924 }
4925
4926 static DEVICE_ATTR_RO(branches);
4927
4928 static struct attribute *lbr_attrs[] = {
4929         &dev_attr_branches.attr,
4930         NULL
4931 };
4932
4933 static char pmu_name_str[30];
4934
4935 static ssize_t pmu_name_show(struct device *cdev,
4936                              struct device_attribute *attr,
4937                              char *buf)
4938 {
4939         return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str);
4940 }
4941
4942 static DEVICE_ATTR_RO(pmu_name);
4943
4944 static struct attribute *intel_pmu_caps_attrs[] = {
4945        &dev_attr_pmu_name.attr,
4946        NULL
4947 };
4948
4949 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
4950                    show_sysctl_tfa,
4951                    set_sysctl_tfa);
4952
4953 static struct attribute *intel_pmu_attrs[] = {
4954         &dev_attr_freeze_on_smi.attr,
4955         &dev_attr_allow_tsx_force_abort.attr,
4956         NULL,
4957 };
4958
4959 static umode_t
4960 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4961 {
4962         return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
4963 }
4964
4965 static umode_t
4966 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4967 {
4968         return x86_pmu.pebs ? attr->mode : 0;
4969 }
4970
4971 static umode_t
4972 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4973 {
4974         return x86_pmu.lbr_nr ? attr->mode : 0;
4975 }
4976
4977 static umode_t
4978 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4979 {
4980         return x86_pmu.version >= 2 ? attr->mode : 0;
4981 }
4982
4983 static umode_t
4984 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4985 {
4986         if (attr == &dev_attr_allow_tsx_force_abort.attr)
4987                 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
4988
4989         return attr->mode;
4990 }
4991
4992 static struct attribute_group group_events_td  = {
4993         .name = "events",
4994 };
4995
4996 static struct attribute_group group_events_mem = {
4997         .name       = "events",
4998         .is_visible = pebs_is_visible,
4999 };
5000
5001 static struct attribute_group group_events_tsx = {
5002         .name       = "events",
5003         .is_visible = tsx_is_visible,
5004 };
5005
5006 static struct attribute_group group_caps_gen = {
5007         .name  = "caps",
5008         .attrs = intel_pmu_caps_attrs,
5009 };
5010
5011 static struct attribute_group group_caps_lbr = {
5012         .name       = "caps",
5013         .attrs      = lbr_attrs,
5014         .is_visible = lbr_is_visible,
5015 };
5016
5017 static struct attribute_group group_format_extra = {
5018         .name       = "format",
5019         .is_visible = exra_is_visible,
5020 };
5021
5022 static struct attribute_group group_format_extra_skl = {
5023         .name       = "format",
5024         .is_visible = exra_is_visible,
5025 };
5026
5027 static struct attribute_group group_default = {
5028         .attrs      = intel_pmu_attrs,
5029         .is_visible = default_is_visible,
5030 };
5031
5032 static const struct attribute_group *attr_update[] = {
5033         &group_events_td,
5034         &group_events_mem,
5035         &group_events_tsx,
5036         &group_caps_gen,
5037         &group_caps_lbr,
5038         &group_format_extra,
5039         &group_format_extra_skl,
5040         &group_default,
5041         NULL,
5042 };
5043
5044 static struct attribute *empty_attrs;
5045
5046 __init int intel_pmu_init(void)
5047 {
5048         struct attribute **extra_skl_attr = &empty_attrs;
5049         struct attribute **extra_attr = &empty_attrs;
5050         struct attribute **td_attr    = &empty_attrs;
5051         struct attribute **mem_attr   = &empty_attrs;
5052         struct attribute **tsx_attr   = &empty_attrs;
5053         union cpuid10_edx edx;
5054         union cpuid10_eax eax;
5055         union cpuid10_ebx ebx;
5056         struct event_constraint *c;
5057         unsigned int fixed_mask;
5058         struct extra_reg *er;
5059         bool pmem = false;
5060         int version, i;
5061         char *name;
5062
5063         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
5064                 switch (boot_cpu_data.x86) {
5065                 case 0x6:
5066                         return p6_pmu_init();
5067                 case 0xb:
5068                         return knc_pmu_init();
5069                 case 0xf:
5070                         return p4_pmu_init();
5071                 }
5072                 return -ENODEV;
5073         }
5074
5075         /*
5076          * Check whether the Architectural PerfMon supports
5077          * Branch Misses Retired hw_event or not.
5078          */
5079         cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
5080         if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
5081                 return -ENODEV;
5082
5083         version = eax.split.version_id;
5084         if (version < 2)
5085                 x86_pmu = core_pmu;
5086         else
5087                 x86_pmu = intel_pmu;
5088
5089         x86_pmu.version                 = version;
5090         x86_pmu.num_counters            = eax.split.num_counters;
5091         x86_pmu.cntval_bits             = eax.split.bit_width;
5092         x86_pmu.cntval_mask             = (1ULL << eax.split.bit_width) - 1;
5093
5094         x86_pmu.events_maskl            = ebx.full;
5095         x86_pmu.events_mask_len         = eax.split.mask_length;
5096
5097         x86_pmu.max_pebs_events         = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
5098
5099         /*
5100          * Quirk: v2 perfmon does not report fixed-purpose events, so
5101          * assume at least 3 events, when not running in a hypervisor:
5102          */
5103         if (version > 1 && version < 5) {
5104                 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
5105
5106                 x86_pmu.num_counters_fixed =
5107                         max((int)edx.split.num_counters_fixed, assume);
5108
5109                 fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1;
5110         } else if (version >= 5)
5111                 x86_pmu.num_counters_fixed = fls(fixed_mask);
5112
5113         if (boot_cpu_has(X86_FEATURE_PDCM)) {
5114                 u64 capabilities;
5115
5116                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
5117                 x86_pmu.intel_cap.capabilities = capabilities;
5118         }
5119
5120         if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
5121                 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
5122                 x86_pmu.lbr_read = intel_pmu_lbr_read_32;
5123         }
5124
5125         if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
5126                 intel_pmu_arch_lbr_init();
5127
5128         intel_ds_init();
5129
5130         x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
5131
5132         if (version >= 5) {
5133                 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated;
5134                 if (x86_pmu.intel_cap.anythread_deprecated)
5135                         pr_cont(" AnyThread deprecated, ");
5136         }
5137
5138         /*
5139          * Install the hw-cache-events table:
5140          */
5141         switch (boot_cpu_data.x86_model) {
5142         case INTEL_FAM6_CORE_YONAH:
5143                 pr_cont("Core events, ");
5144                 name = "core";
5145                 break;
5146
5147         case INTEL_FAM6_CORE2_MEROM:
5148                 x86_add_quirk(intel_clovertown_quirk);
5149                 fallthrough;
5150
5151         case INTEL_FAM6_CORE2_MEROM_L:
5152         case INTEL_FAM6_CORE2_PENRYN:
5153         case INTEL_FAM6_CORE2_DUNNINGTON:
5154                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
5155                        sizeof(hw_cache_event_ids));
5156
5157                 intel_pmu_lbr_init_core();
5158
5159                 x86_pmu.event_constraints = intel_core2_event_constraints;
5160                 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
5161                 pr_cont("Core2 events, ");
5162                 name = "core2";
5163                 break;
5164
5165         case INTEL_FAM6_NEHALEM:
5166         case INTEL_FAM6_NEHALEM_EP:
5167         case INTEL_FAM6_NEHALEM_EX:
5168                 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
5169                        sizeof(hw_cache_event_ids));
5170                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
5171                        sizeof(hw_cache_extra_regs));
5172
5173                 intel_pmu_lbr_init_nhm();
5174
5175                 x86_pmu.event_constraints = intel_nehalem_event_constraints;
5176                 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
5177                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
5178                 x86_pmu.extra_regs = intel_nehalem_extra_regs;
5179                 x86_pmu.limit_period = nhm_limit_period;
5180
5181                 mem_attr = nhm_mem_events_attrs;
5182
5183                 /* UOPS_ISSUED.STALLED_CYCLES */
5184                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5185                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5186                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
5187                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5188                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
5189
5190                 intel_pmu_pebs_data_source_nhm();
5191                 x86_add_quirk(intel_nehalem_quirk);
5192                 x86_pmu.pebs_no_tlb = 1;
5193                 extra_attr = nhm_format_attr;
5194
5195                 pr_cont("Nehalem events, ");
5196                 name = "nehalem";
5197                 break;
5198
5199         case INTEL_FAM6_ATOM_BONNELL:
5200         case INTEL_FAM6_ATOM_BONNELL_MID:
5201         case INTEL_FAM6_ATOM_SALTWELL:
5202         case INTEL_FAM6_ATOM_SALTWELL_MID:
5203         case INTEL_FAM6_ATOM_SALTWELL_TABLET:
5204                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
5205                        sizeof(hw_cache_event_ids));
5206
5207                 intel_pmu_lbr_init_atom();
5208
5209                 x86_pmu.event_constraints = intel_gen_event_constraints;
5210                 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
5211                 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
5212                 pr_cont("Atom events, ");
5213                 name = "bonnell";
5214                 break;
5215
5216         case INTEL_FAM6_ATOM_SILVERMONT:
5217         case INTEL_FAM6_ATOM_SILVERMONT_D:
5218         case INTEL_FAM6_ATOM_SILVERMONT_MID:
5219         case INTEL_FAM6_ATOM_AIRMONT:
5220         case INTEL_FAM6_ATOM_AIRMONT_MID:
5221                 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
5222                         sizeof(hw_cache_event_ids));
5223                 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
5224                        sizeof(hw_cache_extra_regs));
5225
5226                 intel_pmu_lbr_init_slm();
5227
5228                 x86_pmu.event_constraints = intel_slm_event_constraints;
5229                 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
5230                 x86_pmu.extra_regs = intel_slm_extra_regs;
5231                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5232                 td_attr = slm_events_attrs;
5233                 extra_attr = slm_format_attr;
5234                 pr_cont("Silvermont events, ");
5235                 name = "silvermont";
5236                 break;
5237
5238         case INTEL_FAM6_ATOM_GOLDMONT:
5239         case INTEL_FAM6_ATOM_GOLDMONT_D:
5240                 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
5241                        sizeof(hw_cache_event_ids));
5242                 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
5243                        sizeof(hw_cache_extra_regs));
5244
5245                 intel_pmu_lbr_init_skl();
5246
5247                 x86_pmu.event_constraints = intel_slm_event_constraints;
5248                 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
5249                 x86_pmu.extra_regs = intel_glm_extra_regs;
5250                 /*
5251                  * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5252                  * for precise cycles.
5253                  * :pp is identical to :ppp
5254                  */
5255                 x86_pmu.pebs_aliases = NULL;
5256                 x86_pmu.pebs_prec_dist = true;
5257                 x86_pmu.lbr_pt_coexist = true;
5258                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5259                 td_attr = glm_events_attrs;
5260                 extra_attr = slm_format_attr;
5261                 pr_cont("Goldmont events, ");
5262                 name = "goldmont";
5263                 break;
5264
5265         case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5266                 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5267                        sizeof(hw_cache_event_ids));
5268                 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
5269                        sizeof(hw_cache_extra_regs));
5270
5271                 intel_pmu_lbr_init_skl();
5272
5273                 x86_pmu.event_constraints = intel_slm_event_constraints;
5274                 x86_pmu.extra_regs = intel_glm_extra_regs;
5275                 /*
5276                  * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5277                  * for precise cycles.
5278                  */
5279                 x86_pmu.pebs_aliases = NULL;
5280                 x86_pmu.pebs_prec_dist = true;
5281                 x86_pmu.lbr_pt_coexist = true;
5282                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5283                 x86_pmu.flags |= PMU_FL_PEBS_ALL;
5284                 x86_pmu.get_event_constraints = glp_get_event_constraints;
5285                 td_attr = glm_events_attrs;
5286                 /* Goldmont Plus has 4-wide pipeline */
5287                 event_attr_td_total_slots_scale_glm.event_str = "4";
5288                 extra_attr = slm_format_attr;
5289                 pr_cont("Goldmont plus events, ");
5290                 name = "goldmont_plus";
5291                 break;
5292
5293         case INTEL_FAM6_ATOM_TREMONT_D:
5294         case INTEL_FAM6_ATOM_TREMONT:
5295         case INTEL_FAM6_ATOM_TREMONT_L:
5296                 x86_pmu.late_ack = true;
5297                 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5298                        sizeof(hw_cache_event_ids));
5299                 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
5300                        sizeof(hw_cache_extra_regs));
5301                 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
5302
5303                 intel_pmu_lbr_init_skl();
5304
5305                 x86_pmu.event_constraints = intel_slm_event_constraints;
5306                 x86_pmu.extra_regs = intel_tnt_extra_regs;
5307                 /*
5308                  * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5309                  * for precise cycles.
5310                  */
5311                 x86_pmu.pebs_aliases = NULL;
5312                 x86_pmu.pebs_prec_dist = true;
5313                 x86_pmu.lbr_pt_coexist = true;
5314                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5315                 x86_pmu.get_event_constraints = tnt_get_event_constraints;
5316                 td_attr = tnt_events_attrs;
5317                 extra_attr = slm_format_attr;
5318                 pr_cont("Tremont events, ");
5319                 name = "Tremont";
5320                 break;
5321
5322         case INTEL_FAM6_WESTMERE:
5323         case INTEL_FAM6_WESTMERE_EP:
5324         case INTEL_FAM6_WESTMERE_EX:
5325                 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
5326                        sizeof(hw_cache_event_ids));
5327                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
5328                        sizeof(hw_cache_extra_regs));
5329
5330                 intel_pmu_lbr_init_nhm();
5331
5332                 x86_pmu.event_constraints = intel_westmere_event_constraints;
5333                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
5334                 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
5335                 x86_pmu.extra_regs = intel_westmere_extra_regs;
5336                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5337
5338                 mem_attr = nhm_mem_events_attrs;
5339
5340                 /* UOPS_ISSUED.STALLED_CYCLES */
5341                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5342                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5343                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
5344                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5345                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
5346
5347                 intel_pmu_pebs_data_source_nhm();
5348                 extra_attr = nhm_format_attr;
5349                 pr_cont("Westmere events, ");
5350                 name = "westmere";
5351                 break;
5352
5353         case INTEL_FAM6_SANDYBRIDGE:
5354         case INTEL_FAM6_SANDYBRIDGE_X:
5355                 x86_add_quirk(intel_sandybridge_quirk);
5356                 x86_add_quirk(intel_ht_bug);
5357                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
5358                        sizeof(hw_cache_event_ids));
5359                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
5360                        sizeof(hw_cache_extra_regs));
5361
5362                 intel_pmu_lbr_init_snb();
5363
5364                 x86_pmu.event_constraints = intel_snb_event_constraints;
5365                 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
5366                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
5367                 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
5368                         x86_pmu.extra_regs = intel_snbep_extra_regs;
5369                 else
5370                         x86_pmu.extra_regs = intel_snb_extra_regs;
5371
5372
5373                 /* all extra regs are per-cpu when HT is on */
5374                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5375                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5376
5377                 td_attr  = snb_events_attrs;
5378                 mem_attr = snb_mem_events_attrs;
5379
5380                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
5381                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5382                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5383                 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
5384                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5385                         X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
5386
5387                 extra_attr = nhm_format_attr;
5388
5389                 pr_cont("SandyBridge events, ");
5390                 name = "sandybridge";
5391                 break;
5392
5393         case INTEL_FAM6_IVYBRIDGE:
5394         case INTEL_FAM6_IVYBRIDGE_X:
5395                 x86_add_quirk(intel_ht_bug);
5396                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
5397                        sizeof(hw_cache_event_ids));
5398                 /* dTLB-load-misses on IVB is different than SNB */
5399                 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
5400
5401                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
5402                        sizeof(hw_cache_extra_regs));
5403
5404                 intel_pmu_lbr_init_snb();
5405
5406                 x86_pmu.event_constraints = intel_ivb_event_constraints;
5407                 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
5408                 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5409                 x86_pmu.pebs_prec_dist = true;
5410                 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
5411                         x86_pmu.extra_regs = intel_snbep_extra_regs;
5412                 else
5413                         x86_pmu.extra_regs = intel_snb_extra_regs;
5414                 /* all extra regs are per-cpu when HT is on */
5415                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5416                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5417
5418                 td_attr  = snb_events_attrs;
5419                 mem_attr = snb_mem_events_attrs;
5420
5421                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
5422                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5423                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5424
5425                 extra_attr = nhm_format_attr;
5426
5427                 pr_cont("IvyBridge events, ");
5428                 name = "ivybridge";
5429                 break;
5430
5431
5432         case INTEL_FAM6_HASWELL:
5433         case INTEL_FAM6_HASWELL_X:
5434         case INTEL_FAM6_HASWELL_L:
5435         case INTEL_FAM6_HASWELL_G:
5436                 x86_add_quirk(intel_ht_bug);
5437                 x86_add_quirk(intel_pebs_isolation_quirk);
5438                 x86_pmu.late_ack = true;
5439                 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5440                 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5441
5442                 intel_pmu_lbr_init_hsw();
5443
5444                 x86_pmu.event_constraints = intel_hsw_event_constraints;
5445                 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
5446                 x86_pmu.extra_regs = intel_snbep_extra_regs;
5447                 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5448                 x86_pmu.pebs_prec_dist = true;
5449                 /* all extra regs are per-cpu when HT is on */
5450                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5451                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5452
5453                 x86_pmu.hw_config = hsw_hw_config;
5454                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5455                 x86_pmu.lbr_double_abort = true;
5456                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5457                         hsw_format_attr : nhm_format_attr;
5458                 td_attr  = hsw_events_attrs;
5459                 mem_attr = hsw_mem_events_attrs;
5460                 tsx_attr = hsw_tsx_events_attrs;
5461                 pr_cont("Haswell events, ");
5462                 name = "haswell";
5463                 break;
5464
5465         case INTEL_FAM6_BROADWELL:
5466         case INTEL_FAM6_BROADWELL_D:
5467         case INTEL_FAM6_BROADWELL_G:
5468         case INTEL_FAM6_BROADWELL_X:
5469                 x86_add_quirk(intel_pebs_isolation_quirk);
5470                 x86_pmu.late_ack = true;
5471                 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5472                 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5473
5474                 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
5475                 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
5476                                                                          BDW_L3_MISS|HSW_SNOOP_DRAM;
5477                 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
5478                                                                           HSW_SNOOP_DRAM;
5479                 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
5480                                                                              BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
5481                 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
5482                                                                               BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
5483
5484                 intel_pmu_lbr_init_hsw();
5485
5486                 x86_pmu.event_constraints = intel_bdw_event_constraints;
5487                 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
5488                 x86_pmu.extra_regs = intel_snbep_extra_regs;
5489                 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5490                 x86_pmu.pebs_prec_dist = true;
5491                 /* all extra regs are per-cpu when HT is on */
5492                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5493                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5494
5495                 x86_pmu.hw_config = hsw_hw_config;
5496                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5497                 x86_pmu.limit_period = bdw_limit_period;
5498                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5499                         hsw_format_attr : nhm_format_attr;
5500                 td_attr  = hsw_events_attrs;
5501                 mem_attr = hsw_mem_events_attrs;
5502                 tsx_attr = hsw_tsx_events_attrs;
5503                 pr_cont("Broadwell events, ");
5504                 name = "broadwell";
5505                 break;
5506
5507         case INTEL_FAM6_XEON_PHI_KNL:
5508         case INTEL_FAM6_XEON_PHI_KNM:
5509                 memcpy(hw_cache_event_ids,
5510                        slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5511                 memcpy(hw_cache_extra_regs,
5512                        knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5513                 intel_pmu_lbr_init_knl();
5514
5515                 x86_pmu.event_constraints = intel_slm_event_constraints;
5516                 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
5517                 x86_pmu.extra_regs = intel_knl_extra_regs;
5518
5519                 /* all extra regs are per-cpu when HT is on */
5520                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5521                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5522                 extra_attr = slm_format_attr;
5523                 pr_cont("Knights Landing/Mill events, ");
5524                 name = "knights-landing";
5525                 break;
5526
5527         case INTEL_FAM6_SKYLAKE_X:
5528                 pmem = true;
5529                 fallthrough;
5530         case INTEL_FAM6_SKYLAKE_L:
5531         case INTEL_FAM6_SKYLAKE:
5532         case INTEL_FAM6_KABYLAKE_L:
5533         case INTEL_FAM6_KABYLAKE:
5534         case INTEL_FAM6_COMETLAKE_L:
5535         case INTEL_FAM6_COMETLAKE:
5536                 x86_add_quirk(intel_pebs_isolation_quirk);
5537                 x86_pmu.late_ack = true;
5538                 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5539                 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5540                 intel_pmu_lbr_init_skl();
5541
5542                 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
5543                 event_attr_td_recovery_bubbles.event_str_noht =
5544                         "event=0xd,umask=0x1,cmask=1";
5545                 event_attr_td_recovery_bubbles.event_str_ht =
5546                         "event=0xd,umask=0x1,cmask=1,any=1";
5547
5548                 x86_pmu.event_constraints = intel_skl_event_constraints;
5549                 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
5550                 x86_pmu.extra_regs = intel_skl_extra_regs;
5551                 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
5552                 x86_pmu.pebs_prec_dist = true;
5553                 /* all extra regs are per-cpu when HT is on */
5554                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5555                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5556
5557                 x86_pmu.hw_config = hsw_hw_config;
5558                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5559                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5560                         hsw_format_attr : nhm_format_attr;
5561                 extra_skl_attr = skl_format_attr;
5562                 td_attr  = hsw_events_attrs;
5563                 mem_attr = hsw_mem_events_attrs;
5564                 tsx_attr = hsw_tsx_events_attrs;
5565                 intel_pmu_pebs_data_source_skl(pmem);
5566
5567                 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
5568                         x86_pmu.flags |= PMU_FL_TFA;
5569                         x86_pmu.get_event_constraints = tfa_get_event_constraints;
5570                         x86_pmu.enable_all = intel_tfa_pmu_enable_all;
5571                         x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
5572                 }
5573
5574                 pr_cont("Skylake events, ");
5575                 name = "skylake";
5576                 break;
5577
5578         case INTEL_FAM6_ICELAKE_X:
5579         case INTEL_FAM6_ICELAKE_D:
5580                 pmem = true;
5581                 fallthrough;
5582         case INTEL_FAM6_ICELAKE_L:
5583         case INTEL_FAM6_ICELAKE:
5584         case INTEL_FAM6_TIGERLAKE_L:
5585         case INTEL_FAM6_TIGERLAKE:
5586         case INTEL_FAM6_ROCKETLAKE:
5587                 x86_pmu.late_ack = true;
5588                 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5589                 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5590                 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
5591                 intel_pmu_lbr_init_skl();
5592
5593                 x86_pmu.event_constraints = intel_icl_event_constraints;
5594                 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
5595                 x86_pmu.extra_regs = intel_icl_extra_regs;
5596                 x86_pmu.pebs_aliases = NULL;
5597                 x86_pmu.pebs_prec_dist = true;
5598                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5599                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5600
5601                 x86_pmu.hw_config = hsw_hw_config;
5602                 x86_pmu.get_event_constraints = icl_get_event_constraints;
5603                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5604                         hsw_format_attr : nhm_format_attr;
5605                 extra_skl_attr = skl_format_attr;
5606                 mem_attr = icl_events_attrs;
5607                 td_attr = icl_td_events_attrs;
5608                 tsx_attr = icl_tsx_events_attrs;
5609                 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
5610                 x86_pmu.lbr_pt_coexist = true;
5611                 intel_pmu_pebs_data_source_skl(pmem);
5612                 x86_pmu.num_topdown_events = 4;
5613                 x86_pmu.update_topdown_event = icl_update_topdown_event;
5614                 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period;
5615                 pr_cont("Icelake events, ");
5616                 name = "icelake";
5617                 break;
5618
5619         case INTEL_FAM6_SAPPHIRERAPIDS_X:
5620                 pmem = true;
5621                 x86_pmu.late_ack = true;
5622                 memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5623                 memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5624
5625                 x86_pmu.event_constraints = intel_spr_event_constraints;
5626                 x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;
5627                 x86_pmu.extra_regs = intel_spr_extra_regs;
5628                 x86_pmu.limit_period = spr_limit_period;
5629                 x86_pmu.pebs_aliases = NULL;
5630                 x86_pmu.pebs_prec_dist = true;
5631                 x86_pmu.pebs_block = true;
5632                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5633                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5634                 x86_pmu.flags |= PMU_FL_PEBS_ALL;
5635                 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
5636                 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
5637
5638                 x86_pmu.hw_config = hsw_hw_config;
5639                 x86_pmu.get_event_constraints = spr_get_event_constraints;
5640                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5641                         hsw_format_attr : nhm_format_attr;
5642                 extra_skl_attr = skl_format_attr;
5643                 mem_attr = spr_events_attrs;
5644                 td_attr = spr_td_events_attrs;
5645                 tsx_attr = spr_tsx_events_attrs;
5646                 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
5647                 x86_pmu.lbr_pt_coexist = true;
5648                 intel_pmu_pebs_data_source_skl(pmem);
5649                 x86_pmu.num_topdown_events = 8;
5650                 x86_pmu.update_topdown_event = icl_update_topdown_event;
5651                 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period;
5652                 pr_cont("Sapphire Rapids events, ");
5653                 name = "sapphire_rapids";
5654                 break;
5655
5656         default:
5657                 switch (x86_pmu.version) {
5658                 case 1:
5659                         x86_pmu.event_constraints = intel_v1_event_constraints;
5660                         pr_cont("generic architected perfmon v1, ");
5661                         name = "generic_arch_v1";
5662                         break;
5663                 default:
5664                         /*
5665                          * default constraints for v2 and up
5666                          */
5667                         x86_pmu.event_constraints = intel_gen_event_constraints;
5668                         pr_cont("generic architected perfmon, ");
5669                         name = "generic_arch_v2+";
5670                         break;
5671                 }
5672         }
5673
5674         snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
5675
5676
5677         group_events_td.attrs  = td_attr;
5678         group_events_mem.attrs = mem_attr;
5679         group_events_tsx.attrs = tsx_attr;
5680         group_format_extra.attrs = extra_attr;
5681         group_format_extra_skl.attrs = extra_skl_attr;
5682
5683         x86_pmu.attr_update = attr_update;
5684
5685         if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
5686                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
5687                      x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
5688                 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
5689         }
5690         x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1;
5691
5692         if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
5693                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
5694                      x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
5695                 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
5696         }
5697
5698         x86_pmu.intel_ctrl |= (u64)fixed_mask << INTEL_PMC_IDX_FIXED;
5699
5700         /* AnyThread may be deprecated on arch perfmon v5 or later */
5701         if (x86_pmu.intel_cap.anythread_deprecated)
5702                 x86_pmu.format_attrs = intel_arch_formats_attr;
5703
5704         if (x86_pmu.event_constraints) {
5705                 /*
5706                  * event on fixed counter2 (REF_CYCLES) only works on this
5707                  * counter, so do not extend mask to generic counters
5708                  */
5709                 for_each_event_constraint(c, x86_pmu.event_constraints) {
5710                         /*
5711                          * Don't extend the topdown slots and metrics
5712                          * events to the generic counters.
5713                          */
5714                         if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) {
5715                                 /*
5716                                  * Disable topdown slots and metrics events,
5717                                  * if slots event is not in CPUID.
5718                                  */
5719                                 if (!(INTEL_PMC_MSK_FIXED_SLOTS & x86_pmu.intel_ctrl))
5720                                         c->idxmsk64 = 0;
5721                                 c->weight = hweight64(c->idxmsk64);
5722                                 continue;
5723                         }
5724
5725                         if (c->cmask == FIXED_EVENT_FLAGS) {
5726                                 /* Disabled fixed counters which are not in CPUID */
5727                                 c->idxmsk64 &= x86_pmu.intel_ctrl;
5728
5729                                 if (c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES)
5730                                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
5731                         }
5732                         c->idxmsk64 &=
5733                                 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
5734                         c->weight = hweight64(c->idxmsk64);
5735                 }
5736         }
5737
5738         /*
5739          * Access LBR MSR may cause #GP under certain circumstances.
5740          * E.g. KVM doesn't support LBR MSR
5741          * Check all LBT MSR here.
5742          * Disable LBR access if any LBR MSRs can not be accessed.
5743          */
5744         if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
5745                 x86_pmu.lbr_nr = 0;
5746         for (i = 0; i < x86_pmu.lbr_nr; i++) {
5747                 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
5748                       check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
5749                         x86_pmu.lbr_nr = 0;
5750         }
5751
5752         if (x86_pmu.lbr_nr)
5753                 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
5754
5755         /*
5756          * Access extra MSR may cause #GP under certain circumstances.
5757          * E.g. KVM doesn't support offcore event
5758          * Check all extra_regs here.
5759          */
5760         if (x86_pmu.extra_regs) {
5761                 for (er = x86_pmu.extra_regs; er->msr; er++) {
5762                         er->extra_msr_access = check_msr(er->msr, 0x11UL);
5763                         /* Disable LBR select mapping */
5764                         if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
5765                                 x86_pmu.lbr_sel_map = NULL;
5766                 }
5767         }
5768
5769         /* Support full width counters using alternative MSR range */
5770         if (x86_pmu.intel_cap.full_width_write) {
5771                 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
5772                 x86_pmu.perfctr = MSR_IA32_PMC0;
5773                 pr_cont("full-width counters, ");
5774         }
5775
5776         if (x86_pmu.intel_cap.perf_metrics)
5777                 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
5778
5779         return 0;
5780 }
5781
5782 /*
5783  * HT bug: phase 2 init
5784  * Called once we have valid topology information to check
5785  * whether or not HT is enabled
5786  * If HT is off, then we disable the workaround
5787  */
5788 static __init int fixup_ht_bug(void)
5789 {
5790         int c;
5791         /*
5792          * problem not present on this CPU model, nothing to do
5793          */
5794         if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
5795                 return 0;
5796
5797         if (topology_max_smt_threads() > 1) {
5798                 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
5799                 return 0;
5800         }
5801
5802         cpus_read_lock();
5803
5804         hardlockup_detector_perf_stop();
5805
5806         x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
5807
5808         x86_pmu.start_scheduling = NULL;
5809         x86_pmu.commit_scheduling = NULL;
5810         x86_pmu.stop_scheduling = NULL;
5811
5812         hardlockup_detector_perf_restart();
5813
5814         for_each_online_cpu(c)
5815                 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
5816
5817         cpus_read_unlock();
5818         pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
5819         return 0;
5820 }
5821 subsys_initcall(fixup_ht_bug)