drivers/pwm/pwm-atmel.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for Atmel Pulse Width Modulation Controller
   4  *
   5  * Copyright (C) 2013 Atmel Corporation
   6  *               Bo Shen <[email protected]>
   7  *
   8  * Links to reference manuals for the supported PWM chips can be found in
   9  * Documentation/arm/microchip.rst.
  10  *
  11  * Limitations:
  12  * - Periods start with the inactive level.
  13  * - Hardware has to be stopped in general to update settings.
  14  *
  15  * Software bugs/possible improvements:
  16  * - When atmel_pwm_apply() is called with state->enabled=false a change in
  17  *   state->polarity isn't honored.
  18  * - Instead of sleeping to wait for a completed period, the interrupt
  19  *   functionality could be used.
  20  */
  21
  22 #include <linux/clk.h>
  23 #include <linux/delay.h>
  24 #include <linux/err.h>
  25 #include <linux/io.h>
  26 #include <linux/module.h>
  27 #include <linux/mutex.h>
  28 #include <linux/of.h>
  29 #include <linux/of_device.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/pwm.h>
  32 #include <linux/slab.h>
  33
  34 /* The following is global registers for PWM controller */
  35 #define PWM_ENA                 0x04
  36 #define PWM_DIS                 0x08
  37 #define PWM_SR                  0x0C
  38 #define PWM_ISR                 0x1C
  39 /* Bit field in SR */
  40 #define PWM_SR_ALL_CH_ON        0x0F
  41
  42 /* The following register is PWM channel related registers */
  43 #define PWM_CH_REG_OFFSET       0x200
  44 #define PWM_CH_REG_SIZE         0x20
  45
  46 #define PWM_CMR                 0x0
  47 /* Bit field in CMR */
  48 #define PWM_CMR_CPOL            (1 << 9)
  49 #define PWM_CMR_UPD_CDTY        (1 << 10)
  50 #define PWM_CMR_CPRE_MSK        0xF
  51
  52 /* The following registers for PWM v1 */
  53 #define PWMV1_CDTY              0x04
  54 #define PWMV1_CPRD              0x08
  55 #define PWMV1_CUPD              0x10
  56
  57 /* The following registers for PWM v2 */
  58 #define PWMV2_CDTY              0x04
  59 #define PWMV2_CDTYUPD           0x08
  60 #define PWMV2_CPRD              0x0C
  61 #define PWMV2_CPRDUPD           0x10
  62
  63 #define PWM_MAX_PRES            10
  64
  65 struct atmel_pwm_registers {
  66         u8 period;
  67         u8 period_upd;
  68         u8 duty;
  69         u8 duty_upd;
  70 };
  71
  72 struct atmel_pwm_config {
  73         u32 period_bits;
  74 };
  75
  76 struct atmel_pwm_data {
  77         struct atmel_pwm_registers regs;
  78         struct atmel_pwm_config cfg;
  79 };
  80
  81 struct atmel_pwm_chip {
  82         struct pwm_chip chip;
  83         struct clk *clk;
  84         void __iomem *base;
  85         const struct atmel_pwm_data *data;
  86
  87         unsigned int updated_pwms;
  88         /* ISR is cleared when read, ensure only one thread does that */
  89         struct mutex isr_lock;
  90 };
  91
  92 static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
  93 {
  94         return container_of(chip, struct atmel_pwm_chip, chip);
  95 }
  96
  97 static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
  98                                   unsigned long offset)
  99 {
 100         return readl_relaxed(chip->base + offset);
 101 }
 102
 103 static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
 104                                     unsigned long offset, unsigned long val)
 105 {
 106         writel_relaxed(val, chip->base + offset);
 107 }
 108
 109 static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
 110                                      unsigned int ch, unsigned long offset)
 111 {
 112         unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
 113
 114         return atmel_pwm_readl(chip, base + offset);
 115 }
 116
 117 static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
 118                                        unsigned int ch, unsigned long offset,
 119                                        unsigned long val)
 120 {
 121         unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
 122
 123         atmel_pwm_writel(chip, base + offset, val);
 124 }
 125
 126 static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
 127                                              unsigned long clkrate,
 128                                              const struct pwm_state *state,
 129                                              unsigned long *cprd, u32 *pres)
 130 {
 131         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 132         unsigned long long cycles = state->period;
 133         int shift;
 134
 135         /* Calculate the period cycles and prescale value */
 136         cycles *= clkrate;
 137         do_div(cycles, NSEC_PER_SEC);
 138
 139         /*
 140          * The register for the period length is cfg.period_bits bits wide.
 141          * So for each bit the number of clock cycles is wider divide the input
 142          * clock frequency by two using pres and shift cprd accordingly.
 143          */
 144         shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;
 145
 146         if (shift > PWM_MAX_PRES) {
 147                 dev_err(chip->dev, "pres exceeds the maximum value\n");
 148                 return -EINVAL;
 149         } else if (shift > 0) {
 150                 *pres = shift;
 151                 cycles >>= *pres;
 152         } else {
 153                 *pres = 0;
 154         }
 155
 156         *cprd = cycles;
 157
 158         return 0;
 159 }
 160
 161 static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
 162                                      unsigned long clkrate, unsigned long cprd,
 163                                      u32 pres, unsigned long *cdty)
 164 {
 165         unsigned long long cycles = state->duty_cycle;
 166
 167         cycles *= clkrate;
 168         do_div(cycles, NSEC_PER_SEC);
 169         cycles >>= pres;
 170         *cdty = cprd - cycles;
 171 }
 172
 173 static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
 174                                   unsigned long cdty)
 175 {
 176         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 177         u32 val;
 178
 179         if (atmel_pwm->data->regs.duty_upd ==
 180             atmel_pwm->data->regs.period_upd) {
 181                 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
 182                 val &= ~PWM_CMR_UPD_CDTY;
 183                 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
 184         }
 185
 186         atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
 187                             atmel_pwm->data->regs.duty_upd, cdty);
 188 }
 189
 190 static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
 191                                     struct pwm_device *pwm,
 192                                     unsigned long cprd, unsigned long cdty)
 193 {
 194         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 195
 196         atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
 197                             atmel_pwm->data->regs.duty, cdty);
 198         atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
 199                             atmel_pwm->data->regs.period, cprd);
 200 }
 201
 202 static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
 203                               bool disable_clk)
 204 {
 205         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 206         unsigned long timeout = jiffies + 2 * HZ;
 207
 208         /*
 209          * Wait for at least a complete period to have passed before disabling a
 210          * channel to be sure that CDTY has been updated
 211          */
 212         mutex_lock(&atmel_pwm->isr_lock);
 213         atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
 214
 215         while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) &&
 216                time_before(jiffies, timeout)) {
 217                 usleep_range(10, 100);
 218                 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
 219         }
 220
 221         mutex_unlock(&atmel_pwm->isr_lock);
 222         atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
 223
 224         /*
 225          * Wait for the PWM channel disable operation to be effective before
 226          * stopping the clock.
 227          */
 228         timeout = jiffies + 2 * HZ;
 229
 230         while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
 231                time_before(jiffies, timeout))
 232                 usleep_range(10, 100);
 233
 234         if (disable_clk)
 235                 clk_disable(atmel_pwm->clk);
 236 }
 237
 238 static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 239                            const struct pwm_state *state)
 240 {
 241         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 242         struct pwm_state cstate;
 243         unsigned long cprd, cdty;
 244         u32 pres, val;
 245         int ret;
 246
 247         pwm_get_state(pwm, &cstate);
 248
 249         if (state->enabled) {
 250                 unsigned long clkrate = clk_get_rate(atmel_pwm->clk);
 251
 252                 if (cstate.enabled &&
 253                     cstate.polarity == state->polarity &&
 254                     cstate.period == state->period) {
 255                         u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
 256
 257                         cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
 258                                                   atmel_pwm->data->regs.period);
 259                         pres = cmr & PWM_CMR_CPRE_MSK;
 260
 261                         atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
 262                         atmel_pwm_update_cdty(chip, pwm, cdty);
 263                         return 0;
 264                 }
 265
 266                 ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, &cprd,
 267                                                         &pres);
 268                 if (ret) {
 269                         dev_err(chip->dev,
 270                                 "failed to calculate cprd and prescaler\n");
 271                         return ret;
 272                 }
 273
 274                 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
 275
 276                 if (cstate.enabled) {
 277                         atmel_pwm_disable(chip, pwm, false);
 278                 } else {
 279                         ret = clk_enable(atmel_pwm->clk);
 280                         if (ret) {
 281                                 dev_err(chip->dev, "failed to enable clock\n");
 282                                 return ret;
 283                         }
 284                 }
 285
 286                 /* It is necessary to preserve CPOL, inside CMR */
 287                 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
 288                 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
 289                 if (state->polarity == PWM_POLARITY_NORMAL)
 290                         val &= ~PWM_CMR_CPOL;
 291                 else
 292                         val |= PWM_CMR_CPOL;
 293                 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
 294                 atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
 295                 mutex_lock(&atmel_pwm->isr_lock);
 296                 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
 297                 atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm);
 298                 mutex_unlock(&atmel_pwm->isr_lock);
 299                 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
 300         } else if (cstate.enabled) {
 301                 atmel_pwm_disable(chip, pwm, true);
 302         }
 303
 304         return 0;
 305 }
 306
 307 static void atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 308                                 struct pwm_state *state)
 309 {
 310         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 311         u32 sr, cmr;
 312
 313         sr = atmel_pwm_readl(atmel_pwm, PWM_SR);
 314         cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
 315
 316         if (sr & (1 << pwm->hwpwm)) {
 317                 unsigned long rate = clk_get_rate(atmel_pwm->clk);
 318                 u32 cdty, cprd, pres;
 319                 u64 tmp;
 320
 321                 pres = cmr & PWM_CMR_CPRE_MSK;
 322
 323                 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
 324                                           atmel_pwm->data->regs.period);
 325                 tmp = (u64)cprd * NSEC_PER_SEC;
 326                 tmp <<= pres;
 327                 state->period = DIV64_U64_ROUND_UP(tmp, rate);
 328
 329                 cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
 330                                           atmel_pwm->data->regs.duty);
 331                 tmp = (u64)(cprd - cdty) * NSEC_PER_SEC;
 332                 tmp <<= pres;
 333                 state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);
 334
 335                 state->enabled = true;
 336         } else {
 337                 state->enabled = false;
 338         }
 339
 340         if (cmr & PWM_CMR_CPOL)
 341                 state->polarity = PWM_POLARITY_INVERSED;
 342         else
 343                 state->polarity = PWM_POLARITY_NORMAL;
 344 }
 345
 346 static const struct pwm_ops atmel_pwm_ops = {
 347         .apply = atmel_pwm_apply,
 348         .get_state = atmel_pwm_get_state,
 349         .owner = THIS_MODULE,
 350 };
 351
 352 static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
 353         .regs = {
 354                 .period         = PWMV1_CPRD,
 355                 .period_upd     = PWMV1_CUPD,
 356                 .duty           = PWMV1_CDTY,
 357                 .duty_upd       = PWMV1_CUPD,
 358         },
 359         .cfg = {
 360                 /* 16 bits to keep period and duty. */
 361                 .period_bits    = 16,
 362         },
 363 };
 364
 365 static const struct atmel_pwm_data atmel_sama5_pwm_data = {
 366         .regs = {
 367                 .period         = PWMV2_CPRD,
 368                 .period_upd     = PWMV2_CPRDUPD,
 369                 .duty           = PWMV2_CDTY,
 370                 .duty_upd       = PWMV2_CDTYUPD,
 371         },
 372         .cfg = {
 373                 /* 16 bits to keep period and duty. */
 374                 .period_bits    = 16,
 375         },
 376 };
 377
 378 static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
 379         .regs = {
 380                 .period         = PWMV1_CPRD,
 381                 .period_upd     = PWMV1_CUPD,
 382                 .duty           = PWMV1_CDTY,
 383                 .duty_upd       = PWMV1_CUPD,
 384         },
 385         .cfg = {
 386                 /* 32 bits to keep period and duty. */
 387                 .period_bits    = 32,
 388         },
 389 };
 390
 391 static const struct of_device_id atmel_pwm_dt_ids[] = {
 392         {
 393                 .compatible = "atmel,at91sam9rl-pwm",
 394                 .data = &atmel_sam9rl_pwm_data,
 395         }, {
 396                 .compatible = "atmel,sama5d3-pwm",
 397                 .data = &atmel_sama5_pwm_data,
 398         }, {
 399                 .compatible = "atmel,sama5d2-pwm",
 400                 .data = &atmel_sama5_pwm_data,
 401         }, {
 402                 .compatible = "microchip,sam9x60-pwm",
 403                 .data = &mchp_sam9x60_pwm_data,
 404         }, {
 405                 /* sentinel */
 406         },
 407 };
 408 MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
 409
 410 static int atmel_pwm_probe(struct platform_device *pdev)
 411 {
 412         struct atmel_pwm_chip *atmel_pwm;
 413         int ret;
 414
 415         atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
 416         if (!atmel_pwm)
 417                 return -ENOMEM;
 418
 419         mutex_init(&atmel_pwm->isr_lock);
 420         atmel_pwm->data = of_device_get_match_data(&pdev->dev);
 421         atmel_pwm->updated_pwms = 0;
 422
 423         atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0);
 424         if (IS_ERR(atmel_pwm->base))
 425                 return PTR_ERR(atmel_pwm->base);
 426
 427         atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
 428         if (IS_ERR(atmel_pwm->clk))
 429                 return PTR_ERR(atmel_pwm->clk);
 430
 431         ret = clk_prepare(atmel_pwm->clk);
 432         if (ret) {
 433                 dev_err(&pdev->dev, "failed to prepare PWM clock\n");
 434                 return ret;
 435         }
 436
 437         atmel_pwm->chip.dev = &pdev->dev;
 438         atmel_pwm->chip.ops = &atmel_pwm_ops;
 439         atmel_pwm->chip.npwm = 4;
 440
 441         ret = pwmchip_add(&atmel_pwm->chip);
 442         if (ret < 0) {
 443                 dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
 444                 goto unprepare_clk;
 445         }
 446
 447         platform_set_drvdata(pdev, atmel_pwm);
 448
 449         return ret;
 450
 451 unprepare_clk:
 452         clk_unprepare(atmel_pwm->clk);
 453         return ret;
 454 }
 455
 456 static int atmel_pwm_remove(struct platform_device *pdev)
 457 {
 458         struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
 459
 460         pwmchip_remove(&atmel_pwm->chip);
 461
 462         clk_unprepare(atmel_pwm->clk);
 463         mutex_destroy(&atmel_pwm->isr_lock);
 464
 465         return 0;
 466 }
 467
 468 static struct platform_driver atmel_pwm_driver = {
 469         .driver = {
 470                 .name = "atmel-pwm",
 471                 .of_match_table = of_match_ptr(atmel_pwm_dt_ids),
 472         },
 473         .probe = atmel_pwm_probe,
 474         .remove = atmel_pwm_remove,
 475 };
 476 module_platform_driver(atmel_pwm_driver);
 477
 478 MODULE_ALIAS("platform:atmel-pwm");
 479 MODULE_AUTHOR("Bo Shen <[email protected]>");
 480 MODULE_DESCRIPTION("Atmel PWM driver");
 481 MODULE_LICENSE("GPL v2");