drivers/gpu/drm/amd/amdgpu/cik_sdma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_ucode.h"
  30 #include "amdgpu_trace.h"
  31 #include "cikd.h"
  32 #include "cik.h"
  33
  34 #include "bif/bif_4_1_d.h"
  35 #include "bif/bif_4_1_sh_mask.h"
  36
  37 #include "gca/gfx_7_2_d.h"
  38 #include "gca/gfx_7_2_enum.h"
  39 #include "gca/gfx_7_2_sh_mask.h"
  40
  41 #include "gmc/gmc_7_1_d.h"
  42 #include "gmc/gmc_7_1_sh_mask.h"
  43
  44 #include "oss/oss_2_0_d.h"
  45 #include "oss/oss_2_0_sh_mask.h"
  46
  47 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  48 {
  49         SDMA0_REGISTER_OFFSET,
  50         SDMA1_REGISTER_OFFSET
  51 };
  52
  53 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
  54 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
  55 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
  56 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
  57 static int cik_sdma_soft_reset(struct amdgpu_ip_block *ip_block);
  58
  59 MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin");
  60 MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin");
  61 MODULE_FIRMWARE("amdgpu/hawaii_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/hawaii_sdma1.bin");
  63 MODULE_FIRMWARE("amdgpu/kaveri_sdma.bin");
  64 MODULE_FIRMWARE("amdgpu/kaveri_sdma1.bin");
  65 MODULE_FIRMWARE("amdgpu/kabini_sdma.bin");
  66 MODULE_FIRMWARE("amdgpu/kabini_sdma1.bin");
  67 MODULE_FIRMWARE("amdgpu/mullins_sdma.bin");
  68 MODULE_FIRMWARE("amdgpu/mullins_sdma1.bin");
  69
  70 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
  71
  72
  73 static void cik_sdma_free_microcode(struct amdgpu_device *adev)
  74 {
  75         int i;
  76
  77         for (i = 0; i < adev->sdma.num_instances; i++)
  78                 amdgpu_ucode_release(&adev->sdma.instance[i].fw);
  79 }
  80
  81 /*
  82  * sDMA - System DMA
  83  * Starting with CIK, the GPU has new asynchronous
  84  * DMA engines.  These engines are used for compute
  85  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  86  * and each one supports 1 ring buffer used for gfx
  87  * and 2 queues used for compute.
  88  *
  89  * The programming model is very similar to the CP
  90  * (ring buffer, IBs, etc.), but sDMA has it's own
  91  * packet format that is different from the PM4 format
  92  * used by the CP. sDMA supports copying data, writing
  93  * embedded data, solid fills, and a number of other
  94  * things.  It also has support for tiling/detiling of
  95  * buffers.
  96  */
  97
  98 /**
  99  * cik_sdma_init_microcode - load ucode images from disk
 100  *
 101  * @adev: amdgpu_device pointer
 102  *
 103  * Use the firmware interface to load the ucode images into
 104  * the driver (not loaded into hw).
 105  * Returns 0 on success, error on failure.
 106  */
 107 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
 108 {
 109         const char *chip_name;
 110         int err = 0, i;
 111
 112         DRM_DEBUG("\n");
 113
 114         switch (adev->asic_type) {
 115         case CHIP_BONAIRE:
 116                 chip_name = "bonaire";
 117                 break;
 118         case CHIP_HAWAII:
 119                 chip_name = "hawaii";
 120                 break;
 121         case CHIP_KAVERI:
 122                 chip_name = "kaveri";
 123                 break;
 124         case CHIP_KABINI:
 125                 chip_name = "kabini";
 126                 break;
 127         case CHIP_MULLINS:
 128                 chip_name = "mullins";
 129                 break;
 130         default: BUG();
 131         }
 132
 133         for (i = 0; i < adev->sdma.num_instances; i++) {
 134                 if (i == 0)
 135                         err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw,
 136                                                    AMDGPU_UCODE_REQUIRED,
 137                                                    "amdgpu/%s_sdma.bin", chip_name);
 138                 else
 139                         err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw,
 140                                                    AMDGPU_UCODE_REQUIRED,
 141                                                    "amdgpu/%s_sdma1.bin", chip_name);
 142                 if (err)
 143                         goto out;
 144         }
 145 out:
 146         if (err) {
 147                 pr_err("cik_sdma: Failed to load firmware \"%s_sdma%s.bin\"\n",
 148                        chip_name, i == 0 ? "" : "1");
 149                 for (i = 0; i < adev->sdma.num_instances; i++)
 150                         amdgpu_ucode_release(&adev->sdma.instance[i].fw);
 151         }
 152         return err;
 153 }
 154
 155 /**
 156  * cik_sdma_ring_get_rptr - get the current read pointer
 157  *
 158  * @ring: amdgpu ring pointer
 159  *
 160  * Get the current rptr from the hardware (CIK+).
 161  */
 162 static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 163 {
 164         u32 rptr;
 165
 166         rptr = *ring->rptr_cpu_addr;
 167
 168         return (rptr & 0x3fffc) >> 2;
 169 }
 170
 171 /**
 172  * cik_sdma_ring_get_wptr - get the current write pointer
 173  *
 174  * @ring: amdgpu ring pointer
 175  *
 176  * Get the current wptr from the hardware (CIK+).
 177  */
 178 static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 179 {
 180         struct amdgpu_device *adev = ring->adev;
 181
 182         return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
 183 }
 184
 185 /**
 186  * cik_sdma_ring_set_wptr - commit the write pointer
 187  *
 188  * @ring: amdgpu ring pointer
 189  *
 190  * Write the wptr back to the hardware (CIK+).
 191  */
 192 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 193 {
 194         struct amdgpu_device *adev = ring->adev;
 195
 196         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
 197                (ring->wptr << 2) & 0x3fffc);
 198 }
 199
 200 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 201 {
 202         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 203         int i;
 204
 205         for (i = 0; i < count; i++)
 206                 if (sdma && sdma->burst_nop && (i == 0))
 207                         amdgpu_ring_write(ring, ring->funcs->nop |
 208                                           SDMA_NOP_COUNT(count - 1));
 209                 else
 210                         amdgpu_ring_write(ring, ring->funcs->nop);
 211 }
 212
 213 /**
 214  * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
 215  *
 216  * @ring: amdgpu ring pointer
 217  * @job: job to retrive vmid from
 218  * @ib: IB object to schedule
 219  * @flags: unused
 220  *
 221  * Schedule an IB in the DMA ring (CIK).
 222  */
 223 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
 224                                   struct amdgpu_job *job,
 225                                   struct amdgpu_ib *ib,
 226                                   uint32_t flags)
 227 {
 228         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 229         u32 extra_bits = vmid & 0xf;
 230
 231         /* IB packet must end on a 8 DW boundary */
 232         cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7);
 233
 234         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
 235         amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
 236         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
 237         amdgpu_ring_write(ring, ib->length_dw);
 238
 239 }
 240
 241 /**
 242  * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 243  *
 244  * @ring: amdgpu ring pointer
 245  *
 246  * Emit an hdp flush packet on the requested DMA ring.
 247  */
 248 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 249 {
 250         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
 251                           SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
 252         u32 ref_and_mask;
 253
 254         if (ring->me == 0)
 255                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
 256         else
 257                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
 258
 259         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 260         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 261         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 262         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 263         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 264         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 265 }
 266
 267 /**
 268  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
 269  *
 270  * @ring: amdgpu ring pointer
 271  * @addr: address
 272  * @seq: sequence number
 273  * @flags: fence related flags
 274  *
 275  * Add a DMA fence packet to the ring to write
 276  * the fence seq number and DMA trap packet to generate
 277  * an interrupt if needed (CIK).
 278  */
 279 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 280                                      unsigned flags)
 281 {
 282         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 283         /* write the fence */
 284         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 285         amdgpu_ring_write(ring, lower_32_bits(addr));
 286         amdgpu_ring_write(ring, upper_32_bits(addr));
 287         amdgpu_ring_write(ring, lower_32_bits(seq));
 288
 289         /* optionally write high bits as well */
 290         if (write64bit) {
 291                 addr += 4;
 292                 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 293                 amdgpu_ring_write(ring, lower_32_bits(addr));
 294                 amdgpu_ring_write(ring, upper_32_bits(addr));
 295                 amdgpu_ring_write(ring, upper_32_bits(seq));
 296         }
 297
 298         /* generate an interrupt */
 299         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
 300 }
 301
 302 /**
 303  * cik_sdma_gfx_stop - stop the gfx async dma engines
 304  *
 305  * @adev: amdgpu_device pointer
 306  *
 307  * Stop the gfx async dma ring buffers (CIK).
 308  */
 309 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
 310 {
 311         u32 rb_cntl;
 312         int i;
 313
 314         for (i = 0; i < adev->sdma.num_instances; i++) {
 315                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 316                 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
 317                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 318                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
 319         }
 320 }
 321
 322 /**
 323  * cik_sdma_rlc_stop - stop the compute async dma engines
 324  *
 325  * @adev: amdgpu_device pointer
 326  *
 327  * Stop the compute async dma queues (CIK).
 328  */
 329 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
 330 {
 331         /* XXX todo */
 332 }
 333
 334 /**
 335  * cik_ctx_switch_enable - stop the async dma engines context switch
 336  *
 337  * @adev: amdgpu_device pointer
 338  * @enable: enable/disable the DMA MEs context switch.
 339  *
 340  * Halt or unhalt the async dma engines context switch (VI).
 341  */
 342 static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 343 {
 344         u32 f32_cntl, phase_quantum = 0;
 345         int i;
 346
 347         if (amdgpu_sdma_phase_quantum) {
 348                 unsigned value = amdgpu_sdma_phase_quantum;
 349                 unsigned unit = 0;
 350
 351                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 352                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 353                         value = (value + 1) >> 1;
 354                         unit++;
 355                 }
 356                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 357                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 358                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 359                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 360                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 361                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 362                         WARN_ONCE(1,
 363                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 364                                   value << unit);
 365                 }
 366                 phase_quantum =
 367                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 368                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 369         }
 370
 371         for (i = 0; i < adev->sdma.num_instances; i++) {
 372                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 373                 if (enable) {
 374                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 375                                         AUTO_CTXSW_ENABLE, 1);
 376                         if (amdgpu_sdma_phase_quantum) {
 377                                 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
 378                                        phase_quantum);
 379                                 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
 380                                        phase_quantum);
 381                         }
 382                 } else {
 383                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 384                                         AUTO_CTXSW_ENABLE, 0);
 385                 }
 386
 387                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 388         }
 389 }
 390
 391 /**
 392  * cik_sdma_enable - stop the async dma engines
 393  *
 394  * @adev: amdgpu_device pointer
 395  * @enable: enable/disable the DMA MEs.
 396  *
 397  * Halt or unhalt the async dma engines (CIK).
 398  */
 399 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
 400 {
 401         u32 me_cntl;
 402         int i;
 403
 404         if (!enable) {
 405                 cik_sdma_gfx_stop(adev);
 406                 cik_sdma_rlc_stop(adev);
 407         }
 408
 409         for (i = 0; i < adev->sdma.num_instances; i++) {
 410                 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 411                 if (enable)
 412                         me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
 413                 else
 414                         me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
 415                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
 416         }
 417 }
 418
 419 /**
 420  * cik_sdma_gfx_resume - setup and start the async dma engines
 421  *
 422  * @adev: amdgpu_device pointer
 423  *
 424  * Set up the gfx DMA ring buffers and enable them (CIK).
 425  * Returns 0 for success, error for failure.
 426  */
 427 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 428 {
 429         struct amdgpu_ring *ring;
 430         u32 rb_cntl, ib_cntl;
 431         u32 rb_bufsz;
 432         int i, j, r;
 433
 434         for (i = 0; i < adev->sdma.num_instances; i++) {
 435                 ring = &adev->sdma.instance[i].ring;
 436
 437                 mutex_lock(&adev->srbm_mutex);
 438                 for (j = 0; j < 16; j++) {
 439                         cik_srbm_select(adev, 0, 0, 0, j);
 440                         /* SDMA GFX */
 441                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 442                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 443                         /* XXX SDMA RLC - todo */
 444                 }
 445                 cik_srbm_select(adev, 0, 0, 0, 0);
 446                 mutex_unlock(&adev->srbm_mutex);
 447
 448                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 449                        adev->gfx.config.gb_addr_config & 0x70);
 450
 451                 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
 452                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 453
 454                 /* Set ring buffer size in dwords */
 455                 rb_bufsz = order_base_2(ring->ring_size / 4);
 456                 rb_cntl = rb_bufsz << 1;
 457 #ifdef __BIG_ENDIAN
 458                 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
 459                         SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
 460 #endif
 461                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 462
 463                 /* Initialize the ring buffer's read and write pointers */
 464                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 465                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 466                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 467                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 468
 469                 /* set the wb address whether it's enabled or not */
 470                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 471                        upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
 472                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 473                        ((ring->rptr_gpu_addr) & 0xFFFFFFFC));
 474
 475                 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
 476
 477                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 478                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 479
 480                 ring->wptr = 0;
 481                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 482
 483                 /* enable DMA RB */
 484                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
 485                        rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
 486
 487                 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
 488 #ifdef __BIG_ENDIAN
 489                 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
 490 #endif
 491                 /* enable DMA IBs */
 492                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 493         }
 494
 495         cik_sdma_enable(adev, true);
 496
 497         for (i = 0; i < adev->sdma.num_instances; i++) {
 498                 ring = &adev->sdma.instance[i].ring;
 499                 r = amdgpu_ring_test_helper(ring);
 500                 if (r)
 501                         return r;
 502         }
 503
 504         return 0;
 505 }
 506
 507 /**
 508  * cik_sdma_rlc_resume - setup and start the async dma engines
 509  *
 510  * @adev: amdgpu_device pointer
 511  *
 512  * Set up the compute DMA queues and enable them (CIK).
 513  * Returns 0 for success, error for failure.
 514  */
 515 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
 516 {
 517         /* XXX todo */
 518         return 0;
 519 }
 520
 521 /**
 522  * cik_sdma_load_microcode - load the sDMA ME ucode
 523  *
 524  * @adev: amdgpu_device pointer
 525  *
 526  * Loads the sDMA0/1 ucode.
 527  * Returns 0 for success, -EINVAL if the ucode is not available.
 528  */
 529 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
 530 {
 531         const struct sdma_firmware_header_v1_0 *hdr;
 532         const __le32 *fw_data;
 533         u32 fw_size;
 534         int i, j;
 535
 536         /* halt the MEs */
 537         cik_sdma_enable(adev, false);
 538
 539         for (i = 0; i < adev->sdma.num_instances; i++) {
 540                 if (!adev->sdma.instance[i].fw)
 541                         return -EINVAL;
 542                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 543                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 544                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 545                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 546                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 547                 if (adev->sdma.instance[i].feature_version >= 20)
 548                         adev->sdma.instance[i].burst_nop = true;
 549                 fw_data = (const __le32 *)
 550                         (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 551                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 552                 for (j = 0; j < fw_size; j++)
 553                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 554                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 555         }
 556
 557         return 0;
 558 }
 559
 560 /**
 561  * cik_sdma_start - setup and start the async dma engines
 562  *
 563  * @adev: amdgpu_device pointer
 564  *
 565  * Set up the DMA engines and enable them (CIK).
 566  * Returns 0 for success, error for failure.
 567  */
 568 static int cik_sdma_start(struct amdgpu_device *adev)
 569 {
 570         int r;
 571
 572         r = cik_sdma_load_microcode(adev);
 573         if (r)
 574                 return r;
 575
 576         /* halt the engine before programing */
 577         cik_sdma_enable(adev, false);
 578         /* enable sdma ring preemption */
 579         cik_ctx_switch_enable(adev, true);
 580
 581         /* start the gfx rings and rlc compute queues */
 582         r = cik_sdma_gfx_resume(adev);
 583         if (r)
 584                 return r;
 585         r = cik_sdma_rlc_resume(adev);
 586         if (r)
 587                 return r;
 588
 589         return 0;
 590 }
 591
 592 /**
 593  * cik_sdma_ring_test_ring - simple async dma engine test
 594  *
 595  * @ring: amdgpu_ring structure holding ring information
 596  *
 597  * Test the DMA engine by writing using it to write an
 598  * value to memory. (CIK).
 599  * Returns 0 for success, error for failure.
 600  */
 601 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
 602 {
 603         struct amdgpu_device *adev = ring->adev;
 604         unsigned i;
 605         unsigned index;
 606         int r;
 607         u32 tmp;
 608         u64 gpu_addr;
 609
 610         r = amdgpu_device_wb_get(adev, &index);
 611         if (r)
 612                 return r;
 613
 614         gpu_addr = adev->wb.gpu_addr + (index * 4);
 615         tmp = 0xCAFEDEAD;
 616         adev->wb.wb[index] = cpu_to_le32(tmp);
 617
 618         r = amdgpu_ring_alloc(ring, 5);
 619         if (r)
 620                 goto error_free_wb;
 621
 622         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 623         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 624         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 625         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 626         amdgpu_ring_write(ring, 0xDEADBEEF);
 627         amdgpu_ring_commit(ring);
 628
 629         for (i = 0; i < adev->usec_timeout; i++) {
 630                 tmp = le32_to_cpu(adev->wb.wb[index]);
 631                 if (tmp == 0xDEADBEEF)
 632                         break;
 633                 udelay(1);
 634         }
 635
 636         if (i >= adev->usec_timeout)
 637                 r = -ETIMEDOUT;
 638
 639 error_free_wb:
 640         amdgpu_device_wb_free(adev, index);
 641         return r;
 642 }
 643
 644 /**
 645  * cik_sdma_ring_test_ib - test an IB on the DMA engine
 646  *
 647  * @ring: amdgpu_ring structure holding ring information
 648  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 649  *
 650  * Test a simple IB in the DMA ring (CIK).
 651  * Returns 0 on success, error on failure.
 652  */
 653 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 654 {
 655         struct amdgpu_device *adev = ring->adev;
 656         struct amdgpu_ib ib;
 657         struct dma_fence *f = NULL;
 658         unsigned index;
 659         u32 tmp = 0;
 660         u64 gpu_addr;
 661         long r;
 662
 663         r = amdgpu_device_wb_get(adev, &index);
 664         if (r)
 665                 return r;
 666
 667         gpu_addr = adev->wb.gpu_addr + (index * 4);
 668         tmp = 0xCAFEDEAD;
 669         adev->wb.wb[index] = cpu_to_le32(tmp);
 670         memset(&ib, 0, sizeof(ib));
 671         r = amdgpu_ib_get(adev, NULL, 256,
 672                                         AMDGPU_IB_POOL_DIRECT, &ib);
 673         if (r)
 674                 goto err0;
 675
 676         ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 677                                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 678         ib.ptr[1] = lower_32_bits(gpu_addr);
 679         ib.ptr[2] = upper_32_bits(gpu_addr);
 680         ib.ptr[3] = 1;
 681         ib.ptr[4] = 0xDEADBEEF;
 682         ib.length_dw = 5;
 683         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 684         if (r)
 685                 goto err1;
 686
 687         r = dma_fence_wait_timeout(f, false, timeout);
 688         if (r == 0) {
 689                 r = -ETIMEDOUT;
 690                 goto err1;
 691         } else if (r < 0) {
 692                 goto err1;
 693         }
 694         tmp = le32_to_cpu(adev->wb.wb[index]);
 695         if (tmp == 0xDEADBEEF)
 696                 r = 0;
 697         else
 698                 r = -EINVAL;
 699
 700 err1:
 701         amdgpu_ib_free(&ib, NULL);
 702         dma_fence_put(f);
 703 err0:
 704         amdgpu_device_wb_free(adev, index);
 705         return r;
 706 }
 707
 708 /**
 709  * cik_sdma_vm_copy_pte - update PTEs by copying them from the GART
 710  *
 711  * @ib: indirect buffer to fill with commands
 712  * @pe: addr of the page entry
 713  * @src: src addr to copy from
 714  * @count: number of page entries to update
 715  *
 716  * Update PTEs by copying them from the GART using sDMA (CIK).
 717  */
 718 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
 719                                  uint64_t pe, uint64_t src,
 720                                  unsigned count)
 721 {
 722         unsigned bytes = count * 8;
 723
 724         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
 725                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 726         ib->ptr[ib->length_dw++] = bytes;
 727         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 728         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 729         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 730         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 731         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 732 }
 733
 734 /**
 735  * cik_sdma_vm_write_pte - update PTEs by writing them manually
 736  *
 737  * @ib: indirect buffer to fill with commands
 738  * @pe: addr of the page entry
 739  * @value: dst addr to write into pe
 740  * @count: number of page entries to update
 741  * @incr: increase next addr by incr bytes
 742  *
 743  * Update PTEs by writing them manually using sDMA (CIK).
 744  */
 745 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 746                                   uint64_t value, unsigned count,
 747                                   uint32_t incr)
 748 {
 749         unsigned ndw = count * 2;
 750
 751         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 752                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 753         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 754         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 755         ib->ptr[ib->length_dw++] = ndw;
 756         for (; ndw > 0; ndw -= 2) {
 757                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 758                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 759                 value += incr;
 760         }
 761 }
 762
 763 /**
 764  * cik_sdma_vm_set_pte_pde - update the page tables using sDMA
 765  *
 766  * @ib: indirect buffer to fill with commands
 767  * @pe: addr of the page entry
 768  * @addr: dst addr to write into pe
 769  * @count: number of page entries to update
 770  * @incr: increase next addr by incr bytes
 771  * @flags: access flags
 772  *
 773  * Update the page tables using sDMA (CIK).
 774  */
 775 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 776                                     uint64_t addr, unsigned count,
 777                                     uint32_t incr, uint64_t flags)
 778 {
 779         /* for physically contiguous pages (vram) */
 780         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
 781         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 782         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 783         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
 784         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
 785         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 786         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 787         ib->ptr[ib->length_dw++] = incr; /* increment size */
 788         ib->ptr[ib->length_dw++] = 0;
 789         ib->ptr[ib->length_dw++] = count; /* number of entries */
 790 }
 791
 792 /**
 793  * cik_sdma_ring_pad_ib - pad the IB to the required number of dw
 794  *
 795  * @ring: amdgpu_ring structure holding ring information
 796  * @ib: indirect buffer to fill with padding
 797  *
 798  */
 799 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 800 {
 801         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 802         u32 pad_count;
 803         int i;
 804
 805         pad_count = (-ib->length_dw) & 7;
 806         for (i = 0; i < pad_count; i++)
 807                 if (sdma && sdma->burst_nop && (i == 0))
 808                         ib->ptr[ib->length_dw++] =
 809                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
 810                                         SDMA_NOP_COUNT(pad_count - 1);
 811                 else
 812                         ib->ptr[ib->length_dw++] =
 813                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
 814 }
 815
 816 /**
 817  * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
 818  *
 819  * @ring: amdgpu_ring pointer
 820  *
 821  * Make sure all previous operations are completed (CIK).
 822  */
 823 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 824 {
 825         uint32_t seq = ring->fence_drv.sync_seq;
 826         uint64_t addr = ring->fence_drv.gpu_addr;
 827
 828         /* wait for idle */
 829         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
 830                                             SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 831                                             SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
 832                                             SDMA_POLL_REG_MEM_EXTRA_M));
 833         amdgpu_ring_write(ring, addr & 0xfffffffc);
 834         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 835         amdgpu_ring_write(ring, seq); /* reference */
 836         amdgpu_ring_write(ring, 0xffffffff); /* mask */
 837         amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
 838 }
 839
 840 /**
 841  * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
 842  *
 843  * @ring: amdgpu_ring pointer
 844  * @vmid: vmid number to use
 845  * @pd_addr: address
 846  *
 847  * Update the page table base and flush the VM TLB
 848  * using sDMA (CIK).
 849  */
 850 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 851                                         unsigned vmid, uint64_t pd_addr)
 852 {
 853         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 854                           SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 855
 856         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
 857
 858         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 859         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 860         amdgpu_ring_write(ring, 0);
 861         amdgpu_ring_write(ring, 0); /* reference */
 862         amdgpu_ring_write(ring, 0); /* mask */
 863         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 864 }
 865
 866 static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring,
 867                                     uint32_t reg, uint32_t val)
 868 {
 869         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 870         amdgpu_ring_write(ring, reg);
 871         amdgpu_ring_write(ring, val);
 872 }
 873
 874 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
 875                                  bool enable)
 876 {
 877         u32 orig, data;
 878
 879         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
 880                 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
 881                 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
 882         } else {
 883                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
 884                 data |= 0xff000000;
 885                 if (data != orig)
 886                         WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
 887
 888                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
 889                 data |= 0xff000000;
 890                 if (data != orig)
 891                         WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
 892         }
 893 }
 894
 895 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
 896                                  bool enable)
 897 {
 898         u32 orig, data;
 899
 900         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
 901                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 902                 data |= 0x100;
 903                 if (orig != data)
 904                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 905
 906                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 907                 data |= 0x100;
 908                 if (orig != data)
 909                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 910         } else {
 911                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 912                 data &= ~0x100;
 913                 if (orig != data)
 914                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 915
 916                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 917                 data &= ~0x100;
 918                 if (orig != data)
 919                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 920         }
 921 }
 922
 923 static int cik_sdma_early_init(struct amdgpu_ip_block *ip_block)
 924 {
 925         struct amdgpu_device *adev = ip_block->adev;
 926         int r;
 927
 928         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 929
 930         r = cik_sdma_init_microcode(adev);
 931         if (r)
 932                 return r;
 933
 934         cik_sdma_set_ring_funcs(adev);
 935         cik_sdma_set_irq_funcs(adev);
 936         cik_sdma_set_buffer_funcs(adev);
 937         cik_sdma_set_vm_pte_funcs(adev);
 938
 939         return 0;
 940 }
 941
 942 static int cik_sdma_sw_init(struct amdgpu_ip_block *ip_block)
 943 {
 944         struct amdgpu_ring *ring;
 945         struct amdgpu_device *adev = ip_block->adev;
 946         int r, i;
 947
 948         /* SDMA trap event */
 949         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224,
 950                               &adev->sdma.trap_irq);
 951         if (r)
 952                 return r;
 953
 954         /* SDMA Privileged inst */
 955         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
 956                               &adev->sdma.illegal_inst_irq);
 957         if (r)
 958                 return r;
 959
 960         /* SDMA Privileged inst */
 961         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 247,
 962                               &adev->sdma.illegal_inst_irq);
 963         if (r)
 964                 return r;
 965
 966         for (i = 0; i < adev->sdma.num_instances; i++) {
 967                 ring = &adev->sdma.instance[i].ring;
 968                 ring->ring_obj = NULL;
 969                 sprintf(ring->name, "sdma%d", i);
 970                 r = amdgpu_ring_init(adev, ring, 1024,
 971                                      &adev->sdma.trap_irq,
 972                                      (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
 973                                      AMDGPU_SDMA_IRQ_INSTANCE1,
 974                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
 975                 if (r)
 976                         return r;
 977         }
 978
 979         return r;
 980 }
 981
 982 static int cik_sdma_sw_fini(struct amdgpu_ip_block *ip_block)
 983 {
 984         struct amdgpu_device *adev = ip_block->adev;
 985         int i;
 986
 987         for (i = 0; i < adev->sdma.num_instances; i++)
 988                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 989
 990         cik_sdma_free_microcode(adev);
 991         return 0;
 992 }
 993
 994 static int cik_sdma_hw_init(struct amdgpu_ip_block *ip_block)
 995 {
 996         int r;
 997         struct amdgpu_device *adev = ip_block->adev;
 998
 999         r = cik_sdma_start(adev);
1000         if (r)
1001                 return r;
1002
1003         return r;
1004 }
1005
1006 static int cik_sdma_hw_fini(struct amdgpu_ip_block *ip_block)
1007 {
1008         struct amdgpu_device *adev = ip_block->adev;
1009
1010         cik_ctx_switch_enable(adev, false);
1011         cik_sdma_enable(adev, false);
1012
1013         return 0;
1014 }
1015
1016 static int cik_sdma_suspend(struct amdgpu_ip_block *ip_block)
1017 {
1018         return cik_sdma_hw_fini(ip_block);
1019 }
1020
1021 static int cik_sdma_resume(struct amdgpu_ip_block *ip_block)
1022 {
1023         cik_sdma_soft_reset(ip_block);
1024
1025         return cik_sdma_hw_init(ip_block);
1026 }
1027
1028 static bool cik_sdma_is_idle(void *handle)
1029 {
1030         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1031         u32 tmp = RREG32(mmSRBM_STATUS2);
1032
1033         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1034                                 SRBM_STATUS2__SDMA1_BUSY_MASK))
1035             return false;
1036
1037         return true;
1038 }
1039
1040 static int cik_sdma_wait_for_idle(struct amdgpu_ip_block *ip_block)
1041 {
1042         unsigned i;
1043         u32 tmp;
1044         struct amdgpu_device *adev = ip_block->adev;
1045
1046         for (i = 0; i < adev->usec_timeout; i++) {
1047                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1048                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1049
1050                 if (!tmp)
1051                         return 0;
1052                 udelay(1);
1053         }
1054         return -ETIMEDOUT;
1055 }
1056
1057 static int cik_sdma_soft_reset(struct amdgpu_ip_block *ip_block)
1058 {
1059         u32 srbm_soft_reset = 0;
1060         struct amdgpu_device *adev = ip_block->adev;
1061         u32 tmp;
1062
1063         /* sdma0 */
1064         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1065         tmp |= SDMA0_F32_CNTL__HALT_MASK;
1066         WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1067         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1068
1069         /* sdma1 */
1070         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1071         tmp |= SDMA0_F32_CNTL__HALT_MASK;
1072         WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1073         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1074
1075         if (srbm_soft_reset) {
1076                 tmp = RREG32(mmSRBM_SOFT_RESET);
1077                 tmp |= srbm_soft_reset;
1078                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1079                 WREG32(mmSRBM_SOFT_RESET, tmp);
1080                 tmp = RREG32(mmSRBM_SOFT_RESET);
1081
1082                 udelay(50);
1083
1084                 tmp &= ~srbm_soft_reset;
1085                 WREG32(mmSRBM_SOFT_RESET, tmp);
1086                 tmp = RREG32(mmSRBM_SOFT_RESET);
1087
1088                 /* Wait a little for things to settle down */
1089                 udelay(50);
1090         }
1091
1092         return 0;
1093 }
1094
1095 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1096                                        struct amdgpu_irq_src *src,
1097                                        unsigned type,
1098                                        enum amdgpu_interrupt_state state)
1099 {
1100         u32 sdma_cntl;
1101
1102         switch (type) {
1103         case AMDGPU_SDMA_IRQ_INSTANCE0:
1104                 switch (state) {
1105                 case AMDGPU_IRQ_STATE_DISABLE:
1106                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1107                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1108                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1109                         break;
1110                 case AMDGPU_IRQ_STATE_ENABLE:
1111                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1112                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1113                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1114                         break;
1115                 default:
1116                         break;
1117                 }
1118                 break;
1119         case AMDGPU_SDMA_IRQ_INSTANCE1:
1120                 switch (state) {
1121                 case AMDGPU_IRQ_STATE_DISABLE:
1122                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1123                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1124                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1125                         break;
1126                 case AMDGPU_IRQ_STATE_ENABLE:
1127                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1128                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1129                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1130                         break;
1131                 default:
1132                         break;
1133                 }
1134                 break;
1135         default:
1136                 break;
1137         }
1138         return 0;
1139 }
1140
1141 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1142                                      struct amdgpu_irq_src *source,
1143                                      struct amdgpu_iv_entry *entry)
1144 {
1145         u8 instance_id, queue_id;
1146
1147         instance_id = (entry->ring_id & 0x3) >> 0;
1148         queue_id = (entry->ring_id & 0xc) >> 2;
1149         DRM_DEBUG("IH: SDMA trap\n");
1150         switch (instance_id) {
1151         case 0:
1152                 switch (queue_id) {
1153                 case 0:
1154                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1155                         break;
1156                 case 1:
1157                         /* XXX compute */
1158                         break;
1159                 case 2:
1160                         /* XXX compute */
1161                         break;
1162                 }
1163                 break;
1164         case 1:
1165                 switch (queue_id) {
1166                 case 0:
1167                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1168                         break;
1169                 case 1:
1170                         /* XXX compute */
1171                         break;
1172                 case 2:
1173                         /* XXX compute */
1174                         break;
1175                 }
1176                 break;
1177         }
1178
1179         return 0;
1180 }
1181
1182 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1183                                              struct amdgpu_irq_src *source,
1184                                              struct amdgpu_iv_entry *entry)
1185 {
1186         u8 instance_id;
1187
1188         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1189         instance_id = (entry->ring_id & 0x3) >> 0;
1190         drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1191         return 0;
1192 }
1193
1194 static int cik_sdma_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1195                                           enum amd_clockgating_state state)
1196 {
1197         bool gate = false;
1198         struct amdgpu_device *adev = ip_block->adev;
1199
1200         if (state == AMD_CG_STATE_GATE)
1201                 gate = true;
1202
1203         cik_enable_sdma_mgcg(adev, gate);
1204         cik_enable_sdma_mgls(adev, gate);
1205
1206         return 0;
1207 }
1208
1209 static int cik_sdma_set_powergating_state(struct amdgpu_ip_block *ip_block,
1210                                           enum amd_powergating_state state)
1211 {
1212         return 0;
1213 }
1214
1215 static const struct amd_ip_funcs cik_sdma_ip_funcs = {
1216         .name = "cik_sdma",
1217         .early_init = cik_sdma_early_init,
1218         .sw_init = cik_sdma_sw_init,
1219         .sw_fini = cik_sdma_sw_fini,
1220         .hw_init = cik_sdma_hw_init,
1221         .hw_fini = cik_sdma_hw_fini,
1222         .suspend = cik_sdma_suspend,
1223         .resume = cik_sdma_resume,
1224         .is_idle = cik_sdma_is_idle,
1225         .wait_for_idle = cik_sdma_wait_for_idle,
1226         .soft_reset = cik_sdma_soft_reset,
1227         .set_clockgating_state = cik_sdma_set_clockgating_state,
1228         .set_powergating_state = cik_sdma_set_powergating_state,
1229 };
1230
1231 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1232         .type = AMDGPU_RING_TYPE_SDMA,
1233         .align_mask = 0xf,
1234         .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0),
1235         .support_64bit_ptrs = false,
1236         .get_rptr = cik_sdma_ring_get_rptr,
1237         .get_wptr = cik_sdma_ring_get_wptr,
1238         .set_wptr = cik_sdma_ring_set_wptr,
1239         .emit_frame_size =
1240                 6 + /* cik_sdma_ring_emit_hdp_flush */
1241                 3 + /* hdp invalidate */
1242                 6 + /* cik_sdma_ring_emit_pipeline_sync */
1243                 CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */
1244                 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
1245         .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
1246         .emit_ib = cik_sdma_ring_emit_ib,
1247         .emit_fence = cik_sdma_ring_emit_fence,
1248         .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1249         .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1250         .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1251         .test_ring = cik_sdma_ring_test_ring,
1252         .test_ib = cik_sdma_ring_test_ib,
1253         .insert_nop = cik_sdma_ring_insert_nop,
1254         .pad_ib = cik_sdma_ring_pad_ib,
1255         .emit_wreg = cik_sdma_ring_emit_wreg,
1256 };
1257
1258 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1259 {
1260         int i;
1261
1262         for (i = 0; i < adev->sdma.num_instances; i++) {
1263                 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1264                 adev->sdma.instance[i].ring.me = i;
1265         }
1266 }
1267
1268 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1269         .set = cik_sdma_set_trap_irq_state,
1270         .process = cik_sdma_process_trap_irq,
1271 };
1272
1273 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1274         .process = cik_sdma_process_illegal_inst_irq,
1275 };
1276
1277 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1278 {
1279         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1280         adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1281         adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1282 }
1283
1284 /**
1285  * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1286  *
1287  * @ib: indirect buffer to copy to
1288  * @src_offset: src GPU address
1289  * @dst_offset: dst GPU address
1290  * @byte_count: number of bytes to xfer
1291  * @copy_flags: unused
1292  *
1293  * Copy GPU buffers using the DMA engine (CIK).
1294  * Used by the amdgpu ttm implementation to move pages if
1295  * registered as the asic copy callback.
1296  */
1297 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1298                                       uint64_t src_offset,
1299                                       uint64_t dst_offset,
1300                                       uint32_t byte_count,
1301                                       uint32_t copy_flags)
1302 {
1303         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1304         ib->ptr[ib->length_dw++] = byte_count;
1305         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1306         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1307         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1308         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1309         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1310 }
1311
1312 /**
1313  * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1314  *
1315  * @ib: indirect buffer to fill
1316  * @src_data: value to write to buffer
1317  * @dst_offset: dst GPU address
1318  * @byte_count: number of bytes to xfer
1319  *
1320  * Fill GPU buffers using the DMA engine (CIK).
1321  */
1322 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1323                                       uint32_t src_data,
1324                                       uint64_t dst_offset,
1325                                       uint32_t byte_count)
1326 {
1327         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1328         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1329         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1330         ib->ptr[ib->length_dw++] = src_data;
1331         ib->ptr[ib->length_dw++] = byte_count;
1332 }
1333
1334 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1335         .copy_max_bytes = 0x1fffff,
1336         .copy_num_dw = 7,
1337         .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1338
1339         .fill_max_bytes = 0x1fffff,
1340         .fill_num_dw = 5,
1341         .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1342 };
1343
1344 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1345 {
1346         adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1347         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1348 }
1349
1350 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1351         .copy_pte_num_dw = 7,
1352         .copy_pte = cik_sdma_vm_copy_pte,
1353
1354         .write_pte = cik_sdma_vm_write_pte,
1355         .set_pte_pde = cik_sdma_vm_set_pte_pde,
1356 };
1357
1358 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1359 {
1360         unsigned i;
1361
1362         adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1363         for (i = 0; i < adev->sdma.num_instances; i++) {
1364                 adev->vm_manager.vm_pte_scheds[i] =
1365                         &adev->sdma.instance[i].ring.sched;
1366         }
1367         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1368 }
1369
1370 const struct amdgpu_ip_block_version cik_sdma_ip_block =
1371 {
1372         .type = AMD_IP_BLOCK_TYPE_SDMA,
1373         .major = 2,
1374         .minor = 0,
1375         .rev = 0,
1376         .funcs = &cik_sdma_ip_funcs,
1377 };