drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_1_0_offset.h"
  34 #include "gc/gc_10_1_0_sh_mask.h"
  35 #include "hdp/hdp_5_0_0_offset.h"
  36 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  37 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  38
  39 #include "soc15_common.h"
  40 #include "soc15.h"
  41 #include "navi10_sdma_pkt_open.h"
  42 #include "nbio_v2_3.h"
  43 #include "sdma_common.h"
  44 #include "sdma_v5_0.h"
  45
  46 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
  47 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
  48
  49 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
  50 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
  51
  52 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
  53 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
  54
  55 #define SDMA1_REG_OFFSET 0x600
  56 #define SDMA0_HYP_DEC_REG_START 0x5880
  57 #define SDMA0_HYP_DEC_REG_END 0x5893
  58 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  59
  60 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
  61 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
  62 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  63 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
  64
  65 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
  66         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  67         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  68         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  69         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  70         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  71         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  72         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  73         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  74         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  75         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  76         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  77         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
  78         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  79         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  80         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  81         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  82         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  83         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  84         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  85         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  86         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  87         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  88         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  89         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
  90 };
  91
  92 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
  93         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 113 };
 114
 115 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 118 };
 119
 120 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 123 };
 124
 125 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
 126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 128 };
 129
 130 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
 131 {
 132         u32 base;
 133
 134         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
 135             internal_offset <= SDMA0_HYP_DEC_REG_END) {
 136                 base = adev->reg_offset[GC_HWIP][0][1];
 137                 if (instance == 1)
 138                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
 139         } else {
 140                 base = adev->reg_offset[GC_HWIP][0][0];
 141                 if (instance == 1)
 142                         internal_offset += SDMA1_REG_OFFSET;
 143         }
 144
 145         return base + internal_offset;
 146 }
 147
 148 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
 149 {
 150         switch (adev->asic_type) {
 151         case CHIP_NAVI10:
 152                 soc15_program_register_sequence(adev,
 153                                                 golden_settings_sdma_5,
 154                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 155                 soc15_program_register_sequence(adev,
 156                                                 golden_settings_sdma_nv10,
 157                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
 158                 break;
 159         case CHIP_NAVI14:
 160                 soc15_program_register_sequence(adev,
 161                                                 golden_settings_sdma_5,
 162                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 163                 soc15_program_register_sequence(adev,
 164                                                 golden_settings_sdma_nv14,
 165                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
 166                 break;
 167         case CHIP_NAVI12:
 168                 if (amdgpu_sriov_vf(adev))
 169                         soc15_program_register_sequence(adev,
 170                                                         golden_settings_sdma_5_sriov,
 171                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
 172                 else
 173                         soc15_program_register_sequence(adev,
 174                                                         golden_settings_sdma_5,
 175                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 176                 soc15_program_register_sequence(adev,
 177                                                 golden_settings_sdma_nv12,
 178                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
 179                 break;
 180         default:
 181                 break;
 182         }
 183 }
 184
 185 /**
 186  * sdma_v5_0_init_microcode - load ucode images from disk
 187  *
 188  * @adev: amdgpu_device pointer
 189  *
 190  * Use the firmware interface to load the ucode images into
 191  * the driver (not loaded into hw).
 192  * Returns 0 on success, error on failure.
 193  */
 194
 195 // emulation only, won't work on real chip
 196 // navi10 real chip need to use PSP to load firmware
 197 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
 198 {
 199         const char *chip_name;
 200         char fw_name[30];
 201         int err = 0, i;
 202         struct amdgpu_firmware_info *info = NULL;
 203         const struct common_firmware_header *header = NULL;
 204         const struct sdma_firmware_header_v1_0 *hdr;
 205
 206         DRM_DEBUG("\n");
 207
 208         switch (adev->asic_type) {
 209         case CHIP_NAVI10:
 210                 chip_name = "navi10";
 211                 break;
 212         case CHIP_NAVI14:
 213                 chip_name = "navi14";
 214                 break;
 215         case CHIP_NAVI12:
 216                 chip_name = "navi12";
 217                 break;
 218         default:
 219                 BUG();
 220         }
 221
 222         for (i = 0; i < adev->sdma.num_instances; i++) {
 223                 if (i == 0)
 224                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 225                 else
 226                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 227                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 228                 if (err)
 229                         goto out;
 230                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 231                 if (err)
 232                         goto out;
 233                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 234                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 235                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 236                 if (adev->sdma.instance[i].feature_version >= 20)
 237                         adev->sdma.instance[i].burst_nop = true;
 238                 DRM_DEBUG("psp_load == '%s'\n",
 239                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 240
 241                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 242                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 243                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 244                         info->fw = adev->sdma.instance[i].fw;
 245                         header = (const struct common_firmware_header *)info->fw->data;
 246                         adev->firmware.fw_size +=
 247                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 248                 }
 249         }
 250 out:
 251         if (err) {
 252                 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name);
 253                 for (i = 0; i < adev->sdma.num_instances; i++) {
 254                         release_firmware(adev->sdma.instance[i].fw);
 255                         adev->sdma.instance[i].fw = NULL;
 256                 }
 257         }
 258         return err;
 259 }
 260
 261 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
 262 {
 263         unsigned ret;
 264
 265         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 266         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 267         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 268         amdgpu_ring_write(ring, 1);
 269         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 270         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 271
 272         return ret;
 273 }
 274
 275 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
 276                                            unsigned offset)
 277 {
 278         unsigned cur;
 279
 280         BUG_ON(offset > ring->buf_mask);
 281         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 282
 283         cur = (ring->wptr - 1) & ring->buf_mask;
 284         if (cur > offset)
 285                 ring->ring[offset] = cur - offset;
 286         else
 287                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 288 }
 289
 290 /**
 291  * sdma_v5_0_ring_get_rptr - get the current read pointer
 292  *
 293  * @ring: amdgpu ring pointer
 294  *
 295  * Get the current rptr from the hardware (NAVI10+).
 296  */
 297 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
 298 {
 299         u64 *rptr;
 300
 301         /* XXX check if swapping is necessary on BE */
 302         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 303
 304         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 305         return ((*rptr) >> 2);
 306 }
 307
 308 /**
 309  * sdma_v5_0_ring_get_wptr - get the current write pointer
 310  *
 311  * @ring: amdgpu ring pointer
 312  *
 313  * Get the current wptr from the hardware (NAVI10+).
 314  */
 315 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
 316 {
 317         struct amdgpu_device *adev = ring->adev;
 318         u64 wptr;
 319
 320         if (ring->use_doorbell) {
 321                 /* XXX check if swapping is necessary on BE */
 322                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 323                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 324         } else {
 325                 wptr = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 326                 wptr = wptr << 32;
 327                 wptr |= RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 328                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 329         }
 330
 331         return wptr >> 2;
 332 }
 333
 334 /**
 335  * sdma_v5_0_ring_set_wptr - commit the write pointer
 336  *
 337  * @ring: amdgpu ring pointer
 338  *
 339  * Write the wptr back to the hardware (NAVI10+).
 340  */
 341 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
 342 {
 343         struct amdgpu_device *adev = ring->adev;
 344
 345         DRM_DEBUG("Setting write pointer\n");
 346         if (ring->use_doorbell) {
 347                 DRM_DEBUG("Using doorbell -- "
 348                                 "wptr_offs == 0x%08x "
 349                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 350                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 351                                 ring->wptr_offs,
 352                                 lower_32_bits(ring->wptr << 2),
 353                                 upper_32_bits(ring->wptr << 2));
 354                 /* XXX check if swapping is necessary on BE */
 355                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 356                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 357                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 358                                 ring->doorbell_index, ring->wptr << 2);
 359                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 360         } else {
 361                 DRM_DEBUG("Not using doorbell -- "
 362                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 363                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 364                                 ring->me,
 365                                 lower_32_bits(ring->wptr << 2),
 366                                 ring->me,
 367                                 upper_32_bits(ring->wptr << 2));
 368                 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 369                         lower_32_bits(ring->wptr << 2));
 370                 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 371                         upper_32_bits(ring->wptr << 2));
 372         }
 373 }
 374
 375 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 376 {
 377         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 378         int i;
 379
 380         for (i = 0; i < count; i++)
 381                 if (sdma && sdma->burst_nop && (i == 0))
 382                         amdgpu_ring_write(ring, ring->funcs->nop |
 383                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 384                 else
 385                         amdgpu_ring_write(ring, ring->funcs->nop);
 386 }
 387
 388 /**
 389  * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
 390  *
 391  * @ring: amdgpu ring pointer
 392  * @ib: IB object to schedule
 393  *
 394  * Schedule an IB in the DMA ring (NAVI10).
 395  */
 396 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 397                                    struct amdgpu_job *job,
 398                                    struct amdgpu_ib *ib,
 399                                    uint32_t flags)
 400 {
 401         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 402         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 403
 404         /* Invalidate L2, because if we don't do it, we might get stale cache
 405          * lines from previous IBs.
 406          */
 407         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
 408         amdgpu_ring_write(ring, 0);
 409         amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV |
 410                                  SDMA_GCR_GL2_WB |
 411                                  SDMA_GCR_GLM_INV |
 412                                  SDMA_GCR_GLM_WB) << 16);
 413         amdgpu_ring_write(ring, 0xffffff80);
 414         amdgpu_ring_write(ring, 0xffff);
 415
 416         /* An IB packet must end on a 8 DW boundary--the next dword
 417          * must be on a 8-dword boundary. Our IB packet below is 6
 418          * dwords long, thus add x number of NOPs, such that, in
 419          * modular arithmetic,
 420          * wptr + 6 + x = 8k, k >= 0, which in C is,
 421          * (wptr + 6 + x) % 8 = 0.
 422          * The expression below, is a solution of x.
 423          */
 424         sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 425
 426         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 427                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 428         /* base must be 32 byte aligned */
 429         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 430         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 431         amdgpu_ring_write(ring, ib->length_dw);
 432         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 433         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 434 }
 435
 436 /**
 437  * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 438  *
 439  * @ring: amdgpu ring pointer
 440  *
 441  * Emit an hdp flush packet on the requested DMA ring.
 442  */
 443 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 444 {
 445         struct amdgpu_device *adev = ring->adev;
 446         u32 ref_and_mask = 0;
 447         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 448
 449         if (ring->me == 0)
 450                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 451         else
 452                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 453
 454         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 455                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 456                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 457         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 458         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 459         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 460         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 461         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 462                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 463 }
 464
 465 /**
 466  * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
 467  *
 468  * @ring: amdgpu ring pointer
 469  * @fence: amdgpu fence object
 470  *
 471  * Add a DMA fence packet to the ring to write
 472  * the fence seq number and DMA trap packet to generate
 473  * an interrupt if needed (NAVI10).
 474  */
 475 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 476                                       unsigned flags)
 477 {
 478         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 479         /* write the fence */
 480         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 481                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 482         /* zero in first two bits */
 483         BUG_ON(addr & 0x3);
 484         amdgpu_ring_write(ring, lower_32_bits(addr));
 485         amdgpu_ring_write(ring, upper_32_bits(addr));
 486         amdgpu_ring_write(ring, lower_32_bits(seq));
 487
 488         /* optionally write high bits as well */
 489         if (write64bit) {
 490                 addr += 4;
 491                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 492                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 493                 /* zero in first two bits */
 494                 BUG_ON(addr & 0x3);
 495                 amdgpu_ring_write(ring, lower_32_bits(addr));
 496                 amdgpu_ring_write(ring, upper_32_bits(addr));
 497                 amdgpu_ring_write(ring, upper_32_bits(seq));
 498         }
 499
 500         if (flags & AMDGPU_FENCE_FLAG_INT) {
 501                 /* generate an interrupt */
 502                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 503                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 504         }
 505 }
 506
 507
 508 /**
 509  * sdma_v5_0_gfx_stop - stop the gfx async dma engines
 510  *
 511  * @adev: amdgpu_device pointer
 512  *
 513  * Stop the gfx async dma ring buffers (NAVI10).
 514  */
 515 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
 516 {
 517         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 518         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 519         u32 rb_cntl, ib_cntl;
 520         int i;
 521
 522         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 523             (adev->mman.buffer_funcs_ring == sdma1))
 524                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 525
 526         for (i = 0; i < adev->sdma.num_instances; i++) {
 527                 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 528                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 529                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 530                 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 531                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 532                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 533         }
 534 }
 535
 536 /**
 537  * sdma_v5_0_rlc_stop - stop the compute async dma engines
 538  *
 539  * @adev: amdgpu_device pointer
 540  *
 541  * Stop the compute async dma queues (NAVI10).
 542  */
 543 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
 544 {
 545         /* XXX todo */
 546 }
 547
 548 /**
 549  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 550  *
 551  * @adev: amdgpu_device pointer
 552  * @enable: enable/disable the DMA MEs context switch.
 553  *
 554  * Halt or unhalt the async dma engines context switch (NAVI10).
 555  */
 556 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 557 {
 558         u32 f32_cntl = 0, phase_quantum = 0;
 559         int i;
 560
 561         if (amdgpu_sdma_phase_quantum) {
 562                 unsigned value = amdgpu_sdma_phase_quantum;
 563                 unsigned unit = 0;
 564
 565                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 566                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 567                         value = (value + 1) >> 1;
 568                         unit++;
 569                 }
 570                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 571                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 572                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 573                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 574                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 575                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 576                         WARN_ONCE(1,
 577                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 578                                   value << unit);
 579                 }
 580                 phase_quantum =
 581                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 582                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 583         }
 584
 585         for (i = 0; i < adev->sdma.num_instances; i++) {
 586                 if (!amdgpu_sriov_vf(adev)) {
 587                         f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 588                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 589                                                  AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 590                 }
 591
 592                 if (enable && amdgpu_sdma_phase_quantum) {
 593                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 594                                phase_quantum);
 595                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 596                                phase_quantum);
 597                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 598                                phase_quantum);
 599                 }
 600                 if (!amdgpu_sriov_vf(adev))
 601                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 602         }
 603
 604 }
 605
 606 /**
 607  * sdma_v5_0_enable - stop the async dma engines
 608  *
 609  * @adev: amdgpu_device pointer
 610  * @enable: enable/disable the DMA MEs.
 611  *
 612  * Halt or unhalt the async dma engines (NAVI10).
 613  */
 614 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
 615 {
 616         u32 f32_cntl;
 617         int i;
 618
 619         if (enable == false) {
 620                 sdma_v5_0_gfx_stop(adev);
 621                 sdma_v5_0_rlc_stop(adev);
 622         }
 623
 624         if (amdgpu_sriov_vf(adev))
 625                 return;
 626
 627         for (i = 0; i < adev->sdma.num_instances; i++) {
 628                 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 629                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 630                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 631         }
 632 }
 633
 634 /**
 635  * sdma_v5_0_gfx_resume - setup and start the async dma engines
 636  *
 637  * @adev: amdgpu_device pointer
 638  *
 639  * Set up the gfx DMA ring buffers and enable them (NAVI10).
 640  * Returns 0 for success, error for failure.
 641  */
 642 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 643 {
 644         struct amdgpu_ring *ring;
 645         u32 rb_cntl, ib_cntl;
 646         u32 rb_bufsz;
 647         u32 wb_offset;
 648         u32 doorbell;
 649         u32 doorbell_offset;
 650         u32 temp;
 651         u32 wptr_poll_cntl;
 652         u64 wptr_gpu_addr;
 653         int i, r;
 654
 655         for (i = 0; i < adev->sdma.num_instances; i++) {
 656                 ring = &adev->sdma.instance[i].ring;
 657                 wb_offset = (ring->rptr_offs * 4);
 658
 659                 if (!amdgpu_sriov_vf(adev))
 660                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 661
 662                 /* Set ring buffer size in dwords */
 663                 rb_bufsz = order_base_2(ring->ring_size / 4);
 664                 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 665                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 666 #ifdef __BIG_ENDIAN
 667                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 668                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 669                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 670 #endif
 671                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 672
 673                 /* Initialize the ring buffer's read and write pointers */
 674                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 675                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 676                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 677                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 678
 679                 /* setup the wptr shadow polling */
 680                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 681                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 682                        lower_32_bits(wptr_gpu_addr));
 683                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 684                        upper_32_bits(wptr_gpu_addr));
 685                 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
 686                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 687                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 688                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 689                                                F32_POLL_ENABLE, 1);
 690                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 691                        wptr_poll_cntl);
 692
 693                 /* set the wb address whether it's enabled or not */
 694                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 695                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 696                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 697                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 698
 699                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 700
 701                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 702                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 703
 704                 ring->wptr = 0;
 705
 706                 /* before programing wptr to a less value, need set minor_ptr_update first */
 707                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 708
 709                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 710                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 711                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 712                 }
 713
 714                 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 715                 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 716
 717                 if (ring->use_doorbell) {
 718                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 719                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 720                                         OFFSET, ring->doorbell_index);
 721                 } else {
 722                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 723                 }
 724                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 725                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 726
 727                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 728                                                       ring->doorbell_index, 20);
 729
 730                 if (amdgpu_sriov_vf(adev))
 731                         sdma_v5_0_ring_set_wptr(ring);
 732
 733                 /* set minor_ptr_update to 0 after wptr programed */
 734                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 735
 736                 if (!amdgpu_sriov_vf(adev)) {
 737                         /* set utc l1 enable flag always to 1 */
 738                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 739                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 740
 741                         /* enable MCBP */
 742                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 743                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 744
 745                         /* Set up RESP_MODE to non-copy addresses */
 746                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 747                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 748                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 749                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 750
 751                         /* program default cache read and write policy */
 752                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 753                         /* clean read policy and write policy bits */
 754                         temp &= 0xFF0FFF;
 755                         temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
 756                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 757                 }
 758
 759                 if (!amdgpu_sriov_vf(adev)) {
 760                         /* unhalt engine */
 761                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 762                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 763                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 764                 }
 765
 766                 /* enable DMA RB */
 767                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 768                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 769
 770                 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 771                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 772 #ifdef __BIG_ENDIAN
 773                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 774 #endif
 775                 /* enable DMA IBs */
 776                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 777
 778                 ring->sched.ready = true;
 779
 780                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 781                         sdma_v5_0_ctx_switch_enable(adev, true);
 782                         sdma_v5_0_enable(adev, true);
 783                 }
 784
 785                 r = amdgpu_ring_test_helper(ring);
 786                 if (r)
 787                         return r;
 788
 789                 if (adev->mman.buffer_funcs_ring == ring)
 790                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 791         }
 792
 793         return 0;
 794 }
 795
 796 /**
 797  * sdma_v5_0_rlc_resume - setup and start the async dma engines
 798  *
 799  * @adev: amdgpu_device pointer
 800  *
 801  * Set up the compute DMA queues and enable them (NAVI10).
 802  * Returns 0 for success, error for failure.
 803  */
 804 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
 805 {
 806         return 0;
 807 }
 808
 809 /**
 810  * sdma_v5_0_load_microcode - load the sDMA ME ucode
 811  *
 812  * @adev: amdgpu_device pointer
 813  *
 814  * Loads the sDMA0/1 ucode.
 815  * Returns 0 for success, -EINVAL if the ucode is not available.
 816  */
 817 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
 818 {
 819         const struct sdma_firmware_header_v1_0 *hdr;
 820         const __le32 *fw_data;
 821         u32 fw_size;
 822         int i, j;
 823
 824         /* halt the MEs */
 825         sdma_v5_0_enable(adev, false);
 826
 827         for (i = 0; i < adev->sdma.num_instances; i++) {
 828                 if (!adev->sdma.instance[i].fw)
 829                         return -EINVAL;
 830
 831                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 832                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 833                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 834
 835                 fw_data = (const __le32 *)
 836                         (adev->sdma.instance[i].fw->data +
 837                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 838
 839                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 840
 841                 for (j = 0; j < fw_size; j++) {
 842                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 843                                 msleep(1);
 844                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 845                 }
 846
 847                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 848         }
 849
 850         return 0;
 851 }
 852
 853 /**
 854  * sdma_v5_0_start - setup and start the async dma engines
 855  *
 856  * @adev: amdgpu_device pointer
 857  *
 858  * Set up the DMA engines and enable them (NAVI10).
 859  * Returns 0 for success, error for failure.
 860  */
 861 static int sdma_v5_0_start(struct amdgpu_device *adev)
 862 {
 863         int r = 0;
 864
 865         if (amdgpu_sriov_vf(adev)) {
 866                 sdma_v5_0_ctx_switch_enable(adev, false);
 867                 sdma_v5_0_enable(adev, false);
 868
 869                 /* set RB registers */
 870                 r = sdma_v5_0_gfx_resume(adev);
 871                 return r;
 872         }
 873
 874         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 875                 r = sdma_v5_0_load_microcode(adev);
 876                 if (r)
 877                         return r;
 878         }
 879
 880         /* unhalt the MEs */
 881         sdma_v5_0_enable(adev, true);
 882         /* enable sdma ring preemption */
 883         sdma_v5_0_ctx_switch_enable(adev, true);
 884
 885         /* start the gfx rings and rlc compute queues */
 886         r = sdma_v5_0_gfx_resume(adev);
 887         if (r)
 888                 return r;
 889         r = sdma_v5_0_rlc_resume(adev);
 890
 891         return r;
 892 }
 893
 894 /**
 895  * sdma_v5_0_ring_test_ring - simple async dma engine test
 896  *
 897  * @ring: amdgpu_ring structure holding ring information
 898  *
 899  * Test the DMA engine by writing using it to write an
 900  * value to memory. (NAVI10).
 901  * Returns 0 for success, error for failure.
 902  */
 903 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
 904 {
 905         struct amdgpu_device *adev = ring->adev;
 906         unsigned i;
 907         unsigned index;
 908         int r;
 909         u32 tmp;
 910         u64 gpu_addr;
 911
 912         r = amdgpu_device_wb_get(adev, &index);
 913         if (r) {
 914                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 915                 return r;
 916         }
 917
 918         gpu_addr = adev->wb.gpu_addr + (index * 4);
 919         tmp = 0xCAFEDEAD;
 920         adev->wb.wb[index] = cpu_to_le32(tmp);
 921
 922         r = amdgpu_ring_alloc(ring, 5);
 923         if (r) {
 924                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 925                 amdgpu_device_wb_free(adev, index);
 926                 return r;
 927         }
 928
 929         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 930                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 931         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 932         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 933         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 934         amdgpu_ring_write(ring, 0xDEADBEEF);
 935         amdgpu_ring_commit(ring);
 936
 937         for (i = 0; i < adev->usec_timeout; i++) {
 938                 tmp = le32_to_cpu(adev->wb.wb[index]);
 939                 if (tmp == 0xDEADBEEF)
 940                         break;
 941                 if (amdgpu_emu_mode == 1)
 942                         msleep(1);
 943                 else
 944                         udelay(1);
 945         }
 946
 947         if (i >= adev->usec_timeout)
 948                 r = -ETIMEDOUT;
 949
 950         amdgpu_device_wb_free(adev, index);
 951
 952         return r;
 953 }
 954
 955 /**
 956  * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
 957  *
 958  * @ring: amdgpu_ring structure holding ring information
 959  *
 960  * Test a simple IB in the DMA ring (NAVI10).
 961  * Returns 0 on success, error on failure.
 962  */
 963 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 964 {
 965         struct amdgpu_device *adev = ring->adev;
 966         struct amdgpu_ib ib;
 967         struct dma_fence *f = NULL;
 968         unsigned index;
 969         long r;
 970         u32 tmp = 0;
 971         u64 gpu_addr;
 972
 973         r = amdgpu_device_wb_get(adev, &index);
 974         if (r) {
 975                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 976                 return r;
 977         }
 978
 979         gpu_addr = adev->wb.gpu_addr + (index * 4);
 980         tmp = 0xCAFEDEAD;
 981         adev->wb.wb[index] = cpu_to_le32(tmp);
 982         memset(&ib, 0, sizeof(ib));
 983         r = amdgpu_ib_get(adev, NULL, 256,
 984                                         AMDGPU_IB_POOL_DIRECT, &ib);
 985         if (r) {
 986                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 987                 goto err0;
 988         }
 989
 990         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 991                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 992         ib.ptr[1] = lower_32_bits(gpu_addr);
 993         ib.ptr[2] = upper_32_bits(gpu_addr);
 994         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 995         ib.ptr[4] = 0xDEADBEEF;
 996         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 997         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 998         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 999         ib.length_dw = 8;
1000
1001         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1002         if (r)
1003                 goto err1;
1004
1005         r = dma_fence_wait_timeout(f, false, timeout);
1006         if (r == 0) {
1007                 DRM_ERROR("amdgpu: IB test timed out\n");
1008                 r = -ETIMEDOUT;
1009                 goto err1;
1010         } else if (r < 0) {
1011                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1012                 goto err1;
1013         }
1014         tmp = le32_to_cpu(adev->wb.wb[index]);
1015         if (tmp == 0xDEADBEEF)
1016                 r = 0;
1017         else
1018                 r = -EINVAL;
1019
1020 err1:
1021         amdgpu_ib_free(adev, &ib, NULL);
1022         dma_fence_put(f);
1023 err0:
1024         amdgpu_device_wb_free(adev, index);
1025         return r;
1026 }
1027
1028
1029 /**
1030  * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1031  *
1032  * @ib: indirect buffer to fill with commands
1033  * @pe: addr of the page entry
1034  * @src: src addr to copy from
1035  * @count: number of page entries to update
1036  *
1037  * Update PTEs by copying them from the GART using sDMA (NAVI10).
1038  */
1039 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1040                                   uint64_t pe, uint64_t src,
1041                                   unsigned count)
1042 {
1043         unsigned bytes = count * 8;
1044
1045         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1046                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1047         ib->ptr[ib->length_dw++] = bytes - 1;
1048         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1049         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1050         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1051         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1052         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1053
1054 }
1055
1056 /**
1057  * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1058  *
1059  * @ib: indirect buffer to fill with commands
1060  * @pe: addr of the page entry
1061  * @addr: dst addr to write into pe
1062  * @count: number of page entries to update
1063  * @incr: increase next addr by incr bytes
1064  * @flags: access flags
1065  *
1066  * Update PTEs by writing them manually using sDMA (NAVI10).
1067  */
1068 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1069                                    uint64_t value, unsigned count,
1070                                    uint32_t incr)
1071 {
1072         unsigned ndw = count * 2;
1073
1074         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1075                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1076         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1077         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1078         ib->ptr[ib->length_dw++] = ndw - 1;
1079         for (; ndw > 0; ndw -= 2) {
1080                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1081                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1082                 value += incr;
1083         }
1084 }
1085
1086 /**
1087  * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1088  *
1089  * @ib: indirect buffer to fill with commands
1090  * @pe: addr of the page entry
1091  * @addr: dst addr to write into pe
1092  * @count: number of page entries to update
1093  * @incr: increase next addr by incr bytes
1094  * @flags: access flags
1095  *
1096  * Update the page tables using sDMA (NAVI10).
1097  */
1098 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1099                                      uint64_t pe,
1100                                      uint64_t addr, unsigned count,
1101                                      uint32_t incr, uint64_t flags)
1102 {
1103         /* for physically contiguous pages (vram) */
1104         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1105         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1106         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1107         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1108         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1109         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1110         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1111         ib->ptr[ib->length_dw++] = incr; /* increment size */
1112         ib->ptr[ib->length_dw++] = 0;
1113         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1114 }
1115
1116 /**
1117  * sdma_v5_0_ring_pad_ib - pad the IB
1118  * @ib: indirect buffer to fill with padding
1119  *
1120  * Pad the IB with NOPs to a boundary multiple of 8.
1121  */
1122 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1123 {
1124         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1125         u32 pad_count;
1126         int i;
1127
1128         pad_count = (-ib->length_dw) & 0x7;
1129         for (i = 0; i < pad_count; i++)
1130                 if (sdma && sdma->burst_nop && (i == 0))
1131                         ib->ptr[ib->length_dw++] =
1132                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1133                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1134                 else
1135                         ib->ptr[ib->length_dw++] =
1136                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1137 }
1138
1139
1140 /**
1141  * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1142  *
1143  * @ring: amdgpu_ring pointer
1144  *
1145  * Make sure all previous operations are completed (CIK).
1146  */
1147 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1148 {
1149         uint32_t seq = ring->fence_drv.sync_seq;
1150         uint64_t addr = ring->fence_drv.gpu_addr;
1151
1152         /* wait for idle */
1153         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1154                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1155                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1156                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1157         amdgpu_ring_write(ring, addr & 0xfffffffc);
1158         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1159         amdgpu_ring_write(ring, seq); /* reference */
1160         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1161         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1162                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1163 }
1164
1165
1166 /**
1167  * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1168  *
1169  * @ring: amdgpu_ring pointer
1170  * @vm: amdgpu_vm pointer
1171  *
1172  * Update the page table base and flush the VM TLB
1173  * using sDMA (NAVI10).
1174  */
1175 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1176                                          unsigned vmid, uint64_t pd_addr)
1177 {
1178         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1179 }
1180
1181 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1182                                      uint32_t reg, uint32_t val)
1183 {
1184         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1185                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1186         amdgpu_ring_write(ring, reg);
1187         amdgpu_ring_write(ring, val);
1188 }
1189
1190 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1191                                          uint32_t val, uint32_t mask)
1192 {
1193         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1194                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1195                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1196         amdgpu_ring_write(ring, reg << 2);
1197         amdgpu_ring_write(ring, 0);
1198         amdgpu_ring_write(ring, val); /* reference */
1199         amdgpu_ring_write(ring, mask); /* mask */
1200         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1201                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1202 }
1203
1204 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1205                                                    uint32_t reg0, uint32_t reg1,
1206                                                    uint32_t ref, uint32_t mask)
1207 {
1208         amdgpu_ring_emit_wreg(ring, reg0, ref);
1209         /* wait for a cycle to reset vm_inv_eng*_ack */
1210         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1211         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1212 }
1213
1214 static int sdma_v5_0_early_init(void *handle)
1215 {
1216         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1217
1218         adev->sdma.num_instances = 2;
1219
1220         sdma_v5_0_set_ring_funcs(adev);
1221         sdma_v5_0_set_buffer_funcs(adev);
1222         sdma_v5_0_set_vm_pte_funcs(adev);
1223         sdma_v5_0_set_irq_funcs(adev);
1224
1225         return 0;
1226 }
1227
1228
1229 static int sdma_v5_0_sw_init(void *handle)
1230 {
1231         struct amdgpu_ring *ring;
1232         int r, i;
1233         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1234
1235         /* SDMA trap event */
1236         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1237                               SDMA0_5_0__SRCID__SDMA_TRAP,
1238                               &adev->sdma.trap_irq);
1239         if (r)
1240                 return r;
1241
1242         /* SDMA trap event */
1243         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1244                               SDMA1_5_0__SRCID__SDMA_TRAP,
1245                               &adev->sdma.trap_irq);
1246         if (r)
1247                 return r;
1248
1249         r = sdma_v5_0_init_microcode(adev);
1250         if (r) {
1251                 DRM_ERROR("Failed to load sdma firmware!\n");
1252                 return r;
1253         }
1254
1255         for (i = 0; i < adev->sdma.num_instances; i++) {
1256                 ring = &adev->sdma.instance[i].ring;
1257                 ring->ring_obj = NULL;
1258                 ring->use_doorbell = true;
1259
1260                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1261                                 ring->use_doorbell?"true":"false");
1262
1263                 ring->doorbell_index = (i == 0) ?
1264                         (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1265                         : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1266
1267                 sprintf(ring->name, "sdma%d", i);
1268                 r = amdgpu_ring_init(adev, ring, 1024,
1269                                      &adev->sdma.trap_irq,
1270                                      (i == 0) ?
1271                                      AMDGPU_SDMA_IRQ_INSTANCE0 :
1272                                      AMDGPU_SDMA_IRQ_INSTANCE1,
1273                                      AMDGPU_RING_PRIO_DEFAULT);
1274                 if (r)
1275                         return r;
1276         }
1277
1278         return r;
1279 }
1280
1281 static int sdma_v5_0_sw_fini(void *handle)
1282 {
1283         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1284         int i;
1285
1286         for (i = 0; i < adev->sdma.num_instances; i++) {
1287                 release_firmware(adev->sdma.instance[i].fw);
1288                 adev->sdma.instance[i].fw = NULL;
1289
1290                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1291         }
1292
1293         return 0;
1294 }
1295
1296 static int sdma_v5_0_hw_init(void *handle)
1297 {
1298         int r;
1299         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1300
1301         sdma_v5_0_init_golden_registers(adev);
1302
1303         r = sdma_v5_0_start(adev);
1304
1305         return r;
1306 }
1307
1308 static int sdma_v5_0_hw_fini(void *handle)
1309 {
1310         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1311
1312         if (amdgpu_sriov_vf(adev))
1313                 return 0;
1314
1315         sdma_v5_0_ctx_switch_enable(adev, false);
1316         sdma_v5_0_enable(adev, false);
1317
1318         return 0;
1319 }
1320
1321 static int sdma_v5_0_suspend(void *handle)
1322 {
1323         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1324
1325         return sdma_v5_0_hw_fini(adev);
1326 }
1327
1328 static int sdma_v5_0_resume(void *handle)
1329 {
1330         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1331
1332         return sdma_v5_0_hw_init(adev);
1333 }
1334
1335 static bool sdma_v5_0_is_idle(void *handle)
1336 {
1337         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1338         u32 i;
1339
1340         for (i = 0; i < adev->sdma.num_instances; i++) {
1341                 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1342
1343                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1344                         return false;
1345         }
1346
1347         return true;
1348 }
1349
1350 static int sdma_v5_0_wait_for_idle(void *handle)
1351 {
1352         unsigned i;
1353         u32 sdma0, sdma1;
1354         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1355
1356         for (i = 0; i < adev->usec_timeout; i++) {
1357                 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1358                 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1359
1360                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1361                         return 0;
1362                 udelay(1);
1363         }
1364         return -ETIMEDOUT;
1365 }
1366
1367 static int sdma_v5_0_soft_reset(void *handle)
1368 {
1369         /* todo */
1370
1371         return 0;
1372 }
1373
1374 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1375 {
1376         int i, r = 0;
1377         struct amdgpu_device *adev = ring->adev;
1378         u32 index = 0;
1379         u64 sdma_gfx_preempt;
1380
1381         amdgpu_sdma_get_index_from_ring(ring, &index);
1382         if (index == 0)
1383                 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1384         else
1385                 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1386
1387         /* assert preemption condition */
1388         amdgpu_ring_set_preempt_cond_exec(ring, false);
1389
1390         /* emit the trailing fence */
1391         ring->trail_seq += 1;
1392         amdgpu_ring_alloc(ring, 10);
1393         sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1394                                   ring->trail_seq, 0);
1395         amdgpu_ring_commit(ring);
1396
1397         /* assert IB preemption */
1398         WREG32(sdma_gfx_preempt, 1);
1399
1400         /* poll the trailing fence */
1401         for (i = 0; i < adev->usec_timeout; i++) {
1402                 if (ring->trail_seq ==
1403                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1404                         break;
1405                 udelay(1);
1406         }
1407
1408         if (i >= adev->usec_timeout) {
1409                 r = -EINVAL;
1410                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1411         }
1412
1413         /* deassert IB preemption */
1414         WREG32(sdma_gfx_preempt, 0);
1415
1416         /* deassert the preemption condition */
1417         amdgpu_ring_set_preempt_cond_exec(ring, true);
1418         return r;
1419 }
1420
1421 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1422                                         struct amdgpu_irq_src *source,
1423                                         unsigned type,
1424                                         enum amdgpu_interrupt_state state)
1425 {
1426         u32 sdma_cntl;
1427
1428         if (!amdgpu_sriov_vf(adev)) {
1429                 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1430                         sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1431                         sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1432
1433                 sdma_cntl = RREG32(reg_offset);
1434                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1435                                           state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1436                 WREG32(reg_offset, sdma_cntl);
1437         }
1438
1439         return 0;
1440 }
1441
1442 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1443                                       struct amdgpu_irq_src *source,
1444                                       struct amdgpu_iv_entry *entry)
1445 {
1446         DRM_DEBUG("IH: SDMA trap\n");
1447         switch (entry->client_id) {
1448         case SOC15_IH_CLIENTID_SDMA0:
1449                 switch (entry->ring_id) {
1450                 case 0:
1451                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1452                         break;
1453                 case 1:
1454                         /* XXX compute */
1455                         break;
1456                 case 2:
1457                         /* XXX compute */
1458                         break;
1459                 case 3:
1460                         /* XXX page queue*/
1461                         break;
1462                 }
1463                 break;
1464         case SOC15_IH_CLIENTID_SDMA1:
1465                 switch (entry->ring_id) {
1466                 case 0:
1467                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1468                         break;
1469                 case 1:
1470                         /* XXX compute */
1471                         break;
1472                 case 2:
1473                         /* XXX compute */
1474                         break;
1475                 case 3:
1476                         /* XXX page queue*/
1477                         break;
1478                 }
1479                 break;
1480         }
1481         return 0;
1482 }
1483
1484 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1485                                               struct amdgpu_irq_src *source,
1486                                               struct amdgpu_iv_entry *entry)
1487 {
1488         return 0;
1489 }
1490
1491 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1492                                                        bool enable)
1493 {
1494         uint32_t data, def;
1495         int i;
1496
1497         for (i = 0; i < adev->sdma.num_instances; i++) {
1498                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1499                         /* Enable sdma clock gating */
1500                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1501                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1502                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1503                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1504                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1505                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1506                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1507                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1508                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1509                         if (def != data)
1510                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1511                 } else {
1512                         /* Disable sdma clock gating */
1513                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1514                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1515                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1516                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1517                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1518                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1519                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1520                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1521                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1522                         if (def != data)
1523                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1524                 }
1525         }
1526 }
1527
1528 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1529                                                       bool enable)
1530 {
1531         uint32_t data, def;
1532         int i;
1533
1534         for (i = 0; i < adev->sdma.num_instances; i++) {
1535                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1536                         /* Enable sdma mem light sleep */
1537                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1538                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1539                         if (def != data)
1540                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1541
1542                 } else {
1543                         /* Disable sdma mem light sleep */
1544                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1545                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1546                         if (def != data)
1547                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1548
1549                 }
1550         }
1551 }
1552
1553 static int sdma_v5_0_set_clockgating_state(void *handle,
1554                                            enum amd_clockgating_state state)
1555 {
1556         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1557
1558         if (amdgpu_sriov_vf(adev))
1559                 return 0;
1560
1561         switch (adev->asic_type) {
1562         case CHIP_NAVI10:
1563         case CHIP_NAVI14:
1564         case CHIP_NAVI12:
1565                 sdma_v5_0_update_medium_grain_clock_gating(adev,
1566                                 state == AMD_CG_STATE_GATE);
1567                 sdma_v5_0_update_medium_grain_light_sleep(adev,
1568                                 state == AMD_CG_STATE_GATE);
1569                 break;
1570         default:
1571                 break;
1572         }
1573
1574         return 0;
1575 }
1576
1577 static int sdma_v5_0_set_powergating_state(void *handle,
1578                                           enum amd_powergating_state state)
1579 {
1580         return 0;
1581 }
1582
1583 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags)
1584 {
1585         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1586         int data;
1587
1588         if (amdgpu_sriov_vf(adev))
1589                 *flags = 0;
1590
1591         /* AMD_CG_SUPPORT_SDMA_MGCG */
1592         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1593         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1594                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1595
1596         /* AMD_CG_SUPPORT_SDMA_LS */
1597         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1598         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1599                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1600 }
1601
1602 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1603         .name = "sdma_v5_0",
1604         .early_init = sdma_v5_0_early_init,
1605         .late_init = NULL,
1606         .sw_init = sdma_v5_0_sw_init,
1607         .sw_fini = sdma_v5_0_sw_fini,
1608         .hw_init = sdma_v5_0_hw_init,
1609         .hw_fini = sdma_v5_0_hw_fini,
1610         .suspend = sdma_v5_0_suspend,
1611         .resume = sdma_v5_0_resume,
1612         .is_idle = sdma_v5_0_is_idle,
1613         .wait_for_idle = sdma_v5_0_wait_for_idle,
1614         .soft_reset = sdma_v5_0_soft_reset,
1615         .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1616         .set_powergating_state = sdma_v5_0_set_powergating_state,
1617         .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1618 };
1619
1620 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1621         .type = AMDGPU_RING_TYPE_SDMA,
1622         .align_mask = 0xf,
1623         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1624         .support_64bit_ptrs = true,
1625         .vmhub = AMDGPU_GFXHUB_0,
1626         .get_rptr = sdma_v5_0_ring_get_rptr,
1627         .get_wptr = sdma_v5_0_ring_get_wptr,
1628         .set_wptr = sdma_v5_0_ring_set_wptr,
1629         .emit_frame_size =
1630                 5 + /* sdma_v5_0_ring_init_cond_exec */
1631                 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1632                 3 + /* hdp_invalidate */
1633                 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1634                 /* sdma_v5_0_ring_emit_vm_flush */
1635                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1636                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1637                 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1638         .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1639         .emit_ib = sdma_v5_0_ring_emit_ib,
1640         .emit_fence = sdma_v5_0_ring_emit_fence,
1641         .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1642         .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1643         .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1644         .test_ring = sdma_v5_0_ring_test_ring,
1645         .test_ib = sdma_v5_0_ring_test_ib,
1646         .insert_nop = sdma_v5_0_ring_insert_nop,
1647         .pad_ib = sdma_v5_0_ring_pad_ib,
1648         .emit_wreg = sdma_v5_0_ring_emit_wreg,
1649         .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1650         .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1651         .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1652         .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1653         .preempt_ib = sdma_v5_0_ring_preempt_ib,
1654 };
1655
1656 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1657 {
1658         int i;
1659
1660         for (i = 0; i < adev->sdma.num_instances; i++) {
1661                 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1662                 adev->sdma.instance[i].ring.me = i;
1663         }
1664 }
1665
1666 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1667         .set = sdma_v5_0_set_trap_irq_state,
1668         .process = sdma_v5_0_process_trap_irq,
1669 };
1670
1671 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1672         .process = sdma_v5_0_process_illegal_inst_irq,
1673 };
1674
1675 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1676 {
1677         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1678                                         adev->sdma.num_instances;
1679         adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1680         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1681 }
1682
1683 /**
1684  * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1685  *
1686  * @ring: amdgpu_ring structure holding ring information
1687  * @src_offset: src GPU address
1688  * @dst_offset: dst GPU address
1689  * @byte_count: number of bytes to xfer
1690  *
1691  * Copy GPU buffers using the DMA engine (NAVI10).
1692  * Used by the amdgpu ttm implementation to move pages if
1693  * registered as the asic copy callback.
1694  */
1695 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1696                                        uint64_t src_offset,
1697                                        uint64_t dst_offset,
1698                                        uint32_t byte_count,
1699                                        bool tmz)
1700 {
1701         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1702                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1703                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1704         ib->ptr[ib->length_dw++] = byte_count - 1;
1705         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1706         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1707         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1708         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1709         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1710 }
1711
1712 /**
1713  * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1714  *
1715  * @ring: amdgpu_ring structure holding ring information
1716  * @src_data: value to write to buffer
1717  * @dst_offset: dst GPU address
1718  * @byte_count: number of bytes to xfer
1719  *
1720  * Fill GPU buffers using the DMA engine (NAVI10).
1721  */
1722 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1723                                        uint32_t src_data,
1724                                        uint64_t dst_offset,
1725                                        uint32_t byte_count)
1726 {
1727         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1728         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1729         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1730         ib->ptr[ib->length_dw++] = src_data;
1731         ib->ptr[ib->length_dw++] = byte_count - 1;
1732 }
1733
1734 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1735         .copy_max_bytes = 0x400000,
1736         .copy_num_dw = 7,
1737         .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1738
1739         .fill_max_bytes = 0x400000,
1740         .fill_num_dw = 5,
1741         .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1742 };
1743
1744 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1745 {
1746         if (adev->mman.buffer_funcs == NULL) {
1747                 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1748                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1749         }
1750 }
1751
1752 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1753         .copy_pte_num_dw = 7,
1754         .copy_pte = sdma_v5_0_vm_copy_pte,
1755         .write_pte = sdma_v5_0_vm_write_pte,
1756         .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1757 };
1758
1759 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1760 {
1761         unsigned i;
1762
1763         if (adev->vm_manager.vm_pte_funcs == NULL) {
1764                 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1765                 for (i = 0; i < adev->sdma.num_instances; i++) {
1766                         adev->vm_manager.vm_pte_scheds[i] =
1767                                 &adev->sdma.instance[i].ring.sched;
1768                 }
1769                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1770         }
1771 }
1772
1773 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1774         .type = AMD_IP_BLOCK_TYPE_SDMA,
1775         .major = 5,
1776         .minor = 0,
1777         .rev = 0,
1778         .funcs = &sdma_v5_0_ip_funcs,
1779 };