drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  *          Christian König
  28  */
  29 #include <linux/seq_file.h>
  30 #include <linux/slab.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/debugfs.h>
  33
  34 #include <drm/amdgpu_drm.h>
  35 #include "amdgpu.h"
  36 #include "atom.h"
  37
  38 /*
  39  * Rings
  40  * Most engines on the GPU are fed via ring buffers.  Ring
  41  * buffers are areas of GPU accessible memory that the host
  42  * writes commands into and the GPU reads commands out of.
  43  * There is a rptr (read pointer) that determines where the
  44  * GPU is currently reading, and a wptr (write pointer)
  45  * which determines where the host has written.  When the
  46  * pointers are equal, the ring is idle.  When the host
  47  * writes commands to the ring buffer, it increments the
  48  * wptr.  The GPU then starts fetching commands and executes
  49  * them until the pointers are equal again.
  50  */
  51
  52 /**
  53  * amdgpu_ring_max_ibs - Return max IBs that fit in a single submission.
  54  *
  55  * @type: ring type for which to return the limit.
  56  */
  57 unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type)
  58 {
  59         switch (type) {
  60         case AMDGPU_RING_TYPE_GFX:
  61                 /* Need to keep at least 192 on GFX7+ for old radv. */
  62                 return 192;
  63         case AMDGPU_RING_TYPE_COMPUTE:
  64                 return 125;
  65         case AMDGPU_RING_TYPE_VCN_JPEG:
  66                 return 16;
  67         default:
  68                 return 49;
  69         }
  70 }
  71
  72 /**
  73  * amdgpu_ring_alloc - allocate space on the ring buffer
  74  *
  75  * @ring: amdgpu_ring structure holding ring information
  76  * @ndw: number of dwords to allocate in the ring buffer
  77  *
  78  * Allocate @ndw dwords in the ring buffer (all asics).
  79  * Returns 0 on success, error on failure.
  80  */
  81 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw)
  82 {
  83         /* Align requested size with padding so unlock_commit can
  84          * pad safely */
  85         ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
  86
  87         /* Make sure we aren't trying to allocate more space
  88          * than the maximum for one submission
  89          */
  90         if (WARN_ON_ONCE(ndw > ring->max_dw))
  91                 return -ENOMEM;
  92
  93         ring->count_dw = ndw;
  94         ring->wptr_old = ring->wptr;
  95
  96         if (ring->funcs->begin_use)
  97                 ring->funcs->begin_use(ring);
  98
  99         return 0;
 100 }
 101
 102 /** amdgpu_ring_insert_nop - insert NOP packets
 103  *
 104  * @ring: amdgpu_ring structure holding ring information
 105  * @count: the number of NOP packets to insert
 106  *
 107  * This is the generic insert_nop function for rings except SDMA
 108  */
 109 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 110 {
 111         uint32_t occupied, chunk1, chunk2;
 112
 113         occupied = ring->wptr & ring->buf_mask;
 114         chunk1 = ring->buf_mask + 1 - occupied;
 115         chunk1 = (chunk1 >= count) ? count : chunk1;
 116         chunk2 = count - chunk1;
 117
 118         if (chunk1)
 119                 memset32(&ring->ring[occupied], ring->funcs->nop, chunk1);
 120
 121         if (chunk2)
 122                 memset32(ring->ring, ring->funcs->nop, chunk2);
 123
 124         ring->wptr += count;
 125         ring->wptr &= ring->ptr_mask;
 126         ring->count_dw -= count;
 127 }
 128
 129 /**
 130  * amdgpu_ring_generic_pad_ib - pad IB with NOP packets
 131  *
 132  * @ring: amdgpu_ring structure holding ring information
 133  * @ib: IB to add NOP packets to
 134  *
 135  * This is the generic pad_ib function for rings except SDMA
 136  */
 137 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 138 {
 139         while (ib->length_dw & ring->funcs->align_mask)
 140                 ib->ptr[ib->length_dw++] = ring->funcs->nop;
 141 }
 142
 143 /**
 144  * amdgpu_ring_commit - tell the GPU to execute the new
 145  * commands on the ring buffer
 146  *
 147  * @ring: amdgpu_ring structure holding ring information
 148  *
 149  * Update the wptr (write pointer) to tell the GPU to
 150  * execute new commands on the ring buffer (all asics).
 151  */
 152 void amdgpu_ring_commit(struct amdgpu_ring *ring)
 153 {
 154         uint32_t count;
 155
 156         if (ring->count_dw < 0)
 157                 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
 158
 159         /* We pad to match fetch size */
 160         count = ring->funcs->align_mask + 1 -
 161                 (ring->wptr & ring->funcs->align_mask);
 162         count &= ring->funcs->align_mask;
 163
 164         if (count != 0)
 165                 ring->funcs->insert_nop(ring, count);
 166
 167         mb();
 168         amdgpu_ring_set_wptr(ring);
 169
 170         if (ring->funcs->end_use)
 171                 ring->funcs->end_use(ring);
 172 }
 173
 174 /**
 175  * amdgpu_ring_undo - reset the wptr
 176  *
 177  * @ring: amdgpu_ring structure holding ring information
 178  *
 179  * Reset the driver's copy of the wptr (all asics).
 180  */
 181 void amdgpu_ring_undo(struct amdgpu_ring *ring)
 182 {
 183         ring->wptr = ring->wptr_old;
 184
 185         if (ring->funcs->end_use)
 186                 ring->funcs->end_use(ring);
 187 }
 188
 189 #define amdgpu_ring_get_gpu_addr(ring, offset)                          \
 190         (ring->is_mes_queue ?                                           \
 191          (ring->mes_ctx->meta_data_gpu_addr + offset) :                 \
 192          (ring->adev->wb.gpu_addr + offset * 4))
 193
 194 #define amdgpu_ring_get_cpu_addr(ring, offset)                          \
 195         (ring->is_mes_queue ?                                           \
 196          (void *)((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : \
 197          (&ring->adev->wb.wb[offset]))
 198
 199 /**
 200  * amdgpu_ring_init - init driver ring struct.
 201  *
 202  * @adev: amdgpu_device pointer
 203  * @ring: amdgpu_ring structure holding ring information
 204  * @max_dw: maximum number of dw for ring alloc
 205  * @irq_src: interrupt source to use for this ring
 206  * @irq_type: interrupt type to use for this ring
 207  * @hw_prio: ring priority (NORMAL/HIGH)
 208  * @sched_score: optional score atomic shared with other schedulers
 209  *
 210  * Initialize the driver information for the selected ring (all asics).
 211  * Returns 0 on success, error on failure.
 212  */
 213 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
 214                      unsigned int max_dw, struct amdgpu_irq_src *irq_src,
 215                      unsigned int irq_type, unsigned int hw_prio,
 216                      atomic_t *sched_score)
 217 {
 218         int r;
 219         int sched_hw_submission = amdgpu_sched_hw_submission;
 220         u32 *num_sched;
 221         u32 hw_ip;
 222         unsigned int max_ibs_dw;
 223
 224         /* Set the hw submission limit higher for KIQ because
 225          * it's used for a number of gfx/compute tasks by both
 226          * KFD and KGD which may have outstanding fences and
 227          * it doesn't really use the gpu scheduler anyway;
 228          * KIQ tasks get submitted directly to the ring.
 229          */
 230         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
 231                 sched_hw_submission = max(sched_hw_submission, 256);
 232         if (ring->funcs->type == AMDGPU_RING_TYPE_MES)
 233                 sched_hw_submission = 8;
 234         else if (ring == &adev->sdma.instance[0].page)
 235                 sched_hw_submission = 256;
 236
 237         if (ring->adev == NULL) {
 238                 if (adev->num_rings >= AMDGPU_MAX_RINGS)
 239                         return -EINVAL;
 240
 241                 ring->adev = adev;
 242                 ring->num_hw_submission = sched_hw_submission;
 243                 ring->sched_score = sched_score;
 244                 ring->vmid_wait = dma_fence_get_stub();
 245
 246                 if (!ring->is_mes_queue) {
 247                         ring->idx = adev->num_rings++;
 248                         adev->rings[ring->idx] = ring;
 249                 }
 250
 251                 r = amdgpu_fence_driver_init_ring(ring);
 252                 if (r)
 253                         return r;
 254         }
 255
 256         if (ring->is_mes_queue) {
 257                 ring->rptr_offs = amdgpu_mes_ctx_get_offs(ring,
 258                                 AMDGPU_MES_CTX_RPTR_OFFS);
 259                 ring->wptr_offs = amdgpu_mes_ctx_get_offs(ring,
 260                                 AMDGPU_MES_CTX_WPTR_OFFS);
 261                 ring->fence_offs = amdgpu_mes_ctx_get_offs(ring,
 262                                 AMDGPU_MES_CTX_FENCE_OFFS);
 263                 ring->trail_fence_offs = amdgpu_mes_ctx_get_offs(ring,
 264                                 AMDGPU_MES_CTX_TRAIL_FENCE_OFFS);
 265                 ring->cond_exe_offs = amdgpu_mes_ctx_get_offs(ring,
 266                                 AMDGPU_MES_CTX_COND_EXE_OFFS);
 267         } else {
 268                 r = amdgpu_device_wb_get(adev, &ring->rptr_offs);
 269                 if (r) {
 270                         dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
 271                         return r;
 272                 }
 273
 274                 r = amdgpu_device_wb_get(adev, &ring->wptr_offs);
 275                 if (r) {
 276                         dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
 277                         return r;
 278                 }
 279
 280                 r = amdgpu_device_wb_get(adev, &ring->fence_offs);
 281                 if (r) {
 282                         dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
 283                         return r;
 284                 }
 285
 286                 r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs);
 287                 if (r) {
 288                         dev_err(adev->dev, "(%d) ring trail_fence_offs wb alloc failed\n", r);
 289                         return r;
 290                 }
 291
 292                 r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs);
 293                 if (r) {
 294                         dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
 295                         return r;
 296                 }
 297         }
 298
 299         ring->fence_gpu_addr =
 300                 amdgpu_ring_get_gpu_addr(ring, ring->fence_offs);
 301         ring->fence_cpu_addr =
 302                 amdgpu_ring_get_cpu_addr(ring, ring->fence_offs);
 303
 304         ring->rptr_gpu_addr =
 305                 amdgpu_ring_get_gpu_addr(ring, ring->rptr_offs);
 306         ring->rptr_cpu_addr =
 307                 amdgpu_ring_get_cpu_addr(ring, ring->rptr_offs);
 308
 309         ring->wptr_gpu_addr =
 310                 amdgpu_ring_get_gpu_addr(ring, ring->wptr_offs);
 311         ring->wptr_cpu_addr =
 312                 amdgpu_ring_get_cpu_addr(ring, ring->wptr_offs);
 313
 314         ring->trail_fence_gpu_addr =
 315                 amdgpu_ring_get_gpu_addr(ring, ring->trail_fence_offs);
 316         ring->trail_fence_cpu_addr =
 317                 amdgpu_ring_get_cpu_addr(ring, ring->trail_fence_offs);
 318
 319         ring->cond_exe_gpu_addr =
 320                 amdgpu_ring_get_gpu_addr(ring, ring->cond_exe_offs);
 321         ring->cond_exe_cpu_addr =
 322                 amdgpu_ring_get_cpu_addr(ring, ring->cond_exe_offs);
 323
 324         /* always set cond_exec_polling to CONTINUE */
 325         *ring->cond_exe_cpu_addr = 1;
 326
 327         r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
 328         if (r) {
 329                 dev_err(adev->dev, "failed initializing fences (%d).\n", r);
 330                 return r;
 331         }
 332
 333         max_ibs_dw = ring->funcs->emit_frame_size +
 334                      amdgpu_ring_max_ibs(ring->funcs->type) * ring->funcs->emit_ib_size;
 335         max_ibs_dw = (max_ibs_dw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
 336
 337         if (WARN_ON(max_ibs_dw > max_dw))
 338                 max_dw = max_ibs_dw;
 339
 340         ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
 341
 342         ring->buf_mask = (ring->ring_size / 4) - 1;
 343         ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
 344                 0xffffffffffffffff : ring->buf_mask;
 345
 346         /* Allocate ring buffer */
 347         if (ring->is_mes_queue) {
 348                 int offset = 0;
 349
 350                 BUG_ON(ring->ring_size > PAGE_SIZE*4);
 351
 352                 offset = amdgpu_mes_ctx_get_offs(ring,
 353                                          AMDGPU_MES_CTX_RING_OFFS);
 354                 ring->gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 355                 ring->ring = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 356                 amdgpu_ring_clear_ring(ring);
 357
 358         } else if (ring->ring_obj == NULL) {
 359                 r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE,
 360                                             AMDGPU_GEM_DOMAIN_GTT,
 361                                             &ring->ring_obj,
 362                                             &ring->gpu_addr,
 363                                             (void **)&ring->ring);
 364                 if (r) {
 365                         dev_err(adev->dev, "(%d) ring create failed\n", r);
 366                         return r;
 367                 }
 368                 amdgpu_ring_clear_ring(ring);
 369         }
 370
 371         ring->max_dw = max_dw;
 372         ring->hw_prio = hw_prio;
 373
 374         if (!ring->no_scheduler && ring->funcs->type < AMDGPU_HW_IP_NUM) {
 375                 hw_ip = ring->funcs->type;
 376                 num_sched = &adev->gpu_sched[hw_ip][hw_prio].num_scheds;
 377                 adev->gpu_sched[hw_ip][hw_prio].sched[(*num_sched)++] =
 378                         &ring->sched;
 379         }
 380
 381         return 0;
 382 }
 383
 384 /**
 385  * amdgpu_ring_fini - tear down the driver ring struct.
 386  *
 387  * @ring: amdgpu_ring structure holding ring information
 388  *
 389  * Tear down the driver information for the selected ring (all asics).
 390  */
 391 void amdgpu_ring_fini(struct amdgpu_ring *ring)
 392 {
 393
 394         /* Not to finish a ring which is not initialized */
 395         if (!(ring->adev) ||
 396             (!ring->is_mes_queue && !(ring->adev->rings[ring->idx])))
 397                 return;
 398
 399         ring->sched.ready = false;
 400
 401         if (!ring->is_mes_queue) {
 402                 amdgpu_device_wb_free(ring->adev, ring->rptr_offs);
 403                 amdgpu_device_wb_free(ring->adev, ring->wptr_offs);
 404
 405                 amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs);
 406                 amdgpu_device_wb_free(ring->adev, ring->fence_offs);
 407
 408                 amdgpu_bo_free_kernel(&ring->ring_obj,
 409                                       &ring->gpu_addr,
 410                                       (void **)&ring->ring);
 411         } else {
 412                 kfree(ring->fence_drv.fences);
 413         }
 414
 415         dma_fence_put(ring->vmid_wait);
 416         ring->vmid_wait = NULL;
 417         ring->me = 0;
 418
 419         if (!ring->is_mes_queue)
 420                 ring->adev->rings[ring->idx] = NULL;
 421 }
 422
 423 /**
 424  * amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper
 425  *
 426  * @ring: ring to write to
 427  * @reg0: register to write
 428  * @reg1: register to wait on
 429  * @ref: reference value to write/wait on
 430  * @mask: mask to wait on
 431  *
 432  * Helper for rings that don't support write and wait in a
 433  * single oneshot packet.
 434  */
 435 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
 436                                                 uint32_t reg0, uint32_t reg1,
 437                                                 uint32_t ref, uint32_t mask)
 438 {
 439         amdgpu_ring_emit_wreg(ring, reg0, ref);
 440         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
 441 }
 442
 443 /**
 444  * amdgpu_ring_soft_recovery - try to soft recover a ring lockup
 445  *
 446  * @ring: ring to try the recovery on
 447  * @vmid: VMID we try to get going again
 448  * @fence: timedout fence
 449  *
 450  * Tries to get a ring proceeding again when it is stuck.
 451  */
 452 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
 453                                struct dma_fence *fence)
 454 {
 455         unsigned long flags;
 456         ktime_t deadline;
 457
 458         if (unlikely(ring->adev->debug_disable_soft_recovery))
 459                 return false;
 460
 461         deadline = ktime_add_us(ktime_get(), 10000);
 462
 463         if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence)
 464                 return false;
 465
 466         spin_lock_irqsave(fence->lock, flags);
 467         if (!dma_fence_is_signaled_locked(fence))
 468                 dma_fence_set_error(fence, -ENODATA);
 469         spin_unlock_irqrestore(fence->lock, flags);
 470
 471         atomic_inc(&ring->adev->gpu_reset_counter);
 472         while (!dma_fence_is_signaled(fence) &&
 473                ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)
 474                 ring->funcs->soft_recovery(ring, vmid);
 475
 476         return dma_fence_is_signaled(fence);
 477 }
 478
 479 /*
 480  * Debugfs info
 481  */
 482 #if defined(CONFIG_DEBUG_FS)
 483
 484 /* Layout of file is 12 bytes consisting of
 485  * - rptr
 486  * - wptr
 487  * - driver's copy of wptr
 488  *
 489  * followed by n-words of ring data
 490  */
 491 static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
 492                                         size_t size, loff_t *pos)
 493 {
 494         struct amdgpu_ring *ring = file_inode(f)->i_private;
 495         uint32_t value, result, early[3];
 496         loff_t i;
 497         int r;
 498
 499         if (*pos & 3 || size & 3)
 500                 return -EINVAL;
 501
 502         result = 0;
 503
 504         if (*pos < 12) {
 505                 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
 506                 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
 507                 early[2] = ring->wptr & ring->buf_mask;
 508                 for (i = *pos / 4; i < 3 && size; i++) {
 509                         r = put_user(early[i], (uint32_t *)buf);
 510                         if (r)
 511                                 return r;
 512                         buf += 4;
 513                         result += 4;
 514                         size -= 4;
 515                         *pos += 4;
 516                 }
 517         }
 518
 519         while (size) {
 520                 if (*pos >= (ring->ring_size + 12))
 521                         return result;
 522
 523                 value = ring->ring[(*pos - 12)/4];
 524                 r = put_user(value, (uint32_t *)buf);
 525                 if (r)
 526                         return r;
 527                 buf += 4;
 528                 result += 4;
 529                 size -= 4;
 530                 *pos += 4;
 531         }
 532
 533         return result;
 534 }
 535
 536 static const struct file_operations amdgpu_debugfs_ring_fops = {
 537         .owner = THIS_MODULE,
 538         .read = amdgpu_debugfs_ring_read,
 539         .llseek = default_llseek
 540 };
 541
 542 static ssize_t amdgpu_debugfs_mqd_read(struct file *f, char __user *buf,
 543                                        size_t size, loff_t *pos)
 544 {
 545         struct amdgpu_ring *ring = file_inode(f)->i_private;
 546         volatile u32 *mqd;
 547         u32 *kbuf;
 548         int r, i;
 549         uint32_t value, result;
 550
 551         if (*pos & 3 || size & 3)
 552                 return -EINVAL;
 553
 554         kbuf = kmalloc(ring->mqd_size, GFP_KERNEL);
 555         if (!kbuf)
 556                 return -ENOMEM;
 557
 558         r = amdgpu_bo_reserve(ring->mqd_obj, false);
 559         if (unlikely(r != 0))
 560                 goto err_free;
 561
 562         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&mqd);
 563         if (r)
 564                 goto err_unreserve;
 565
 566         /*
 567          * Copy to local buffer to avoid put_user(), which might fault
 568          * and acquire mmap_sem, under reservation_ww_class_mutex.
 569          */
 570         for (i = 0; i < ring->mqd_size/sizeof(u32); i++)
 571                 kbuf[i] = mqd[i];
 572
 573         amdgpu_bo_kunmap(ring->mqd_obj);
 574         amdgpu_bo_unreserve(ring->mqd_obj);
 575
 576         result = 0;
 577         while (size) {
 578                 if (*pos >= ring->mqd_size)
 579                         break;
 580
 581                 value = kbuf[*pos/4];
 582                 r = put_user(value, (uint32_t *)buf);
 583                 if (r)
 584                         goto err_free;
 585                 buf += 4;
 586                 result += 4;
 587                 size -= 4;
 588                 *pos += 4;
 589         }
 590
 591         kfree(kbuf);
 592         return result;
 593
 594 err_unreserve:
 595         amdgpu_bo_unreserve(ring->mqd_obj);
 596 err_free:
 597         kfree(kbuf);
 598         return r;
 599 }
 600
 601 static const struct file_operations amdgpu_debugfs_mqd_fops = {
 602         .owner = THIS_MODULE,
 603         .read = amdgpu_debugfs_mqd_read,
 604         .llseek = default_llseek
 605 };
 606
 607 static int amdgpu_debugfs_ring_error(void *data, u64 val)
 608 {
 609         struct amdgpu_ring *ring = data;
 610
 611         amdgpu_fence_driver_set_error(ring, val);
 612         return 0;
 613 }
 614
 615 DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(amdgpu_debugfs_error_fops, NULL,
 616                                 amdgpu_debugfs_ring_error, "%lld\n");
 617
 618 #endif
 619
 620 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
 621                               struct amdgpu_ring *ring)
 622 {
 623 #if defined(CONFIG_DEBUG_FS)
 624         struct drm_minor *minor = adev_to_drm(adev)->primary;
 625         struct dentry *root = minor->debugfs_root;
 626         char name[32];
 627
 628         sprintf(name, "amdgpu_ring_%s", ring->name);
 629         debugfs_create_file_size(name, S_IFREG | 0444, root, ring,
 630                                  &amdgpu_debugfs_ring_fops,
 631                                  ring->ring_size + 12);
 632
 633         if (ring->mqd_obj) {
 634                 sprintf(name, "amdgpu_mqd_%s", ring->name);
 635                 debugfs_create_file_size(name, S_IFREG | 0444, root, ring,
 636                                          &amdgpu_debugfs_mqd_fops,
 637                                          ring->mqd_size);
 638         }
 639
 640         sprintf(name, "amdgpu_error_%s", ring->name);
 641         debugfs_create_file(name, 0200, root, ring,
 642                             &amdgpu_debugfs_error_fops);
 643
 644 #endif
 645 }
 646
 647 /**
 648  * amdgpu_ring_test_helper - tests ring and set sched readiness status
 649  *
 650  * @ring: ring to try the recovery on
 651  *
 652  * Tests ring and set sched readiness status
 653  *
 654  * Returns 0 on success, error on failure.
 655  */
 656 int amdgpu_ring_test_helper(struct amdgpu_ring *ring)
 657 {
 658         struct amdgpu_device *adev = ring->adev;
 659         int r;
 660
 661         r = amdgpu_ring_test_ring(ring);
 662         if (r)
 663                 DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n",
 664                               ring->name, r);
 665         else
 666                 DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n",
 667                               ring->name);
 668
 669         ring->sched.ready = !r;
 670
 671         return r;
 672 }
 673
 674 static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring,
 675                                     struct amdgpu_mqd_prop *prop)
 676 {
 677         struct amdgpu_device *adev = ring->adev;
 678         bool is_high_prio_compute = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE &&
 679                                     amdgpu_gfx_is_high_priority_compute_queue(adev, ring);
 680         bool is_high_prio_gfx = ring->funcs->type == AMDGPU_RING_TYPE_GFX &&
 681                                 amdgpu_gfx_is_high_priority_graphics_queue(adev, ring);
 682
 683         memset(prop, 0, sizeof(*prop));
 684
 685         prop->mqd_gpu_addr = ring->mqd_gpu_addr;
 686         prop->hqd_base_gpu_addr = ring->gpu_addr;
 687         prop->rptr_gpu_addr = ring->rptr_gpu_addr;
 688         prop->wptr_gpu_addr = ring->wptr_gpu_addr;
 689         prop->queue_size = ring->ring_size;
 690         prop->eop_gpu_addr = ring->eop_gpu_addr;
 691         prop->use_doorbell = ring->use_doorbell;
 692         prop->doorbell_index = ring->doorbell_index;
 693
 694         /* map_queues packet doesn't need activate the queue,
 695          * so only kiq need set this field.
 696          */
 697         prop->hqd_active = ring->funcs->type == AMDGPU_RING_TYPE_KIQ;
 698
 699         prop->allow_tunneling = is_high_prio_compute;
 700         if (is_high_prio_compute || is_high_prio_gfx) {
 701                 prop->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
 702                 prop->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
 703         }
 704 }
 705
 706 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring)
 707 {
 708         struct amdgpu_device *adev = ring->adev;
 709         struct amdgpu_mqd *mqd_mgr;
 710         struct amdgpu_mqd_prop prop;
 711
 712         amdgpu_ring_to_mqd_prop(ring, &prop);
 713
 714         ring->wptr = 0;
 715
 716         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
 717                 mqd_mgr = &adev->mqds[AMDGPU_HW_IP_COMPUTE];
 718         else
 719                 mqd_mgr = &adev->mqds[ring->funcs->type];
 720
 721         return mqd_mgr->init_mqd(adev, ring->mqd_ptr, &prop);
 722 }
 723
 724 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring)
 725 {
 726         if (ring->is_sw_ring)
 727                 amdgpu_sw_ring_ib_begin(ring);
 728 }
 729
 730 void amdgpu_ring_ib_end(struct amdgpu_ring *ring)
 731 {
 732         if (ring->is_sw_ring)
 733                 amdgpu_sw_ring_ib_end(ring);
 734 }
 735
 736 void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring)
 737 {
 738         if (ring->is_sw_ring)
 739                 amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_CONTROL);
 740 }
 741
 742 void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring)
 743 {
 744         if (ring->is_sw_ring)
 745                 amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_CE);
 746 }
 747
 748 void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring)
 749 {
 750         if (ring->is_sw_ring)
 751                 amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_DE);
 752 }
 753
 754 bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring)
 755 {
 756         if (!ring)
 757                 return false;
 758
 759         if (ring->no_scheduler || !drm_sched_wqueue_ready(&ring->sched))
 760                 return false;
 761
 762         return true;
 763 }