drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_JPEG_H__
  25 #define __AMDGPU_JPEG_H__
  26
  27 #include "amdgpu_ras.h"
  28
  29 #define AMDGPU_MAX_JPEG_INSTANCES       4
  30 #define AMDGPU_MAX_JPEG_RINGS           10
  31 #define AMDGPU_MAX_JPEG_RINGS_4_0_3     8
  32
  33 #define AMDGPU_JPEG_HARVEST_JPEG0 (1 << 0)
  34 #define AMDGPU_JPEG_HARVEST_JPEG1 (1 << 1)
  35
  36 #define WREG32_SOC15_JPEG_DPG_MODE(inst_idx, offset, value, indirect)                   \
  37         do {                                                                            \
  38                 if (!indirect) {                                                        \
  39                         WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx),                    \
  40                                      mmUVD_DPG_LMA_DATA, value);                        \
  41                         WREG32_SOC15(                                                   \
  42                                 JPEG, GET_INST(JPEG, inst_idx),                         \
  43                                 mmUVD_DPG_LMA_CTL,                                      \
  44                                 (UVD_DPG_LMA_CTL__READ_WRITE_MASK |                     \
  45                                  offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT |    \
  46                                  indirect << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT));        \
  47                 } else {                                                                \
  48                         *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ =               \
  49                                 offset;                                                 \
  50                         *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ =               \
  51                                 value;                                                  \
  52                 }                                                                       \
  53         } while (0)
  54
  55 #define RREG32_SOC15_JPEG_DPG_MODE(inst_idx, offset, mask_en)                                   \
  56         ({                                                                                      \
  57                 WREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_CTL,                                 \
  58                         (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT |                            \
  59                         mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT |                            \
  60                         offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT));                    \
  61                 RREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_DATA);                               \
  62         })
  63
  64 #define WREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, value, indirect)           \
  65         do {                                                                    \
  66                 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx),                    \
  67                              regUVD_DPG_LMA_DATA, value);                       \
  68                 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx),                    \
  69                              regUVD_DPG_LMA_MASK, 0xFFFFFFFF);                  \
  70                 WREG32_SOC15(                                                   \
  71                         JPEG, GET_INST(JPEG, inst_idx),                         \
  72                         regUVD_DPG_LMA_CTL,                                     \
  73                         (UVD_DPG_LMA_CTL__READ_WRITE_MASK |                     \
  74                          offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT |    \
  75                          indirect << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT));        \
  76         } while (0)
  77
  78 #define RREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, mask_en)                   \
  79         do {                                                                    \
  80                 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx),                    \
  81                         regUVD_DPG_LMA_MASK, 0xFFFFFFFF);                       \
  82                 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx),                    \
  83                         regUVD_DPG_LMA_CTL,                                     \
  84                         (UVD_DPG_LMA_CTL__MASK_EN_MASK |                        \
  85                         offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT));    \
  86                 RREG32_SOC15(JPEG, inst_idx, regUVD_DPG_LMA_DATA);              \
  87         } while (0)
  88
  89 #define ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, offset, value, indirect)           \
  90         do {                                                                    \
  91                 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = offset;       \
  92                 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = value;        \
  93         } while (0)
  94
  95 struct amdgpu_jpeg_reg{
  96         unsigned jpeg_pitch[AMDGPU_MAX_JPEG_RINGS];
  97 };
  98
  99 struct amdgpu_jpeg_inst {
 100         struct amdgpu_ring ring_dec[AMDGPU_MAX_JPEG_RINGS];
 101         struct amdgpu_irq_src irq;
 102         struct amdgpu_irq_src ras_poison_irq;
 103         struct amdgpu_jpeg_reg external;
 104         struct amdgpu_bo        *dpg_sram_bo;
 105         struct dpg_pause_state  pause_state;
 106         void                    *dpg_sram_cpu_addr;
 107         uint64_t                dpg_sram_gpu_addr;
 108         uint32_t                *dpg_sram_curr_addr;
 109         uint8_t aid_id;
 110 };
 111
 112 struct amdgpu_jpeg_ras {
 113         struct amdgpu_ras_block_object ras_block;
 114 };
 115
 116 struct amdgpu_jpeg {
 117         uint8_t num_jpeg_inst;
 118         struct amdgpu_jpeg_inst inst[AMDGPU_MAX_JPEG_INSTANCES];
 119         unsigned num_jpeg_rings;
 120         struct amdgpu_jpeg_reg internal;
 121         unsigned harvest_config;
 122         struct delayed_work idle_work;
 123         enum amd_powergating_state cur_state;
 124         struct mutex jpeg_pg_lock;
 125         atomic_t total_submission_cnt;
 126         struct ras_common_if    *ras_if;
 127         struct amdgpu_jpeg_ras  *ras;
 128
 129         uint16_t inst_mask;
 130         uint8_t num_inst_per_aid;
 131         bool    indirect_sram;
 132         uint32_t supported_reset;
 133 };
 134
 135 int amdgpu_jpeg_sw_init(struct amdgpu_device *adev);
 136 int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev);
 137 int amdgpu_jpeg_suspend(struct amdgpu_device *adev);
 138 int amdgpu_jpeg_resume(struct amdgpu_device *adev);
 139
 140 void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring);
 141 void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring);
 142
 143 int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring);
 144 int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 145
 146 int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev,
 147                                 struct amdgpu_irq_src *source,
 148                                 struct amdgpu_iv_entry *entry);
 149 int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev,
 150                                 struct ras_common_if *ras_block);
 151 int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev);
 152 int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
 153                                enum AMDGPU_UCODE_ID ucode_id);
 154 void amdgpu_debugfs_jpeg_sched_mask_init(struct amdgpu_device *adev);
 155 int amdgpu_jpeg_sysfs_reset_mask_init(struct amdgpu_device *adev);
 156 void amdgpu_jpeg_sysfs_reset_mask_fini(struct amdgpu_device *adev);
 157
 158 #endif /*__AMDGPU_JPEG_H__*/