sound/soc/codecs/cs35l56-shared.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // Components shared between ASoC and HDA CS35L56 drivers
   4 //
   5 // Copyright (C) 2023 Cirrus Logic, Inc. and
   6 //                    Cirrus Logic International Semiconductor Ltd.
   7
   8 #include <linux/regmap.h>
   9 #include <linux/regulator/consumer.h>
  10 #include <linux/types.h>
  11
  12 #include "cs35l56.h"
  13
  14 static const struct reg_sequence cs35l56_patch[] = {
  15         /* These are not reset by a soft-reset, so patch to defaults. */
  16         { CS35L56_MAIN_RENDER_USER_MUTE,        0x00000000 },
  17         { CS35L56_MAIN_RENDER_USER_VOLUME,      0x00000000 },
  18         { CS35L56_MAIN_POSTURE_NUMBER,          0x00000000 },
  19 };
  20
  21 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base)
  22 {
  23         return regmap_register_patch(cs35l56_base->regmap, cs35l56_patch,
  24                                      ARRAY_SIZE(cs35l56_patch));
  25 }
  26 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, SND_SOC_CS35L56_SHARED);
  27
  28 static const struct reg_default cs35l56_reg_defaults[] = {
  29         { CS35L56_ASP1_ENABLES1,                0x00000000 },
  30         { CS35L56_ASP1_CONTROL1,                0x00000028 },
  31         { CS35L56_ASP1_CONTROL2,                0x18180200 },
  32         { CS35L56_ASP1_CONTROL3,                0x00000002 },
  33         { CS35L56_ASP1_FRAME_CONTROL1,          0x03020100 },
  34         { CS35L56_ASP1_FRAME_CONTROL5,          0x00020100 },
  35         { CS35L56_ASP1_DATA_CONTROL1,           0x00000018 },
  36         { CS35L56_ASP1_DATA_CONTROL5,           0x00000018 },
  37         { CS35L56_ASP1TX1_INPUT,                0x00000018 },
  38         { CS35L56_ASP1TX2_INPUT,                0x00000019 },
  39         { CS35L56_ASP1TX3_INPUT,                0x00000020 },
  40         { CS35L56_ASP1TX4_INPUT,                0x00000028 },
  41         { CS35L56_SWIRE_DP3_CH1_INPUT,          0x00000018 },
  42         { CS35L56_SWIRE_DP3_CH2_INPUT,          0x00000019 },
  43         { CS35L56_SWIRE_DP3_CH3_INPUT,          0x00000029 },
  44         { CS35L56_SWIRE_DP3_CH4_INPUT,          0x00000028 },
  45         { CS35L56_IRQ1_CFG,                     0x00000000 },
  46         { CS35L56_IRQ1_MASK_1,                  0x83ffffff },
  47         { CS35L56_IRQ1_MASK_2,                  0xffff7fff },
  48         { CS35L56_IRQ1_MASK_4,                  0xe0ffffff },
  49         { CS35L56_IRQ1_MASK_8,                  0xfc000fff },
  50         { CS35L56_IRQ1_MASK_18,                 0x1f7df0ff },
  51         { CS35L56_IRQ1_MASK_20,                 0x15c00000 },
  52         { CS35L56_MAIN_RENDER_USER_MUTE,        0x00000000 },
  53         { CS35L56_MAIN_RENDER_USER_VOLUME,      0x00000000 },
  54         { CS35L56_MAIN_POSTURE_NUMBER,          0x00000000 },
  55 };
  56
  57 static bool cs35l56_is_dsp_memory(unsigned int reg)
  58 {
  59         switch (reg) {
  60         case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
  61         case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095:
  62         case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191:
  63         case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
  64         case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070:
  65         case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141:
  66         case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
  67                 return true;
  68         default:
  69                 return false;
  70         }
  71 }
  72
  73 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg)
  74 {
  75         switch (reg) {
  76         case CS35L56_DEVID:
  77         case CS35L56_REVID:
  78         case CS35L56_RELID:
  79         case CS35L56_OTPID:
  80         case CS35L56_SFT_RESET:
  81         case CS35L56_GLOBAL_ENABLES:
  82         case CS35L56_BLOCK_ENABLES:
  83         case CS35L56_BLOCK_ENABLES2:
  84         case CS35L56_REFCLK_INPUT:
  85         case CS35L56_GLOBAL_SAMPLE_RATE:
  86         case CS35L56_ASP1_ENABLES1:
  87         case CS35L56_ASP1_CONTROL1:
  88         case CS35L56_ASP1_CONTROL2:
  89         case CS35L56_ASP1_CONTROL3:
  90         case CS35L56_ASP1_FRAME_CONTROL1:
  91         case CS35L56_ASP1_FRAME_CONTROL5:
  92         case CS35L56_ASP1_DATA_CONTROL1:
  93         case CS35L56_ASP1_DATA_CONTROL5:
  94         case CS35L56_DACPCM1_INPUT:
  95         case CS35L56_DACPCM2_INPUT:
  96         case CS35L56_ASP1TX1_INPUT:
  97         case CS35L56_ASP1TX2_INPUT:
  98         case CS35L56_ASP1TX3_INPUT:
  99         case CS35L56_ASP1TX4_INPUT:
 100         case CS35L56_DSP1RX1_INPUT:
 101         case CS35L56_DSP1RX2_INPUT:
 102         case CS35L56_SWIRE_DP3_CH1_INPUT:
 103         case CS35L56_SWIRE_DP3_CH2_INPUT:
 104         case CS35L56_SWIRE_DP3_CH3_INPUT:
 105         case CS35L56_SWIRE_DP3_CH4_INPUT:
 106         case CS35L56_IRQ1_CFG:
 107         case CS35L56_IRQ1_STATUS:
 108         case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
 109         case CS35L56_IRQ1_EINT_18:
 110         case CS35L56_IRQ1_EINT_20:
 111         case CS35L56_IRQ1_MASK_1:
 112         case CS35L56_IRQ1_MASK_2:
 113         case CS35L56_IRQ1_MASK_4:
 114         case CS35L56_IRQ1_MASK_8:
 115         case CS35L56_IRQ1_MASK_18:
 116         case CS35L56_IRQ1_MASK_20:
 117         case CS35L56_DSP_VIRTUAL1_MBOX_1:
 118         case CS35L56_DSP_VIRTUAL1_MBOX_2:
 119         case CS35L56_DSP_VIRTUAL1_MBOX_3:
 120         case CS35L56_DSP_VIRTUAL1_MBOX_4:
 121         case CS35L56_DSP_VIRTUAL1_MBOX_5:
 122         case CS35L56_DSP_VIRTUAL1_MBOX_6:
 123         case CS35L56_DSP_VIRTUAL1_MBOX_7:
 124         case CS35L56_DSP_VIRTUAL1_MBOX_8:
 125         case CS35L56_DSP_RESTRICT_STS1:
 126         case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
 127         case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
 128         case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
 129         case CS35L56_DSP1_SCRATCH1:
 130         case CS35L56_DSP1_SCRATCH2:
 131         case CS35L56_DSP1_SCRATCH3:
 132         case CS35L56_DSP1_SCRATCH4:
 133                 return true;
 134         default:
 135                 return cs35l56_is_dsp_memory(reg);
 136         }
 137 }
 138
 139 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg)
 140 {
 141         switch (reg) {
 142         case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
 143         case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
 144         case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
 145                 return true;
 146         default:
 147                 return false;
 148         }
 149 }
 150
 151 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg)
 152 {
 153         switch (reg) {
 154         case CS35L56_DEVID:
 155         case CS35L56_REVID:
 156         case CS35L56_RELID:
 157         case CS35L56_OTPID:
 158         case CS35L56_SFT_RESET:
 159         case CS35L56_GLOBAL_ENABLES:               /* owned by firmware */
 160         case CS35L56_BLOCK_ENABLES:                /* owned by firmware */
 161         case CS35L56_BLOCK_ENABLES2:               /* owned by firmware */
 162         case CS35L56_REFCLK_INPUT:                 /* owned by firmware */
 163         case CS35L56_GLOBAL_SAMPLE_RATE:           /* owned by firmware */
 164         case CS35L56_DACPCM1_INPUT:                /* owned by firmware */
 165         case CS35L56_DACPCM2_INPUT:                /* owned by firmware */
 166         case CS35L56_DSP1RX1_INPUT:                /* owned by firmware */
 167         case CS35L56_DSP1RX2_INPUT:                /* owned by firmware */
 168         case CS35L56_IRQ1_STATUS:
 169         case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
 170         case CS35L56_IRQ1_EINT_18:
 171         case CS35L56_IRQ1_EINT_20:
 172         case CS35L56_DSP_VIRTUAL1_MBOX_1:
 173         case CS35L56_DSP_VIRTUAL1_MBOX_2:
 174         case CS35L56_DSP_VIRTUAL1_MBOX_3:
 175         case CS35L56_DSP_VIRTUAL1_MBOX_4:
 176         case CS35L56_DSP_VIRTUAL1_MBOX_5:
 177         case CS35L56_DSP_VIRTUAL1_MBOX_6:
 178         case CS35L56_DSP_VIRTUAL1_MBOX_7:
 179         case CS35L56_DSP_VIRTUAL1_MBOX_8:
 180         case CS35L56_DSP_RESTRICT_STS1:
 181         case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
 182         case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
 183         case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
 184         case CS35L56_DSP1_SCRATCH1:
 185         case CS35L56_DSP1_SCRATCH2:
 186         case CS35L56_DSP1_SCRATCH3:
 187         case CS35L56_DSP1_SCRATCH4:
 188                 return true;
 189         case CS35L56_MAIN_RENDER_USER_MUTE:
 190         case CS35L56_MAIN_RENDER_USER_VOLUME:
 191         case CS35L56_MAIN_POSTURE_NUMBER:
 192                 return false;
 193         default:
 194                 return cs35l56_is_dsp_memory(reg);
 195         }
 196 }
 197
 198 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command)
 199 {
 200         unsigned int val;
 201         int ret;
 202
 203         regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command);
 204         ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
 205                                        val, (val == 0),
 206                                        CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US);
 207         if (ret) {
 208                 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret);
 209                 return ret;
 210         }
 211
 212         return 0;
 213 }
 214 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, SND_SOC_CS35L56_SHARED);
 215
 216 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base)
 217 {
 218         int ret;
 219         unsigned int reg;
 220         unsigned int val;
 221
 222         ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN);
 223         if (ret)
 224                 return ret;
 225
 226         if (cs35l56_base->rev < CS35L56_REVID_B0)
 227                 reg = CS35L56_DSP1_PM_CUR_STATE_A1;
 228         else
 229                 reg = CS35L56_DSP1_PM_CUR_STATE;
 230
 231         ret = regmap_read_poll_timeout(cs35l56_base->regmap,  reg,
 232                                        val, (val == CS35L56_HALO_STATE_SHUTDOWN),
 233                                        CS35L56_HALO_STATE_POLL_US,
 234                                        CS35L56_HALO_STATE_TIMEOUT_US);
 235         if (ret < 0)
 236                 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n",
 237                         val, ret);
 238         return ret;
 239 }
 240 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, SND_SOC_CS35L56_SHARED);
 241
 242 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base)
 243 {
 244         unsigned int reg;
 245         unsigned int val = 0;
 246         int read_ret, poll_ret;
 247
 248         if (cs35l56_base->rev < CS35L56_REVID_B0)
 249                 reg = CS35L56_DSP1_HALO_STATE_A1;
 250         else
 251                 reg = CS35L56_DSP1_HALO_STATE;
 252
 253         /*
 254          * This can't be a regmap_read_poll_timeout() because cs35l56 will NAK
 255          * I2C until it has booted which would terminate the poll
 256          */
 257         poll_ret = read_poll_timeout(regmap_read, read_ret,
 258                                      (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE),
 259                                      CS35L56_HALO_STATE_POLL_US,
 260                                      CS35L56_HALO_STATE_TIMEOUT_US,
 261                                      false,
 262                                      cs35l56_base->regmap, reg, &val);
 263
 264         if (poll_ret) {
 265                 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n",
 266                         read_ret, val);
 267                 return -EIO;
 268         }
 269
 270         return 0;
 271 }
 272 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, SND_SOC_CS35L56_SHARED);
 273
 274 void cs35l56_wait_control_port_ready(void)
 275 {
 276         /* Wait for control port to be ready (datasheet tIRS). */
 277         usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US);
 278 }
 279 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, SND_SOC_CS35L56_SHARED);
 280
 281 void cs35l56_wait_min_reset_pulse(void)
 282 {
 283         /* Satisfy minimum reset pulse width spec */
 284         usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US);
 285 }
 286 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, SND_SOC_CS35L56_SHARED);
 287
 288 static const struct reg_sequence cs35l56_system_reset_seq[] = {
 289         REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
 290 };
 291
 292 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire)
 293 {
 294         /*
 295          * Must enter cache-only first so there can't be any more register
 296          * accesses other than the controlled system reset sequence below.
 297          */
 298         regcache_cache_only(cs35l56_base->regmap, true);
 299         regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
 300                                         cs35l56_system_reset_seq,
 301                                         ARRAY_SIZE(cs35l56_system_reset_seq));
 302
 303         /* On SoundWire the registers won't be accessible until it re-enumerates. */
 304         if (is_soundwire)
 305                 return;
 306
 307         cs35l56_wait_control_port_ready();
 308         regcache_cache_only(cs35l56_base->regmap, false);
 309 }
 310 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, SND_SOC_CS35L56_SHARED);
 311
 312 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq)
 313 {
 314         int ret;
 315
 316         if (!irq)
 317                 return 0;
 318
 319         ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq,
 320                                         IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW,
 321                                         "cs35l56", cs35l56_base);
 322         if (!ret)
 323                 cs35l56_base->irq = irq;
 324         else
 325                 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret);
 326
 327         return ret;
 328 }
 329 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_SOC_CS35L56_SHARED);
 330
 331 irqreturn_t cs35l56_irq(int irq, void *data)
 332 {
 333         struct cs35l56_base *cs35l56_base = data;
 334         unsigned int status1 = 0, status8 = 0, status20 = 0;
 335         unsigned int mask1, mask8, mask20;
 336         unsigned int val;
 337         int rv;
 338
 339         irqreturn_t ret = IRQ_NONE;
 340
 341         if (!cs35l56_base->init_done)
 342                 return IRQ_NONE;
 343
 344         mutex_lock(&cs35l56_base->irq_lock);
 345
 346         rv = pm_runtime_resume_and_get(cs35l56_base->dev);
 347         if (rv < 0) {
 348                 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv);
 349                 goto err_unlock;
 350         }
 351
 352         regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val);
 353         if ((val & CS35L56_IRQ1_STS_MASK) == 0) {
 354                 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n");
 355                 goto err;
 356         }
 357
 358         /* Ack interrupts */
 359         regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1);
 360         regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1);
 361         status1 &= ~mask1;
 362         regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1);
 363
 364         regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8);
 365         regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8);
 366         status8 &= ~mask8;
 367         regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8);
 368
 369         regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20);
 370         regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20);
 371         status20 &= ~mask20;
 372         /* We don't want EINT20 but they default to unmasked: force mask */
 373         regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
 374
 375         dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8);
 376
 377         /* Check to see if unmasked bits are active */
 378         if (!status1 && !status8 && !status20)
 379                 goto err;
 380
 381         if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK)
 382                 dev_crit(cs35l56_base->dev, "Amp short error\n");
 383
 384         if (status8 & CS35L56_TEMP_ERR_EINT1_MASK)
 385                 dev_crit(cs35l56_base->dev, "Overtemp error\n");
 386
 387         ret = IRQ_HANDLED;
 388
 389 err:
 390         pm_runtime_put(cs35l56_base->dev);
 391 err_unlock:
 392         mutex_unlock(&cs35l56_base->irq_lock);
 393
 394         return ret;
 395 }
 396 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35L56_SHARED);
 397
 398 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base)
 399 {
 400         unsigned int val;
 401         int ret;
 402
 403         /* Nothing to re-patch if we haven't done any patching yet. */
 404         if (!cs35l56_base->fw_patched)
 405                 return false;
 406
 407         /*
 408          * If we have control of RESET we will have asserted it so the firmware
 409          * will need re-patching.
 410          */
 411         if (cs35l56_base->reset_gpio)
 412                 return true;
 413
 414         /*
 415          * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so
 416          * can't be used here to test for memory retention.
 417          * Assume that tuning must be re-loaded.
 418          */
 419         if (cs35l56_base->secured)
 420                 return true;
 421
 422         ret = pm_runtime_resume_and_get(cs35l56_base->dev);
 423         if (ret) {
 424                 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret);
 425                 return ret;
 426         }
 427
 428         ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &val);
 429         if (ret)
 430                 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret);
 431         else
 432                 ret = !!(val & CS35L56_FIRMWARE_MISSING);
 433
 434         pm_runtime_put_autosuspend(cs35l56_base->dev);
 435
 436         return ret;
 437 }
 438 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, SND_SOC_CS35L56_SHARED);
 439
 440 static const struct reg_sequence cs35l56_hibernate_seq[] = {
 441         /* This must be the last register access */
 442         REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE),
 443 };
 444
 445 static const struct reg_sequence cs35l56_hibernate_wake_seq[] = {
 446         REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP),
 447 };
 448
 449 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base)
 450 {
 451         /*
 452          * Dummy transactions to trigger I2C/SPI auto-wake. Issue two
 453          * transactions to meet the minimum required time from the rising edge
 454          * to the last falling edge of wake.
 455          *
 456          * It uses bypassed write because we must wake the chip before
 457          * disabling regmap cache-only.
 458          *
 459          * This can NAK on I2C which will terminate the write sequence so the
 460          * single-write sequence is issued twice.
 461          */
 462         regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
 463                                         cs35l56_hibernate_wake_seq,
 464                                         ARRAY_SIZE(cs35l56_hibernate_wake_seq));
 465
 466         usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US);
 467
 468         regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
 469                                         cs35l56_hibernate_wake_seq,
 470                                         ARRAY_SIZE(cs35l56_hibernate_wake_seq));
 471
 472         cs35l56_wait_control_port_ready();
 473 }
 474
 475 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base)
 476 {
 477         unsigned int val;
 478         int ret;
 479
 480         if (!cs35l56_base->init_done)
 481                 return 0;
 482
 483         /* Firmware must have entered a power-save state */
 484         ret = regmap_read_poll_timeout(cs35l56_base->regmap,
 485                                        CS35L56_TRANSDUCER_ACTUAL_PS,
 486                                        val, (val >= CS35L56_PS3),
 487                                        CS35L56_PS3_POLL_US,
 488                                        CS35L56_PS3_TIMEOUT_US);
 489         if (ret)
 490                 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret);
 491
 492         /* Clear BOOT_DONE so it can be used to detect a reboot */
 493         regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK);
 494
 495         if (!cs35l56_base->can_hibernate) {
 496                 regcache_cache_only(cs35l56_base->regmap, true);
 497                 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate");
 498
 499                 return 0;
 500         }
 501
 502         /*
 503          * Must enter cache-only first so there can't be any more register
 504          * accesses other than the controlled hibernate sequence below.
 505          */
 506         regcache_cache_only(cs35l56_base->regmap, true);
 507
 508         regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
 509                                         cs35l56_hibernate_seq,
 510                                         ARRAY_SIZE(cs35l56_hibernate_seq));
 511
 512         dev_dbg(cs35l56_base->dev, "Suspended: hibernate");
 513
 514         return 0;
 515 }
 516 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, SND_SOC_CS35L56_SHARED);
 517
 518 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire)
 519 {
 520         unsigned int val;
 521         int ret;
 522
 523         if (!cs35l56_base->init_done)
 524                 return 0;
 525
 526         if (!cs35l56_base->can_hibernate)
 527                 goto out_sync;
 528
 529         /* Must be done before releasing cache-only */
 530         if (!is_soundwire)
 531                 cs35l56_issue_wake_event(cs35l56_base);
 532
 533 out_sync:
 534         regcache_cache_only(cs35l56_base->regmap, false);
 535
 536         ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
 537         if (ret) {
 538                 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret);
 539                 goto err;
 540         }
 541
 542         ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE);
 543         if (ret)
 544                 goto err;
 545
 546         /* BOOT_DONE will be 1 if the amp reset */
 547         regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val);
 548         if (val & CS35L56_OTP_BOOT_DONE_MASK) {
 549                 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n");
 550                 regcache_mark_dirty(cs35l56_base->regmap);
 551         }
 552
 553         regcache_sync(cs35l56_base->regmap);
 554
 555         dev_dbg(cs35l56_base->dev, "Resumed");
 556
 557         return 0;
 558
 559 err:
 560         regcache_cache_only(cs35l56_base->regmap, true);
 561
 562         regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
 563                                         cs35l56_hibernate_seq,
 564                                         ARRAY_SIZE(cs35l56_hibernate_seq));
 565
 566         return ret;
 567 }
 568 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_SHARED);
 569
 570 static const struct cs_dsp_region cs35l56_dsp1_regions[] = {
 571         { .type = WMFW_HALO_PM_PACKED,  .base = CS35L56_DSP1_PMEM_0 },
 572         { .type = WMFW_HALO_XM_PACKED,  .base = CS35L56_DSP1_XMEM_PACKED_0 },
 573         { .type = WMFW_HALO_YM_PACKED,  .base = CS35L56_DSP1_YMEM_PACKED_0 },
 574         { .type = WMFW_ADSP2_XM,        .base = CS35L56_DSP1_XMEM_UNPACKED24_0 },
 575         { .type = WMFW_ADSP2_YM,        .base = CS35L56_DSP1_YMEM_UNPACKED24_0 },
 576 };
 577
 578 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp)
 579 {
 580         cs_dsp->num = 1;
 581         cs_dsp->type = WMFW_HALO;
 582         cs_dsp->rev = 0;
 583         cs_dsp->dev = cs35l56_base->dev;
 584         cs_dsp->regmap = cs35l56_base->regmap;
 585         cs_dsp->base = CS35L56_DSP1_CORE_BASE;
 586         cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID;
 587         cs_dsp->mem = cs35l56_dsp1_regions;
 588         cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions);
 589         cs_dsp->no_core_startstop = true;
 590 }
 591 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, SND_SOC_CS35L56_SHARED);
 592
 593 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base)
 594 {
 595         int ret;
 596         unsigned int devid, revid, otpid, secured;
 597
 598         /*
 599          * When the system is not using a reset_gpio ensure the device is
 600          * awake, otherwise the device has just been released from reset and
 601          * the driver must wait for the control port to become usable.
 602          */
 603         if (!cs35l56_base->reset_gpio)
 604                 cs35l56_issue_wake_event(cs35l56_base);
 605         else
 606                 cs35l56_wait_control_port_ready();
 607
 608         /*
 609          * The HALO_STATE register is in different locations on Ax and B0
 610          * devices so the REVID needs to be determined before waiting for the
 611          * firmware to boot.
 612          */
 613         ret = regmap_read(cs35l56_base->regmap, CS35L56_REVID, &revid);
 614         if (ret < 0) {
 615                 dev_err(cs35l56_base->dev, "Get Revision ID failed\n");
 616                 return ret;
 617         }
 618         cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK);
 619
 620         ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
 621         if (ret)
 622                 return ret;
 623
 624         ret = regmap_read(cs35l56_base->regmap, CS35L56_DEVID, &devid);
 625         if (ret < 0) {
 626                 dev_err(cs35l56_base->dev, "Get Device ID failed\n");
 627                 return ret;
 628         }
 629         devid &= CS35L56_DEVID_MASK;
 630
 631         switch (devid) {
 632         case 0x35A56:
 633                 break;
 634         default:
 635                 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid);
 636                 return ret;
 637         }
 638
 639         ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured);
 640         if (ret) {
 641                 dev_err(cs35l56_base->dev, "Get Secure status failed\n");
 642                 return ret;
 643         }
 644
 645         /* When any bus is restricted treat the device as secured */
 646         if (secured & CS35L56_RESTRICTED_MASK)
 647                 cs35l56_base->secured = true;
 648
 649         ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid);
 650         if (ret < 0) {
 651                 dev_err(cs35l56_base->dev, "Get OTP ID failed\n");
 652                 return ret;
 653         }
 654
 655         dev_info(cs35l56_base->dev, "Cirrus Logic CS35L56%s Rev %02X OTP%d\n",
 656                  cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid);
 657
 658         /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */
 659         regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
 660         regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1,
 661                            CS35L56_AMP_SHORT_ERR_EINT1_MASK,
 662                            0);
 663         regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8,
 664                            CS35L56_TEMP_ERR_EINT1_MASK,
 665                            0);
 666
 667         return 0;
 668 }
 669 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, SND_SOC_CS35L56_SHARED);
 670
 671 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = {
 672         [0x0C] = 128000,
 673         [0x0F] = 256000,
 674         [0x11] = 384000,
 675         [0x12] = 512000,
 676         [0x15] = 768000,
 677         [0x17] = 1024000,
 678         [0x1A] = 1500000,
 679         [0x1B] = 1536000,
 680         [0x1C] = 2000000,
 681         [0x1D] = 2048000,
 682         [0x1E] = 2400000,
 683         [0x20] = 3000000,
 684         [0x21] = 3072000,
 685         [0x23] = 4000000,
 686         [0x24] = 4096000,
 687         [0x25] = 4800000,
 688         [0x27] = 6000000,
 689         [0x28] = 6144000,
 690         [0x29] = 6250000,
 691         [0x2A] = 6400000,
 692         [0x2E] = 8000000,
 693         [0x2F] = 8192000,
 694         [0x30] = 9600000,
 695         [0x32] = 12000000,
 696         [0x33] = 12288000,
 697         [0x37] = 13500000,
 698         [0x38] = 19200000,
 699         [0x39] = 22579200,
 700         [0x3B] = 24576000,
 701 };
 702
 703 int cs35l56_get_bclk_freq_id(unsigned int freq)
 704 {
 705         int i;
 706
 707         if (freq == 0)
 708                 return -EINVAL;
 709
 710         /* The BCLK frequency must be a valid PLL REFCLK */
 711         for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) {
 712                 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq)
 713                         return i;
 714         }
 715
 716         return -EINVAL;
 717 }
 718 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, SND_SOC_CS35L56_SHARED);
 719
 720 static const char * const cs35l56_supplies[/* auto-sized */] = {
 721         "VDD_P",
 722         "VDD_IO",
 723         "VDD_A",
 724 };
 725
 726 void cs35l56_fill_supply_names(struct regulator_bulk_data *data)
 727 {
 728         int i;
 729
 730         BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES);
 731         for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++)
 732                 data[i].supply = cs35l56_supplies[i];
 733 }
 734 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, SND_SOC_CS35L56_SHARED);
 735
 736 const char * const cs35l56_tx_input_texts[] = {
 737         "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH",
 738         "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4",
 739         "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON",
 740         "INTERPOLATOR", "SDW1RX1", "SDW1RX2",
 741 };
 742 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, SND_SOC_CS35L56_SHARED);
 743
 744 const unsigned int cs35l56_tx_input_values[] = {
 745         CS35L56_INPUT_SRC_NONE,
 746         CS35L56_INPUT_SRC_ASP1RX1,
 747         CS35L56_INPUT_SRC_ASP1RX2,
 748         CS35L56_INPUT_SRC_VMON,
 749         CS35L56_INPUT_SRC_IMON,
 750         CS35L56_INPUT_SRC_ERR_VOL,
 751         CS35L56_INPUT_SRC_CLASSH,
 752         CS35L56_INPUT_SRC_VDDBMON,
 753         CS35L56_INPUT_SRC_VBSTMON,
 754         CS35L56_INPUT_SRC_DSP1TX1,
 755         CS35L56_INPUT_SRC_DSP1TX2,
 756         CS35L56_INPUT_SRC_DSP1TX3,
 757         CS35L56_INPUT_SRC_DSP1TX4,
 758         CS35L56_INPUT_SRC_DSP1TX5,
 759         CS35L56_INPUT_SRC_DSP1TX6,
 760         CS35L56_INPUT_SRC_DSP1TX7,
 761         CS35L56_INPUT_SRC_DSP1TX8,
 762         CS35L56_INPUT_SRC_TEMPMON,
 763         CS35L56_INPUT_SRC_INTERPOLATOR,
 764         CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1,
 765         CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2,
 766 };
 767 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, SND_SOC_CS35L56_SHARED);
 768
 769 struct regmap_config cs35l56_regmap_i2c = {
 770         .reg_bits = 32,
 771         .val_bits = 32,
 772         .reg_stride = 4,
 773         .reg_format_endian = REGMAP_ENDIAN_BIG,
 774         .val_format_endian = REGMAP_ENDIAN_BIG,
 775         .max_register = CS35L56_DSP1_PMEM_5114,
 776         .reg_defaults = cs35l56_reg_defaults,
 777         .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
 778         .volatile_reg = cs35l56_volatile_reg,
 779         .readable_reg = cs35l56_readable_reg,
 780         .precious_reg = cs35l56_precious_reg,
 781         .cache_type = REGCACHE_MAPLE,
 782 };
 783 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, SND_SOC_CS35L56_SHARED);
 784
 785 struct regmap_config cs35l56_regmap_spi = {
 786         .reg_bits = 32,
 787         .val_bits = 32,
 788         .pad_bits = 16,
 789         .reg_stride = 4,
 790         .reg_format_endian = REGMAP_ENDIAN_BIG,
 791         .val_format_endian = REGMAP_ENDIAN_BIG,
 792         .max_register = CS35L56_DSP1_PMEM_5114,
 793         .reg_defaults = cs35l56_reg_defaults,
 794         .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
 795         .volatile_reg = cs35l56_volatile_reg,
 796         .readable_reg = cs35l56_readable_reg,
 797         .precious_reg = cs35l56_precious_reg,
 798         .cache_type = REGCACHE_MAPLE,
 799 };
 800 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, SND_SOC_CS35L56_SHARED);
 801
 802 struct regmap_config cs35l56_regmap_sdw = {
 803         .reg_bits = 32,
 804         .val_bits = 32,
 805         .reg_stride = 4,
 806         .reg_format_endian = REGMAP_ENDIAN_LITTLE,
 807         .val_format_endian = REGMAP_ENDIAN_BIG,
 808         .max_register = CS35L56_DSP1_PMEM_5114,
 809         .reg_defaults = cs35l56_reg_defaults,
 810         .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
 811         .volatile_reg = cs35l56_volatile_reg,
 812         .readable_reg = cs35l56_readable_reg,
 813         .precious_reg = cs35l56_precious_reg,
 814         .cache_type = REGCACHE_MAPLE,
 815 };
 816 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, SND_SOC_CS35L56_SHARED);
 817
 818 MODULE_DESCRIPTION("ASoC CS35L56 Shared");
 819 MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
 820 MODULE_AUTHOR("Simon Trimmer <[email protected]>");
 821 MODULE_LICENSE("GPL");