drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_11_0_0_offset.h"
  34 #include "gc/gc_11_0_0_sh_mask.h"
  35 #include "gc/gc_11_0_0_default.h"
  36 #include "hdp/hdp_6_0_0_offset.h"
  37 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
  38
  39 #include "soc15_common.h"
  40 #include "soc15.h"
  41 #include "sdma_v6_0_0_pkt_open.h"
  42 #include "nbio_v4_3.h"
  43 #include "sdma_common.h"
  44 #include "sdma_v6_0.h"
  45 #include "v11_structs.h"
  46
  47 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin");
  48 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin");
  49 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin");
  50 MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin");
  51 MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin");
  52 MODULE_FIRMWARE("amdgpu/sdma_6_1_1.bin");
  53 MODULE_FIRMWARE("amdgpu/sdma_6_1_2.bin");
  54
  55 #define SDMA1_REG_OFFSET 0x600
  56 #define SDMA0_HYP_DEC_REG_START 0x5880
  57 #define SDMA0_HYP_DEC_REG_END 0x589a
  58 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  59
  60 static const struct amdgpu_hwip_reg_entry sdma_reg_list_6_0[] = {
  61         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG),
  62         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG),
  63         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG),
  64         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG),
  65         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG),
  66         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG),
  67         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG),
  68         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_CHECKSUM),
  69         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI),
  70         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH),
  71         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_STATUS),
  72         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_STATUS),
  73         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK0),
  74         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK1),
  75         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK0),
  76         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK1),
  77         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL),
  78         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR),
  79         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR_HI),
  80         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR),
  81         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR_HI),
  82         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_OFFSET),
  83         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_LO),
  84         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_HI),
  85         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_CNTL),
  86         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_RPTR),
  87         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_SUB_REMAIN),
  88         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_DUMMY_REG),
  89         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE_STATUS0),
  90         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_CNTL),
  91         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR),
  92         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR_HI),
  93         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR),
  94         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR_HI),
  95         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_OFFSET),
  96         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_LO),
  97         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_HI),
  98         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_RPTR),
  99         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_SUB_REMAIN),
 100         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_DUMMY_REG),
 101         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_CNTL),
 102         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR),
 103         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR_HI),
 104         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR),
 105         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR_HI),
 106         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_OFFSET),
 107         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_LO),
 108         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_HI),
 109         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_RPTR),
 110         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_SUB_REMAIN),
 111         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_DUMMY_REG),
 112         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS),
 113         SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
 114         SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_CHICKEN_BITS),
 115 };
 116
 117 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev);
 118 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev);
 119 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev);
 120 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev);
 121 static int sdma_v6_0_start(struct amdgpu_device *adev);
 122
 123 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
 124 {
 125         u32 base;
 126
 127         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
 128             internal_offset <= SDMA0_HYP_DEC_REG_END) {
 129                 base = adev->reg_offset[GC_HWIP][0][1];
 130                 if (instance != 0)
 131                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
 132         } else {
 133                 base = adev->reg_offset[GC_HWIP][0][0];
 134                 if (instance == 1)
 135                         internal_offset += SDMA1_REG_OFFSET;
 136         }
 137
 138         return base + internal_offset;
 139 }
 140
 141 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring,
 142                                               uint64_t addr)
 143 {
 144         unsigned ret;
 145
 146         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE));
 147         amdgpu_ring_write(ring, lower_32_bits(addr));
 148         amdgpu_ring_write(ring, upper_32_bits(addr));
 149         amdgpu_ring_write(ring, 1);
 150         /* this is the offset we need patch later */
 151         ret = ring->wptr & ring->buf_mask;
 152         /* insert dummy here and patch it later */
 153         amdgpu_ring_write(ring, 0);
 154
 155         return ret;
 156 }
 157
 158 /**
 159  * sdma_v6_0_ring_get_rptr - get the current read pointer
 160  *
 161  * @ring: amdgpu ring pointer
 162  *
 163  * Get the current rptr from the hardware.
 164  */
 165 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
 166 {
 167         u64 *rptr;
 168
 169         /* XXX check if swapping is necessary on BE */
 170         rptr = (u64 *)ring->rptr_cpu_addr;
 171
 172         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 173         return ((*rptr) >> 2);
 174 }
 175
 176 /**
 177  * sdma_v6_0_ring_get_wptr - get the current write pointer
 178  *
 179  * @ring: amdgpu ring pointer
 180  *
 181  * Get the current wptr from the hardware.
 182  */
 183 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
 184 {
 185         u64 wptr = 0;
 186
 187         if (ring->use_doorbell) {
 188                 /* XXX check if swapping is necessary on BE */
 189                 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
 190                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 191         }
 192
 193         return wptr >> 2;
 194 }
 195
 196 /**
 197  * sdma_v6_0_ring_set_wptr - commit the write pointer
 198  *
 199  * @ring: amdgpu ring pointer
 200  *
 201  * Write the wptr back to the hardware.
 202  */
 203 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
 204 {
 205         struct amdgpu_device *adev = ring->adev;
 206
 207         if (ring->use_doorbell) {
 208                 DRM_DEBUG("Using doorbell -- "
 209                           "wptr_offs == 0x%08x "
 210                           "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 211                           "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 212                           ring->wptr_offs,
 213                           lower_32_bits(ring->wptr << 2),
 214                           upper_32_bits(ring->wptr << 2));
 215                 /* XXX check if swapping is necessary on BE */
 216                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
 217                              ring->wptr << 2);
 218                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 219                           ring->doorbell_index, ring->wptr << 2);
 220                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 221         } else {
 222                 DRM_DEBUG("Not using doorbell -- "
 223                           "regSDMA%i_GFX_RB_WPTR == 0x%08x "
 224                           "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 225                           ring->me,
 226                           lower_32_bits(ring->wptr << 2),
 227                           ring->me,
 228                           upper_32_bits(ring->wptr << 2));
 229                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
 230                                                              ring->me, regSDMA0_QUEUE0_RB_WPTR),
 231                                 lower_32_bits(ring->wptr << 2));
 232                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
 233                                                              ring->me, regSDMA0_QUEUE0_RB_WPTR_HI),
 234                                 upper_32_bits(ring->wptr << 2));
 235         }
 236 }
 237
 238 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 239 {
 240         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 241         int i;
 242
 243         for (i = 0; i < count; i++)
 244                 if (sdma && sdma->burst_nop && (i == 0))
 245                         amdgpu_ring_write(ring, ring->funcs->nop |
 246                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 247                 else
 248                         amdgpu_ring_write(ring, ring->funcs->nop);
 249 }
 250
 251 /*
 252  * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine
 253  *
 254  * @ring: amdgpu ring pointer
 255  * @ib: IB object to schedule
 256  * @flags: unused
 257  * @job: job to retrieve vmid from
 258  *
 259  * Schedule an IB in the DMA ring.
 260  */
 261 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
 262                                    struct amdgpu_job *job,
 263                                    struct amdgpu_ib *ib,
 264                                    uint32_t flags)
 265 {
 266         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 267         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 268
 269         /* An IB packet must end on a 8 DW boundary--the next dword
 270          * must be on a 8-dword boundary. Our IB packet below is 6
 271          * dwords long, thus add x number of NOPs, such that, in
 272          * modular arithmetic,
 273          * wptr + 6 + x = 8k, k >= 0, which in C is,
 274          * (wptr + 6 + x) % 8 = 0.
 275          * The expression below, is a solution of x.
 276          */
 277         sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 278
 279         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) |
 280                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 281         /* base must be 32 byte aligned */
 282         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 283         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 284         amdgpu_ring_write(ring, ib->length_dw);
 285         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 286         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 287 }
 288
 289 /**
 290  * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
 291  *
 292  * @ring: amdgpu ring pointer
 293  *
 294  * flush the IB by graphics cache rinse.
 295  */
 296 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
 297 {
 298         uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
 299                             SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
 300                             SDMA_GCR_GLI_INV(1);
 301
 302         /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
 303         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ));
 304         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
 305         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
 306                           SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
 307         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
 308                           SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
 309         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
 310                           SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
 311 }
 312
 313
 314 /**
 315  * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 316  *
 317  * @ring: amdgpu ring pointer
 318  *
 319  * Emit an hdp flush packet on the requested DMA ring.
 320  */
 321 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 322 {
 323         struct amdgpu_device *adev = ring->adev;
 324         u32 ref_and_mask = 0;
 325         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 326
 327         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 328
 329         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 330                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 331                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 332         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 333         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 334         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 335         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 336         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 337                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 338 }
 339
 340 /**
 341  * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring
 342  *
 343  * @ring: amdgpu ring pointer
 344  * @addr: address
 345  * @seq: fence seq number
 346  * @flags: fence flags
 347  *
 348  * Add a DMA fence packet to the ring to write
 349  * the fence seq number and DMA trap packet to generate
 350  * an interrupt if needed.
 351  */
 352 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 353                                       unsigned flags)
 354 {
 355         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 356         /* write the fence */
 357         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
 358                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 359         /* zero in first two bits */
 360         BUG_ON(addr & 0x3);
 361         amdgpu_ring_write(ring, lower_32_bits(addr));
 362         amdgpu_ring_write(ring, upper_32_bits(addr));
 363         amdgpu_ring_write(ring, lower_32_bits(seq));
 364
 365         /* optionally write high bits as well */
 366         if (write64bit) {
 367                 addr += 4;
 368                 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
 369                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 370                 /* zero in first two bits */
 371                 BUG_ON(addr & 0x3);
 372                 amdgpu_ring_write(ring, lower_32_bits(addr));
 373                 amdgpu_ring_write(ring, upper_32_bits(addr));
 374                 amdgpu_ring_write(ring, upper_32_bits(seq));
 375         }
 376
 377         if (flags & AMDGPU_FENCE_FLAG_INT) {
 378                 uint32_t ctx = ring->is_mes_queue ?
 379                         (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
 380                 /* generate an interrupt */
 381                 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP));
 382                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
 383         }
 384 }
 385
 386 /**
 387  * sdma_v6_0_gfx_stop - stop the gfx async dma engines
 388  *
 389  * @adev: amdgpu_device pointer
 390  *
 391  * Stop the gfx async dma ring buffers.
 392  */
 393 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev)
 394 {
 395         u32 rb_cntl, ib_cntl;
 396         int i;
 397
 398         for (i = 0; i < adev->sdma.num_instances; i++) {
 399                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
 400                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0);
 401                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
 402                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
 403                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0);
 404                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
 405         }
 406 }
 407
 408 /**
 409  * sdma_v6_0_rlc_stop - stop the compute async dma engines
 410  *
 411  * @adev: amdgpu_device pointer
 412  *
 413  * Stop the compute async dma queues.
 414  */
 415 static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev)
 416 {
 417         /* XXX todo */
 418 }
 419
 420 /**
 421  * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts
 422  *
 423  * @adev: amdgpu_device pointer
 424  * @enable: enable/disable context switching due to queue empty conditions
 425  *
 426  * Enable or disable the async dma engines queue empty context switch.
 427  */
 428 static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable)
 429 {
 430         u32 f32_cntl;
 431         int i;
 432
 433         if (!amdgpu_sriov_vf(adev)) {
 434                 for (i = 0; i < adev->sdma.num_instances; i++) {
 435                         f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL));
 436                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 437                                         CTXEMPTY_INT_ENABLE, enable ? 1 : 0);
 438                         WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl);
 439                 }
 440         }
 441 }
 442
 443 /**
 444  * sdma_v6_0_enable - stop the async dma engines
 445  *
 446  * @adev: amdgpu_device pointer
 447  * @enable: enable/disable the DMA MEs.
 448  *
 449  * Halt or unhalt the async dma engines.
 450  */
 451 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)
 452 {
 453         u32 f32_cntl;
 454         int i;
 455
 456         if (!enable) {
 457                 sdma_v6_0_gfx_stop(adev);
 458                 sdma_v6_0_rlc_stop(adev);
 459         }
 460
 461         if (amdgpu_sriov_vf(adev))
 462                 return;
 463
 464         for (i = 0; i < adev->sdma.num_instances; i++) {
 465                 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
 466                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 467                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl);
 468         }
 469 }
 470
 471 /**
 472  * sdma_v6_0_gfx_resume - setup and start the async dma engines
 473  *
 474  * @adev: amdgpu_device pointer
 475  *
 476  * Set up the gfx DMA ring buffers and enable them.
 477  * Returns 0 for success, error for failure.
 478  */
 479 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
 480 {
 481         struct amdgpu_ring *ring;
 482         u32 rb_cntl, ib_cntl;
 483         u32 rb_bufsz;
 484         u32 doorbell;
 485         u32 doorbell_offset;
 486         u32 temp;
 487         u64 wptr_gpu_addr;
 488         int i, r;
 489
 490         for (i = 0; i < adev->sdma.num_instances; i++) {
 491                 ring = &adev->sdma.instance[i].ring;
 492
 493                 if (!amdgpu_sriov_vf(adev))
 494                         WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 495
 496                 /* Set ring buffer size in dwords */
 497                 rb_bufsz = order_base_2(ring->ring_size / 4);
 498                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
 499                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);
 500 #ifdef __BIG_ENDIAN
 501                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);
 502                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,
 503                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 504 #endif
 505                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);
 506                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
 507
 508                 /* Initialize the ring buffer's read and write pointers */
 509                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
 510                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
 511                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
 512                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
 513
 514                 /* setup the wptr shadow polling */
 515                 wptr_gpu_addr = ring->wptr_gpu_addr;
 516                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
 517                        lower_32_bits(wptr_gpu_addr));
 518                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),
 519                        upper_32_bits(wptr_gpu_addr));
 520
 521                 /* set the wb address whether it's enabled or not */
 522                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),
 523                        upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
 524                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),
 525                        lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
 526
 527                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 528                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);
 529                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);
 530
 531                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
 532                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
 533
 534                 ring->wptr = 0;
 535
 536                 /* before programing wptr to a less value, need set minor_ptr_update first */
 537                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
 538
 539                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 540                         WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 541                         WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 542                 }
 543
 544                 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));
 545                 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));
 546
 547                 if (ring->use_doorbell) {
 548                         doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
 549                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,
 550                                         OFFSET, ring->doorbell_index);
 551                 } else {
 552                         doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);
 553                 }
 554                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);
 555                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);
 556
 557                 if (i == 0)
 558                         adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 559                                                       ring->doorbell_index,
 560                                                       adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances);
 561
 562                 if (amdgpu_sriov_vf(adev))
 563                         sdma_v6_0_ring_set_wptr(ring);
 564
 565                 /* set minor_ptr_update to 0 after wptr programed */
 566                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);
 567
 568                 /* Set up sdma hang watchdog */
 569                 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL));
 570                 /* 100ms per unit */
 571                 temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT,
 572                                      max(adev->usec_timeout/100000, 1));
 573                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp);
 574
 575                 /* Set up RESP_MODE to non-copy addresses */
 576                 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));
 577                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 578                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 579                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);
 580
 581                 /* program default cache read and write policy */
 582                 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));
 583                 /* clean read policy and write policy bits */
 584                 temp &= 0xFF0FFF;
 585                 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 586                          (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
 587                          SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
 588                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);
 589
 590                 if (!amdgpu_sriov_vf(adev)) {
 591                         /* unhalt engine */
 592                         temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
 593                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 594                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0);
 595                         WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);
 596                 }
 597
 598                 /* enable DMA RB */
 599                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);
 600                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
 601
 602                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
 603                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);
 604 #ifdef __BIG_ENDIAN
 605                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);
 606 #endif
 607                 /* enable DMA IBs */
 608                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
 609
 610                 if (amdgpu_sriov_vf(adev))
 611                         sdma_v6_0_enable(adev, true);
 612
 613                 r = amdgpu_ring_test_helper(ring);
 614                 if (r)
 615                         return r;
 616         }
 617
 618         return 0;
 619 }
 620
 621 /**
 622  * sdma_v6_0_rlc_resume - setup and start the async dma engines
 623  *
 624  * @adev: amdgpu_device pointer
 625  *
 626  * Set up the compute DMA queues and enable them.
 627  * Returns 0 for success, error for failure.
 628  */
 629 static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev)
 630 {
 631         return 0;
 632 }
 633
 634 /**
 635  * sdma_v6_0_load_microcode - load the sDMA ME ucode
 636  *
 637  * @adev: amdgpu_device pointer
 638  *
 639  * Loads the sDMA0/1 ucode.
 640  * Returns 0 for success, -EINVAL if the ucode is not available.
 641  */
 642 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev)
 643 {
 644         const struct sdma_firmware_header_v2_0 *hdr;
 645         const __le32 *fw_data;
 646         u32 fw_size;
 647         int i, j;
 648         bool use_broadcast;
 649
 650         /* halt the MEs */
 651         sdma_v6_0_enable(adev, false);
 652
 653         if (!adev->sdma.instance[0].fw)
 654                 return -EINVAL;
 655
 656         /* use broadcast mode to load SDMA microcode by default */
 657         use_broadcast = true;
 658
 659         if (use_broadcast) {
 660                 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n");
 661                 /* load Control Thread microcode */
 662                 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
 663                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 664                 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
 665
 666                 fw_data = (const __le32 *)
 667                         (adev->sdma.instance[0].fw->data +
 668                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 669
 670                 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0);
 671
 672                 for (j = 0; j < fw_size; j++) {
 673                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 674                                 msleep(1);
 675                         WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
 676                 }
 677
 678                 /* load Context Switch microcode */
 679                 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
 680
 681                 fw_data = (const __le32 *)
 682                         (adev->sdma.instance[0].fw->data +
 683                                 le32_to_cpu(hdr->ctl_ucode_offset));
 684
 685                 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000);
 686
 687                 for (j = 0; j < fw_size; j++) {
 688                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 689                                 msleep(1);
 690                         WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
 691                 }
 692         } else {
 693                 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n");
 694                 for (i = 0; i < adev->sdma.num_instances; i++) {
 695                         /* load Control Thread microcode */
 696                         hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
 697                         amdgpu_ucode_print_sdma_hdr(&hdr->header);
 698                         fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
 699
 700                         fw_data = (const __le32 *)
 701                                 (adev->sdma.instance[0].fw->data +
 702                                         le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 703
 704                         WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0);
 705
 706                         for (j = 0; j < fw_size; j++) {
 707                                 if (amdgpu_emu_mode == 1 && j % 500 == 0)
 708                                         msleep(1);
 709                                 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 710                         }
 711
 712                         WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
 713
 714                         /* load Context Switch microcode */
 715                         fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
 716
 717                         fw_data = (const __le32 *)
 718                                 (adev->sdma.instance[0].fw->data +
 719                                         le32_to_cpu(hdr->ctl_ucode_offset));
 720
 721                         WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000);
 722
 723                         for (j = 0; j < fw_size; j++) {
 724                                 if (amdgpu_emu_mode == 1 && j % 500 == 0)
 725                                         msleep(1);
 726                                 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 727                         }
 728
 729                         WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
 730                 }
 731         }
 732
 733         return 0;
 734 }
 735
 736 static int sdma_v6_0_soft_reset(void *handle)
 737 {
 738         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 739         u32 tmp;
 740         int i;
 741
 742         sdma_v6_0_gfx_stop(adev);
 743
 744         for (i = 0; i < adev->sdma.num_instances; i++) {
 745                 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE));
 746                 tmp |= SDMA0_FREEZE__FREEZE_MASK;
 747                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);
 748                 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
 749                 tmp |= SDMA0_F32_CNTL__HALT_MASK;
 750                 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK;
 751                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp);
 752
 753                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);
 754
 755                 udelay(100);
 756
 757                 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i;
 758                 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
 759                 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
 760
 761                 udelay(100);
 762
 763                 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0);
 764                 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
 765
 766                 udelay(100);
 767         }
 768
 769         return sdma_v6_0_start(adev);
 770 }
 771
 772 static bool sdma_v6_0_check_soft_reset(void *handle)
 773 {
 774         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 775         struct amdgpu_ring *ring;
 776         int i, r;
 777         long tmo = msecs_to_jiffies(1000);
 778
 779         for (i = 0; i < adev->sdma.num_instances; i++) {
 780                 ring = &adev->sdma.instance[i].ring;
 781                 r = amdgpu_ring_test_ib(ring, tmo);
 782                 if (r)
 783                         return true;
 784         }
 785
 786         return false;
 787 }
 788
 789 /**
 790  * sdma_v6_0_start - setup and start the async dma engines
 791  *
 792  * @adev: amdgpu_device pointer
 793  *
 794  * Set up the DMA engines and enable them.
 795  * Returns 0 for success, error for failure.
 796  */
 797 static int sdma_v6_0_start(struct amdgpu_device *adev)
 798 {
 799         int r = 0;
 800
 801         if (amdgpu_sriov_vf(adev)) {
 802                 sdma_v6_0_enable(adev, false);
 803
 804                 /* set RB registers */
 805                 r = sdma_v6_0_gfx_resume(adev);
 806                 return r;
 807         }
 808
 809         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 810                 r = sdma_v6_0_load_microcode(adev);
 811                 if (r)
 812                         return r;
 813
 814                 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */
 815                 if (amdgpu_emu_mode == 1)
 816                         msleep(1000);
 817         }
 818
 819         /* unhalt the MEs */
 820         sdma_v6_0_enable(adev, true);
 821         /* enable sdma ring preemption */
 822         sdma_v6_0_ctxempty_int_enable(adev, true);
 823
 824         /* start the gfx rings and rlc compute queues */
 825         r = sdma_v6_0_gfx_resume(adev);
 826         if (r)
 827                 return r;
 828         r = sdma_v6_0_rlc_resume(adev);
 829
 830         return r;
 831 }
 832
 833 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd,
 834                               struct amdgpu_mqd_prop *prop)
 835 {
 836         struct v11_sdma_mqd *m = mqd;
 837         uint64_t wb_gpu_addr;
 838
 839         m->sdmax_rlcx_rb_cntl =
 840                 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
 841                 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
 842                 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
 843                 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT;
 844
 845         m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
 846         m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
 847
 848         wb_gpu_addr = prop->wptr_gpu_addr;
 849         m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
 850         m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
 851
 852         wb_gpu_addr = prop->rptr_gpu_addr;
 853         m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
 854         m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
 855
 856         m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0,
 857                                                         regSDMA0_QUEUE0_IB_CNTL));
 858
 859         m->sdmax_rlcx_doorbell_offset =
 860                 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;
 861
 862         m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
 863
 864         m->sdmax_rlcx_skip_cntl = 0;
 865         m->sdmax_rlcx_context_status = 0;
 866         m->sdmax_rlcx_doorbell_log = 0;
 867
 868         m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT;
 869         m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT;
 870
 871         return 0;
 872 }
 873
 874 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev)
 875 {
 876         adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd);
 877         adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init;
 878 }
 879
 880 /**
 881  * sdma_v6_0_ring_test_ring - simple async dma engine test
 882  *
 883  * @ring: amdgpu_ring structure holding ring information
 884  *
 885  * Test the DMA engine by writing using it to write an
 886  * value to memory.
 887  * Returns 0 for success, error for failure.
 888  */
 889 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 890 {
 891         struct amdgpu_device *adev = ring->adev;
 892         unsigned i;
 893         unsigned index;
 894         int r;
 895         u32 tmp;
 896         u64 gpu_addr;
 897         volatile uint32_t *cpu_ptr = NULL;
 898
 899         tmp = 0xCAFEDEAD;
 900
 901         if (ring->is_mes_queue) {
 902                 uint32_t offset = 0;
 903                 offset = amdgpu_mes_ctx_get_offs(ring,
 904                                          AMDGPU_MES_CTX_PADDING_OFFS);
 905                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 906                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 907                 *cpu_ptr = tmp;
 908         } else {
 909                 r = amdgpu_device_wb_get(adev, &index);
 910                 if (r) {
 911                         dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 912                         return r;
 913                 }
 914
 915                 gpu_addr = adev->wb.gpu_addr + (index * 4);
 916                 adev->wb.wb[index] = cpu_to_le32(tmp);
 917         }
 918
 919         r = amdgpu_ring_alloc(ring, 5);
 920         if (r) {
 921                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 922                 if (!ring->is_mes_queue)
 923                         amdgpu_device_wb_free(adev, index);
 924                 return r;
 925         }
 926
 927         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
 928                           SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 929         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 930         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 931         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 932         amdgpu_ring_write(ring, 0xDEADBEEF);
 933         amdgpu_ring_commit(ring);
 934
 935         for (i = 0; i < adev->usec_timeout; i++) {
 936                 if (ring->is_mes_queue)
 937                         tmp = le32_to_cpu(*cpu_ptr);
 938                 else
 939                         tmp = le32_to_cpu(adev->wb.wb[index]);
 940                 if (tmp == 0xDEADBEEF)
 941                         break;
 942                 if (amdgpu_emu_mode == 1)
 943                         msleep(1);
 944                 else
 945                         udelay(1);
 946         }
 947
 948         if (i >= adev->usec_timeout)
 949                 r = -ETIMEDOUT;
 950
 951         if (!ring->is_mes_queue)
 952                 amdgpu_device_wb_free(adev, index);
 953
 954         return r;
 955 }
 956
 957 /*
 958  * sdma_v6_0_ring_test_ib - test an IB on the DMA engine
 959  *
 960  * @ring: amdgpu_ring structure holding ring information
 961  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 962  *
 963  * Test a simple IB in the DMA ring.
 964  * Returns 0 on success, error on failure.
 965  */
 966 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 967 {
 968         struct amdgpu_device *adev = ring->adev;
 969         struct amdgpu_ib ib;
 970         struct dma_fence *f = NULL;
 971         unsigned index;
 972         long r;
 973         u32 tmp = 0;
 974         u64 gpu_addr;
 975         volatile uint32_t *cpu_ptr = NULL;
 976
 977         tmp = 0xCAFEDEAD;
 978         memset(&ib, 0, sizeof(ib));
 979
 980         if (ring->is_mes_queue) {
 981                 uint32_t offset = 0;
 982                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
 983                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 984                 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 985
 986                 offset = amdgpu_mes_ctx_get_offs(ring,
 987                                          AMDGPU_MES_CTX_PADDING_OFFS);
 988                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 989                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 990                 *cpu_ptr = tmp;
 991         } else {
 992                 r = amdgpu_device_wb_get(adev, &index);
 993                 if (r) {
 994                         dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 995                         return r;
 996                 }
 997
 998                 gpu_addr = adev->wb.gpu_addr + (index * 4);
 999                 adev->wb.wb[index] = cpu_to_le32(tmp);
1000
1001                 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
1002                 if (r) {
1003                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1004                         goto err0;
1005                 }
1006         }
1007
1008         ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1009                 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1010         ib.ptr[1] = lower_32_bits(gpu_addr);
1011         ib.ptr[2] = upper_32_bits(gpu_addr);
1012         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1013         ib.ptr[4] = 0xDEADBEEF;
1014         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1015         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1016         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1017         ib.length_dw = 8;
1018
1019         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1020         if (r)
1021                 goto err1;
1022
1023         r = dma_fence_wait_timeout(f, false, timeout);
1024         if (r == 0) {
1025                 DRM_ERROR("amdgpu: IB test timed out\n");
1026                 r = -ETIMEDOUT;
1027                 goto err1;
1028         } else if (r < 0) {
1029                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1030                 goto err1;
1031         }
1032
1033         if (ring->is_mes_queue)
1034                 tmp = le32_to_cpu(*cpu_ptr);
1035         else
1036                 tmp = le32_to_cpu(adev->wb.wb[index]);
1037
1038         if (tmp == 0xDEADBEEF)
1039                 r = 0;
1040         else
1041                 r = -EINVAL;
1042
1043 err1:
1044         amdgpu_ib_free(adev, &ib, NULL);
1045         dma_fence_put(f);
1046 err0:
1047         if (!ring->is_mes_queue)
1048                 amdgpu_device_wb_free(adev, index);
1049         return r;
1050 }
1051
1052
1053 /**
1054  * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART
1055  *
1056  * @ib: indirect buffer to fill with commands
1057  * @pe: addr of the page entry
1058  * @src: src addr to copy from
1059  * @count: number of page entries to update
1060  *
1061  * Update PTEs by copying them from the GART using sDMA.
1062  */
1063 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib,
1064                                   uint64_t pe, uint64_t src,
1065                                   unsigned count)
1066 {
1067         unsigned bytes = count * 8;
1068
1069         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1070                 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1071         ib->ptr[ib->length_dw++] = bytes - 1;
1072         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1073         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1074         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1075         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1076         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1077
1078 }
1079
1080 /**
1081  * sdma_v6_0_vm_write_pte - update PTEs by writing them manually
1082  *
1083  * @ib: indirect buffer to fill with commands
1084  * @pe: addr of the page entry
1085  * @value: dst addr to write into pe
1086  * @count: number of page entries to update
1087  * @incr: increase next addr by incr bytes
1088  *
1089  * Update PTEs by writing them manually using sDMA.
1090  */
1091 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1092                                    uint64_t value, unsigned count,
1093                                    uint32_t incr)
1094 {
1095         unsigned ndw = count * 2;
1096
1097         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1098                 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1099         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1100         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1101         ib->ptr[ib->length_dw++] = ndw - 1;
1102         for (; ndw > 0; ndw -= 2) {
1103                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1104                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1105                 value += incr;
1106         }
1107 }
1108
1109 /**
1110  * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA
1111  *
1112  * @ib: indirect buffer to fill with commands
1113  * @pe: addr of the page entry
1114  * @addr: dst addr to write into pe
1115  * @count: number of page entries to update
1116  * @incr: increase next addr by incr bytes
1117  * @flags: access flags
1118  *
1119  * Update the page tables using sDMA.
1120  */
1121 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1122                                      uint64_t pe,
1123                                      uint64_t addr, unsigned count,
1124                                      uint32_t incr, uint64_t flags)
1125 {
1126         /* for physically contiguous pages (vram) */
1127         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE);
1128         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1129         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1130         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1131         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1132         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1133         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1134         ib->ptr[ib->length_dw++] = incr; /* increment size */
1135         ib->ptr[ib->length_dw++] = 0;
1136         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1137 }
1138
1139 /*
1140  * sdma_v6_0_ring_pad_ib - pad the IB
1141  * @ib: indirect buffer to fill with padding
1142  * @ring: amdgpu ring pointer
1143  *
1144  * Pad the IB with NOPs to a boundary multiple of 8.
1145  */
1146 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1147 {
1148         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1149         u32 pad_count;
1150         int i;
1151
1152         pad_count = (-ib->length_dw) & 0x7;
1153         for (i = 0; i < pad_count; i++)
1154                 if (sdma && sdma->burst_nop && (i == 0))
1155                         ib->ptr[ib->length_dw++] =
1156                                 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) |
1157                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1158                 else
1159                         ib->ptr[ib->length_dw++] =
1160                                 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP);
1161 }
1162
1163 /**
1164  * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline
1165  *
1166  * @ring: amdgpu_ring pointer
1167  *
1168  * Make sure all previous operations are completed (CIK).
1169  */
1170 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1171 {
1172         uint32_t seq = ring->fence_drv.sync_seq;
1173         uint64_t addr = ring->fence_drv.gpu_addr;
1174
1175         /* wait for idle */
1176         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1177                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1178                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1179                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1180         amdgpu_ring_write(ring, addr & 0xfffffffc);
1181         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1182         amdgpu_ring_write(ring, seq); /* reference */
1183         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1184         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1185                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1186 }
1187
1188 /*
1189  * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA
1190  *
1191  * @ring: amdgpu_ring pointer
1192  * @vmid: vmid number to use
1193  * @pd_addr: address
1194  *
1195  * Update the page table base and flush the VM TLB
1196  * using sDMA.
1197  */
1198 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1199                                          unsigned vmid, uint64_t pd_addr)
1200 {
1201         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1202         uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
1203
1204         /* Update the PD address for this VMID. */
1205         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
1206                               (hub->ctx_addr_distance * vmid),
1207                               lower_32_bits(pd_addr));
1208         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
1209                               (hub->ctx_addr_distance * vmid),
1210                               upper_32_bits(pd_addr));
1211
1212         /* Trigger invalidation. */
1213         amdgpu_ring_write(ring,
1214                           SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1215                           SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) |
1216                           SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) |
1217                           SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f));
1218         amdgpu_ring_write(ring, req);
1219         amdgpu_ring_write(ring, 0xFFFFFFFF);
1220         amdgpu_ring_write(ring,
1221                           SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) |
1222                           SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F));
1223 }
1224
1225 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
1226                                      uint32_t reg, uint32_t val)
1227 {
1228         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1229                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1230         amdgpu_ring_write(ring, reg);
1231         amdgpu_ring_write(ring, val);
1232 }
1233
1234 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1235                                          uint32_t val, uint32_t mask)
1236 {
1237         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1238                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1239                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1240         amdgpu_ring_write(ring, reg << 2);
1241         amdgpu_ring_write(ring, 0);
1242         amdgpu_ring_write(ring, val); /* reference */
1243         amdgpu_ring_write(ring, mask); /* mask */
1244         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1245                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1246 }
1247
1248 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1249                                                    uint32_t reg0, uint32_t reg1,
1250                                                    uint32_t ref, uint32_t mask)
1251 {
1252         amdgpu_ring_emit_wreg(ring, reg0, ref);
1253         /* wait for a cycle to reset vm_inv_eng*_ack */
1254         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1255         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1256 }
1257
1258 static struct amdgpu_sdma_ras sdma_v6_0_3_ras = {
1259         .ras_block = {
1260                 .ras_late_init = amdgpu_ras_block_late_init,
1261         },
1262 };
1263
1264 static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev)
1265 {
1266         switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1267         case IP_VERSION(6, 0, 3):
1268                 adev->sdma.ras = &sdma_v6_0_3_ras;
1269                 break;
1270         default:
1271                 break;
1272         }
1273 }
1274
1275 static int sdma_v6_0_early_init(void *handle)
1276 {
1277         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1278         int r;
1279
1280         r = amdgpu_sdma_init_microcode(adev, 0, true);
1281         if (r)
1282                 return r;
1283
1284         sdma_v6_0_set_ring_funcs(adev);
1285         sdma_v6_0_set_buffer_funcs(adev);
1286         sdma_v6_0_set_vm_pte_funcs(adev);
1287         sdma_v6_0_set_irq_funcs(adev);
1288         sdma_v6_0_set_mqd_funcs(adev);
1289         sdma_v6_0_set_ras_funcs(adev);
1290
1291         return 0;
1292 }
1293
1294 static int sdma_v6_0_sw_init(void *handle)
1295 {
1296         struct amdgpu_ring *ring;
1297         int r, i;
1298         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1299         uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);
1300         uint32_t *ptr;
1301
1302         /* SDMA trap event */
1303         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1304                               GFX_11_0_0__SRCID__SDMA_TRAP,
1305                               &adev->sdma.trap_irq);
1306         if (r)
1307                 return r;
1308
1309         for (i = 0; i < adev->sdma.num_instances; i++) {
1310                 ring = &adev->sdma.instance[i].ring;
1311                 ring->ring_obj = NULL;
1312                 ring->use_doorbell = true;
1313                 ring->me = i;
1314
1315                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1316                                 ring->use_doorbell?"true":"false");
1317
1318                 ring->doorbell_index =
1319                         (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset
1320
1321                 ring->vm_hub = AMDGPU_GFXHUB(0);
1322                 sprintf(ring->name, "sdma%d", i);
1323                 r = amdgpu_ring_init(adev, ring, 1024,
1324                                      &adev->sdma.trap_irq,
1325                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1326                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1327                 if (r)
1328                         return r;
1329         }
1330
1331         if (amdgpu_sdma_ras_sw_init(adev)) {
1332                 dev_err(adev->dev, "Failed to initialize sdma ras block!\n");
1333                 return -EINVAL;
1334         }
1335
1336         /* Allocate memory for SDMA IP Dump buffer */
1337         ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);
1338         if (ptr)
1339                 adev->sdma.ip_dump = ptr;
1340         else
1341                 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
1342
1343         return r;
1344 }
1345
1346 static int sdma_v6_0_sw_fini(void *handle)
1347 {
1348         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1349         int i;
1350
1351         for (i = 0; i < adev->sdma.num_instances; i++)
1352                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1353
1354         amdgpu_sdma_destroy_inst_ctx(adev, true);
1355
1356         kfree(adev->sdma.ip_dump);
1357
1358         return 0;
1359 }
1360
1361 static int sdma_v6_0_hw_init(void *handle)
1362 {
1363         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1364
1365         return sdma_v6_0_start(adev);
1366 }
1367
1368 static int sdma_v6_0_hw_fini(void *handle)
1369 {
1370         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1371
1372         if (amdgpu_sriov_vf(adev))
1373                 return 0;
1374
1375         sdma_v6_0_ctxempty_int_enable(adev, false);
1376         sdma_v6_0_enable(adev, false);
1377
1378         return 0;
1379 }
1380
1381 static int sdma_v6_0_suspend(void *handle)
1382 {
1383         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1384
1385         return sdma_v6_0_hw_fini(adev);
1386 }
1387
1388 static int sdma_v6_0_resume(void *handle)
1389 {
1390         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1391
1392         return sdma_v6_0_hw_init(adev);
1393 }
1394
1395 static bool sdma_v6_0_is_idle(void *handle)
1396 {
1397         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1398         u32 i;
1399
1400         for (i = 0; i < adev->sdma.num_instances; i++) {
1401                 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
1402
1403                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1404                         return false;
1405         }
1406
1407         return true;
1408 }
1409
1410 static int sdma_v6_0_wait_for_idle(void *handle)
1411 {
1412         unsigned i;
1413         u32 sdma0, sdma1;
1414         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1415
1416         for (i = 0; i < adev->usec_timeout; i++) {
1417                 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));
1418                 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));
1419
1420                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1421                         return 0;
1422                 udelay(1);
1423         }
1424         return -ETIMEDOUT;
1425 }
1426
1427 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring)
1428 {
1429         int i, r = 0;
1430         struct amdgpu_device *adev = ring->adev;
1431         u32 index = 0;
1432         u64 sdma_gfx_preempt;
1433
1434         amdgpu_sdma_get_index_from_ring(ring, &index);
1435         sdma_gfx_preempt =
1436                 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT);
1437
1438         /* assert preemption condition */
1439         amdgpu_ring_set_preempt_cond_exec(ring, false);
1440
1441         /* emit the trailing fence */
1442         ring->trail_seq += 1;
1443         amdgpu_ring_alloc(ring, 10);
1444         sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1445                                   ring->trail_seq, 0);
1446         amdgpu_ring_commit(ring);
1447
1448         /* assert IB preemption */
1449         WREG32(sdma_gfx_preempt, 1);
1450
1451         /* poll the trailing fence */
1452         for (i = 0; i < adev->usec_timeout; i++) {
1453                 if (ring->trail_seq ==
1454                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1455                         break;
1456                 udelay(1);
1457         }
1458
1459         if (i >= adev->usec_timeout) {
1460                 r = -EINVAL;
1461                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1462         }
1463
1464         /* deassert IB preemption */
1465         WREG32(sdma_gfx_preempt, 0);
1466
1467         /* deassert the preemption condition */
1468         amdgpu_ring_set_preempt_cond_exec(ring, true);
1469         return r;
1470 }
1471
1472 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev,
1473                                         struct amdgpu_irq_src *source,
1474                                         unsigned type,
1475                                         enum amdgpu_interrupt_state state)
1476 {
1477         u32 sdma_cntl;
1478
1479         u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL);
1480
1481         if (!amdgpu_sriov_vf(adev)) {
1482                 sdma_cntl = RREG32(reg_offset);
1483                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1484                                 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1485                 WREG32(reg_offset, sdma_cntl);
1486         }
1487
1488         return 0;
1489 }
1490
1491 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev,
1492                                       struct amdgpu_irq_src *source,
1493                                       struct amdgpu_iv_entry *entry)
1494 {
1495         int instances, queue;
1496         uint32_t mes_queue_id = entry->src_data[0];
1497
1498         DRM_DEBUG("IH: SDMA trap\n");
1499
1500         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1501                 struct amdgpu_mes_queue *queue;
1502
1503                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1504
1505                 spin_lock(&adev->mes.queue_id_lock);
1506                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1507                 if (queue) {
1508                         DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1509                         amdgpu_fence_process(queue->ring);
1510                 }
1511                 spin_unlock(&adev->mes.queue_id_lock);
1512                 return 0;
1513         }
1514
1515         queue = entry->ring_id & 0xf;
1516         instances = (entry->ring_id & 0xf0) >> 4;
1517         if (instances > 1) {
1518                 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n");
1519                 return -EINVAL;
1520         }
1521
1522         switch (entry->client_id) {
1523         case SOC21_IH_CLIENTID_GFX:
1524                 switch (queue) {
1525                 case 0:
1526                         amdgpu_fence_process(&adev->sdma.instance[instances].ring);
1527                         break;
1528                 default:
1529                         break;
1530                 }
1531                 break;
1532         }
1533         return 0;
1534 }
1535
1536 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1537                                               struct amdgpu_irq_src *source,
1538                                               struct amdgpu_iv_entry *entry)
1539 {
1540         return 0;
1541 }
1542
1543 static int sdma_v6_0_set_clockgating_state(void *handle,
1544                                            enum amd_clockgating_state state)
1545 {
1546         return 0;
1547 }
1548
1549 static int sdma_v6_0_set_powergating_state(void *handle,
1550                                           enum amd_powergating_state state)
1551 {
1552         return 0;
1553 }
1554
1555 static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags)
1556 {
1557 }
1558
1559 static void sdma_v6_0_print_ip_state(void *handle, struct drm_printer *p)
1560 {
1561         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1562         int i, j;
1563         uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);
1564         uint32_t instance_offset;
1565
1566         if (!adev->sdma.ip_dump)
1567                 return;
1568
1569         drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);
1570         for (i = 0; i < adev->sdma.num_instances; i++) {
1571                 instance_offset = i * reg_count;
1572                 drm_printf(p, "\nInstance:%d\n", i);
1573
1574                 for (j = 0; j < reg_count; j++)
1575                         drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_6_0[j].reg_name,
1576                                    adev->sdma.ip_dump[instance_offset + j]);
1577         }
1578 }
1579
1580 static void sdma_v6_0_dump_ip_state(void *handle)
1581 {
1582         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1583         int i, j;
1584         uint32_t instance_offset;
1585         uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);
1586
1587         if (!adev->sdma.ip_dump)
1588                 return;
1589
1590         amdgpu_gfx_off_ctrl(adev, false);
1591         for (i = 0; i < adev->sdma.num_instances; i++) {
1592                 instance_offset = i * reg_count;
1593                 for (j = 0; j < reg_count; j++)
1594                         adev->sdma.ip_dump[instance_offset + j] =
1595                                 RREG32(sdma_v6_0_get_reg_offset(adev, i,
1596                                        sdma_reg_list_6_0[j].reg_offset));
1597         }
1598         amdgpu_gfx_off_ctrl(adev, true);
1599 }
1600
1601 const struct amd_ip_funcs sdma_v6_0_ip_funcs = {
1602         .name = "sdma_v6_0",
1603         .early_init = sdma_v6_0_early_init,
1604         .late_init = NULL,
1605         .sw_init = sdma_v6_0_sw_init,
1606         .sw_fini = sdma_v6_0_sw_fini,
1607         .hw_init = sdma_v6_0_hw_init,
1608         .hw_fini = sdma_v6_0_hw_fini,
1609         .suspend = sdma_v6_0_suspend,
1610         .resume = sdma_v6_0_resume,
1611         .is_idle = sdma_v6_0_is_idle,
1612         .wait_for_idle = sdma_v6_0_wait_for_idle,
1613         .soft_reset = sdma_v6_0_soft_reset,
1614         .check_soft_reset = sdma_v6_0_check_soft_reset,
1615         .set_clockgating_state = sdma_v6_0_set_clockgating_state,
1616         .set_powergating_state = sdma_v6_0_set_powergating_state,
1617         .get_clockgating_state = sdma_v6_0_get_clockgating_state,
1618         .dump_ip_state = sdma_v6_0_dump_ip_state,
1619         .print_ip_state = sdma_v6_0_print_ip_state,
1620 };
1621
1622 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = {
1623         .type = AMDGPU_RING_TYPE_SDMA,
1624         .align_mask = 0xf,
1625         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1626         .support_64bit_ptrs = true,
1627         .secure_submission_supported = true,
1628         .get_rptr = sdma_v6_0_ring_get_rptr,
1629         .get_wptr = sdma_v6_0_ring_get_wptr,
1630         .set_wptr = sdma_v6_0_ring_set_wptr,
1631         .emit_frame_size =
1632                 5 + /* sdma_v6_0_ring_init_cond_exec */
1633                 6 + /* sdma_v6_0_ring_emit_hdp_flush */
1634                 6 + /* sdma_v6_0_ring_emit_pipeline_sync */
1635                 /* sdma_v6_0_ring_emit_vm_flush */
1636                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1637                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1638                 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */
1639         .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */
1640         .emit_ib = sdma_v6_0_ring_emit_ib,
1641         .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync,
1642         .emit_fence = sdma_v6_0_ring_emit_fence,
1643         .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync,
1644         .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush,
1645         .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush,
1646         .test_ring = sdma_v6_0_ring_test_ring,
1647         .test_ib = sdma_v6_0_ring_test_ib,
1648         .insert_nop = sdma_v6_0_ring_insert_nop,
1649         .pad_ib = sdma_v6_0_ring_pad_ib,
1650         .emit_wreg = sdma_v6_0_ring_emit_wreg,
1651         .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait,
1652         .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait,
1653         .init_cond_exec = sdma_v6_0_ring_init_cond_exec,
1654         .preempt_ib = sdma_v6_0_ring_preempt_ib,
1655 };
1656
1657 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1658 {
1659         int i;
1660
1661         for (i = 0; i < adev->sdma.num_instances; i++) {
1662                 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs;
1663                 adev->sdma.instance[i].ring.me = i;
1664         }
1665 }
1666
1667 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = {
1668         .set = sdma_v6_0_set_trap_irq_state,
1669         .process = sdma_v6_0_process_trap_irq,
1670 };
1671
1672 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = {
1673         .process = sdma_v6_0_process_illegal_inst_irq,
1674 };
1675
1676 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1677 {
1678         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1679                                         adev->sdma.num_instances;
1680         adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs;
1681         adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs;
1682 }
1683
1684 /**
1685  * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine
1686  *
1687  * @ib: indirect buffer to fill with commands
1688  * @src_offset: src GPU address
1689  * @dst_offset: dst GPU address
1690  * @byte_count: number of bytes to xfer
1691  * @copy_flags: copy flags for the buffers
1692  *
1693  * Copy GPU buffers using the DMA engine.
1694  * Used by the amdgpu ttm implementation to move pages if
1695  * registered as the asic copy callback.
1696  */
1697 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib,
1698                                        uint64_t src_offset,
1699                                        uint64_t dst_offset,
1700                                        uint32_t byte_count,
1701                                        uint32_t copy_flags)
1702 {
1703         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1704                 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1705                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);
1706         ib->ptr[ib->length_dw++] = byte_count - 1;
1707         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1708         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1709         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1710         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1711         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1712 }
1713
1714 /**
1715  * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine
1716  *
1717  * @ib: indirect buffer to fill
1718  * @src_data: value to write to buffer
1719  * @dst_offset: dst GPU address
1720  * @byte_count: number of bytes to xfer
1721  *
1722  * Fill GPU buffers using the DMA engine.
1723  */
1724 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib,
1725                                        uint32_t src_data,
1726                                        uint64_t dst_offset,
1727                                        uint32_t byte_count)
1728 {
1729         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL);
1730         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1731         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1732         ib->ptr[ib->length_dw++] = src_data;
1733         ib->ptr[ib->length_dw++] = byte_count - 1;
1734 }
1735
1736 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = {
1737         .copy_max_bytes = 0x400000,
1738         .copy_num_dw = 7,
1739         .emit_copy_buffer = sdma_v6_0_emit_copy_buffer,
1740
1741         .fill_max_bytes = 0x400000,
1742         .fill_num_dw = 5,
1743         .emit_fill_buffer = sdma_v6_0_emit_fill_buffer,
1744 };
1745
1746 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev)
1747 {
1748         adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs;
1749         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1750 }
1751
1752 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = {
1753         .copy_pte_num_dw = 7,
1754         .copy_pte = sdma_v6_0_vm_copy_pte,
1755         .write_pte = sdma_v6_0_vm_write_pte,
1756         .set_pte_pde = sdma_v6_0_vm_set_pte_pde,
1757 };
1758
1759 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1760 {
1761         unsigned i;
1762
1763         adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs;
1764         for (i = 0; i < adev->sdma.num_instances; i++) {
1765                 adev->vm_manager.vm_pte_scheds[i] =
1766                         &adev->sdma.instance[i].ring.sched;
1767         }
1768         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1769 }
1770
1771 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = {
1772         .type = AMD_IP_BLOCK_TYPE_SDMA,
1773         .major = 6,
1774         .minor = 0,
1775         .rev = 0,
1776         .funcs = &sdma_v6_0_ip_funcs,
1777 };