drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/kthread.h>
  25 #include <linux/wait.h>
  26 #include <linux/sched.h>
  27
  28 #include <drm/drm_drv.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_trace.h"
  32 #include "amdgpu_reset.h"
  33 #include "amdgpu_dev_coredump.h"
  34 #include "amdgpu_xgmi.h"
  35
  36 static void amdgpu_job_do_core_dump(struct amdgpu_device *adev,
  37                                     struct amdgpu_job *job)
  38 {
  39         int i;
  40
  41         dev_info(adev->dev, "Dumping IP State\n");
  42         for (i = 0; i < adev->num_ip_blocks; i++)
  43                 if (adev->ip_blocks[i].version->funcs->dump_ip_state)
  44                         adev->ip_blocks[i].version->funcs
  45                                 ->dump_ip_state((void *)adev);
  46         dev_info(adev->dev, "Dumping IP State Completed\n");
  47
  48         amdgpu_coredump(adev, true, false, job);
  49 }
  50
  51 static void amdgpu_job_core_dump(struct amdgpu_device *adev,
  52                                  struct amdgpu_job *job)
  53 {
  54         struct list_head device_list, *device_list_handle =  NULL;
  55         struct amdgpu_device *tmp_adev = NULL;
  56         struct amdgpu_hive_info *hive = NULL;
  57
  58         if (!amdgpu_sriov_vf(adev))
  59                 hive = amdgpu_get_xgmi_hive(adev);
  60         if (hive)
  61                 mutex_lock(&hive->hive_lock);
  62         /*
  63          * Reuse the logic in amdgpu_device_gpu_recover() to build list of
  64          * devices for code dump
  65          */
  66         INIT_LIST_HEAD(&device_list);
  67         if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1) && hive) {
  68                 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head)
  69                         list_add_tail(&tmp_adev->reset_list, &device_list);
  70                 if (!list_is_first(&adev->reset_list, &device_list))
  71                         list_rotate_to_front(&adev->reset_list, &device_list);
  72                 device_list_handle = &device_list;
  73         } else {
  74                 list_add_tail(&adev->reset_list, &device_list);
  75                 device_list_handle = &device_list;
  76         }
  77
  78         /* Do the coredump for each device */
  79         list_for_each_entry(tmp_adev, device_list_handle, reset_list)
  80                 amdgpu_job_do_core_dump(tmp_adev, job);
  81
  82         if (hive) {
  83                 mutex_unlock(&hive->hive_lock);
  84                 amdgpu_put_xgmi_hive(hive);
  85         }
  86 }
  87
  88 static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
  89 {
  90         struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
  91         struct amdgpu_job *job = to_amdgpu_job(s_job);
  92         struct amdgpu_task_info *ti;
  93         struct amdgpu_device *adev = ring->adev;
  94         int idx;
  95         int r;
  96
  97         if (!drm_dev_enter(adev_to_drm(adev), &idx)) {
  98                 dev_info(adev->dev, "%s - device unplugged skipping recovery on scheduler:%s",
  99                          __func__, s_job->sched->name);
 100
 101                 /* Effectively the job is aborted as the device is gone */
 102                 return DRM_GPU_SCHED_STAT_ENODEV;
 103         }
 104
 105         adev->job_hang = true;
 106
 107         /*
 108          * Do the coredump immediately after a job timeout to get a very
 109          * close dump/snapshot/representation of GPU's current error status
 110          * Skip it for SRIOV, since VF FLR will be triggered by host driver
 111          * before job timeout
 112          */
 113         if (!amdgpu_sriov_vf(adev))
 114                 amdgpu_job_core_dump(adev, job);
 115
 116         if (amdgpu_gpu_recovery &&
 117             amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) {
 118                 dev_err(adev->dev, "ring %s timeout, but soft recovered\n",
 119                         s_job->sched->name);
 120                 goto exit;
 121         }
 122
 123         dev_err(adev->dev, "ring %s timeout, signaled seq=%u, emitted seq=%u\n",
 124                 job->base.sched->name, atomic_read(&ring->fence_drv.last_seq),
 125                 ring->fence_drv.sync_seq);
 126
 127         ti = amdgpu_vm_get_task_info_pasid(ring->adev, job->pasid);
 128         if (ti) {
 129                 dev_err(adev->dev,
 130                         "Process information: process %s pid %d thread %s pid %d\n",
 131                         ti->process_name, ti->tgid, ti->task_name, ti->pid);
 132                 amdgpu_vm_put_task_info(ti);
 133         }
 134
 135         dma_fence_set_error(&s_job->s_fence->finished, -ETIME);
 136
 137         /* attempt a per ring reset */
 138         if (amdgpu_gpu_recovery &&
 139             ring->funcs->reset) {
 140                 /* stop the scheduler, but don't mess with the
 141                  * bad job yet because if ring reset fails
 142                  * we'll fall back to full GPU reset.
 143                  */
 144                 drm_sched_wqueue_stop(&ring->sched);
 145                 r = amdgpu_ring_reset(ring, job->vmid);
 146                 if (!r) {
 147                         if (amdgpu_ring_sched_ready(ring))
 148                                 drm_sched_stop(&ring->sched, s_job);
 149                         atomic_inc(&ring->adev->gpu_reset_counter);
 150                         amdgpu_fence_driver_force_completion(ring);
 151                         if (amdgpu_ring_sched_ready(ring))
 152                                 drm_sched_start(&ring->sched);
 153                         goto exit;
 154                 }
 155         }
 156
 157         if (amdgpu_device_should_recover_gpu(ring->adev)) {
 158                 struct amdgpu_reset_context reset_context;
 159                 memset(&reset_context, 0, sizeof(reset_context));
 160
 161                 reset_context.method = AMD_RESET_METHOD_NONE;
 162                 reset_context.reset_req_dev = adev;
 163                 reset_context.src = AMDGPU_RESET_SRC_JOB;
 164                 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
 165
 166                 /*
 167                  * To avoid an unnecessary extra coredump, as we have already
 168                  * got the very close representation of GPU's error status
 169                  */
 170                 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags);
 171
 172                 r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context);
 173                 if (r)
 174                         dev_err(adev->dev, "GPU Recovery Failed: %d\n", r);
 175         } else {
 176                 drm_sched_suspend_timeout(&ring->sched);
 177                 if (amdgpu_sriov_vf(adev))
 178                         adev->virt.tdr_debug = true;
 179         }
 180
 181 exit:
 182         adev->job_hang = false;
 183         drm_dev_exit(idx);
 184         return DRM_GPU_SCHED_STAT_NOMINAL;
 185 }
 186
 187 int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 188                      struct drm_sched_entity *entity, void *owner,
 189                      unsigned int num_ibs, struct amdgpu_job **job)
 190 {
 191         if (num_ibs == 0)
 192                 return -EINVAL;
 193
 194         *job = kzalloc(struct_size(*job, ibs, num_ibs), GFP_KERNEL);
 195         if (!*job)
 196                 return -ENOMEM;
 197
 198         /*
 199          * Initialize the scheduler to at least some ring so that we always
 200          * have a pointer to adev.
 201          */
 202         (*job)->base.sched = &adev->rings[0]->sched;
 203         (*job)->vm = vm;
 204
 205         amdgpu_sync_create(&(*job)->explicit_sync);
 206         (*job)->generation = amdgpu_vm_generation(adev, vm);
 207         (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET;
 208
 209         if (!entity)
 210                 return 0;
 211
 212         return drm_sched_job_init(&(*job)->base, entity, 1, owner);
 213 }
 214
 215 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev,
 216                              struct drm_sched_entity *entity, void *owner,
 217                              size_t size, enum amdgpu_ib_pool_type pool_type,
 218                              struct amdgpu_job **job)
 219 {
 220         int r;
 221
 222         r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job);
 223         if (r)
 224                 return r;
 225
 226         (*job)->num_ibs = 1;
 227         r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]);
 228         if (r) {
 229                 if (entity)
 230                         drm_sched_job_cleanup(&(*job)->base);
 231                 kfree(*job);
 232         }
 233
 234         return r;
 235 }
 236
 237 void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds,
 238                               struct amdgpu_bo *gws, struct amdgpu_bo *oa)
 239 {
 240         if (gds) {
 241                 job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
 242                 job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
 243         }
 244         if (gws) {
 245                 job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
 246                 job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
 247         }
 248         if (oa) {
 249                 job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
 250                 job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
 251         }
 252 }
 253
 254 void amdgpu_job_free_resources(struct amdgpu_job *job)
 255 {
 256         struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched);
 257         struct dma_fence *f;
 258         unsigned i;
 259
 260         /* Check if any fences where initialized */
 261         if (job->base.s_fence && job->base.s_fence->finished.ops)
 262                 f = &job->base.s_fence->finished;
 263         else if (job->hw_fence.ops)
 264                 f = &job->hw_fence;
 265         else
 266                 f = NULL;
 267
 268         for (i = 0; i < job->num_ibs; ++i)
 269                 amdgpu_ib_free(ring->adev, &job->ibs[i], f);
 270 }
 271
 272 static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
 273 {
 274         struct amdgpu_job *job = to_amdgpu_job(s_job);
 275
 276         drm_sched_job_cleanup(s_job);
 277
 278         amdgpu_sync_free(&job->explicit_sync);
 279
 280         /* only put the hw fence if has embedded fence */
 281         if (!job->hw_fence.ops)
 282                 kfree(job);
 283         else
 284                 dma_fence_put(&job->hw_fence);
 285 }
 286
 287 void amdgpu_job_set_gang_leader(struct amdgpu_job *job,
 288                                 struct amdgpu_job *leader)
 289 {
 290         struct dma_fence *fence = &leader->base.s_fence->scheduled;
 291
 292         WARN_ON(job->gang_submit);
 293
 294         /*
 295          * Don't add a reference when we are the gang leader to avoid circle
 296          * dependency.
 297          */
 298         if (job != leader)
 299                 dma_fence_get(fence);
 300         job->gang_submit = fence;
 301 }
 302
 303 void amdgpu_job_free(struct amdgpu_job *job)
 304 {
 305         if (job->base.entity)
 306                 drm_sched_job_cleanup(&job->base);
 307
 308         amdgpu_job_free_resources(job);
 309         amdgpu_sync_free(&job->explicit_sync);
 310         if (job->gang_submit != &job->base.s_fence->scheduled)
 311                 dma_fence_put(job->gang_submit);
 312
 313         if (!job->hw_fence.ops)
 314                 kfree(job);
 315         else
 316                 dma_fence_put(&job->hw_fence);
 317 }
 318
 319 struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job)
 320 {
 321         struct dma_fence *f;
 322
 323         drm_sched_job_arm(&job->base);
 324         f = dma_fence_get(&job->base.s_fence->finished);
 325         amdgpu_job_free_resources(job);
 326         drm_sched_entity_push_job(&job->base);
 327
 328         return f;
 329 }
 330
 331 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
 332                              struct dma_fence **fence)
 333 {
 334         int r;
 335
 336         job->base.sched = &ring->sched;
 337         r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, fence);
 338
 339         if (r)
 340                 return r;
 341
 342         amdgpu_job_free(job);
 343         return 0;
 344 }
 345
 346 static struct dma_fence *
 347 amdgpu_job_prepare_job(struct drm_sched_job *sched_job,
 348                       struct drm_sched_entity *s_entity)
 349 {
 350         struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched);
 351         struct amdgpu_job *job = to_amdgpu_job(sched_job);
 352         struct dma_fence *fence = NULL;
 353         int r;
 354
 355         r = drm_sched_entity_error(s_entity);
 356         if (r)
 357                 goto error;
 358
 359         if (!fence && job->gang_submit)
 360                 fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit);
 361
 362         while (!fence && job->vm && !job->vmid) {
 363                 r = amdgpu_vmid_grab(job->vm, ring, job, &fence);
 364                 if (r) {
 365                         dev_err(ring->adev->dev, "Error getting VM ID (%d)\n", r);
 366                         goto error;
 367                 }
 368         }
 369
 370         return fence;
 371
 372 error:
 373         dma_fence_set_error(&job->base.s_fence->finished, r);
 374         return NULL;
 375 }
 376
 377 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
 378 {
 379         struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched);
 380         struct amdgpu_device *adev = ring->adev;
 381         struct dma_fence *fence = NULL, *finished;
 382         struct amdgpu_job *job;
 383         int r = 0;
 384
 385         job = to_amdgpu_job(sched_job);
 386         finished = &job->base.s_fence->finished;
 387
 388         trace_amdgpu_sched_run_job(job);
 389
 390         /* Skip job if VRAM is lost and never resubmit gangs */
 391         if (job->generation != amdgpu_vm_generation(adev, job->vm) ||
 392             (job->job_run_counter && job->gang_submit))
 393                 dma_fence_set_error(finished, -ECANCELED);
 394
 395         if (finished->error < 0) {
 396                 dev_dbg(adev->dev, "Skip scheduling IBs in ring(%s)",
 397                         ring->name);
 398         } else {
 399                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job,
 400                                        &fence);
 401                 if (r)
 402                         dev_err(adev->dev,
 403                                 "Error scheduling IBs (%d) in ring(%s)", r,
 404                                 ring->name);
 405         }
 406
 407         job->job_run_counter++;
 408         amdgpu_job_free_resources(job);
 409
 410         fence = r ? ERR_PTR(r) : fence;
 411         return fence;
 412 }
 413
 414 #define to_drm_sched_job(sched_job)             \
 415                 container_of((sched_job), struct drm_sched_job, queue_node)
 416
 417 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched)
 418 {
 419         struct drm_sched_job *s_job;
 420         struct drm_sched_entity *s_entity = NULL;
 421         int i;
 422
 423         /* Signal all jobs not yet scheduled */
 424         for (i = DRM_SCHED_PRIORITY_KERNEL; i < sched->num_rqs; i++) {
 425                 struct drm_sched_rq *rq = sched->sched_rq[i];
 426                 spin_lock(&rq->lock);
 427                 list_for_each_entry(s_entity, &rq->entities, list) {
 428                         while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) {
 429                                 struct drm_sched_fence *s_fence = s_job->s_fence;
 430
 431                                 dma_fence_signal(&s_fence->scheduled);
 432                                 dma_fence_set_error(&s_fence->finished, -EHWPOISON);
 433                                 dma_fence_signal(&s_fence->finished);
 434                         }
 435                 }
 436                 spin_unlock(&rq->lock);
 437         }
 438
 439         /* Signal all jobs already scheduled to HW */
 440         list_for_each_entry(s_job, &sched->pending_list, list) {
 441                 struct drm_sched_fence *s_fence = s_job->s_fence;
 442
 443                 dma_fence_set_error(&s_fence->finished, -EHWPOISON);
 444                 dma_fence_signal(&s_fence->finished);
 445         }
 446 }
 447
 448 const struct drm_sched_backend_ops amdgpu_sched_ops = {
 449         .prepare_job = amdgpu_job_prepare_job,
 450         .run_job = amdgpu_job_run,
 451         .timedout_job = amdgpu_job_timedout,
 452         .free_job = amdgpu_job_free_cb
 453 };