drivers/pwm/pwm-lpc18xx-sct.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * NXP LPC18xx State Configurable Timer - Pulse Width Modulator driver
   4  *
   5  * Copyright (c) 2015 Ariel D'Alessandro <[email protected]>
   6  *
   7  * Notes
   8  * =====
   9  * NXP LPC18xx provides a State Configurable Timer (SCT) which can be configured
  10  * as a Pulse Width Modulator.
  11  *
  12  * SCT supports 16 outputs, 16 events and 16 registers. Each event will be
  13  * triggered when its related register matches the SCT counter value, and it
  14  * will set or clear a selected output.
  15  *
  16  * One of the events is preselected to generate the period, thus the maximum
  17  * number of simultaneous channels is limited to 15. Notice that period is
  18  * global to all the channels, thus PWM driver will refuse setting different
  19  * values to it, unless there's only one channel requested.
  20  */
  21
  22 #include <linux/clk.h>
  23 #include <linux/err.h>
  24 #include <linux/io.h>
  25 #include <linux/mod_devicetable.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pwm.h>
  29
  30 /* LPC18xx SCT registers */
  31 #define LPC18XX_PWM_CONFIG              0x000
  32 #define LPC18XX_PWM_CONFIG_UNIFY        BIT(0)
  33 #define LPC18XX_PWM_CONFIG_NORELOAD     BIT(7)
  34
  35 #define LPC18XX_PWM_CTRL                0x004
  36 #define LPC18XX_PWM_CTRL_HALT           BIT(2)
  37 #define LPC18XX_PWM_BIDIR               BIT(4)
  38 #define LPC18XX_PWM_PRE_SHIFT           5
  39 #define LPC18XX_PWM_PRE_MASK            (0xff << LPC18XX_PWM_PRE_SHIFT)
  40 #define LPC18XX_PWM_PRE(x)              (x << LPC18XX_PWM_PRE_SHIFT)
  41
  42 #define LPC18XX_PWM_LIMIT               0x008
  43
  44 #define LPC18XX_PWM_RES_BASE            0x058
  45 #define LPC18XX_PWM_RES_SHIFT(_ch)      (_ch * 2)
  46 #define LPC18XX_PWM_RES(_ch, _action)   (_action << LPC18XX_PWM_RES_SHIFT(_ch))
  47 #define LPC18XX_PWM_RES_MASK(_ch)       (0x3 << LPC18XX_PWM_RES_SHIFT(_ch))
  48
  49 #define LPC18XX_PWM_MATCH_BASE          0x100
  50 #define LPC18XX_PWM_MATCH(_ch)          (LPC18XX_PWM_MATCH_BASE + _ch * 4)
  51
  52 #define LPC18XX_PWM_MATCHREL_BASE       0x200
  53 #define LPC18XX_PWM_MATCHREL(_ch)       (LPC18XX_PWM_MATCHREL_BASE + _ch * 4)
  54
  55 #define LPC18XX_PWM_EVSTATEMSK_BASE     0x300
  56 #define LPC18XX_PWM_EVSTATEMSK(_ch)     (LPC18XX_PWM_EVSTATEMSK_BASE + _ch * 8)
  57 #define LPC18XX_PWM_EVSTATEMSK_ALL      0xffffffff
  58
  59 #define LPC18XX_PWM_EVCTRL_BASE         0x304
  60 #define LPC18XX_PWM_EVCTRL(_ev)         (LPC18XX_PWM_EVCTRL_BASE + _ev * 8)
  61
  62 #define LPC18XX_PWM_EVCTRL_MATCH(_ch)   _ch
  63
  64 #define LPC18XX_PWM_EVCTRL_COMB_SHIFT   12
  65 #define LPC18XX_PWM_EVCTRL_COMB_MATCH   (0x1 << LPC18XX_PWM_EVCTRL_COMB_SHIFT)
  66
  67 #define LPC18XX_PWM_OUTPUTSET_BASE      0x500
  68 #define LPC18XX_PWM_OUTPUTSET(_ch)      (LPC18XX_PWM_OUTPUTSET_BASE + _ch * 8)
  69
  70 #define LPC18XX_PWM_OUTPUTCL_BASE       0x504
  71 #define LPC18XX_PWM_OUTPUTCL(_ch)       (LPC18XX_PWM_OUTPUTCL_BASE + _ch * 8)
  72
  73 /* LPC18xx SCT unified counter */
  74 #define LPC18XX_PWM_TIMER_MAX           0xffffffff
  75
  76 /* LPC18xx SCT events */
  77 #define LPC18XX_PWM_EVENT_PERIOD        0
  78 #define LPC18XX_PWM_EVENT_MAX           16
  79
  80 #define LPC18XX_NUM_PWMS                16
  81
  82 /* SCT conflict resolution */
  83 enum lpc18xx_pwm_res_action {
  84         LPC18XX_PWM_RES_NONE,
  85         LPC18XX_PWM_RES_SET,
  86         LPC18XX_PWM_RES_CLEAR,
  87         LPC18XX_PWM_RES_TOGGLE,
  88 };
  89
  90 struct lpc18xx_pwm_data {
  91         unsigned int duty_event;
  92 };
  93
  94 struct lpc18xx_pwm_chip {
  95         struct device *dev;
  96         struct pwm_chip chip;
  97         void __iomem *base;
  98         struct clk *pwm_clk;
  99         unsigned long clk_rate;
 100         unsigned int period_ns;
 101         unsigned int min_period_ns;
 102         u64 max_period_ns;
 103         unsigned int period_event;
 104         unsigned long event_map;
 105         struct mutex res_lock;
 106         struct mutex period_lock;
 107         struct lpc18xx_pwm_data channeldata[LPC18XX_NUM_PWMS];
 108 };
 109
 110 static inline struct lpc18xx_pwm_chip *
 111 to_lpc18xx_pwm_chip(struct pwm_chip *chip)
 112 {
 113         return container_of(chip, struct lpc18xx_pwm_chip, chip);
 114 }
 115
 116 static inline void lpc18xx_pwm_writel(struct lpc18xx_pwm_chip *lpc18xx_pwm,
 117                                       u32 reg, u32 val)
 118 {
 119         writel(val, lpc18xx_pwm->base + reg);
 120 }
 121
 122 static inline u32 lpc18xx_pwm_readl(struct lpc18xx_pwm_chip *lpc18xx_pwm,
 123                                     u32 reg)
 124 {
 125         return readl(lpc18xx_pwm->base + reg);
 126 }
 127
 128 static void lpc18xx_pwm_set_conflict_res(struct lpc18xx_pwm_chip *lpc18xx_pwm,
 129                                          struct pwm_device *pwm,
 130                                          enum lpc18xx_pwm_res_action action)
 131 {
 132         u32 val;
 133
 134         mutex_lock(&lpc18xx_pwm->res_lock);
 135
 136         /*
 137          * Simultaneous set and clear may happen on an output, that is the case
 138          * when duty_ns == period_ns. LPC18xx SCT allows to set a conflict
 139          * resolution action to be taken in such a case.
 140          */
 141         val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_RES_BASE);
 142         val &= ~LPC18XX_PWM_RES_MASK(pwm->hwpwm);
 143         val |= LPC18XX_PWM_RES(pwm->hwpwm, action);
 144         lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_RES_BASE, val);
 145
 146         mutex_unlock(&lpc18xx_pwm->res_lock);
 147 }
 148
 149 static void lpc18xx_pwm_config_period(struct pwm_chip *chip, u64 period_ns)
 150 {
 151         struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
 152         u32 val;
 153
 154         /*
 155          * With clk_rate < NSEC_PER_SEC this cannot overflow.
 156          * With period_ns < max_period_ns this also fits into an u32.
 157          * As period_ns >= min_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, lpc18xx_pwm->clk_rate);
 158          * we have val >= 1.
 159          */
 160         val = mul_u64_u64_div_u64(period_ns, lpc18xx_pwm->clk_rate, NSEC_PER_SEC);
 161
 162         lpc18xx_pwm_writel(lpc18xx_pwm,
 163                            LPC18XX_PWM_MATCH(lpc18xx_pwm->period_event),
 164                            val - 1);
 165
 166         lpc18xx_pwm_writel(lpc18xx_pwm,
 167                            LPC18XX_PWM_MATCHREL(lpc18xx_pwm->period_event),
 168                            val - 1);
 169 }
 170
 171 static void lpc18xx_pwm_config_duty(struct pwm_chip *chip,
 172                                     struct pwm_device *pwm, u64 duty_ns)
 173 {
 174         struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
 175         struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
 176         u32 val;
 177
 178         /*
 179          * With clk_rate <= NSEC_PER_SEC this cannot overflow.
 180          * With duty_ns <= period_ns < max_period_ns this also fits into an u32.
 181          */
 182         val = mul_u64_u64_div_u64(duty_ns, lpc18xx_pwm->clk_rate, NSEC_PER_SEC);
 183
 184         lpc18xx_pwm_writel(lpc18xx_pwm,
 185                            LPC18XX_PWM_MATCH(lpc18xx_data->duty_event),
 186                            val);
 187
 188         lpc18xx_pwm_writel(lpc18xx_pwm,
 189                            LPC18XX_PWM_MATCHREL(lpc18xx_data->duty_event),
 190                            val);
 191 }
 192
 193 static int lpc18xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 194                               int duty_ns, int period_ns)
 195 {
 196         struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
 197         int requested_events;
 198
 199         if (period_ns < lpc18xx_pwm->min_period_ns ||
 200             period_ns > lpc18xx_pwm->max_period_ns) {
 201                 dev_err(chip->dev, "period %d not in range\n", period_ns);
 202                 return -ERANGE;
 203         }
 204
 205         mutex_lock(&lpc18xx_pwm->period_lock);
 206
 207         requested_events = bitmap_weight(&lpc18xx_pwm->event_map,
 208                                          LPC18XX_PWM_EVENT_MAX);
 209
 210         /*
 211          * The PWM supports only a single period for all PWM channels.
 212          * Once the period is set, it can only be changed if no more than one
 213          * channel is requested at that moment.
 214          */
 215         if (requested_events > 2 && lpc18xx_pwm->period_ns != period_ns &&
 216             lpc18xx_pwm->period_ns) {
 217                 dev_err(chip->dev, "conflicting period requested for PWM %u\n",
 218                         pwm->hwpwm);
 219                 mutex_unlock(&lpc18xx_pwm->period_lock);
 220                 return -EBUSY;
 221         }
 222
 223         if ((requested_events <= 2 && lpc18xx_pwm->period_ns != period_ns) ||
 224             !lpc18xx_pwm->period_ns) {
 225                 lpc18xx_pwm->period_ns = period_ns;
 226                 lpc18xx_pwm_config_period(chip, period_ns);
 227         }
 228
 229         mutex_unlock(&lpc18xx_pwm->period_lock);
 230
 231         lpc18xx_pwm_config_duty(chip, pwm, duty_ns);
 232
 233         return 0;
 234 }
 235
 236 static int lpc18xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, enum pwm_polarity polarity)
 237 {
 238         struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
 239         struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
 240         enum lpc18xx_pwm_res_action res_action;
 241         unsigned int set_event, clear_event;
 242
 243         lpc18xx_pwm_writel(lpc18xx_pwm,
 244                            LPC18XX_PWM_EVCTRL(lpc18xx_data->duty_event),
 245                            LPC18XX_PWM_EVCTRL_MATCH(lpc18xx_data->duty_event) |
 246                            LPC18XX_PWM_EVCTRL_COMB_MATCH);
 247
 248         lpc18xx_pwm_writel(lpc18xx_pwm,
 249                            LPC18XX_PWM_EVSTATEMSK(lpc18xx_data->duty_event),
 250                            LPC18XX_PWM_EVSTATEMSK_ALL);
 251
 252         if (polarity == PWM_POLARITY_NORMAL) {
 253                 set_event = lpc18xx_pwm->period_event;
 254                 clear_event = lpc18xx_data->duty_event;
 255                 res_action = LPC18XX_PWM_RES_SET;
 256         } else {
 257                 set_event = lpc18xx_data->duty_event;
 258                 clear_event = lpc18xx_pwm->period_event;
 259                 res_action = LPC18XX_PWM_RES_CLEAR;
 260         }
 261
 262         lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm),
 263                            BIT(set_event));
 264         lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm),
 265                            BIT(clear_event));
 266         lpc18xx_pwm_set_conflict_res(lpc18xx_pwm, pwm, res_action);
 267
 268         return 0;
 269 }
 270
 271 static void lpc18xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 272 {
 273         struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
 274         struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
 275
 276         lpc18xx_pwm_writel(lpc18xx_pwm,
 277                            LPC18XX_PWM_EVCTRL(lpc18xx_data->duty_event), 0);
 278         lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), 0);
 279         lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), 0);
 280 }
 281
 282 static int lpc18xx_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
 283 {
 284         struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
 285         struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
 286         unsigned long event;
 287
 288         event = find_first_zero_bit(&lpc18xx_pwm->event_map,
 289                                     LPC18XX_PWM_EVENT_MAX);
 290
 291         if (event >= LPC18XX_PWM_EVENT_MAX) {
 292                 dev_err(lpc18xx_pwm->dev,
 293                         "maximum number of simultaneous channels reached\n");
 294                 return -EBUSY;
 295         }
 296
 297         set_bit(event, &lpc18xx_pwm->event_map);
 298         lpc18xx_data->duty_event = event;
 299
 300         return 0;
 301 }
 302
 303 static void lpc18xx_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
 304 {
 305         struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
 306         struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
 307
 308         clear_bit(lpc18xx_data->duty_event, &lpc18xx_pwm->event_map);
 309 }
 310
 311 static int lpc18xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 312                              const struct pwm_state *state)
 313 {
 314         int err;
 315         bool enabled = pwm->state.enabled;
 316
 317         if (state->polarity != pwm->state.polarity && pwm->state.enabled) {
 318                 lpc18xx_pwm_disable(chip, pwm);
 319                 enabled = false;
 320         }
 321
 322         if (!state->enabled) {
 323                 if (enabled)
 324                         lpc18xx_pwm_disable(chip, pwm);
 325
 326                 return 0;
 327         }
 328
 329         err = lpc18xx_pwm_config(chip, pwm, state->duty_cycle, state->period);
 330         if (err)
 331                 return err;
 332
 333         if (!enabled)
 334                 err = lpc18xx_pwm_enable(chip, pwm, state->polarity);
 335
 336         return err;
 337 }
 338 static const struct pwm_ops lpc18xx_pwm_ops = {
 339         .apply = lpc18xx_pwm_apply,
 340         .request = lpc18xx_pwm_request,
 341         .free = lpc18xx_pwm_free,
 342 };
 343
 344 static const struct of_device_id lpc18xx_pwm_of_match[] = {
 345         { .compatible = "nxp,lpc1850-sct-pwm" },
 346         {}
 347 };
 348 MODULE_DEVICE_TABLE(of, lpc18xx_pwm_of_match);
 349
 350 static int lpc18xx_pwm_probe(struct platform_device *pdev)
 351 {
 352         struct lpc18xx_pwm_chip *lpc18xx_pwm;
 353         int ret;
 354         u64 val;
 355
 356         lpc18xx_pwm = devm_kzalloc(&pdev->dev, sizeof(*lpc18xx_pwm),
 357                                    GFP_KERNEL);
 358         if (!lpc18xx_pwm)
 359                 return -ENOMEM;
 360
 361         lpc18xx_pwm->dev = &pdev->dev;
 362
 363         lpc18xx_pwm->base = devm_platform_ioremap_resource(pdev, 0);
 364         if (IS_ERR(lpc18xx_pwm->base))
 365                 return PTR_ERR(lpc18xx_pwm->base);
 366
 367         lpc18xx_pwm->pwm_clk = devm_clk_get_enabled(&pdev->dev, "pwm");
 368         if (IS_ERR(lpc18xx_pwm->pwm_clk))
 369                 return dev_err_probe(&pdev->dev, PTR_ERR(lpc18xx_pwm->pwm_clk),
 370                                      "failed to get pwm clock\n");
 371
 372         lpc18xx_pwm->clk_rate = clk_get_rate(lpc18xx_pwm->pwm_clk);
 373         if (!lpc18xx_pwm->clk_rate)
 374                 return dev_err_probe(&pdev->dev,
 375                                      -EINVAL, "pwm clock has no frequency\n");
 376
 377         /*
 378          * If clkrate is too fast, the calculations in .apply() might overflow.
 379          */
 380         if (lpc18xx_pwm->clk_rate > NSEC_PER_SEC)
 381                 return dev_err_probe(&pdev->dev, -EINVAL, "pwm clock to fast\n");
 382
 383         mutex_init(&lpc18xx_pwm->res_lock);
 384         mutex_init(&lpc18xx_pwm->period_lock);
 385
 386         lpc18xx_pwm->max_period_ns =
 387                 mul_u64_u64_div_u64(NSEC_PER_SEC, LPC18XX_PWM_TIMER_MAX, lpc18xx_pwm->clk_rate);
 388
 389         lpc18xx_pwm->min_period_ns = DIV_ROUND_UP(NSEC_PER_SEC,
 390                                                   lpc18xx_pwm->clk_rate);
 391
 392         lpc18xx_pwm->chip.dev = &pdev->dev;
 393         lpc18xx_pwm->chip.ops = &lpc18xx_pwm_ops;
 394         lpc18xx_pwm->chip.npwm = LPC18XX_NUM_PWMS;
 395
 396         /* SCT counter must be in unify (32 bit) mode */
 397         lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CONFIG,
 398                            LPC18XX_PWM_CONFIG_UNIFY);
 399
 400         /*
 401          * Everytime the timer counter reaches the period value, the related
 402          * event will be triggered and the counter reset to 0.
 403          */
 404         set_bit(LPC18XX_PWM_EVENT_PERIOD, &lpc18xx_pwm->event_map);
 405         lpc18xx_pwm->period_event = LPC18XX_PWM_EVENT_PERIOD;
 406
 407         lpc18xx_pwm_writel(lpc18xx_pwm,
 408                            LPC18XX_PWM_EVSTATEMSK(lpc18xx_pwm->period_event),
 409                            LPC18XX_PWM_EVSTATEMSK_ALL);
 410
 411         val = LPC18XX_PWM_EVCTRL_MATCH(lpc18xx_pwm->period_event) |
 412               LPC18XX_PWM_EVCTRL_COMB_MATCH;
 413         lpc18xx_pwm_writel(lpc18xx_pwm,
 414                            LPC18XX_PWM_EVCTRL(lpc18xx_pwm->period_event), val);
 415
 416         lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_LIMIT,
 417                            BIT(lpc18xx_pwm->period_event));
 418
 419         val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL);
 420         val &= ~LPC18XX_PWM_BIDIR;
 421         val &= ~LPC18XX_PWM_CTRL_HALT;
 422         val &= ~LPC18XX_PWM_PRE_MASK;
 423         val |= LPC18XX_PWM_PRE(0);
 424         lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL, val);
 425
 426         ret = pwmchip_add(&lpc18xx_pwm->chip);
 427         if (ret < 0)
 428                 return dev_err_probe(&pdev->dev, ret, "pwmchip_add failed\n");
 429
 430         platform_set_drvdata(pdev, lpc18xx_pwm);
 431
 432         return 0;
 433 }
 434
 435 static void lpc18xx_pwm_remove(struct platform_device *pdev)
 436 {
 437         struct lpc18xx_pwm_chip *lpc18xx_pwm = platform_get_drvdata(pdev);
 438         u32 val;
 439
 440         pwmchip_remove(&lpc18xx_pwm->chip);
 441
 442         val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL);
 443         lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL,
 444                            val | LPC18XX_PWM_CTRL_HALT);
 445 }
 446
 447 static struct platform_driver lpc18xx_pwm_driver = {
 448         .driver = {
 449                 .name = "lpc18xx-sct-pwm",
 450                 .of_match_table = lpc18xx_pwm_of_match,
 451         },
 452         .probe = lpc18xx_pwm_probe,
 453         .remove_new = lpc18xx_pwm_remove,
 454 };
 455 module_platform_driver(lpc18xx_pwm_driver);
 456
 457 MODULE_AUTHOR("Ariel D'Alessandro <[email protected]>");
 458 MODULE_DESCRIPTION("NXP LPC18xx PWM driver");
 459 MODULE_LICENSE("GPL v2");