drivers/pwm/pwm-bcm2835.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2014 Bart Tanghe <[email protected]>
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/err.h>
   8 #include <linux/io.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/pwm.h>
  13
  14 #define PWM_CONTROL             0x000
  15 #define PWM_CONTROL_SHIFT(x)    ((x) * 8)
  16 #define PWM_CONTROL_MASK        0xff
  17 #define PWM_MODE                0x80            /* set timer in PWM mode */
  18 #define PWM_ENABLE              (1 << 0)
  19 #define PWM_POLARITY            (1 << 4)
  20
  21 #define PERIOD(x)               (((x) * 0x10) + 0x10)
  22 #define DUTY(x)                 (((x) * 0x10) + 0x14)
  23
  24 #define PERIOD_MIN              0x2
  25
  26 struct bcm2835_pwm {
  27         struct pwm_chip chip;
  28         struct device *dev;
  29         void __iomem *base;
  30         struct clk *clk;
  31         unsigned long rate;
  32 };
  33
  34 static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip)
  35 {
  36         return container_of(chip, struct bcm2835_pwm, chip);
  37 }
  38
  39 static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
  40 {
  41         struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
  42         u32 value;
  43
  44         value = readl(pc->base + PWM_CONTROL);
  45         value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
  46         value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm));
  47         writel(value, pc->base + PWM_CONTROL);
  48
  49         return 0;
  50 }
  51
  52 static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
  53 {
  54         struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
  55         u32 value;
  56
  57         value = readl(pc->base + PWM_CONTROL);
  58         value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
  59         writel(value, pc->base + PWM_CONTROL);
  60 }
  61
  62 static int bcm2835_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  63                              const struct pwm_state *state)
  64 {
  65
  66         struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
  67         unsigned long long period_cycles;
  68         u64 max_period;
  69
  70         u32 val;
  71
  72         /*
  73          * period_cycles must be a 32 bit value, so period * rate / NSEC_PER_SEC
  74          * must be <= U32_MAX. As U32_MAX * NSEC_PER_SEC < U64_MAX the
  75          * multiplication period * rate doesn't overflow.
  76          * To calculate the maximal possible period that guarantees the
  77          * above inequality:
  78          *
  79          *     round(period * rate / NSEC_PER_SEC) <= U32_MAX
  80          * <=> period * rate / NSEC_PER_SEC < U32_MAX + 0.5
  81          * <=> period * rate < (U32_MAX + 0.5) * NSEC_PER_SEC
  82          * <=> period < ((U32_MAX + 0.5) * NSEC_PER_SEC) / rate
  83          * <=> period < ((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate
  84          * <=> period <= ceil((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate) - 1
  85          */
  86         max_period = DIV_ROUND_UP_ULL((u64)U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC / 2, pc->rate) - 1;
  87
  88         if (state->period > max_period)
  89                 return -EINVAL;
  90
  91         /* set period */
  92         period_cycles = DIV_ROUND_CLOSEST_ULL(state->period * pc->rate, NSEC_PER_SEC);
  93
  94         /* don't accept a period that is too small */
  95         if (period_cycles < PERIOD_MIN)
  96                 return -EINVAL;
  97
  98         writel(period_cycles, pc->base + PERIOD(pwm->hwpwm));
  99
 100         /* set duty cycle */
 101         val = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pc->rate, NSEC_PER_SEC);
 102         writel(val, pc->base + DUTY(pwm->hwpwm));
 103
 104         /* set polarity */
 105         val = readl(pc->base + PWM_CONTROL);
 106
 107         if (state->polarity == PWM_POLARITY_NORMAL)
 108                 val &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm));
 109         else
 110                 val |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm);
 111
 112         /* enable/disable */
 113         if (state->enabled)
 114                 val |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm);
 115         else
 116                 val &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm));
 117
 118         writel(val, pc->base + PWM_CONTROL);
 119
 120         return 0;
 121 }
 122
 123 static const struct pwm_ops bcm2835_pwm_ops = {
 124         .request = bcm2835_pwm_request,
 125         .free = bcm2835_pwm_free,
 126         .apply = bcm2835_pwm_apply,
 127 };
 128
 129 static void devm_clk_rate_exclusive_put(void *data)
 130 {
 131         struct clk *clk = data;
 132
 133         clk_rate_exclusive_put(clk);
 134 }
 135
 136 static int bcm2835_pwm_probe(struct platform_device *pdev)
 137 {
 138         struct bcm2835_pwm *pc;
 139         int ret;
 140
 141         pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 142         if (!pc)
 143                 return -ENOMEM;
 144
 145         pc->dev = &pdev->dev;
 146
 147         pc->base = devm_platform_ioremap_resource(pdev, 0);
 148         if (IS_ERR(pc->base))
 149                 return PTR_ERR(pc->base);
 150
 151         pc->clk = devm_clk_get_enabled(&pdev->dev, NULL);
 152         if (IS_ERR(pc->clk))
 153                 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
 154                                      "clock not found\n");
 155
 156         ret = clk_rate_exclusive_get(pc->clk);
 157         if (ret)
 158                 return dev_err_probe(&pdev->dev, ret,
 159                                      "fail to get exclusive rate\n");
 160
 161         ret = devm_add_action_or_reset(&pdev->dev, devm_clk_rate_exclusive_put,
 162                                        pc->clk);
 163         if (ret) {
 164                 clk_rate_exclusive_put(pc->clk);
 165                 return ret;
 166         }
 167
 168         pc->rate = clk_get_rate(pc->clk);
 169         if (!pc->rate)
 170                 return dev_err_probe(&pdev->dev, -EINVAL,
 171                                      "failed to get clock rate\n");
 172
 173         pc->chip.dev = &pdev->dev;
 174         pc->chip.ops = &bcm2835_pwm_ops;
 175         pc->chip.atomic = true;
 176         pc->chip.npwm = 2;
 177
 178         platform_set_drvdata(pdev, pc);
 179
 180         ret = devm_pwmchip_add(&pdev->dev, &pc->chip);
 181         if (ret < 0)
 182                 return dev_err_probe(&pdev->dev, ret,
 183                                      "failed to add pwmchip\n");
 184
 185         return 0;
 186 }
 187
 188 static int bcm2835_pwm_suspend(struct device *dev)
 189 {
 190         struct bcm2835_pwm *pc = dev_get_drvdata(dev);
 191
 192         clk_disable_unprepare(pc->clk);
 193
 194         return 0;
 195 }
 196
 197 static int bcm2835_pwm_resume(struct device *dev)
 198 {
 199         struct bcm2835_pwm *pc = dev_get_drvdata(dev);
 200
 201         return clk_prepare_enable(pc->clk);
 202 }
 203
 204 static DEFINE_SIMPLE_DEV_PM_OPS(bcm2835_pwm_pm_ops, bcm2835_pwm_suspend,
 205                                 bcm2835_pwm_resume);
 206
 207 static const struct of_device_id bcm2835_pwm_of_match[] = {
 208         { .compatible = "brcm,bcm2835-pwm", },
 209         { /* sentinel */ }
 210 };
 211 MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match);
 212
 213 static struct platform_driver bcm2835_pwm_driver = {
 214         .driver = {
 215                 .name = "bcm2835-pwm",
 216                 .of_match_table = bcm2835_pwm_of_match,
 217                 .pm = pm_ptr(&bcm2835_pwm_pm_ops),
 218         },
 219         .probe = bcm2835_pwm_probe,
 220 };
 221 module_platform_driver(bcm2835_pwm_driver);
 222
 223 MODULE_AUTHOR("Bart Tanghe <[email protected]>");
 224 MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver");
 225 MODULE_LICENSE("GPL v2");