drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25
  26 #include <drm/drm_drv.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_ras.h"
  30 #include "vi.h"
  31 #include "soc15.h"
  32 #include "nv.h"
  33
  34 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \
  35         do { \
  36                 vf2pf_info->ucode_info[ucode].id = ucode; \
  37                 vf2pf_info->ucode_info[ucode].version = ver; \
  38         } while (0)
  39
  40 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
  41 {
  42         /* By now all MMIO pages except mailbox are blocked */
  43         /* if blocking is enabled in hypervisor. Choose the */
  44         /* SCRATCH_REG0 to test. */
  45         return RREG32_NO_KIQ(0xc040) == 0xffffffff;
  46 }
  47
  48 void amdgpu_virt_init_setting(struct amdgpu_device *adev)
  49 {
  50         struct drm_device *ddev = adev_to_drm(adev);
  51
  52         /* enable virtual display */
  53         if (adev->asic_type != CHIP_ALDEBARAN &&
  54             adev->asic_type != CHIP_ARCTURUS) {
  55                 if (adev->mode_info.num_crtc == 0)
  56                         adev->mode_info.num_crtc = 1;
  57                 adev->enable_virtual_display = true;
  58         }
  59         ddev->driver_features &= ~DRIVER_ATOMIC;
  60         adev->cg_flags = 0;
  61         adev->pg_flags = 0;
  62 }
  63
  64 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
  65                                         uint32_t reg0, uint32_t reg1,
  66                                         uint32_t ref, uint32_t mask)
  67 {
  68         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
  69         struct amdgpu_ring *ring = &kiq->ring;
  70         signed long r, cnt = 0;
  71         unsigned long flags;
  72         uint32_t seq;
  73
  74         spin_lock_irqsave(&kiq->ring_lock, flags);
  75         amdgpu_ring_alloc(ring, 32);
  76         amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,
  77                                             ref, mask);
  78         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
  79         if (r)
  80                 goto failed_undo;
  81
  82         amdgpu_ring_commit(ring);
  83         spin_unlock_irqrestore(&kiq->ring_lock, flags);
  84
  85         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
  86
  87         /* don't wait anymore for IRQ context */
  88         if (r < 1 && in_interrupt())
  89                 goto failed_kiq;
  90
  91         might_sleep();
  92         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
  93
  94                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
  95                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
  96         }
  97
  98         if (cnt > MAX_KIQ_REG_TRY)
  99                 goto failed_kiq;
 100
 101         return;
 102
 103 failed_undo:
 104         amdgpu_ring_undo(ring);
 105         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 106 failed_kiq:
 107         dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1);
 108 }
 109
 110 /**
 111  * amdgpu_virt_request_full_gpu() - request full gpu access
 112  * @adev:       amdgpu device.
 113  * @init:       is driver init time.
 114  * When start to init/fini driver, first need to request full gpu access.
 115  * Return: Zero if request success, otherwise will return error.
 116  */
 117 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)
 118 {
 119         struct amdgpu_virt *virt = &adev->virt;
 120         int r;
 121
 122         if (virt->ops && virt->ops->req_full_gpu) {
 123                 r = virt->ops->req_full_gpu(adev, init);
 124                 if (r)
 125                         return r;
 126
 127                 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
 128         }
 129
 130         return 0;
 131 }
 132
 133 /**
 134  * amdgpu_virt_release_full_gpu() - release full gpu access
 135  * @adev:       amdgpu device.
 136  * @init:       is driver init time.
 137  * When finishing driver init/fini, need to release full gpu access.
 138  * Return: Zero if release success, otherwise will returen error.
 139  */
 140 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
 141 {
 142         struct amdgpu_virt *virt = &adev->virt;
 143         int r;
 144
 145         if (virt->ops && virt->ops->rel_full_gpu) {
 146                 r = virt->ops->rel_full_gpu(adev, init);
 147                 if (r)
 148                         return r;
 149
 150                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
 151         }
 152         return 0;
 153 }
 154
 155 /**
 156  * amdgpu_virt_reset_gpu() - reset gpu
 157  * @adev:       amdgpu device.
 158  * Send reset command to GPU hypervisor to reset GPU that VM is using
 159  * Return: Zero if reset success, otherwise will return error.
 160  */
 161 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
 162 {
 163         struct amdgpu_virt *virt = &adev->virt;
 164         int r;
 165
 166         if (virt->ops && virt->ops->reset_gpu) {
 167                 r = virt->ops->reset_gpu(adev);
 168                 if (r)
 169                         return r;
 170
 171                 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
 172         }
 173
 174         return 0;
 175 }
 176
 177 void amdgpu_virt_request_init_data(struct amdgpu_device *adev)
 178 {
 179         struct amdgpu_virt *virt = &adev->virt;
 180
 181         if (virt->ops && virt->ops->req_init_data)
 182                 virt->ops->req_init_data(adev);
 183
 184         if (adev->virt.req_init_data_ver > 0)
 185                 DRM_INFO("host supports REQ_INIT_DATA handshake\n");
 186         else
 187                 DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n");
 188 }
 189
 190 /**
 191  * amdgpu_virt_wait_reset() - wait for reset gpu completed
 192  * @adev:       amdgpu device.
 193  * Wait for GPU reset completed.
 194  * Return: Zero if reset success, otherwise will return error.
 195  */
 196 int amdgpu_virt_wait_reset(struct amdgpu_device *adev)
 197 {
 198         struct amdgpu_virt *virt = &adev->virt;
 199
 200         if (!virt->ops || !virt->ops->wait_reset)
 201                 return -EINVAL;
 202
 203         return virt->ops->wait_reset(adev);
 204 }
 205
 206 /**
 207  * amdgpu_virt_alloc_mm_table() - alloc memory for mm table
 208  * @adev:       amdgpu device.
 209  * MM table is used by UVD and VCE for its initialization
 210  * Return: Zero if allocate success.
 211  */
 212 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)
 213 {
 214         int r;
 215
 216         if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr)
 217                 return 0;
 218
 219         r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
 220                                     AMDGPU_GEM_DOMAIN_VRAM,
 221                                     &adev->virt.mm_table.bo,
 222                                     &adev->virt.mm_table.gpu_addr,
 223                                     (void *)&adev->virt.mm_table.cpu_addr);
 224         if (r) {
 225                 DRM_ERROR("failed to alloc mm table and error = %d.\n", r);
 226                 return r;
 227         }
 228
 229         memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE);
 230         DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n",
 231                  adev->virt.mm_table.gpu_addr,
 232                  adev->virt.mm_table.cpu_addr);
 233         return 0;
 234 }
 235
 236 /**
 237  * amdgpu_virt_free_mm_table() - free mm table memory
 238  * @adev:       amdgpu device.
 239  * Free MM table memory
 240  */
 241 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)
 242 {
 243         if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr)
 244                 return;
 245
 246         amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,
 247                               &adev->virt.mm_table.gpu_addr,
 248                               (void *)&adev->virt.mm_table.cpu_addr);
 249         adev->virt.mm_table.gpu_addr = 0;
 250 }
 251
 252
 253 unsigned int amd_sriov_msg_checksum(void *obj,
 254                                 unsigned long obj_size,
 255                                 unsigned int key,
 256                                 unsigned int checksum)
 257 {
 258         unsigned int ret = key;
 259         unsigned long i = 0;
 260         unsigned char *pos;
 261
 262         pos = (char *)obj;
 263         /* calculate checksum */
 264         for (i = 0; i < obj_size; ++i)
 265                 ret += *(pos + i);
 266         /* minus the checksum itself */
 267         pos = (char *)&checksum;
 268         for (i = 0; i < sizeof(checksum); ++i)
 269                 ret -= *(pos + i);
 270         return ret;
 271 }
 272
 273 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev)
 274 {
 275         struct amdgpu_virt *virt = &adev->virt;
 276         struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data;
 277         /* GPU will be marked bad on host if bp count more then 10,
 278          * so alloc 512 is enough.
 279          */
 280         unsigned int align_space = 512;
 281         void *bps = NULL;
 282         struct amdgpu_bo **bps_bo = NULL;
 283
 284         *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL);
 285         if (!*data)
 286                 return -ENOMEM;
 287
 288         bps = kmalloc_array(align_space, sizeof((*data)->bps), GFP_KERNEL);
 289         bps_bo = kmalloc_array(align_space, sizeof((*data)->bps_bo), GFP_KERNEL);
 290
 291         if (!bps || !bps_bo) {
 292                 kfree(bps);
 293                 kfree(bps_bo);
 294                 kfree(*data);
 295                 return -ENOMEM;
 296         }
 297
 298         (*data)->bps = bps;
 299         (*data)->bps_bo = bps_bo;
 300         (*data)->count = 0;
 301         (*data)->last_reserved = 0;
 302
 303         virt->ras_init_done = true;
 304
 305         return 0;
 306 }
 307
 308 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev)
 309 {
 310         struct amdgpu_virt *virt = &adev->virt;
 311         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 312         struct amdgpu_bo *bo;
 313         int i;
 314
 315         if (!data)
 316                 return;
 317
 318         for (i = data->last_reserved - 1; i >= 0; i--) {
 319                 bo = data->bps_bo[i];
 320                 amdgpu_bo_free_kernel(&bo, NULL, NULL);
 321                 data->bps_bo[i] = bo;
 322                 data->last_reserved = i;
 323         }
 324 }
 325
 326 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev)
 327 {
 328         struct amdgpu_virt *virt = &adev->virt;
 329         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 330
 331         virt->ras_init_done = false;
 332
 333         if (!data)
 334                 return;
 335
 336         amdgpu_virt_ras_release_bp(adev);
 337
 338         kfree(data->bps);
 339         kfree(data->bps_bo);
 340         kfree(data);
 341         virt->virt_eh_data = NULL;
 342 }
 343
 344 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev,
 345                 struct eeprom_table_record *bps, int pages)
 346 {
 347         struct amdgpu_virt *virt = &adev->virt;
 348         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 349
 350         if (!data)
 351                 return;
 352
 353         memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps));
 354         data->count += pages;
 355 }
 356
 357 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev)
 358 {
 359         struct amdgpu_virt *virt = &adev->virt;
 360         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 361         struct amdgpu_bo *bo = NULL;
 362         uint64_t bp;
 363         int i;
 364
 365         if (!data)
 366                 return;
 367
 368         for (i = data->last_reserved; i < data->count; i++) {
 369                 bp = data->bps[i].retired_page;
 370
 371                 /* There are two cases of reserve error should be ignored:
 372                  * 1) a ras bad page has been allocated (used by someone);
 373                  * 2) a ras bad page has been reserved (duplicate error injection
 374                  *    for one page);
 375                  */
 376                 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT,
 377                                                AMDGPU_GPU_PAGE_SIZE,
 378                                                AMDGPU_GEM_DOMAIN_VRAM,
 379                                                &bo, NULL))
 380                         DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp);
 381
 382                 data->bps_bo[i] = bo;
 383                 data->last_reserved = i + 1;
 384                 bo = NULL;
 385         }
 386 }
 387
 388 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev,
 389                 uint64_t retired_page)
 390 {
 391         struct amdgpu_virt *virt = &adev->virt;
 392         struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
 393         int i;
 394
 395         if (!data)
 396                 return true;
 397
 398         for (i = 0; i < data->count; i++)
 399                 if (retired_page == data->bps[i].retired_page)
 400                         return true;
 401
 402         return false;
 403 }
 404
 405 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev,
 406                 uint64_t bp_block_offset, uint32_t bp_block_size)
 407 {
 408         struct eeprom_table_record bp;
 409         uint64_t retired_page;
 410         uint32_t bp_idx, bp_cnt;
 411
 412         if (bp_block_size) {
 413                 bp_cnt = bp_block_size / sizeof(uint64_t);
 414                 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) {
 415                         retired_page = *(uint64_t *)(adev->mman.fw_vram_usage_va +
 416                                         bp_block_offset + bp_idx * sizeof(uint64_t));
 417                         bp.retired_page = retired_page;
 418
 419                         if (amdgpu_virt_ras_check_bad_page(adev, retired_page))
 420                                 continue;
 421
 422                         amdgpu_virt_ras_add_bps(adev, &bp, 1);
 423
 424                         amdgpu_virt_ras_reserve_bps(adev);
 425                 }
 426         }
 427 }
 428
 429 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)
 430 {
 431         struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf;
 432         uint32_t checksum;
 433         uint32_t checkval;
 434
 435         if (adev->virt.fw_reserve.p_pf2vf == NULL)
 436                 return -EINVAL;
 437
 438         if (pf2vf_info->size > 1024) {
 439                 DRM_ERROR("invalid pf2vf message size\n");
 440                 return -EINVAL;
 441         }
 442
 443         switch (pf2vf_info->version) {
 444         case 1:
 445                 checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum;
 446                 checkval = amd_sriov_msg_checksum(
 447                         adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
 448                         adev->virt.fw_reserve.checksum_key, checksum);
 449                 if (checksum != checkval) {
 450                         DRM_ERROR("invalid pf2vf message\n");
 451                         return -EINVAL;
 452                 }
 453
 454                 adev->virt.gim_feature =
 455                         ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags;
 456                 break;
 457         case 2:
 458                 /* TODO: missing key, need to add it later */
 459                 checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum;
 460                 checkval = amd_sriov_msg_checksum(
 461                         adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
 462                         0, checksum);
 463                 if (checksum != checkval) {
 464                         DRM_ERROR("invalid pf2vf message\n");
 465                         return -EINVAL;
 466                 }
 467
 468                 adev->virt.vf2pf_update_interval_ms =
 469                         ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms;
 470                 adev->virt.gim_feature =
 471                         ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all;
 472                 adev->virt.reg_access =
 473                         ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all;
 474
 475                 break;
 476         default:
 477                 DRM_ERROR("invalid pf2vf version\n");
 478                 return -EINVAL;
 479         }
 480
 481         /* correct too large or too little interval value */
 482         if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000)
 483                 adev->virt.vf2pf_update_interval_ms = 2000;
 484
 485         return 0;
 486 }
 487
 488 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev)
 489 {
 490         struct amd_sriov_msg_vf2pf_info *vf2pf_info;
 491         vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;
 492
 493         if (adev->virt.fw_reserve.p_vf2pf == NULL)
 494                 return;
 495
 496         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE,      adev->vce.fw_version);
 497         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD,      adev->uvd.fw_version);
 498         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC,       adev->gmc.fw_version);
 499         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME,       adev->gfx.me_fw_version);
 500         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP,      adev->gfx.pfp_fw_version);
 501         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE,       adev->gfx.ce_fw_version);
 502         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC,      adev->gfx.rlc_fw_version);
 503         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version);
 504         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version);
 505         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version);
 506         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC,      adev->gfx.mec_fw_version);
 507         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2,     adev->gfx.mec2_fw_version);
 508         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS,      adev->psp.sos_fw_version);
 509         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD,      adev->psp.asd_fw_version);
 510         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS,   adev->psp.ta_ras_ucode_version);
 511         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI,  adev->psp.ta_xgmi_ucode_version);
 512         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC,      adev->pm.fw_version);
 513         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA,     adev->sdma.instance[0].fw_version);
 514         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2,    adev->sdma.instance[1].fw_version);
 515         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN,      adev->vcn.fw_version);
 516         POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU,     adev->dm.dmcu_fw_version);
 517 }
 518
 519 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev)
 520 {
 521         struct amd_sriov_msg_vf2pf_info *vf2pf_info;
 522         struct ttm_resource_manager *vram_man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
 523
 524         vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;
 525
 526         if (adev->virt.fw_reserve.p_vf2pf == NULL)
 527                 return -EINVAL;
 528
 529         memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info));
 530
 531         vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info);
 532         vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER;
 533
 534 #ifdef MODULE
 535         if (THIS_MODULE->version != NULL)
 536                 strcpy(vf2pf_info->driver_version, THIS_MODULE->version);
 537         else
 538 #endif
 539                 strcpy(vf2pf_info->driver_version, "N/A");
 540
 541         vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all
 542         vf2pf_info->driver_cert = 0;
 543         vf2pf_info->os_info.all = 0;
 544
 545         vf2pf_info->fb_usage = amdgpu_vram_mgr_usage(vram_man) >> 20;
 546         vf2pf_info->fb_vis_usage = amdgpu_vram_mgr_vis_usage(vram_man) >> 20;
 547         vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20;
 548         vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20;
 549
 550         amdgpu_virt_populate_vf2pf_ucode_info(adev);
 551
 552         /* TODO: read dynamic info */
 553         vf2pf_info->gfx_usage = 0;
 554         vf2pf_info->compute_usage = 0;
 555         vf2pf_info->encode_usage = 0;
 556         vf2pf_info->decode_usage = 0;
 557
 558         vf2pf_info->checksum =
 559                 amd_sriov_msg_checksum(
 560                 vf2pf_info, vf2pf_info->header.size, 0, 0);
 561
 562         return 0;
 563 }
 564
 565 static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work)
 566 {
 567         struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work);
 568         int ret;
 569
 570         ret = amdgpu_virt_read_pf2vf_data(adev);
 571         if (ret)
 572                 goto out;
 573         amdgpu_virt_write_vf2pf_data(adev);
 574
 575 out:
 576         schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms);
 577 }
 578
 579 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev)
 580 {
 581         if (adev->virt.vf2pf_update_interval_ms != 0) {
 582                 DRM_INFO("clean up the vf2pf work item\n");
 583                 cancel_delayed_work_sync(&adev->virt.vf2pf_work);
 584                 adev->virt.vf2pf_update_interval_ms = 0;
 585         }
 586 }
 587
 588 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
 589 {
 590         uint64_t bp_block_offset = 0;
 591         uint32_t bp_block_size = 0;
 592         struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL;
 593
 594         adev->virt.fw_reserve.p_pf2vf = NULL;
 595         adev->virt.fw_reserve.p_vf2pf = NULL;
 596         adev->virt.vf2pf_update_interval_ms = 0;
 597
 598         if (adev->mman.fw_vram_usage_va != NULL) {
 599                 adev->virt.vf2pf_update_interval_ms = 2000;
 600
 601                 adev->virt.fw_reserve.p_pf2vf =
 602                         (struct amd_sriov_msg_pf2vf_info_header *)
 603                         (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
 604                 adev->virt.fw_reserve.p_vf2pf =
 605                         (struct amd_sriov_msg_vf2pf_info_header *)
 606                         (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
 607
 608                 amdgpu_virt_read_pf2vf_data(adev);
 609                 amdgpu_virt_write_vf2pf_data(adev);
 610
 611                 /* bad page handling for version 2 */
 612                 if (adev->virt.fw_reserve.p_pf2vf->version == 2) {
 613                                 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf;
 614
 615                                 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) |
 616                                                 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000);
 617                                 bp_block_size = pf2vf_v2->bp_block_size;
 618
 619                                 if (bp_block_size && !adev->virt.ras_init_done)
 620                                         amdgpu_virt_init_ras_err_handler_data(adev);
 621
 622                                 if (adev->virt.ras_init_done)
 623                                         amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size);
 624                         }
 625         } else if (adev->bios != NULL) {
 626                 adev->virt.fw_reserve.p_pf2vf =
 627                         (struct amd_sriov_msg_pf2vf_info_header *)
 628                         (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
 629
 630                 amdgpu_virt_read_pf2vf_data(adev);
 631
 632                 return;
 633         }
 634
 635         if (adev->virt.vf2pf_update_interval_ms != 0) {
 636                 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);
 637                 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms);
 638         }
 639 }
 640
 641 void amdgpu_detect_virtualization(struct amdgpu_device *adev)
 642 {
 643         uint32_t reg;
 644
 645         switch (adev->asic_type) {
 646         case CHIP_TONGA:
 647         case CHIP_FIJI:
 648                 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
 649                 break;
 650         case CHIP_VEGA10:
 651         case CHIP_VEGA20:
 652         case CHIP_NAVI10:
 653         case CHIP_NAVI12:
 654         case CHIP_SIENNA_CICHLID:
 655         case CHIP_ARCTURUS:
 656         case CHIP_ALDEBARAN:
 657                 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
 658                 break;
 659         default: /* other chip doesn't support SRIOV */
 660                 reg = 0;
 661                 break;
 662         }
 663
 664         if (reg & 1)
 665                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
 666
 667         if (reg & 0x80000000)
 668                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
 669
 670         if (!reg) {
 671                 if (is_virtual_machine())       /* passthrough mode exclus sriov mod */
 672                         adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 673         }
 674
 675         /* we have the ability to check now */
 676         if (amdgpu_sriov_vf(adev)) {
 677                 switch (adev->asic_type) {
 678                 case CHIP_TONGA:
 679                 case CHIP_FIJI:
 680                         vi_set_virt_ops(adev);
 681                         break;
 682                 case CHIP_VEGA10:
 683                 case CHIP_VEGA20:
 684                 case CHIP_ARCTURUS:
 685                 case CHIP_ALDEBARAN:
 686                         soc15_set_virt_ops(adev);
 687                         break;
 688                 case CHIP_NAVI10:
 689                 case CHIP_NAVI12:
 690                 case CHIP_SIENNA_CICHLID:
 691                         nv_set_virt_ops(adev);
 692                         /* try send GPU_INIT_DATA request to host */
 693                         amdgpu_virt_request_init_data(adev);
 694                         break;
 695                 default: /* other chip doesn't support SRIOV */
 696                         DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type);
 697                         break;
 698                 }
 699         }
 700 }
 701
 702 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)
 703 {
 704         return amdgpu_sriov_is_debug(adev) ? true : false;
 705 }
 706
 707 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)
 708 {
 709         return amdgpu_sriov_is_normal(adev) ? true : false;
 710 }
 711
 712 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev)
 713 {
 714         if (!amdgpu_sriov_vf(adev) ||
 715             amdgpu_virt_access_debugfs_is_kiq(adev))
 716                 return 0;
 717
 718         if (amdgpu_virt_access_debugfs_is_mmio(adev))
 719                 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
 720         else
 721                 return -EPERM;
 722
 723         return 0;
 724 }
 725
 726 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev)
 727 {
 728         if (amdgpu_sriov_vf(adev))
 729                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
 730 }
 731
 732 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev)
 733 {
 734         enum amdgpu_sriov_vf_mode mode;
 735
 736         if (amdgpu_sriov_vf(adev)) {
 737                 if (amdgpu_sriov_is_pp_one_vf(adev))
 738                         mode = SRIOV_VF_MODE_ONE_VF;
 739                 else
 740                         mode = SRIOV_VF_MODE_MULTI_VF;
 741         } else {
 742                 mode = SRIOV_VF_MODE_BARE_METAL;
 743         }
 744
 745         return mode;
 746 }