drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25
  26 #include <drm/drm_debugfs.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_drv.h"
  30 #include "amdgpu_pm.h"
  31 #include "amdgpu_dpm.h"
  32 #include "amdgpu_display.h"
  33 #include "amdgpu_smu.h"
  34 #include "atom.h"
  35 #include <linux/power_supply.h>
  36 #include <linux/pci.h>
  37 #include <linux/hwmon.h>
  38 #include <linux/hwmon-sysfs.h>
  39 #include <linux/nospec.h>
  40 #include <linux/pm_runtime.h>
  41 #include "hwmgr.h"
  42 #define WIDTH_4K 3840
  43
  44 static const struct cg_flag_name clocks[] = {
  45         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  50         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  51         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  52         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  53         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  55         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  56         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  58         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  61         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  64         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  65         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  67         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  68         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  69
  70         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
  71         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
  72         {0, NULL},
  73 };
  74
  75 static const struct hwmon_temp_label {
  76         enum PP_HWMON_TEMP channel;
  77         const char *label;
  78 } temp_label[] = {
  79         {PP_TEMP_EDGE, "edge"},
  80         {PP_TEMP_JUNCTION, "junction"},
  81         {PP_TEMP_MEM, "mem"},
  82 };
  83
  84 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  85 {
  86         if (adev->pm.dpm_enabled) {
  87                 mutex_lock(&adev->pm.mutex);
  88                 if (power_supply_is_system_supplied() > 0)
  89                         adev->pm.ac_power = true;
  90                 else
  91                         adev->pm.ac_power = false;
  92                 if (adev->powerplay.pp_funcs &&
  93                     adev->powerplay.pp_funcs->enable_bapm)
  94                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  95                 mutex_unlock(&adev->pm.mutex);
  96
  97                 if (is_support_sw_smu(adev))
  98                         smu_set_ac_dc(&adev->smu);
  99         }
 100 }
 101
 102 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
 103                            void *data, uint32_t *size)
 104 {
 105         int ret = 0;
 106
 107         if (!data || !size)
 108                 return -EINVAL;
 109
 110         if (is_support_sw_smu(adev))
 111                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
 112         else {
 113                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
 114                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
 115                                                                     sensor, data, size);
 116                 else
 117                         ret = -EINVAL;
 118         }
 119
 120         return ret;
 121 }
 122
 123 /**
 124  * DOC: power_dpm_state
 125  *
 126  * The power_dpm_state file is a legacy interface and is only provided for
 127  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 128  * certain power related parameters.  The file power_dpm_state is used for this.
 129  * It accepts the following arguments:
 130  *
 131  * - battery
 132  *
 133  * - balanced
 134  *
 135  * - performance
 136  *
 137  * battery
 138  *
 139  * On older GPUs, the vbios provided a special power state for battery
 140  * operation.  Selecting battery switched to this state.  This is no
 141  * longer provided on newer GPUs so the option does nothing in that case.
 142  *
 143  * balanced
 144  *
 145  * On older GPUs, the vbios provided a special power state for balanced
 146  * operation.  Selecting balanced switched to this state.  This is no
 147  * longer provided on newer GPUs so the option does nothing in that case.
 148  *
 149  * performance
 150  *
 151  * On older GPUs, the vbios provided a special power state for performance
 152  * operation.  Selecting performance switched to this state.  This is no
 153  * longer provided on newer GPUs so the option does nothing in that case.
 154  *
 155  */
 156
 157 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
 158                                           struct device_attribute *attr,
 159                                           char *buf)
 160 {
 161         struct drm_device *ddev = dev_get_drvdata(dev);
 162         struct amdgpu_device *adev = ddev->dev_private;
 163         enum amd_pm_state_type pm;
 164         int ret;
 165
 166         if (adev->in_gpu_reset)
 167                 return -EPERM;
 168
 169         ret = pm_runtime_get_sync(ddev->dev);
 170         if (ret < 0) {
 171                 pm_runtime_put_autosuspend(ddev->dev);
 172                 return ret;
 173         }
 174
 175         if (is_support_sw_smu(adev)) {
 176                 if (adev->smu.ppt_funcs->get_current_power_state)
 177                         pm = smu_get_current_power_state(&adev->smu);
 178                 else
 179                         pm = adev->pm.dpm.user_state;
 180         } else if (adev->powerplay.pp_funcs->get_current_power_state) {
 181                 pm = amdgpu_dpm_get_current_power_state(adev);
 182         } else {
 183                 pm = adev->pm.dpm.user_state;
 184         }
 185
 186         pm_runtime_mark_last_busy(ddev->dev);
 187         pm_runtime_put_autosuspend(ddev->dev);
 188
 189         return snprintf(buf, PAGE_SIZE, "%s\n",
 190                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 191                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 192 }
 193
 194 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
 195                                           struct device_attribute *attr,
 196                                           const char *buf,
 197                                           size_t count)
 198 {
 199         struct drm_device *ddev = dev_get_drvdata(dev);
 200         struct amdgpu_device *adev = ddev->dev_private;
 201         enum amd_pm_state_type  state;
 202         int ret;
 203
 204         if (adev->in_gpu_reset)
 205                 return -EPERM;
 206
 207         if (strncmp("battery", buf, strlen("battery")) == 0)
 208                 state = POWER_STATE_TYPE_BATTERY;
 209         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 210                 state = POWER_STATE_TYPE_BALANCED;
 211         else if (strncmp("performance", buf, strlen("performance")) == 0)
 212                 state = POWER_STATE_TYPE_PERFORMANCE;
 213         else
 214                 return -EINVAL;
 215
 216         ret = pm_runtime_get_sync(ddev->dev);
 217         if (ret < 0) {
 218                 pm_runtime_put_autosuspend(ddev->dev);
 219                 return ret;
 220         }
 221
 222         if (is_support_sw_smu(adev)) {
 223                 mutex_lock(&adev->pm.mutex);
 224                 adev->pm.dpm.user_state = state;
 225                 mutex_unlock(&adev->pm.mutex);
 226         } else if (adev->powerplay.pp_funcs->dispatch_tasks) {
 227                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 228         } else {
 229                 mutex_lock(&adev->pm.mutex);
 230                 adev->pm.dpm.user_state = state;
 231                 mutex_unlock(&adev->pm.mutex);
 232
 233                 amdgpu_pm_compute_clocks(adev);
 234         }
 235         pm_runtime_mark_last_busy(ddev->dev);
 236         pm_runtime_put_autosuspend(ddev->dev);
 237
 238         return count;
 239 }
 240
 241
 242 /**
 243  * DOC: power_dpm_force_performance_level
 244  *
 245  * The amdgpu driver provides a sysfs API for adjusting certain power
 246  * related parameters.  The file power_dpm_force_performance_level is
 247  * used for this.  It accepts the following arguments:
 248  *
 249  * - auto
 250  *
 251  * - low
 252  *
 253  * - high
 254  *
 255  * - manual
 256  *
 257  * - profile_standard
 258  *
 259  * - profile_min_sclk
 260  *
 261  * - profile_min_mclk
 262  *
 263  * - profile_peak
 264  *
 265  * auto
 266  *
 267  * When auto is selected, the driver will attempt to dynamically select
 268  * the optimal power profile for current conditions in the driver.
 269  *
 270  * low
 271  *
 272  * When low is selected, the clocks are forced to the lowest power state.
 273  *
 274  * high
 275  *
 276  * When high is selected, the clocks are forced to the highest power state.
 277  *
 278  * manual
 279  *
 280  * When manual is selected, the user can manually adjust which power states
 281  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 282  * and pp_dpm_pcie files and adjust the power state transition heuristics
 283  * via the pp_power_profile_mode sysfs file.
 284  *
 285  * profile_standard
 286  * profile_min_sclk
 287  * profile_min_mclk
 288  * profile_peak
 289  *
 290  * When the profiling modes are selected, clock and power gating are
 291  * disabled and the clocks are set for different profiling cases. This
 292  * mode is recommended for profiling specific work loads where you do
 293  * not want clock or power gating for clock fluctuation to interfere
 294  * with your results. profile_standard sets the clocks to a fixed clock
 295  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 296  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 297  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 298  *
 299  */
 300
 301 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 302                                                             struct device_attribute *attr,
 303                                                             char *buf)
 304 {
 305         struct drm_device *ddev = dev_get_drvdata(dev);
 306         struct amdgpu_device *adev = ddev->dev_private;
 307         enum amd_dpm_forced_level level = 0xff;
 308         int ret;
 309
 310         if (adev->in_gpu_reset)
 311                 return -EPERM;
 312
 313         ret = pm_runtime_get_sync(ddev->dev);
 314         if (ret < 0) {
 315                 pm_runtime_put_autosuspend(ddev->dev);
 316                 return ret;
 317         }
 318
 319         if (is_support_sw_smu(adev))
 320                 level = smu_get_performance_level(&adev->smu);
 321         else if (adev->powerplay.pp_funcs->get_performance_level)
 322                 level = amdgpu_dpm_get_performance_level(adev);
 323         else
 324                 level = adev->pm.dpm.forced_level;
 325
 326         pm_runtime_mark_last_busy(ddev->dev);
 327         pm_runtime_put_autosuspend(ddev->dev);
 328
 329         return snprintf(buf, PAGE_SIZE, "%s\n",
 330                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 331                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 332                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 333                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 334                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 335                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 336                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 337                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 338                         "unknown");
 339 }
 340
 341 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 342                                                             struct device_attribute *attr,
 343                                                             const char *buf,
 344                                                             size_t count)
 345 {
 346         struct drm_device *ddev = dev_get_drvdata(dev);
 347         struct amdgpu_device *adev = ddev->dev_private;
 348         enum amd_dpm_forced_level level;
 349         enum amd_dpm_forced_level current_level = 0xff;
 350         int ret = 0;
 351
 352         if (adev->in_gpu_reset)
 353                 return -EPERM;
 354
 355         if (strncmp("low", buf, strlen("low")) == 0) {
 356                 level = AMD_DPM_FORCED_LEVEL_LOW;
 357         } else if (strncmp("high", buf, strlen("high")) == 0) {
 358                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 359         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 360                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 361         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 362                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 363         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 364                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 365         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 366                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 367         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 368                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 369         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 370                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 371         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 372                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 373         }  else {
 374                 return -EINVAL;
 375         }
 376
 377         ret = pm_runtime_get_sync(ddev->dev);
 378         if (ret < 0) {
 379                 pm_runtime_put_autosuspend(ddev->dev);
 380                 return ret;
 381         }
 382
 383         if (is_support_sw_smu(adev))
 384                 current_level = smu_get_performance_level(&adev->smu);
 385         else if (adev->powerplay.pp_funcs->get_performance_level)
 386                 current_level = amdgpu_dpm_get_performance_level(adev);
 387
 388         if (current_level == level) {
 389                 pm_runtime_mark_last_busy(ddev->dev);
 390                 pm_runtime_put_autosuspend(ddev->dev);
 391                 return count;
 392         }
 393
 394         if (adev->asic_type == CHIP_RAVEN) {
 395                 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) {
 396                         if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && level == AMD_DPM_FORCED_LEVEL_MANUAL)
 397                                 amdgpu_gfx_off_ctrl(adev, false);
 398                         else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && level != AMD_DPM_FORCED_LEVEL_MANUAL)
 399                                 amdgpu_gfx_off_ctrl(adev, true);
 400                 }
 401         }
 402
 403         /* profile_exit setting is valid only when current mode is in profile mode */
 404         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 405             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 406             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 407             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 408             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 409                 pr_err("Currently not in any profile mode!\n");
 410                 pm_runtime_mark_last_busy(ddev->dev);
 411                 pm_runtime_put_autosuspend(ddev->dev);
 412                 return -EINVAL;
 413         }
 414
 415         if (is_support_sw_smu(adev)) {
 416                 ret = smu_force_performance_level(&adev->smu, level);
 417                 if (ret) {
 418                         pm_runtime_mark_last_busy(ddev->dev);
 419                         pm_runtime_put_autosuspend(ddev->dev);
 420                         return -EINVAL;
 421                 }
 422         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 423                 mutex_lock(&adev->pm.mutex);
 424                 if (adev->pm.dpm.thermal_active) {
 425                         mutex_unlock(&adev->pm.mutex);
 426                         pm_runtime_mark_last_busy(ddev->dev);
 427                         pm_runtime_put_autosuspend(ddev->dev);
 428                         return -EINVAL;
 429                 }
 430                 ret = amdgpu_dpm_force_performance_level(adev, level);
 431                 if (ret) {
 432                         mutex_unlock(&adev->pm.mutex);
 433                         pm_runtime_mark_last_busy(ddev->dev);
 434                         pm_runtime_put_autosuspend(ddev->dev);
 435                         return -EINVAL;
 436                 } else {
 437                         adev->pm.dpm.forced_level = level;
 438                 }
 439                 mutex_unlock(&adev->pm.mutex);
 440         }
 441         pm_runtime_mark_last_busy(ddev->dev);
 442         pm_runtime_put_autosuspend(ddev->dev);
 443
 444         return count;
 445 }
 446
 447 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 448                 struct device_attribute *attr,
 449                 char *buf)
 450 {
 451         struct drm_device *ddev = dev_get_drvdata(dev);
 452         struct amdgpu_device *adev = ddev->dev_private;
 453         struct pp_states_info data;
 454         int i, buf_len, ret;
 455
 456         if (adev->in_gpu_reset)
 457                 return -EPERM;
 458
 459         ret = pm_runtime_get_sync(ddev->dev);
 460         if (ret < 0) {
 461                 pm_runtime_put_autosuspend(ddev->dev);
 462                 return ret;
 463         }
 464
 465         if (is_support_sw_smu(adev)) {
 466                 ret = smu_get_power_num_states(&adev->smu, &data);
 467                 if (ret)
 468                         return ret;
 469         } else if (adev->powerplay.pp_funcs->get_pp_num_states) {
 470                 amdgpu_dpm_get_pp_num_states(adev, &data);
 471         } else {
 472                 memset(&data, 0, sizeof(data));
 473         }
 474
 475         pm_runtime_mark_last_busy(ddev->dev);
 476         pm_runtime_put_autosuspend(ddev->dev);
 477
 478         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 479         for (i = 0; i < data.nums; i++)
 480                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 481                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 482                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 483                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 484                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 485
 486         return buf_len;
 487 }
 488
 489 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 490                 struct device_attribute *attr,
 491                 char *buf)
 492 {
 493         struct drm_device *ddev = dev_get_drvdata(dev);
 494         struct amdgpu_device *adev = ddev->dev_private;
 495         struct pp_states_info data;
 496         struct smu_context *smu = &adev->smu;
 497         enum amd_pm_state_type pm = 0;
 498         int i = 0, ret = 0;
 499
 500         if (adev->in_gpu_reset)
 501                 return -EPERM;
 502
 503         ret = pm_runtime_get_sync(ddev->dev);
 504         if (ret < 0) {
 505                 pm_runtime_put_autosuspend(ddev->dev);
 506                 return ret;
 507         }
 508
 509         if (is_support_sw_smu(adev)) {
 510                 pm = smu_get_current_power_state(smu);
 511                 ret = smu_get_power_num_states(smu, &data);
 512                 if (ret)
 513                         return ret;
 514         } else if (adev->powerplay.pp_funcs->get_current_power_state
 515                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 516                 pm = amdgpu_dpm_get_current_power_state(adev);
 517                 amdgpu_dpm_get_pp_num_states(adev, &data);
 518         }
 519
 520         pm_runtime_mark_last_busy(ddev->dev);
 521         pm_runtime_put_autosuspend(ddev->dev);
 522
 523         for (i = 0; i < data.nums; i++) {
 524                 if (pm == data.states[i])
 525                         break;
 526         }
 527
 528         if (i == data.nums)
 529                 i = -EINVAL;
 530
 531         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 532 }
 533
 534 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 535                 struct device_attribute *attr,
 536                 char *buf)
 537 {
 538         struct drm_device *ddev = dev_get_drvdata(dev);
 539         struct amdgpu_device *adev = ddev->dev_private;
 540
 541         if (adev->in_gpu_reset)
 542                 return -EPERM;
 543
 544         if (adev->pp_force_state_enabled)
 545                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 546         else
 547                 return snprintf(buf, PAGE_SIZE, "\n");
 548 }
 549
 550 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 551                 struct device_attribute *attr,
 552                 const char *buf,
 553                 size_t count)
 554 {
 555         struct drm_device *ddev = dev_get_drvdata(dev);
 556         struct amdgpu_device *adev = ddev->dev_private;
 557         enum amd_pm_state_type state = 0;
 558         unsigned long idx;
 559         int ret;
 560
 561         if (adev->in_gpu_reset)
 562                 return -EPERM;
 563
 564         if (strlen(buf) == 1)
 565                 adev->pp_force_state_enabled = false;
 566         else if (is_support_sw_smu(adev))
 567                 adev->pp_force_state_enabled = false;
 568         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 569                         adev->powerplay.pp_funcs->get_pp_num_states) {
 570                 struct pp_states_info data;
 571
 572                 ret = kstrtoul(buf, 0, &idx);
 573                 if (ret || idx >= ARRAY_SIZE(data.states))
 574                         return -EINVAL;
 575
 576                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 577
 578                 amdgpu_dpm_get_pp_num_states(adev, &data);
 579                 state = data.states[idx];
 580
 581                 ret = pm_runtime_get_sync(ddev->dev);
 582                 if (ret < 0) {
 583                         pm_runtime_put_autosuspend(ddev->dev);
 584                         return ret;
 585                 }
 586
 587                 /* only set user selected power states */
 588                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 589                     state != POWER_STATE_TYPE_DEFAULT) {
 590                         amdgpu_dpm_dispatch_task(adev,
 591                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 592                         adev->pp_force_state_enabled = true;
 593                 }
 594                 pm_runtime_mark_last_busy(ddev->dev);
 595                 pm_runtime_put_autosuspend(ddev->dev);
 596         }
 597
 598         return count;
 599 }
 600
 601 /**
 602  * DOC: pp_table
 603  *
 604  * The amdgpu driver provides a sysfs API for uploading new powerplay
 605  * tables.  The file pp_table is used for this.  Reading the file
 606  * will dump the current power play table.  Writing to the file
 607  * will attempt to upload a new powerplay table and re-initialize
 608  * powerplay using that new table.
 609  *
 610  */
 611
 612 static ssize_t amdgpu_get_pp_table(struct device *dev,
 613                 struct device_attribute *attr,
 614                 char *buf)
 615 {
 616         struct drm_device *ddev = dev_get_drvdata(dev);
 617         struct amdgpu_device *adev = ddev->dev_private;
 618         char *table = NULL;
 619         int size, ret;
 620
 621         if (adev->in_gpu_reset)
 622                 return -EPERM;
 623
 624         ret = pm_runtime_get_sync(ddev->dev);
 625         if (ret < 0) {
 626                 pm_runtime_put_autosuspend(ddev->dev);
 627                 return ret;
 628         }
 629
 630         if (is_support_sw_smu(adev)) {
 631                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 632                 pm_runtime_mark_last_busy(ddev->dev);
 633                 pm_runtime_put_autosuspend(ddev->dev);
 634                 if (size < 0)
 635                         return size;
 636         } else if (adev->powerplay.pp_funcs->get_pp_table) {
 637                 size = amdgpu_dpm_get_pp_table(adev, &table);
 638                 pm_runtime_mark_last_busy(ddev->dev);
 639                 pm_runtime_put_autosuspend(ddev->dev);
 640                 if (size < 0)
 641                         return size;
 642         } else {
 643                 pm_runtime_mark_last_busy(ddev->dev);
 644                 pm_runtime_put_autosuspend(ddev->dev);
 645                 return 0;
 646         }
 647
 648         if (size >= PAGE_SIZE)
 649                 size = PAGE_SIZE - 1;
 650
 651         memcpy(buf, table, size);
 652
 653         return size;
 654 }
 655
 656 static ssize_t amdgpu_set_pp_table(struct device *dev,
 657                 struct device_attribute *attr,
 658                 const char *buf,
 659                 size_t count)
 660 {
 661         struct drm_device *ddev = dev_get_drvdata(dev);
 662         struct amdgpu_device *adev = ddev->dev_private;
 663         int ret = 0;
 664
 665         if (adev->in_gpu_reset)
 666                 return -EPERM;
 667
 668         ret = pm_runtime_get_sync(ddev->dev);
 669         if (ret < 0) {
 670                 pm_runtime_put_autosuspend(ddev->dev);
 671                 return ret;
 672         }
 673
 674         if (is_support_sw_smu(adev)) {
 675                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 676                 if (ret) {
 677                         pm_runtime_mark_last_busy(ddev->dev);
 678                         pm_runtime_put_autosuspend(ddev->dev);
 679                         return ret;
 680                 }
 681         } else if (adev->powerplay.pp_funcs->set_pp_table)
 682                 amdgpu_dpm_set_pp_table(adev, buf, count);
 683
 684         pm_runtime_mark_last_busy(ddev->dev);
 685         pm_runtime_put_autosuspend(ddev->dev);
 686
 687         return count;
 688 }
 689
 690 /**
 691  * DOC: pp_od_clk_voltage
 692  *
 693  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 694  * in each power level within a power state.  The pp_od_clk_voltage is used for
 695  * this.
 696  *
 697  * < For Vega10 and previous ASICs >
 698  *
 699  * Reading the file will display:
 700  *
 701  * - a list of engine clock levels and voltages labeled OD_SCLK
 702  *
 703  * - a list of memory clock levels and voltages labeled OD_MCLK
 704  *
 705  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 706  *
 707  * To manually adjust these settings, first select manual using
 708  * power_dpm_force_performance_level. Enter a new value for each
 709  * level by writing a string that contains "s/m level clock voltage" to
 710  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 711  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 712  * 810 mV.  When you have edited all of the states as needed, write
 713  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 714  * default power levels, write "r" (reset) to the file to reset them.
 715  *
 716  *
 717  * < For Vega20 and newer ASICs >
 718  *
 719  * Reading the file will display:
 720  *
 721  * - minimum and maximum engine clock labeled OD_SCLK
 722  *
 723  * - maximum memory clock labeled OD_MCLK
 724  *
 725  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 726  *   They can be used to calibrate the sclk voltage curve.
 727  *
 728  * - a list of valid ranges for sclk, mclk, and voltage curve points
 729  *   labeled OD_RANGE
 730  *
 731  * To manually adjust these settings:
 732  *
 733  * - First select manual using power_dpm_force_performance_level
 734  *
 735  * - For clock frequency setting, enter a new value by writing a
 736  *   string that contains "s/m index clock" to the file. The index
 737  *   should be 0 if to set minimum clock. And 1 if to set maximum
 738  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 739  *   "m 1 800" will update maximum mclk to be 800Mhz.
 740  *
 741  *   For sclk voltage curve, enter the new values by writing a
 742  *   string that contains "vc point clock voltage" to the file. The
 743  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 744  *   update point1 with clock set as 300Mhz and voltage as
 745  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 746  *   as 1000Mhz and voltage 1000mV.
 747  *
 748  * - When you have edited all of the states as needed, write "c" (commit)
 749  *   to the file to commit your changes
 750  *
 751  * - If you want to reset to the default power levels, write "r" (reset)
 752  *   to the file to reset them
 753  *
 754  */
 755
 756 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 757                 struct device_attribute *attr,
 758                 const char *buf,
 759                 size_t count)
 760 {
 761         struct drm_device *ddev = dev_get_drvdata(dev);
 762         struct amdgpu_device *adev = ddev->dev_private;
 763         int ret;
 764         uint32_t parameter_size = 0;
 765         long parameter[64];
 766         char buf_cpy[128];
 767         char *tmp_str;
 768         char *sub_str;
 769         const char delimiter[3] = {' ', '\n', '\0'};
 770         uint32_t type;
 771
 772         if (adev->in_gpu_reset)
 773                 return -EPERM;
 774
 775         if (count > 127)
 776                 return -EINVAL;
 777
 778         if (*buf == 's')
 779                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 780         else if (*buf == 'm')
 781                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 782         else if(*buf == 'r')
 783                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 784         else if (*buf == 'c')
 785                 type = PP_OD_COMMIT_DPM_TABLE;
 786         else if (!strncmp(buf, "vc", 2))
 787                 type = PP_OD_EDIT_VDDC_CURVE;
 788         else
 789                 return -EINVAL;
 790
 791         memcpy(buf_cpy, buf, count+1);
 792
 793         tmp_str = buf_cpy;
 794
 795         if (type == PP_OD_EDIT_VDDC_CURVE)
 796                 tmp_str++;
 797         while (isspace(*++tmp_str));
 798
 799         while (tmp_str[0]) {
 800                 sub_str = strsep(&tmp_str, delimiter);
 801                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 802                 if (ret)
 803                         return -EINVAL;
 804                 parameter_size++;
 805
 806                 while (isspace(*tmp_str))
 807                         tmp_str++;
 808         }
 809
 810         ret = pm_runtime_get_sync(ddev->dev);
 811         if (ret < 0) {
 812                 pm_runtime_put_autosuspend(ddev->dev);
 813                 return ret;
 814         }
 815
 816         if (is_support_sw_smu(adev)) {
 817                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 818                                             parameter, parameter_size);
 819
 820                 if (ret) {
 821                         pm_runtime_mark_last_busy(ddev->dev);
 822                         pm_runtime_put_autosuspend(ddev->dev);
 823                         return -EINVAL;
 824                 }
 825         } else {
 826                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
 827                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 828                                                 parameter, parameter_size);
 829                         if (ret) {
 830                                 pm_runtime_mark_last_busy(ddev->dev);
 831                                 pm_runtime_put_autosuspend(ddev->dev);
 832                                 return -EINVAL;
 833                         }
 834                 }
 835
 836                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 837                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 838                                 amdgpu_dpm_dispatch_task(adev,
 839                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 840                                                 NULL);
 841                                 pm_runtime_mark_last_busy(ddev->dev);
 842                                 pm_runtime_put_autosuspend(ddev->dev);
 843                                 return count;
 844                         } else {
 845                                 pm_runtime_mark_last_busy(ddev->dev);
 846                                 pm_runtime_put_autosuspend(ddev->dev);
 847                                 return -EINVAL;
 848                         }
 849                 }
 850         }
 851         pm_runtime_mark_last_busy(ddev->dev);
 852         pm_runtime_put_autosuspend(ddev->dev);
 853
 854         return count;
 855 }
 856
 857 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 858                 struct device_attribute *attr,
 859                 char *buf)
 860 {
 861         struct drm_device *ddev = dev_get_drvdata(dev);
 862         struct amdgpu_device *adev = ddev->dev_private;
 863         ssize_t size;
 864         int ret;
 865
 866         if (adev->in_gpu_reset)
 867                 return -EPERM;
 868
 869         ret = pm_runtime_get_sync(ddev->dev);
 870         if (ret < 0) {
 871                 pm_runtime_put_autosuspend(ddev->dev);
 872                 return ret;
 873         }
 874
 875         if (is_support_sw_smu(adev)) {
 876                 size = smu_print_clk_levels(&adev->smu, SMU_OD_SCLK, buf);
 877                 size += smu_print_clk_levels(&adev->smu, SMU_OD_MCLK, buf+size);
 878                 size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size);
 879                 size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size);
 880         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 881                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 882                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 883                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 884                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 885         } else {
 886                 size = snprintf(buf, PAGE_SIZE, "\n");
 887         }
 888         pm_runtime_mark_last_busy(ddev->dev);
 889         pm_runtime_put_autosuspend(ddev->dev);
 890
 891         return size;
 892 }
 893
 894 /**
 895  * DOC: pp_features
 896  *
 897  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 898  * features to be enabled. The file pp_features is used for this. And
 899  * this is only available for Vega10 and later dGPUs.
 900  *
 901  * Reading back the file will show you the followings:
 902  * - Current ppfeature masks
 903  * - List of the all supported powerplay features with their naming,
 904  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 905  *
 906  * To manually enable or disable a specific feature, just set or clear
 907  * the corresponding bit from original ppfeature masks and input the
 908  * new ppfeature masks.
 909  */
 910 static ssize_t amdgpu_set_pp_features(struct device *dev,
 911                                       struct device_attribute *attr,
 912                                       const char *buf,
 913                                       size_t count)
 914 {
 915         struct drm_device *ddev = dev_get_drvdata(dev);
 916         struct amdgpu_device *adev = ddev->dev_private;
 917         uint64_t featuremask;
 918         int ret;
 919
 920         if (adev->in_gpu_reset)
 921                 return -EPERM;
 922
 923         ret = kstrtou64(buf, 0, &featuremask);
 924         if (ret)
 925                 return -EINVAL;
 926
 927         pr_debug("featuremask = 0x%llx\n", featuremask);
 928
 929         ret = pm_runtime_get_sync(ddev->dev);
 930         if (ret < 0) {
 931                 pm_runtime_put_autosuspend(ddev->dev);
 932                 return ret;
 933         }
 934
 935         if (is_support_sw_smu(adev)) {
 936                 ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
 937                 if (ret) {
 938                         pm_runtime_mark_last_busy(ddev->dev);
 939                         pm_runtime_put_autosuspend(ddev->dev);
 940                         return -EINVAL;
 941                 }
 942         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 943                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 944                 if (ret) {
 945                         pm_runtime_mark_last_busy(ddev->dev);
 946                         pm_runtime_put_autosuspend(ddev->dev);
 947                         return -EINVAL;
 948                 }
 949         }
 950         pm_runtime_mark_last_busy(ddev->dev);
 951         pm_runtime_put_autosuspend(ddev->dev);
 952
 953         return count;
 954 }
 955
 956 static ssize_t amdgpu_get_pp_features(struct device *dev,
 957                                       struct device_attribute *attr,
 958                                       char *buf)
 959 {
 960         struct drm_device *ddev = dev_get_drvdata(dev);
 961         struct amdgpu_device *adev = ddev->dev_private;
 962         ssize_t size;
 963         int ret;
 964
 965         if (adev->in_gpu_reset)
 966                 return -EPERM;
 967
 968         ret = pm_runtime_get_sync(ddev->dev);
 969         if (ret < 0) {
 970                 pm_runtime_put_autosuspend(ddev->dev);
 971                 return ret;
 972         }
 973
 974         if (is_support_sw_smu(adev))
 975                 size = smu_sys_get_pp_feature_mask(&adev->smu, buf);
 976         else if (adev->powerplay.pp_funcs->get_ppfeature_status)
 977                 size = amdgpu_dpm_get_ppfeature_status(adev, buf);
 978         else
 979                 size = snprintf(buf, PAGE_SIZE, "\n");
 980
 981         pm_runtime_mark_last_busy(ddev->dev);
 982         pm_runtime_put_autosuspend(ddev->dev);
 983
 984         return size;
 985 }
 986
 987 /**
 988  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
 989  *
 990  * The amdgpu driver provides a sysfs API for adjusting what power levels
 991  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 992  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 993  * this.
 994  *
 995  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 996  * Vega10 and later ASICs.
 997  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 998  *
 999  * Reading back the files will show you the available power levels within
1000  * the power state and the clock information for those levels.
1001  *
1002  * To manually adjust these states, first select manual using
1003  * power_dpm_force_performance_level.
1004  * Secondly, enter a new value for each level by inputing a string that
1005  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
1006  * E.g.,
1007  *
1008  * .. code-block:: bash
1009  *
1010  *      echo "4 5 6" > pp_dpm_sclk
1011  *
1012  * will enable sclk levels 4, 5, and 6.
1013  *
1014  * NOTE: change to the dcefclk max dpm level is not supported now
1015  */
1016
1017 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1018                 struct device_attribute *attr,
1019                 char *buf)
1020 {
1021         struct drm_device *ddev = dev_get_drvdata(dev);
1022         struct amdgpu_device *adev = ddev->dev_private;
1023         ssize_t size;
1024         int ret;
1025
1026         if (adev->in_gpu_reset)
1027                 return -EPERM;
1028
1029         ret = pm_runtime_get_sync(ddev->dev);
1030         if (ret < 0) {
1031                 pm_runtime_put_autosuspend(ddev->dev);
1032                 return ret;
1033         }
1034
1035         if (is_support_sw_smu(adev))
1036                 size = smu_print_clk_levels(&adev->smu, SMU_SCLK, buf);
1037         else if (adev->powerplay.pp_funcs->print_clock_levels)
1038                 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
1039         else
1040                 size = snprintf(buf, PAGE_SIZE, "\n");
1041
1042         pm_runtime_mark_last_busy(ddev->dev);
1043         pm_runtime_put_autosuspend(ddev->dev);
1044
1045         return size;
1046 }
1047
1048 /*
1049  * Worst case: 32 bits individually specified, in octal at 12 characters
1050  * per line (+1 for \n).
1051  */
1052 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1053
1054 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1055 {
1056         int ret;
1057         long level;
1058         char *sub_str = NULL;
1059         char *tmp;
1060         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1061         const char delimiter[3] = {' ', '\n', '\0'};
1062         size_t bytes;
1063
1064         *mask = 0;
1065
1066         bytes = min(count, sizeof(buf_cpy) - 1);
1067         memcpy(buf_cpy, buf, bytes);
1068         buf_cpy[bytes] = '\0';
1069         tmp = buf_cpy;
1070         while (tmp[0]) {
1071                 sub_str = strsep(&tmp, delimiter);
1072                 if (strlen(sub_str)) {
1073                         ret = kstrtol(sub_str, 0, &level);
1074                         if (ret)
1075                                 return -EINVAL;
1076                         *mask |= 1 << level;
1077                 } else
1078                         break;
1079         }
1080
1081         return 0;
1082 }
1083
1084 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1085                 struct device_attribute *attr,
1086                 const char *buf,
1087                 size_t count)
1088 {
1089         struct drm_device *ddev = dev_get_drvdata(dev);
1090         struct amdgpu_device *adev = ddev->dev_private;
1091         int ret;
1092         uint32_t mask = 0;
1093
1094         if (adev->in_gpu_reset)
1095                 return -EPERM;
1096
1097         ret = amdgpu_read_mask(buf, count, &mask);
1098         if (ret)
1099                 return ret;
1100
1101         ret = pm_runtime_get_sync(ddev->dev);
1102         if (ret < 0) {
1103                 pm_runtime_put_autosuspend(ddev->dev);
1104                 return ret;
1105         }
1106
1107         if (is_support_sw_smu(adev))
1108                 ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask, true);
1109         else if (adev->powerplay.pp_funcs->force_clock_level)
1110                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
1111
1112         pm_runtime_mark_last_busy(ddev->dev);
1113         pm_runtime_put_autosuspend(ddev->dev);
1114
1115         if (ret)
1116                 return -EINVAL;
1117
1118         return count;
1119 }
1120
1121 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1122                 struct device_attribute *attr,
1123                 char *buf)
1124 {
1125         struct drm_device *ddev = dev_get_drvdata(dev);
1126         struct amdgpu_device *adev = ddev->dev_private;
1127         ssize_t size;
1128         int ret;
1129
1130         if (adev->in_gpu_reset)
1131                 return -EPERM;
1132
1133         ret = pm_runtime_get_sync(ddev->dev);
1134         if (ret < 0) {
1135                 pm_runtime_put_autosuspend(ddev->dev);
1136                 return ret;
1137         }
1138
1139         if (is_support_sw_smu(adev))
1140                 size = smu_print_clk_levels(&adev->smu, SMU_MCLK, buf);
1141         else if (adev->powerplay.pp_funcs->print_clock_levels)
1142                 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
1143         else
1144                 size = snprintf(buf, PAGE_SIZE, "\n");
1145
1146         pm_runtime_mark_last_busy(ddev->dev);
1147         pm_runtime_put_autosuspend(ddev->dev);
1148
1149         return size;
1150 }
1151
1152 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1153                 struct device_attribute *attr,
1154                 const char *buf,
1155                 size_t count)
1156 {
1157         struct drm_device *ddev = dev_get_drvdata(dev);
1158         struct amdgpu_device *adev = ddev->dev_private;
1159         uint32_t mask = 0;
1160         int ret;
1161
1162         if (adev->in_gpu_reset)
1163                 return -EPERM;
1164
1165         ret = amdgpu_read_mask(buf, count, &mask);
1166         if (ret)
1167                 return ret;
1168
1169         ret = pm_runtime_get_sync(ddev->dev);
1170         if (ret < 0) {
1171                 pm_runtime_put_autosuspend(ddev->dev);
1172                 return ret;
1173         }
1174
1175         if (is_support_sw_smu(adev))
1176                 ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask, true);
1177         else if (adev->powerplay.pp_funcs->force_clock_level)
1178                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
1179
1180         pm_runtime_mark_last_busy(ddev->dev);
1181         pm_runtime_put_autosuspend(ddev->dev);
1182
1183         if (ret)
1184                 return -EINVAL;
1185
1186         return count;
1187 }
1188
1189 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1190                 struct device_attribute *attr,
1191                 char *buf)
1192 {
1193         struct drm_device *ddev = dev_get_drvdata(dev);
1194         struct amdgpu_device *adev = ddev->dev_private;
1195         ssize_t size;
1196         int ret;
1197
1198         if (adev->in_gpu_reset)
1199                 return -EPERM;
1200
1201         ret = pm_runtime_get_sync(ddev->dev);
1202         if (ret < 0) {
1203                 pm_runtime_put_autosuspend(ddev->dev);
1204                 return ret;
1205         }
1206
1207         if (is_support_sw_smu(adev))
1208                 size = smu_print_clk_levels(&adev->smu, SMU_SOCCLK, buf);
1209         else if (adev->powerplay.pp_funcs->print_clock_levels)
1210                 size = amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
1211         else
1212                 size = snprintf(buf, PAGE_SIZE, "\n");
1213
1214         pm_runtime_mark_last_busy(ddev->dev);
1215         pm_runtime_put_autosuspend(ddev->dev);
1216
1217         return size;
1218 }
1219
1220 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1221                 struct device_attribute *attr,
1222                 const char *buf,
1223                 size_t count)
1224 {
1225         struct drm_device *ddev = dev_get_drvdata(dev);
1226         struct amdgpu_device *adev = ddev->dev_private;
1227         int ret;
1228         uint32_t mask = 0;
1229
1230         if (adev->in_gpu_reset)
1231                 return -EPERM;
1232
1233         ret = amdgpu_read_mask(buf, count, &mask);
1234         if (ret)
1235                 return ret;
1236
1237         ret = pm_runtime_get_sync(ddev->dev);
1238         if (ret < 0) {
1239                 pm_runtime_put_autosuspend(ddev->dev);
1240                 return ret;
1241         }
1242
1243         if (is_support_sw_smu(adev))
1244                 ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask, true);
1245         else if (adev->powerplay.pp_funcs->force_clock_level)
1246                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
1247         else
1248                 ret = 0;
1249
1250         pm_runtime_mark_last_busy(ddev->dev);
1251         pm_runtime_put_autosuspend(ddev->dev);
1252
1253         if (ret)
1254                 return -EINVAL;
1255
1256         return count;
1257 }
1258
1259 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1260                 struct device_attribute *attr,
1261                 char *buf)
1262 {
1263         struct drm_device *ddev = dev_get_drvdata(dev);
1264         struct amdgpu_device *adev = ddev->dev_private;
1265         ssize_t size;
1266         int ret;
1267
1268         if (adev->in_gpu_reset)
1269                 return -EPERM;
1270
1271         ret = pm_runtime_get_sync(ddev->dev);
1272         if (ret < 0) {
1273                 pm_runtime_put_autosuspend(ddev->dev);
1274                 return ret;
1275         }
1276
1277         if (is_support_sw_smu(adev))
1278                 size = smu_print_clk_levels(&adev->smu, SMU_FCLK, buf);
1279         else if (adev->powerplay.pp_funcs->print_clock_levels)
1280                 size = amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
1281         else
1282                 size = snprintf(buf, PAGE_SIZE, "\n");
1283
1284         pm_runtime_mark_last_busy(ddev->dev);
1285         pm_runtime_put_autosuspend(ddev->dev);
1286
1287         return size;
1288 }
1289
1290 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1291                 struct device_attribute *attr,
1292                 const char *buf,
1293                 size_t count)
1294 {
1295         struct drm_device *ddev = dev_get_drvdata(dev);
1296         struct amdgpu_device *adev = ddev->dev_private;
1297         int ret;
1298         uint32_t mask = 0;
1299
1300         if (adev->in_gpu_reset)
1301                 return -EPERM;
1302
1303         ret = amdgpu_read_mask(buf, count, &mask);
1304         if (ret)
1305                 return ret;
1306
1307         ret = pm_runtime_get_sync(ddev->dev);
1308         if (ret < 0) {
1309                 pm_runtime_put_autosuspend(ddev->dev);
1310                 return ret;
1311         }
1312
1313         if (is_support_sw_smu(adev))
1314                 ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask, true);
1315         else if (adev->powerplay.pp_funcs->force_clock_level)
1316                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
1317         else
1318                 ret = 0;
1319
1320         pm_runtime_mark_last_busy(ddev->dev);
1321         pm_runtime_put_autosuspend(ddev->dev);
1322
1323         if (ret)
1324                 return -EINVAL;
1325
1326         return count;
1327 }
1328
1329 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1330                 struct device_attribute *attr,
1331                 char *buf)
1332 {
1333         struct drm_device *ddev = dev_get_drvdata(dev);
1334         struct amdgpu_device *adev = ddev->dev_private;
1335         ssize_t size;
1336         int ret;
1337
1338         if (adev->in_gpu_reset)
1339                 return -EPERM;
1340
1341         ret = pm_runtime_get_sync(ddev->dev);
1342         if (ret < 0) {
1343                 pm_runtime_put_autosuspend(ddev->dev);
1344                 return ret;
1345         }
1346
1347         if (is_support_sw_smu(adev))
1348                 size = smu_print_clk_levels(&adev->smu, SMU_DCEFCLK, buf);
1349         else if (adev->powerplay.pp_funcs->print_clock_levels)
1350                 size = amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
1351         else
1352                 size = snprintf(buf, PAGE_SIZE, "\n");
1353
1354         pm_runtime_mark_last_busy(ddev->dev);
1355         pm_runtime_put_autosuspend(ddev->dev);
1356
1357         return size;
1358 }
1359
1360 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1361                 struct device_attribute *attr,
1362                 const char *buf,
1363                 size_t count)
1364 {
1365         struct drm_device *ddev = dev_get_drvdata(dev);
1366         struct amdgpu_device *adev = ddev->dev_private;
1367         int ret;
1368         uint32_t mask = 0;
1369
1370         if (adev->in_gpu_reset)
1371                 return -EPERM;
1372
1373         ret = amdgpu_read_mask(buf, count, &mask);
1374         if (ret)
1375                 return ret;
1376
1377         ret = pm_runtime_get_sync(ddev->dev);
1378         if (ret < 0) {
1379                 pm_runtime_put_autosuspend(ddev->dev);
1380                 return ret;
1381         }
1382
1383         if (is_support_sw_smu(adev))
1384                 ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask, true);
1385         else if (adev->powerplay.pp_funcs->force_clock_level)
1386                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1387         else
1388                 ret = 0;
1389
1390         pm_runtime_mark_last_busy(ddev->dev);
1391         pm_runtime_put_autosuspend(ddev->dev);
1392
1393         if (ret)
1394                 return -EINVAL;
1395
1396         return count;
1397 }
1398
1399 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1400                 struct device_attribute *attr,
1401                 char *buf)
1402 {
1403         struct drm_device *ddev = dev_get_drvdata(dev);
1404         struct amdgpu_device *adev = ddev->dev_private;
1405         ssize_t size;
1406         int ret;
1407
1408         if (adev->in_gpu_reset)
1409                 return -EPERM;
1410
1411         ret = pm_runtime_get_sync(ddev->dev);
1412         if (ret < 0) {
1413                 pm_runtime_put_autosuspend(ddev->dev);
1414                 return ret;
1415         }
1416
1417         if (is_support_sw_smu(adev))
1418                 size = smu_print_clk_levels(&adev->smu, SMU_PCIE, buf);
1419         else if (adev->powerplay.pp_funcs->print_clock_levels)
1420                 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1421         else
1422                 size = snprintf(buf, PAGE_SIZE, "\n");
1423
1424         pm_runtime_mark_last_busy(ddev->dev);
1425         pm_runtime_put_autosuspend(ddev->dev);
1426
1427         return size;
1428 }
1429
1430 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1431                 struct device_attribute *attr,
1432                 const char *buf,
1433                 size_t count)
1434 {
1435         struct drm_device *ddev = dev_get_drvdata(dev);
1436         struct amdgpu_device *adev = ddev->dev_private;
1437         int ret;
1438         uint32_t mask = 0;
1439
1440         if (adev->in_gpu_reset)
1441                 return -EPERM;
1442
1443         ret = amdgpu_read_mask(buf, count, &mask);
1444         if (ret)
1445                 return ret;
1446
1447         ret = pm_runtime_get_sync(ddev->dev);
1448         if (ret < 0) {
1449                 pm_runtime_put_autosuspend(ddev->dev);
1450                 return ret;
1451         }
1452
1453         if (is_support_sw_smu(adev))
1454                 ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask, true);
1455         else if (adev->powerplay.pp_funcs->force_clock_level)
1456                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1457         else
1458                 ret = 0;
1459
1460         pm_runtime_mark_last_busy(ddev->dev);
1461         pm_runtime_put_autosuspend(ddev->dev);
1462
1463         if (ret)
1464                 return -EINVAL;
1465
1466         return count;
1467 }
1468
1469 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1470                 struct device_attribute *attr,
1471                 char *buf)
1472 {
1473         struct drm_device *ddev = dev_get_drvdata(dev);
1474         struct amdgpu_device *adev = ddev->dev_private;
1475         uint32_t value = 0;
1476         int ret;
1477
1478         if (adev->in_gpu_reset)
1479                 return -EPERM;
1480
1481         ret = pm_runtime_get_sync(ddev->dev);
1482         if (ret < 0) {
1483                 pm_runtime_put_autosuspend(ddev->dev);
1484                 return ret;
1485         }
1486
1487         if (is_support_sw_smu(adev))
1488                 value = smu_get_od_percentage(&(adev->smu), SMU_OD_SCLK);
1489         else if (adev->powerplay.pp_funcs->get_sclk_od)
1490                 value = amdgpu_dpm_get_sclk_od(adev);
1491
1492         pm_runtime_mark_last_busy(ddev->dev);
1493         pm_runtime_put_autosuspend(ddev->dev);
1494
1495         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1496 }
1497
1498 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1499                 struct device_attribute *attr,
1500                 const char *buf,
1501                 size_t count)
1502 {
1503         struct drm_device *ddev = dev_get_drvdata(dev);
1504         struct amdgpu_device *adev = ddev->dev_private;
1505         int ret;
1506         long int value;
1507
1508         if (adev->in_gpu_reset)
1509                 return -EPERM;
1510
1511         ret = kstrtol(buf, 0, &value);
1512
1513         if (ret)
1514                 return -EINVAL;
1515
1516         ret = pm_runtime_get_sync(ddev->dev);
1517         if (ret < 0) {
1518                 pm_runtime_put_autosuspend(ddev->dev);
1519                 return ret;
1520         }
1521
1522         if (is_support_sw_smu(adev)) {
1523                 value = smu_set_od_percentage(&(adev->smu), SMU_OD_SCLK, (uint32_t)value);
1524         } else {
1525                 if (adev->powerplay.pp_funcs->set_sclk_od)
1526                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1527
1528                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1529                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1530                 } else {
1531                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1532                         amdgpu_pm_compute_clocks(adev);
1533                 }
1534         }
1535
1536         pm_runtime_mark_last_busy(ddev->dev);
1537         pm_runtime_put_autosuspend(ddev->dev);
1538
1539         return count;
1540 }
1541
1542 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1543                 struct device_attribute *attr,
1544                 char *buf)
1545 {
1546         struct drm_device *ddev = dev_get_drvdata(dev);
1547         struct amdgpu_device *adev = ddev->dev_private;
1548         uint32_t value = 0;
1549         int ret;
1550
1551         if (adev->in_gpu_reset)
1552                 return -EPERM;
1553
1554         ret = pm_runtime_get_sync(ddev->dev);
1555         if (ret < 0) {
1556                 pm_runtime_put_autosuspend(ddev->dev);
1557                 return ret;
1558         }
1559
1560         if (is_support_sw_smu(adev))
1561                 value = smu_get_od_percentage(&(adev->smu), SMU_OD_MCLK);
1562         else if (adev->powerplay.pp_funcs->get_mclk_od)
1563                 value = amdgpu_dpm_get_mclk_od(adev);
1564
1565         pm_runtime_mark_last_busy(ddev->dev);
1566         pm_runtime_put_autosuspend(ddev->dev);
1567
1568         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1569 }
1570
1571 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1572                 struct device_attribute *attr,
1573                 const char *buf,
1574                 size_t count)
1575 {
1576         struct drm_device *ddev = dev_get_drvdata(dev);
1577         struct amdgpu_device *adev = ddev->dev_private;
1578         int ret;
1579         long int value;
1580
1581         if (adev->in_gpu_reset)
1582                 return -EPERM;
1583
1584         ret = kstrtol(buf, 0, &value);
1585
1586         if (ret)
1587                 return -EINVAL;
1588
1589         ret = pm_runtime_get_sync(ddev->dev);
1590         if (ret < 0) {
1591                 pm_runtime_put_autosuspend(ddev->dev);
1592                 return ret;
1593         }
1594
1595         if (is_support_sw_smu(adev)) {
1596                 value = smu_set_od_percentage(&(adev->smu), SMU_OD_MCLK, (uint32_t)value);
1597         } else {
1598                 if (adev->powerplay.pp_funcs->set_mclk_od)
1599                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1600
1601                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1602                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1603                 } else {
1604                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1605                         amdgpu_pm_compute_clocks(adev);
1606                 }
1607         }
1608
1609         pm_runtime_mark_last_busy(ddev->dev);
1610         pm_runtime_put_autosuspend(ddev->dev);
1611
1612         return count;
1613 }
1614
1615 /**
1616  * DOC: pp_power_profile_mode
1617  *
1618  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1619  * related to switching between power levels in a power state.  The file
1620  * pp_power_profile_mode is used for this.
1621  *
1622  * Reading this file outputs a list of all of the predefined power profiles
1623  * and the relevant heuristics settings for that profile.
1624  *
1625  * To select a profile or create a custom profile, first select manual using
1626  * power_dpm_force_performance_level.  Writing the number of a predefined
1627  * profile to pp_power_profile_mode will enable those heuristics.  To
1628  * create a custom set of heuristics, write a string of numbers to the file
1629  * starting with the number of the custom profile along with a setting
1630  * for each heuristic parameter.  Due to differences across asic families
1631  * the heuristic parameters vary from family to family.
1632  *
1633  */
1634
1635 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1636                 struct device_attribute *attr,
1637                 char *buf)
1638 {
1639         struct drm_device *ddev = dev_get_drvdata(dev);
1640         struct amdgpu_device *adev = ddev->dev_private;
1641         ssize_t size;
1642         int ret;
1643
1644         if (adev->in_gpu_reset)
1645                 return -EPERM;
1646
1647         ret = pm_runtime_get_sync(ddev->dev);
1648         if (ret < 0) {
1649                 pm_runtime_put_autosuspend(ddev->dev);
1650                 return ret;
1651         }
1652
1653         if (is_support_sw_smu(adev))
1654                 size = smu_get_power_profile_mode(&adev->smu, buf);
1655         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1656                 size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1657         else
1658                 size = snprintf(buf, PAGE_SIZE, "\n");
1659
1660         pm_runtime_mark_last_busy(ddev->dev);
1661         pm_runtime_put_autosuspend(ddev->dev);
1662
1663         return size;
1664 }
1665
1666
1667 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1668                 struct device_attribute *attr,
1669                 const char *buf,
1670                 size_t count)
1671 {
1672         int ret;
1673         struct drm_device *ddev = dev_get_drvdata(dev);
1674         struct amdgpu_device *adev = ddev->dev_private;
1675         uint32_t parameter_size = 0;
1676         long parameter[64];
1677         char *sub_str, buf_cpy[128];
1678         char *tmp_str;
1679         uint32_t i = 0;
1680         char tmp[2];
1681         long int profile_mode = 0;
1682         const char delimiter[3] = {' ', '\n', '\0'};
1683
1684         if (adev->in_gpu_reset)
1685                 return -EPERM;
1686
1687         tmp[0] = *(buf);
1688         tmp[1] = '\0';
1689         ret = kstrtol(tmp, 0, &profile_mode);
1690         if (ret)
1691                 return -EINVAL;
1692
1693         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1694                 if (count < 2 || count > 127)
1695                         return -EINVAL;
1696                 while (isspace(*++buf))
1697                         i++;
1698                 memcpy(buf_cpy, buf, count-i);
1699                 tmp_str = buf_cpy;
1700                 while (tmp_str[0]) {
1701                         sub_str = strsep(&tmp_str, delimiter);
1702                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1703                         if (ret)
1704                                 return -EINVAL;
1705                         parameter_size++;
1706                         while (isspace(*tmp_str))
1707                                 tmp_str++;
1708                 }
1709         }
1710         parameter[parameter_size] = profile_mode;
1711
1712         ret = pm_runtime_get_sync(ddev->dev);
1713         if (ret < 0) {
1714                 pm_runtime_put_autosuspend(ddev->dev);
1715                 return ret;
1716         }
1717
1718         if (is_support_sw_smu(adev))
1719                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true);
1720         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1721                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1722
1723         pm_runtime_mark_last_busy(ddev->dev);
1724         pm_runtime_put_autosuspend(ddev->dev);
1725
1726         if (!ret)
1727                 return count;
1728
1729         return -EINVAL;
1730 }
1731
1732 /**
1733  * DOC: gpu_busy_percent
1734  *
1735  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1736  * is as a percentage.  The file gpu_busy_percent is used for this.
1737  * The SMU firmware computes a percentage of load based on the
1738  * aggregate activity level in the IP cores.
1739  */
1740 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1741                                            struct device_attribute *attr,
1742                                            char *buf)
1743 {
1744         struct drm_device *ddev = dev_get_drvdata(dev);
1745         struct amdgpu_device *adev = ddev->dev_private;
1746         int r, value, size = sizeof(value);
1747
1748         if (adev->in_gpu_reset)
1749                 return -EPERM;
1750
1751         r = pm_runtime_get_sync(ddev->dev);
1752         if (r < 0) {
1753                 pm_runtime_put_autosuspend(ddev->dev);
1754                 return r;
1755         }
1756
1757         /* read the IP busy sensor */
1758         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1759                                    (void *)&value, &size);
1760
1761         pm_runtime_mark_last_busy(ddev->dev);
1762         pm_runtime_put_autosuspend(ddev->dev);
1763
1764         if (r)
1765                 return r;
1766
1767         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1768 }
1769
1770 /**
1771  * DOC: mem_busy_percent
1772  *
1773  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1774  * is as a percentage.  The file mem_busy_percent is used for this.
1775  * The SMU firmware computes a percentage of load based on the
1776  * aggregate activity level in the IP cores.
1777  */
1778 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1779                                            struct device_attribute *attr,
1780                                            char *buf)
1781 {
1782         struct drm_device *ddev = dev_get_drvdata(dev);
1783         struct amdgpu_device *adev = ddev->dev_private;
1784         int r, value, size = sizeof(value);
1785
1786         if (adev->in_gpu_reset)
1787                 return -EPERM;
1788
1789         r = pm_runtime_get_sync(ddev->dev);
1790         if (r < 0) {
1791                 pm_runtime_put_autosuspend(ddev->dev);
1792                 return r;
1793         }
1794
1795         /* read the IP busy sensor */
1796         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1797                                    (void *)&value, &size);
1798
1799         pm_runtime_mark_last_busy(ddev->dev);
1800         pm_runtime_put_autosuspend(ddev->dev);
1801
1802         if (r)
1803                 return r;
1804
1805         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1806 }
1807
1808 /**
1809  * DOC: pcie_bw
1810  *
1811  * The amdgpu driver provides a sysfs API for estimating how much data
1812  * has been received and sent by the GPU in the last second through PCIe.
1813  * The file pcie_bw is used for this.
1814  * The Perf counters count the number of received and sent messages and return
1815  * those values, as well as the maximum payload size of a PCIe packet (mps).
1816  * Note that it is not possible to easily and quickly obtain the size of each
1817  * packet transmitted, so we output the max payload size (mps) to allow for
1818  * quick estimation of the PCIe bandwidth usage
1819  */
1820 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1821                 struct device_attribute *attr,
1822                 char *buf)
1823 {
1824         struct drm_device *ddev = dev_get_drvdata(dev);
1825         struct amdgpu_device *adev = ddev->dev_private;
1826         uint64_t count0 = 0, count1 = 0;
1827         int ret;
1828
1829         if (adev->in_gpu_reset)
1830                 return -EPERM;
1831
1832         if (adev->flags & AMD_IS_APU)
1833                 return -ENODATA;
1834
1835         if (!adev->asic_funcs->get_pcie_usage)
1836                 return -ENODATA;
1837
1838         ret = pm_runtime_get_sync(ddev->dev);
1839         if (ret < 0) {
1840                 pm_runtime_put_autosuspend(ddev->dev);
1841                 return ret;
1842         }
1843
1844         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1845
1846         pm_runtime_mark_last_busy(ddev->dev);
1847         pm_runtime_put_autosuspend(ddev->dev);
1848
1849         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1850                         count0, count1, pcie_get_mps(adev->pdev));
1851 }
1852
1853 /**
1854  * DOC: unique_id
1855  *
1856  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1857  * The file unique_id is used for this.
1858  * This will provide a Unique ID that will persist from machine to machine
1859  *
1860  * NOTE: This will only work for GFX9 and newer. This file will be absent
1861  * on unsupported ASICs (GFX8 and older)
1862  */
1863 static ssize_t amdgpu_get_unique_id(struct device *dev,
1864                 struct device_attribute *attr,
1865                 char *buf)
1866 {
1867         struct drm_device *ddev = dev_get_drvdata(dev);
1868         struct amdgpu_device *adev = ddev->dev_private;
1869
1870         if (adev->in_gpu_reset)
1871                 return -EPERM;
1872
1873         if (adev->unique_id)
1874                 return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id);
1875
1876         return 0;
1877 }
1878
1879 /**
1880  * DOC: thermal_throttling_logging
1881  *
1882  * Thermal throttling pulls down the clock frequency and thus the performance.
1883  * It's an useful mechanism to protect the chip from overheating. Since it
1884  * impacts performance, the user controls whether it is enabled and if so,
1885  * the log frequency.
1886  *
1887  * Reading back the file shows you the status(enabled or disabled) and
1888  * the interval(in seconds) between each thermal logging.
1889  *
1890  * Writing an integer to the file, sets a new logging interval, in seconds.
1891  * The value should be between 1 and 3600. If the value is less than 1,
1892  * thermal logging is disabled. Values greater than 3600 are ignored.
1893  */
1894 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1895                                                      struct device_attribute *attr,
1896                                                      char *buf)
1897 {
1898         struct drm_device *ddev = dev_get_drvdata(dev);
1899         struct amdgpu_device *adev = ddev->dev_private;
1900
1901         return snprintf(buf, PAGE_SIZE, "%s: thermal throttling logging %s, with interval %d seconds\n",
1902                         adev->ddev->unique,
1903                         atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1904                         adev->throttling_logging_rs.interval / HZ + 1);
1905 }
1906
1907 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1908                                                      struct device_attribute *attr,
1909                                                      const char *buf,
1910                                                      size_t count)
1911 {
1912         struct drm_device *ddev = dev_get_drvdata(dev);
1913         struct amdgpu_device *adev = ddev->dev_private;
1914         long throttling_logging_interval;
1915         unsigned long flags;
1916         int ret = 0;
1917
1918         ret = kstrtol(buf, 0, &throttling_logging_interval);
1919         if (ret)
1920                 return ret;
1921
1922         if (throttling_logging_interval > 3600)
1923                 return -EINVAL;
1924
1925         if (throttling_logging_interval > 0) {
1926                 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1927                 /*
1928                  * Reset the ratelimit timer internals.
1929                  * This can effectively restart the timer.
1930                  */
1931                 adev->throttling_logging_rs.interval =
1932                         (throttling_logging_interval - 1) * HZ;
1933                 adev->throttling_logging_rs.begin = 0;
1934                 adev->throttling_logging_rs.printed = 0;
1935                 adev->throttling_logging_rs.missed = 0;
1936                 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1937
1938                 atomic_set(&adev->throttling_logging_enabled, 1);
1939         } else {
1940                 atomic_set(&adev->throttling_logging_enabled, 0);
1941         }
1942
1943         return count;
1944 }
1945
1946 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
1947         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1948         AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC),
1949         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC),
1950         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC),
1951         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC),
1952         AMDGPU_DEVICE_ATTR_RW(pp_table,                                 ATTR_FLAG_BASIC),
1953         AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1954         AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1955         AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1956         AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
1957         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,                           ATTR_FLAG_BASIC),
1958         AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,                              ATTR_FLAG_BASIC),
1959         AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,                               ATTR_FLAG_BASIC),
1960         AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,                               ATTR_FLAG_BASIC),
1961         AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,                    ATTR_FLAG_BASIC),
1962         AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,                        ATTR_FLAG_BASIC),
1963         AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,                         ATTR_FLAG_BASIC),
1964         AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,                         ATTR_FLAG_BASIC),
1965         AMDGPU_DEVICE_ATTR_RO(pcie_bw,                                  ATTR_FLAG_BASIC),
1966         AMDGPU_DEVICE_ATTR_RW(pp_features,                              ATTR_FLAG_BASIC),
1967         AMDGPU_DEVICE_ATTR_RO(unique_id,                                ATTR_FLAG_BASIC),
1968         AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,               ATTR_FLAG_BASIC),
1969 };
1970
1971 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1972                                uint32_t mask, enum amdgpu_device_attr_states *states)
1973 {
1974         struct device_attribute *dev_attr = &attr->dev_attr;
1975         const char *attr_name = dev_attr->attr.name;
1976         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
1977         enum amd_asic_type asic_type = adev->asic_type;
1978
1979         if (!(attr->flags & mask)) {
1980                 *states = ATTR_STATE_UNSUPPORTED;
1981                 return 0;
1982         }
1983
1984 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))
1985
1986         if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
1987                 if (asic_type < CHIP_VEGA10)
1988                         *states = ATTR_STATE_UNSUPPORTED;
1989         } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
1990                 if (asic_type < CHIP_VEGA10 || asic_type == CHIP_ARCTURUS)
1991                         *states = ATTR_STATE_UNSUPPORTED;
1992         } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
1993                 if (asic_type < CHIP_VEGA20)
1994                         *states = ATTR_STATE_UNSUPPORTED;
1995         } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
1996                 if (asic_type == CHIP_ARCTURUS)
1997                         *states = ATTR_STATE_UNSUPPORTED;
1998         } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
1999                 *states = ATTR_STATE_UNSUPPORTED;
2000                 if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2001                     (!is_support_sw_smu(adev) && hwmgr->od_enabled))
2002                         *states = ATTR_STATE_SUPPORTED;
2003         } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2004                 if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
2005                         *states = ATTR_STATE_UNSUPPORTED;
2006         } else if (DEVICE_ATTR_IS(pcie_bw)) {
2007                 /* PCIe Perf counters won't work on APU nodes */
2008                 if (adev->flags & AMD_IS_APU)
2009                         *states = ATTR_STATE_UNSUPPORTED;
2010         } else if (DEVICE_ATTR_IS(unique_id)) {
2011                 if (asic_type != CHIP_VEGA10 &&
2012                     asic_type != CHIP_VEGA20 &&
2013                     asic_type != CHIP_ARCTURUS)
2014                         *states = ATTR_STATE_UNSUPPORTED;
2015         } else if (DEVICE_ATTR_IS(pp_features)) {
2016                 if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
2017                         *states = ATTR_STATE_UNSUPPORTED;
2018         }
2019
2020         if (asic_type == CHIP_ARCTURUS) {
2021                 /* Arcturus does not support standalone mclk/socclk/fclk level setting */
2022                 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2023                     DEVICE_ATTR_IS(pp_dpm_socclk) ||
2024                     DEVICE_ATTR_IS(pp_dpm_fclk)) {
2025                         dev_attr->attr.mode &= ~S_IWUGO;
2026                         dev_attr->store = NULL;
2027                 }
2028         }
2029
2030 #undef DEVICE_ATTR_IS
2031
2032         return 0;
2033 }
2034
2035
2036 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2037                                      struct amdgpu_device_attr *attr,
2038                                      uint32_t mask, struct list_head *attr_list)
2039 {
2040         int ret = 0;
2041         struct device_attribute *dev_attr = &attr->dev_attr;
2042         const char *name = dev_attr->attr.name;
2043         enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2044         struct amdgpu_device_attr_entry *attr_entry;
2045
2046         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2047                            uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2048
2049         BUG_ON(!attr);
2050
2051         attr_update = attr->attr_update ? attr_update : default_attr_update;
2052
2053         ret = attr_update(adev, attr, mask, &attr_states);
2054         if (ret) {
2055                 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2056                         name, ret);
2057                 return ret;
2058         }
2059
2060         if (attr_states == ATTR_STATE_UNSUPPORTED)
2061                 return 0;
2062
2063         ret = device_create_file(adev->dev, dev_attr);
2064         if (ret) {
2065                 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2066                         name, ret);
2067         }
2068
2069         attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2070         if (!attr_entry)
2071                 return -ENOMEM;
2072
2073         attr_entry->attr = attr;
2074         INIT_LIST_HEAD(&attr_entry->entry);
2075
2076         list_add_tail(&attr_entry->entry, attr_list);
2077
2078         return ret;
2079 }
2080
2081 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2082 {
2083         struct device_attribute *dev_attr = &attr->dev_attr;
2084
2085         device_remove_file(adev->dev, dev_attr);
2086 }
2087
2088 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2089                                              struct list_head *attr_list);
2090
2091 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2092                                             struct amdgpu_device_attr *attrs,
2093                                             uint32_t counts,
2094                                             uint32_t mask,
2095                                             struct list_head *attr_list)
2096 {
2097         int ret = 0;
2098         uint32_t i = 0;
2099
2100         for (i = 0; i < counts; i++) {
2101                 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2102                 if (ret)
2103                         goto failed;
2104         }
2105
2106         return 0;
2107
2108 failed:
2109         amdgpu_device_attr_remove_groups(adev, attr_list);
2110
2111         return ret;
2112 }
2113
2114 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2115                                              struct list_head *attr_list)
2116 {
2117         struct amdgpu_device_attr_entry *entry, *entry_tmp;
2118
2119         if (list_empty(attr_list))
2120                 return ;
2121
2122         list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2123                 amdgpu_device_attr_remove(adev, entry->attr);
2124                 list_del(&entry->entry);
2125                 kfree(entry);
2126         }
2127 }
2128
2129 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2130                                       struct device_attribute *attr,
2131                                       char *buf)
2132 {
2133         struct amdgpu_device *adev = dev_get_drvdata(dev);
2134         int channel = to_sensor_dev_attr(attr)->index;
2135         int r, temp = 0, size = sizeof(temp);
2136
2137         if (adev->in_gpu_reset)
2138                 return -EPERM;
2139
2140         if (channel >= PP_TEMP_MAX)
2141                 return -EINVAL;
2142
2143         r = pm_runtime_get_sync(adev->ddev->dev);
2144         if (r < 0) {
2145                 pm_runtime_put_autosuspend(adev->ddev->dev);
2146                 return r;
2147         }
2148
2149         switch (channel) {
2150         case PP_TEMP_JUNCTION:
2151                 /* get current junction temperature */
2152                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2153                                            (void *)&temp, &size);
2154                 break;
2155         case PP_TEMP_EDGE:
2156                 /* get current edge temperature */
2157                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2158                                            (void *)&temp, &size);
2159                 break;
2160         case PP_TEMP_MEM:
2161                 /* get current memory temperature */
2162                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2163                                            (void *)&temp, &size);
2164                 break;
2165         default:
2166                 r = -EINVAL;
2167                 break;
2168         }
2169
2170         pm_runtime_mark_last_busy(adev->ddev->dev);
2171         pm_runtime_put_autosuspend(adev->ddev->dev);
2172
2173         if (r)
2174                 return r;
2175
2176         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2177 }
2178
2179 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2180                                              struct device_attribute *attr,
2181                                              char *buf)
2182 {
2183         struct amdgpu_device *adev = dev_get_drvdata(dev);
2184         int hyst = to_sensor_dev_attr(attr)->index;
2185         int temp;
2186
2187         if (hyst)
2188                 temp = adev->pm.dpm.thermal.min_temp;
2189         else
2190                 temp = adev->pm.dpm.thermal.max_temp;
2191
2192         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2193 }
2194
2195 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2196                                              struct device_attribute *attr,
2197                                              char *buf)
2198 {
2199         struct amdgpu_device *adev = dev_get_drvdata(dev);
2200         int hyst = to_sensor_dev_attr(attr)->index;
2201         int temp;
2202
2203         if (hyst)
2204                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2205         else
2206                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2207
2208         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2209 }
2210
2211 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2212                                              struct device_attribute *attr,
2213                                              char *buf)
2214 {
2215         struct amdgpu_device *adev = dev_get_drvdata(dev);
2216         int hyst = to_sensor_dev_attr(attr)->index;
2217         int temp;
2218
2219         if (hyst)
2220                 temp = adev->pm.dpm.thermal.min_mem_temp;
2221         else
2222                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2223
2224         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2225 }
2226
2227 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2228                                              struct device_attribute *attr,
2229                                              char *buf)
2230 {
2231         int channel = to_sensor_dev_attr(attr)->index;
2232
2233         if (channel >= PP_TEMP_MAX)
2234                 return -EINVAL;
2235
2236         return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
2237 }
2238
2239 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2240                                              struct device_attribute *attr,
2241                                              char *buf)
2242 {
2243         struct amdgpu_device *adev = dev_get_drvdata(dev);
2244         int channel = to_sensor_dev_attr(attr)->index;
2245         int temp = 0;
2246
2247         if (channel >= PP_TEMP_MAX)
2248                 return -EINVAL;
2249
2250         switch (channel) {
2251         case PP_TEMP_JUNCTION:
2252                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2253                 break;
2254         case PP_TEMP_EDGE:
2255                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2256                 break;
2257         case PP_TEMP_MEM:
2258                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2259                 break;
2260         }
2261
2262         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2263 }
2264
2265 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2266                                             struct device_attribute *attr,
2267                                             char *buf)
2268 {
2269         struct amdgpu_device *adev = dev_get_drvdata(dev);
2270         u32 pwm_mode = 0;
2271         int ret;
2272
2273         if (adev->in_gpu_reset)
2274                 return -EPERM;
2275
2276         ret = pm_runtime_get_sync(adev->ddev->dev);
2277         if (ret < 0) {
2278                 pm_runtime_put_autosuspend(adev->ddev->dev);
2279                 return ret;
2280         }
2281
2282         if (is_support_sw_smu(adev)) {
2283                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2284         } else {
2285                 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2286                         pm_runtime_mark_last_busy(adev->ddev->dev);
2287                         pm_runtime_put_autosuspend(adev->ddev->dev);
2288                         return -EINVAL;
2289                 }
2290
2291                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2292         }
2293
2294         pm_runtime_mark_last_busy(adev->ddev->dev);
2295         pm_runtime_put_autosuspend(adev->ddev->dev);
2296
2297         return sprintf(buf, "%i\n", pwm_mode);
2298 }
2299
2300 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2301                                             struct device_attribute *attr,
2302                                             const char *buf,
2303                                             size_t count)
2304 {
2305         struct amdgpu_device *adev = dev_get_drvdata(dev);
2306         int err, ret;
2307         int value;
2308
2309         if (adev->in_gpu_reset)
2310                 return -EPERM;
2311
2312         err = kstrtoint(buf, 10, &value);
2313         if (err)
2314                 return err;
2315
2316         ret = pm_runtime_get_sync(adev->ddev->dev);
2317         if (ret < 0) {
2318                 pm_runtime_put_autosuspend(adev->ddev->dev);
2319                 return ret;
2320         }
2321
2322         if (is_support_sw_smu(adev)) {
2323                 smu_set_fan_control_mode(&adev->smu, value);
2324         } else {
2325                 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2326                         pm_runtime_mark_last_busy(adev->ddev->dev);
2327                         pm_runtime_put_autosuspend(adev->ddev->dev);
2328                         return -EINVAL;
2329                 }
2330
2331                 amdgpu_dpm_set_fan_control_mode(adev, value);
2332         }
2333
2334         pm_runtime_mark_last_busy(adev->ddev->dev);
2335         pm_runtime_put_autosuspend(adev->ddev->dev);
2336
2337         return count;
2338 }
2339
2340 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2341                                          struct device_attribute *attr,
2342                                          char *buf)
2343 {
2344         return sprintf(buf, "%i\n", 0);
2345 }
2346
2347 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2348                                          struct device_attribute *attr,
2349                                          char *buf)
2350 {
2351         return sprintf(buf, "%i\n", 255);
2352 }
2353
2354 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2355                                      struct device_attribute *attr,
2356                                      const char *buf, size_t count)
2357 {
2358         struct amdgpu_device *adev = dev_get_drvdata(dev);
2359         int err;
2360         u32 value;
2361         u32 pwm_mode;
2362
2363         if (adev->in_gpu_reset)
2364                 return -EPERM;
2365
2366         err = pm_runtime_get_sync(adev->ddev->dev);
2367         if (err < 0) {
2368                 pm_runtime_put_autosuspend(adev->ddev->dev);
2369                 return err;
2370         }
2371
2372         if (is_support_sw_smu(adev))
2373                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2374         else
2375                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2376
2377         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2378                 pr_info("manual fan speed control should be enabled first\n");
2379                 pm_runtime_mark_last_busy(adev->ddev->dev);
2380                 pm_runtime_put_autosuspend(adev->ddev->dev);
2381                 return -EINVAL;
2382         }
2383
2384         err = kstrtou32(buf, 10, &value);
2385         if (err) {
2386                 pm_runtime_mark_last_busy(adev->ddev->dev);
2387                 pm_runtime_put_autosuspend(adev->ddev->dev);
2388                 return err;
2389         }
2390
2391         value = (value * 100) / 255;
2392
2393         if (is_support_sw_smu(adev))
2394                 err = smu_set_fan_speed_percent(&adev->smu, value);
2395         else if (adev->powerplay.pp_funcs->set_fan_speed_percent)
2396                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
2397         else
2398                 err = -EINVAL;
2399
2400         pm_runtime_mark_last_busy(adev->ddev->dev);
2401         pm_runtime_put_autosuspend(adev->ddev->dev);
2402
2403         if (err)
2404                 return err;
2405
2406         return count;
2407 }
2408
2409 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2410                                      struct device_attribute *attr,
2411                                      char *buf)
2412 {
2413         struct amdgpu_device *adev = dev_get_drvdata(dev);
2414         int err;
2415         u32 speed = 0;
2416
2417         if (adev->in_gpu_reset)
2418                 return -EPERM;
2419
2420         err = pm_runtime_get_sync(adev->ddev->dev);
2421         if (err < 0) {
2422                 pm_runtime_put_autosuspend(adev->ddev->dev);
2423                 return err;
2424         }
2425
2426         if (is_support_sw_smu(adev))
2427                 err = smu_get_fan_speed_percent(&adev->smu, &speed);
2428         else if (adev->powerplay.pp_funcs->get_fan_speed_percent)
2429                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
2430         else
2431                 err = -EINVAL;
2432
2433         pm_runtime_mark_last_busy(adev->ddev->dev);
2434         pm_runtime_put_autosuspend(adev->ddev->dev);
2435
2436         if (err)
2437                 return err;
2438
2439         speed = (speed * 255) / 100;
2440
2441         return sprintf(buf, "%i\n", speed);
2442 }
2443
2444 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2445                                            struct device_attribute *attr,
2446                                            char *buf)
2447 {
2448         struct amdgpu_device *adev = dev_get_drvdata(dev);
2449         int err;
2450         u32 speed = 0;
2451
2452         if (adev->in_gpu_reset)
2453                 return -EPERM;
2454
2455         err = pm_runtime_get_sync(adev->ddev->dev);
2456         if (err < 0) {
2457                 pm_runtime_put_autosuspend(adev->ddev->dev);
2458                 return err;
2459         }
2460
2461         if (is_support_sw_smu(adev))
2462                 err = smu_get_fan_speed_rpm(&adev->smu, &speed);
2463         else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2464                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2465         else
2466                 err = -EINVAL;
2467
2468         pm_runtime_mark_last_busy(adev->ddev->dev);
2469         pm_runtime_put_autosuspend(adev->ddev->dev);
2470
2471         if (err)
2472                 return err;
2473
2474         return sprintf(buf, "%i\n", speed);
2475 }
2476
2477 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2478                                          struct device_attribute *attr,
2479                                          char *buf)
2480 {
2481         struct amdgpu_device *adev = dev_get_drvdata(dev);
2482         u32 min_rpm = 0;
2483         u32 size = sizeof(min_rpm);
2484         int r;
2485
2486         if (adev->in_gpu_reset)
2487                 return -EPERM;
2488
2489         r = pm_runtime_get_sync(adev->ddev->dev);
2490         if (r < 0) {
2491                 pm_runtime_put_autosuspend(adev->ddev->dev);
2492                 return r;
2493         }
2494
2495         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2496                                    (void *)&min_rpm, &size);
2497
2498         pm_runtime_mark_last_busy(adev->ddev->dev);
2499         pm_runtime_put_autosuspend(adev->ddev->dev);
2500
2501         if (r)
2502                 return r;
2503
2504         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
2505 }
2506
2507 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2508                                          struct device_attribute *attr,
2509                                          char *buf)
2510 {
2511         struct amdgpu_device *adev = dev_get_drvdata(dev);
2512         u32 max_rpm = 0;
2513         u32 size = sizeof(max_rpm);
2514         int r;
2515
2516         if (adev->in_gpu_reset)
2517                 return -EPERM;
2518
2519         r = pm_runtime_get_sync(adev->ddev->dev);
2520         if (r < 0) {
2521                 pm_runtime_put_autosuspend(adev->ddev->dev);
2522                 return r;
2523         }
2524
2525         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2526                                    (void *)&max_rpm, &size);
2527
2528         pm_runtime_mark_last_busy(adev->ddev->dev);
2529         pm_runtime_put_autosuspend(adev->ddev->dev);
2530
2531         if (r)
2532                 return r;
2533
2534         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
2535 }
2536
2537 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2538                                            struct device_attribute *attr,
2539                                            char *buf)
2540 {
2541         struct amdgpu_device *adev = dev_get_drvdata(dev);
2542         int err;
2543         u32 rpm = 0;
2544
2545         if (adev->in_gpu_reset)
2546                 return -EPERM;
2547
2548         err = pm_runtime_get_sync(adev->ddev->dev);
2549         if (err < 0) {
2550                 pm_runtime_put_autosuspend(adev->ddev->dev);
2551                 return err;
2552         }
2553
2554         if (is_support_sw_smu(adev))
2555                 err = smu_get_fan_speed_rpm(&adev->smu, &rpm);
2556         else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2557                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2558         else
2559                 err = -EINVAL;
2560
2561         pm_runtime_mark_last_busy(adev->ddev->dev);
2562         pm_runtime_put_autosuspend(adev->ddev->dev);
2563
2564         if (err)
2565                 return err;
2566
2567         return sprintf(buf, "%i\n", rpm);
2568 }
2569
2570 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2571                                      struct device_attribute *attr,
2572                                      const char *buf, size_t count)
2573 {
2574         struct amdgpu_device *adev = dev_get_drvdata(dev);
2575         int err;
2576         u32 value;
2577         u32 pwm_mode;
2578
2579         if (adev->in_gpu_reset)
2580                 return -EPERM;
2581
2582         err = pm_runtime_get_sync(adev->ddev->dev);
2583         if (err < 0) {
2584                 pm_runtime_put_autosuspend(adev->ddev->dev);
2585                 return err;
2586         }
2587
2588         if (is_support_sw_smu(adev))
2589                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2590         else
2591                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2592
2593         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2594                 pm_runtime_mark_last_busy(adev->ddev->dev);
2595                 pm_runtime_put_autosuspend(adev->ddev->dev);
2596                 return -ENODATA;
2597         }
2598
2599         err = kstrtou32(buf, 10, &value);
2600         if (err) {
2601                 pm_runtime_mark_last_busy(adev->ddev->dev);
2602                 pm_runtime_put_autosuspend(adev->ddev->dev);
2603                 return err;
2604         }
2605
2606         if (is_support_sw_smu(adev))
2607                 err = smu_set_fan_speed_rpm(&adev->smu, value);
2608         else if (adev->powerplay.pp_funcs->set_fan_speed_rpm)
2609                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2610         else
2611                 err = -EINVAL;
2612
2613         pm_runtime_mark_last_busy(adev->ddev->dev);
2614         pm_runtime_put_autosuspend(adev->ddev->dev);
2615
2616         if (err)
2617                 return err;
2618
2619         return count;
2620 }
2621
2622 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2623                                             struct device_attribute *attr,
2624                                             char *buf)
2625 {
2626         struct amdgpu_device *adev = dev_get_drvdata(dev);
2627         u32 pwm_mode = 0;
2628         int ret;
2629
2630         if (adev->in_gpu_reset)
2631                 return -EPERM;
2632
2633         ret = pm_runtime_get_sync(adev->ddev->dev);
2634         if (ret < 0) {
2635                 pm_runtime_put_autosuspend(adev->ddev->dev);
2636                 return ret;
2637         }
2638
2639         if (is_support_sw_smu(adev)) {
2640                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2641         } else {
2642                 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2643                         pm_runtime_mark_last_busy(adev->ddev->dev);
2644                         pm_runtime_put_autosuspend(adev->ddev->dev);
2645                         return -EINVAL;
2646                 }
2647
2648                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2649         }
2650
2651         pm_runtime_mark_last_busy(adev->ddev->dev);
2652         pm_runtime_put_autosuspend(adev->ddev->dev);
2653
2654         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2655 }
2656
2657 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2658                                             struct device_attribute *attr,
2659                                             const char *buf,
2660                                             size_t count)
2661 {
2662         struct amdgpu_device *adev = dev_get_drvdata(dev);
2663         int err;
2664         int value;
2665         u32 pwm_mode;
2666
2667         if (adev->in_gpu_reset)
2668                 return -EPERM;
2669
2670         err = kstrtoint(buf, 10, &value);
2671         if (err)
2672                 return err;
2673
2674         if (value == 0)
2675                 pwm_mode = AMD_FAN_CTRL_AUTO;
2676         else if (value == 1)
2677                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2678         else
2679                 return -EINVAL;
2680
2681         err = pm_runtime_get_sync(adev->ddev->dev);
2682         if (err < 0) {
2683                 pm_runtime_put_autosuspend(adev->ddev->dev);
2684                 return err;
2685         }
2686
2687         if (is_support_sw_smu(adev)) {
2688                 smu_set_fan_control_mode(&adev->smu, pwm_mode);
2689         } else {
2690                 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2691                         pm_runtime_mark_last_busy(adev->ddev->dev);
2692                         pm_runtime_put_autosuspend(adev->ddev->dev);
2693                         return -EINVAL;
2694                 }
2695                 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2696         }
2697
2698         pm_runtime_mark_last_busy(adev->ddev->dev);
2699         pm_runtime_put_autosuspend(adev->ddev->dev);
2700
2701         return count;
2702 }
2703
2704 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2705                                         struct device_attribute *attr,
2706                                         char *buf)
2707 {
2708         struct amdgpu_device *adev = dev_get_drvdata(dev);
2709         u32 vddgfx;
2710         int r, size = sizeof(vddgfx);
2711
2712         if (adev->in_gpu_reset)
2713                 return -EPERM;
2714
2715         r = pm_runtime_get_sync(adev->ddev->dev);
2716         if (r < 0) {
2717                 pm_runtime_put_autosuspend(adev->ddev->dev);
2718                 return r;
2719         }
2720
2721         /* get the voltage */
2722         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
2723                                    (void *)&vddgfx, &size);
2724
2725         pm_runtime_mark_last_busy(adev->ddev->dev);
2726         pm_runtime_put_autosuspend(adev->ddev->dev);
2727
2728         if (r)
2729                 return r;
2730
2731         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
2732 }
2733
2734 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2735                                               struct device_attribute *attr,
2736                                               char *buf)
2737 {
2738         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
2739 }
2740
2741 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2742                                        struct device_attribute *attr,
2743                                        char *buf)
2744 {
2745         struct amdgpu_device *adev = dev_get_drvdata(dev);
2746         u32 vddnb;
2747         int r, size = sizeof(vddnb);
2748
2749         if (adev->in_gpu_reset)
2750                 return -EPERM;
2751
2752         /* only APUs have vddnb */
2753         if  (!(adev->flags & AMD_IS_APU))
2754                 return -EINVAL;
2755
2756         r = pm_runtime_get_sync(adev->ddev->dev);
2757         if (r < 0) {
2758                 pm_runtime_put_autosuspend(adev->ddev->dev);
2759                 return r;
2760         }
2761
2762         /* get the voltage */
2763         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
2764                                    (void *)&vddnb, &size);
2765
2766         pm_runtime_mark_last_busy(adev->ddev->dev);
2767         pm_runtime_put_autosuspend(adev->ddev->dev);
2768
2769         if (r)
2770                 return r;
2771
2772         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
2773 }
2774
2775 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2776                                               struct device_attribute *attr,
2777                                               char *buf)
2778 {
2779         return snprintf(buf, PAGE_SIZE, "vddnb\n");
2780 }
2781
2782 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2783                                            struct device_attribute *attr,
2784                                            char *buf)
2785 {
2786         struct amdgpu_device *adev = dev_get_drvdata(dev);
2787         u32 query = 0;
2788         int r, size = sizeof(u32);
2789         unsigned uw;
2790
2791         if (adev->in_gpu_reset)
2792                 return -EPERM;
2793
2794         r = pm_runtime_get_sync(adev->ddev->dev);
2795         if (r < 0) {
2796                 pm_runtime_put_autosuspend(adev->ddev->dev);
2797                 return r;
2798         }
2799
2800         /* get the voltage */
2801         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
2802                                    (void *)&query, &size);
2803
2804         pm_runtime_mark_last_busy(adev->ddev->dev);
2805         pm_runtime_put_autosuspend(adev->ddev->dev);
2806
2807         if (r)
2808                 return r;
2809
2810         /* convert to microwatts */
2811         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2812
2813         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
2814 }
2815
2816 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2817                                          struct device_attribute *attr,
2818                                          char *buf)
2819 {
2820         return sprintf(buf, "%i\n", 0);
2821 }
2822
2823 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2824                                          struct device_attribute *attr,
2825                                          char *buf)
2826 {
2827         struct amdgpu_device *adev = dev_get_drvdata(dev);
2828         uint32_t limit = 0;
2829         ssize_t size;
2830         int r;
2831
2832         if (adev->in_gpu_reset)
2833                 return -EPERM;
2834
2835         r = pm_runtime_get_sync(adev->ddev->dev);
2836         if (r < 0) {
2837                 pm_runtime_put_autosuspend(adev->ddev->dev);
2838                 return r;
2839         }
2840
2841         if (is_support_sw_smu(adev)) {
2842                 smu_get_power_limit(&adev->smu, &limit, true);
2843                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2844         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2845                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
2846                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2847         } else {
2848                 size = snprintf(buf, PAGE_SIZE, "\n");
2849         }
2850
2851         pm_runtime_mark_last_busy(adev->ddev->dev);
2852         pm_runtime_put_autosuspend(adev->ddev->dev);
2853
2854         return size;
2855 }
2856
2857 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2858                                          struct device_attribute *attr,
2859                                          char *buf)
2860 {
2861         struct amdgpu_device *adev = dev_get_drvdata(dev);
2862         uint32_t limit = 0;
2863         ssize_t size;
2864         int r;
2865
2866         if (adev->in_gpu_reset)
2867                 return -EPERM;
2868
2869         r = pm_runtime_get_sync(adev->ddev->dev);
2870         if (r < 0) {
2871                 pm_runtime_put_autosuspend(adev->ddev->dev);
2872                 return r;
2873         }
2874
2875         if (is_support_sw_smu(adev)) {
2876                 smu_get_power_limit(&adev->smu, &limit, false);
2877                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2878         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2879                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
2880                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2881         } else {
2882                 size = snprintf(buf, PAGE_SIZE, "\n");
2883         }
2884
2885         pm_runtime_mark_last_busy(adev->ddev->dev);
2886         pm_runtime_put_autosuspend(adev->ddev->dev);
2887
2888         return size;
2889 }
2890
2891
2892 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2893                 struct device_attribute *attr,
2894                 const char *buf,
2895                 size_t count)
2896 {
2897         struct amdgpu_device *adev = dev_get_drvdata(dev);
2898         int err;
2899         u32 value;
2900
2901         if (adev->in_gpu_reset)
2902                 return -EPERM;
2903
2904         if (amdgpu_sriov_vf(adev))
2905                 return -EINVAL;
2906
2907         err = kstrtou32(buf, 10, &value);
2908         if (err)
2909                 return err;
2910
2911         value = value / 1000000; /* convert to Watt */
2912
2913
2914         err = pm_runtime_get_sync(adev->ddev->dev);
2915         if (err < 0) {
2916                 pm_runtime_put_autosuspend(adev->ddev->dev);
2917                 return err;
2918         }
2919
2920         if (is_support_sw_smu(adev))
2921                 err = smu_set_power_limit(&adev->smu, value);
2922         else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit)
2923                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
2924         else
2925                 err = -EINVAL;
2926
2927         pm_runtime_mark_last_busy(adev->ddev->dev);
2928         pm_runtime_put_autosuspend(adev->ddev->dev);
2929
2930         if (err)
2931                 return err;
2932
2933         return count;
2934 }
2935
2936 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2937                                       struct device_attribute *attr,
2938                                       char *buf)
2939 {
2940         struct amdgpu_device *adev = dev_get_drvdata(dev);
2941         uint32_t sclk;
2942         int r, size = sizeof(sclk);
2943
2944         if (adev->in_gpu_reset)
2945                 return -EPERM;
2946
2947         r = pm_runtime_get_sync(adev->ddev->dev);
2948         if (r < 0) {
2949                 pm_runtime_put_autosuspend(adev->ddev->dev);
2950                 return r;
2951         }
2952
2953         /* get the sclk */
2954         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2955                                    (void *)&sclk, &size);
2956
2957         pm_runtime_mark_last_busy(adev->ddev->dev);
2958         pm_runtime_put_autosuspend(adev->ddev->dev);
2959
2960         if (r)
2961                 return r;
2962
2963         return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
2964 }
2965
2966 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2967                                             struct device_attribute *attr,
2968                                             char *buf)
2969 {
2970         return snprintf(buf, PAGE_SIZE, "sclk\n");
2971 }
2972
2973 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2974                                       struct device_attribute *attr,
2975                                       char *buf)
2976 {
2977         struct amdgpu_device *adev = dev_get_drvdata(dev);
2978         uint32_t mclk;
2979         int r, size = sizeof(mclk);
2980
2981         if (adev->in_gpu_reset)
2982                 return -EPERM;
2983
2984         r = pm_runtime_get_sync(adev->ddev->dev);
2985         if (r < 0) {
2986                 pm_runtime_put_autosuspend(adev->ddev->dev);
2987                 return r;
2988         }
2989
2990         /* get the sclk */
2991         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
2992                                    (void *)&mclk, &size);
2993
2994         pm_runtime_mark_last_busy(adev->ddev->dev);
2995         pm_runtime_put_autosuspend(adev->ddev->dev);
2996
2997         if (r)
2998                 return r;
2999
3000         return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
3001 }
3002
3003 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
3004                                             struct device_attribute *attr,
3005                                             char *buf)
3006 {
3007         return snprintf(buf, PAGE_SIZE, "mclk\n");
3008 }
3009
3010 /**
3011  * DOC: hwmon
3012  *
3013  * The amdgpu driver exposes the following sensor interfaces:
3014  *
3015  * - GPU temperature (via the on-die sensor)
3016  *
3017  * - GPU voltage
3018  *
3019  * - Northbridge voltage (APUs only)
3020  *
3021  * - GPU power
3022  *
3023  * - GPU fan
3024  *
3025  * - GPU gfx/compute engine clock
3026  *
3027  * - GPU memory clock (dGPU only)
3028  *
3029  * hwmon interfaces for GPU temperature:
3030  *
3031  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3032  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
3033  *
3034  * - temp[1-3]_label: temperature channel label
3035  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
3036  *
3037  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3038  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3039  *
3040  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3041  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3042  *
3043  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3044  *   - these are supported on SOC15 dGPUs only
3045  *
3046  * hwmon interfaces for GPU voltage:
3047  *
3048  * - in0_input: the voltage on the GPU in millivolts
3049  *
3050  * - in1_input: the voltage on the Northbridge in millivolts
3051  *
3052  * hwmon interfaces for GPU power:
3053  *
3054  * - power1_average: average power used by the GPU in microWatts
3055  *
3056  * - power1_cap_min: minimum cap supported in microWatts
3057  *
3058  * - power1_cap_max: maximum cap supported in microWatts
3059  *
3060  * - power1_cap: selected power cap in microWatts
3061  *
3062  * hwmon interfaces for GPU fan:
3063  *
3064  * - pwm1: pulse width modulation fan level (0-255)
3065  *
3066  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3067  *
3068  * - pwm1_min: pulse width modulation fan control minimum level (0)
3069  *
3070  * - pwm1_max: pulse width modulation fan control maximum level (255)
3071  *
3072  * - fan1_min: an minimum value Unit: revolution/min (RPM)
3073  *
3074  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
3075  *
3076  * - fan1_input: fan speed in RPM
3077  *
3078  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3079  *
3080  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3081  *
3082  * hwmon interfaces for GPU clocks:
3083  *
3084  * - freq1_input: the gfx/compute clock in hertz
3085  *
3086  * - freq2_input: the memory clock in hertz
3087  *
3088  * You can use hwmon tools like sensors to view this information on your system.
3089  *
3090  */
3091
3092 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3093 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3094 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3095 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3096 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3097 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3098 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3099 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3100 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3101 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3102 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3103 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3104 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3105 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3106 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3107 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3108 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3109 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3110 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3111 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3112 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3113 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3114 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3115 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3116 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3117 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3118 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3119 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3120 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3121 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3122 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3123 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3124 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3125 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3126 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3127 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3128
3129 static struct attribute *hwmon_attributes[] = {
3130         &sensor_dev_attr_temp1_input.dev_attr.attr,
3131         &sensor_dev_attr_temp1_crit.dev_attr.attr,
3132         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3133         &sensor_dev_attr_temp2_input.dev_attr.attr,
3134         &sensor_dev_attr_temp2_crit.dev_attr.attr,
3135         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3136         &sensor_dev_attr_temp3_input.dev_attr.attr,
3137         &sensor_dev_attr_temp3_crit.dev_attr.attr,
3138         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3139         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3140         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3141         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3142         &sensor_dev_attr_temp1_label.dev_attr.attr,
3143         &sensor_dev_attr_temp2_label.dev_attr.attr,
3144         &sensor_dev_attr_temp3_label.dev_attr.attr,
3145         &sensor_dev_attr_pwm1.dev_attr.attr,
3146         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3147         &sensor_dev_attr_pwm1_min.dev_attr.attr,
3148         &sensor_dev_attr_pwm1_max.dev_attr.attr,
3149         &sensor_dev_attr_fan1_input.dev_attr.attr,
3150         &sensor_dev_attr_fan1_min.dev_attr.attr,
3151         &sensor_dev_attr_fan1_max.dev_attr.attr,
3152         &sensor_dev_attr_fan1_target.dev_attr.attr,
3153         &sensor_dev_attr_fan1_enable.dev_attr.attr,
3154         &sensor_dev_attr_in0_input.dev_attr.attr,
3155         &sensor_dev_attr_in0_label.dev_attr.attr,
3156         &sensor_dev_attr_in1_input.dev_attr.attr,
3157         &sensor_dev_attr_in1_label.dev_attr.attr,
3158         &sensor_dev_attr_power1_average.dev_attr.attr,
3159         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3160         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3161         &sensor_dev_attr_power1_cap.dev_attr.attr,
3162         &sensor_dev_attr_freq1_input.dev_attr.attr,
3163         &sensor_dev_attr_freq1_label.dev_attr.attr,
3164         &sensor_dev_attr_freq2_input.dev_attr.attr,
3165         &sensor_dev_attr_freq2_label.dev_attr.attr,
3166         NULL
3167 };
3168
3169 static umode_t hwmon_attributes_visible(struct kobject *kobj,
3170                                         struct attribute *attr, int index)
3171 {
3172         struct device *dev = kobj_to_dev(kobj);
3173         struct amdgpu_device *adev = dev_get_drvdata(dev);
3174         umode_t effective_mode = attr->mode;
3175
3176         /* under multi-vf mode, the hwmon attributes are all not supported */
3177         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
3178                 return 0;
3179
3180         /* there is no fan under pp one vf mode */
3181         if (amdgpu_sriov_is_pp_one_vf(adev) &&
3182             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3183              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3184              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3185              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3186              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3187              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3188              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3189              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3190              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3191                 return 0;
3192
3193         /* Skip fan attributes if fan is not present */
3194         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3195             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3196             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3197             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3198             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3199             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3200             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3201             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3202             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3203                 return 0;
3204
3205         /* Skip fan attributes on APU */
3206         if ((adev->flags & AMD_IS_APU) &&
3207             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3208              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3209              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3210              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3211              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3212              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3213              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3214              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3215              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3216                 return 0;
3217
3218         /* Skip limit attributes if DPM is not enabled */
3219         if (!adev->pm.dpm_enabled &&
3220             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3221              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3222              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3223              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3224              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3225              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3226              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3227              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3228              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3229              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3230              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3231                 return 0;
3232
3233         if (!is_support_sw_smu(adev)) {
3234                 /* mask fan attributes if we have no bindings for this asic to expose */
3235                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
3236                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3237                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
3238                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3239                         effective_mode &= ~S_IRUGO;
3240
3241                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
3242                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3243                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
3244                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3245                         effective_mode &= ~S_IWUSR;
3246         }
3247
3248         if (((adev->flags & AMD_IS_APU) ||
3249              adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3250              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
3251             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
3252              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3253              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
3254              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
3255                 return 0;
3256
3257         if (!is_support_sw_smu(adev)) {
3258                 /* hide max/min values if we can't both query and manage the fan */
3259                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
3260                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
3261                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3262                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3263                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3264                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3265                         return 0;
3266
3267                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3268                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3269                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3270                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3271                         return 0;
3272         }
3273
3274         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3275              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
3276             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3277              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3278                 return 0;
3279
3280         /* only APUs have vddnb */
3281         if (!(adev->flags & AMD_IS_APU) &&
3282             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3283              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3284                 return 0;
3285
3286         /* no mclk on APUs */
3287         if ((adev->flags & AMD_IS_APU) &&
3288             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3289              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3290                 return 0;
3291
3292         /* only SOC15 dGPUs support hotspot and mem temperatures */
3293         if (((adev->flags & AMD_IS_APU) ||
3294              adev->asic_type < CHIP_VEGA10) &&
3295             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3296              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3297              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
3298              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3299              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3300              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3301              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
3302              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3303              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3304              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3305              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
3306                 return 0;
3307
3308         return effective_mode;
3309 }
3310
3311 static const struct attribute_group hwmon_attrgroup = {
3312         .attrs = hwmon_attributes,
3313         .is_visible = hwmon_attributes_visible,
3314 };
3315
3316 static const struct attribute_group *hwmon_groups[] = {
3317         &hwmon_attrgroup,
3318         NULL
3319 };
3320
3321 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
3322 {
3323         struct amdgpu_device *adev =
3324                 container_of(work, struct amdgpu_device,
3325                              pm.dpm.thermal.work);
3326         /* switch to the thermal state */
3327         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
3328         int temp, size = sizeof(temp);
3329
3330         if (!adev->pm.dpm_enabled)
3331                 return;
3332
3333         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
3334                                     (void *)&temp, &size)) {
3335                 if (temp < adev->pm.dpm.thermal.min_temp)
3336                         /* switch back the user state */
3337                         dpm_state = adev->pm.dpm.user_state;
3338         } else {
3339                 if (adev->pm.dpm.thermal.high_to_low)
3340                         /* switch back the user state */
3341                         dpm_state = adev->pm.dpm.user_state;
3342         }
3343         mutex_lock(&adev->pm.mutex);
3344         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
3345                 adev->pm.dpm.thermal_active = true;
3346         else
3347                 adev->pm.dpm.thermal_active = false;
3348         adev->pm.dpm.state = dpm_state;
3349         mutex_unlock(&adev->pm.mutex);
3350
3351         amdgpu_pm_compute_clocks(adev);
3352 }
3353
3354 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
3355                                                      enum amd_pm_state_type dpm_state)
3356 {
3357         int i;
3358         struct amdgpu_ps *ps;
3359         u32 ui_class;
3360         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
3361                 true : false;
3362
3363         /* check if the vblank period is too short to adjust the mclk */
3364         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
3365                 if (amdgpu_dpm_vblank_too_short(adev))
3366                         single_display = false;
3367         }
3368
3369         /* certain older asics have a separare 3D performance state,
3370          * so try that first if the user selected performance
3371          */
3372         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
3373                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
3374         /* balanced states don't exist at the moment */
3375         if (dpm_state == POWER_STATE_TYPE_BALANCED)
3376                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
3377
3378 restart_search:
3379         /* Pick the best power state based on current conditions */
3380         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
3381                 ps = &adev->pm.dpm.ps[i];
3382                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
3383                 switch (dpm_state) {
3384                 /* user states */
3385                 case POWER_STATE_TYPE_BATTERY:
3386                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
3387                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3388                                         if (single_display)
3389                                                 return ps;
3390                                 } else
3391                                         return ps;
3392                         }
3393                         break;
3394                 case POWER_STATE_TYPE_BALANCED:
3395                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
3396                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3397                                         if (single_display)
3398                                                 return ps;
3399                                 } else
3400                                         return ps;
3401                         }
3402                         break;
3403                 case POWER_STATE_TYPE_PERFORMANCE:
3404                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
3405                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
3406                                         if (single_display)
3407                                                 return ps;
3408                                 } else
3409                                         return ps;
3410                         }
3411                         break;
3412                 /* internal states */
3413                 case POWER_STATE_TYPE_INTERNAL_UVD:
3414                         if (adev->pm.dpm.uvd_ps)
3415                                 return adev->pm.dpm.uvd_ps;
3416                         else
3417                                 break;
3418                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
3419                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3420                                 return ps;
3421                         break;
3422                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
3423                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3424                                 return ps;
3425                         break;
3426                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
3427                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3428                                 return ps;
3429                         break;
3430                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
3431                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3432                                 return ps;
3433                         break;
3434                 case POWER_STATE_TYPE_INTERNAL_BOOT:
3435                         return adev->pm.dpm.boot_ps;
3436                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
3437                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
3438                                 return ps;
3439                         break;
3440                 case POWER_STATE_TYPE_INTERNAL_ACPI:
3441                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
3442                                 return ps;
3443                         break;
3444                 case POWER_STATE_TYPE_INTERNAL_ULV:
3445                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
3446                                 return ps;
3447                         break;
3448                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
3449                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
3450                                 return ps;
3451                         break;
3452                 default:
3453                         break;
3454                 }
3455         }
3456         /* use a fallback state if we didn't match */
3457         switch (dpm_state) {
3458         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
3459                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
3460                 goto restart_search;
3461         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
3462         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
3463         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
3464                 if (adev->pm.dpm.uvd_ps) {
3465                         return adev->pm.dpm.uvd_ps;
3466                 } else {
3467                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
3468                         goto restart_search;
3469                 }
3470         case POWER_STATE_TYPE_INTERNAL_THERMAL:
3471                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
3472                 goto restart_search;
3473         case POWER_STATE_TYPE_INTERNAL_ACPI:
3474                 dpm_state = POWER_STATE_TYPE_BATTERY;
3475                 goto restart_search;
3476         case POWER_STATE_TYPE_BATTERY:
3477         case POWER_STATE_TYPE_BALANCED:
3478         case POWER_STATE_TYPE_INTERNAL_3DPERF:
3479                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
3480                 goto restart_search;
3481         default:
3482                 break;
3483         }
3484
3485         return NULL;
3486 }
3487
3488 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
3489 {
3490         struct amdgpu_ps *ps;
3491         enum amd_pm_state_type dpm_state;
3492         int ret;
3493         bool equal = false;
3494
3495         /* if dpm init failed */
3496         if (!adev->pm.dpm_enabled)
3497                 return;
3498
3499         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
3500                 /* add other state override checks here */
3501                 if ((!adev->pm.dpm.thermal_active) &&
3502                     (!adev->pm.dpm.uvd_active))
3503                         adev->pm.dpm.state = adev->pm.dpm.user_state;
3504         }
3505         dpm_state = adev->pm.dpm.state;
3506
3507         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
3508         if (ps)
3509                 adev->pm.dpm.requested_ps = ps;
3510         else
3511                 return;
3512
3513         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
3514                 printk("switching from power state:\n");
3515                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
3516                 printk("switching to power state:\n");
3517                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
3518         }
3519
3520         /* update whether vce is active */
3521         ps->vce_active = adev->pm.dpm.vce_active;
3522         if (adev->powerplay.pp_funcs->display_configuration_changed)
3523                 amdgpu_dpm_display_configuration_changed(adev);
3524
3525         ret = amdgpu_dpm_pre_set_power_state(adev);
3526         if (ret)
3527                 return;
3528
3529         if (adev->powerplay.pp_funcs->check_state_equal) {
3530                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
3531                         equal = false;
3532         }
3533
3534         if (equal)
3535                 return;
3536
3537         amdgpu_dpm_set_power_state(adev);
3538         amdgpu_dpm_post_set_power_state(adev);
3539
3540         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
3541         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
3542
3543         if (adev->powerplay.pp_funcs->force_performance_level) {
3544                 if (adev->pm.dpm.thermal_active) {
3545                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
3546                         /* force low perf level for thermal */
3547                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
3548                         /* save the user's level */
3549                         adev->pm.dpm.forced_level = level;
3550                 } else {
3551                         /* otherwise, user selected level */
3552                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
3553                 }
3554         }
3555 }
3556
3557 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
3558 {
3559         int ret = 0;
3560
3561         if (adev->family == AMDGPU_FAMILY_SI) {
3562                 if (enable) {
3563                         mutex_lock(&adev->pm.mutex);
3564                         adev->pm.dpm.uvd_active = true;
3565                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
3566                         mutex_unlock(&adev->pm.mutex);
3567                 } else {
3568                         mutex_lock(&adev->pm.mutex);
3569                         adev->pm.dpm.uvd_active = false;
3570                         mutex_unlock(&adev->pm.mutex);
3571                 }
3572
3573                 amdgpu_pm_compute_clocks(adev);
3574         } else {
3575                 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
3576                 if (ret)
3577                         DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
3578                                   enable ? "enable" : "disable", ret);
3579
3580                 /* enable/disable Low Memory PState for UVD (4k videos) */
3581                 if (adev->asic_type == CHIP_STONEY &&
3582                         adev->uvd.decode_image_width >= WIDTH_4K) {
3583                         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
3584
3585                         if (hwmgr && hwmgr->hwmgr_func &&
3586                             hwmgr->hwmgr_func->update_nbdpm_pstate)
3587                                 hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
3588                                                                        !enable,
3589                                                                        true);
3590                 }
3591         }
3592 }
3593
3594 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
3595 {
3596         int ret = 0;
3597
3598         if (adev->family == AMDGPU_FAMILY_SI) {
3599                 if (enable) {
3600                         mutex_lock(&adev->pm.mutex);
3601                         adev->pm.dpm.vce_active = true;
3602                         /* XXX select vce level based on ring/task */
3603                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
3604                         mutex_unlock(&adev->pm.mutex);
3605                 } else {
3606                         mutex_lock(&adev->pm.mutex);
3607                         adev->pm.dpm.vce_active = false;
3608                         mutex_unlock(&adev->pm.mutex);
3609                 }
3610
3611                 amdgpu_pm_compute_clocks(adev);
3612         } else {
3613                 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
3614                 if (ret)
3615                         DRM_ERROR("Dpm %s vce failed, ret = %d. \n",
3616                                   enable ? "enable" : "disable", ret);
3617         }
3618 }
3619
3620 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
3621 {
3622         int i;
3623
3624         if (adev->powerplay.pp_funcs->print_power_state == NULL)
3625                 return;
3626
3627         for (i = 0; i < adev->pm.dpm.num_ps; i++)
3628                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
3629
3630 }
3631
3632 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)
3633 {
3634         int ret = 0;
3635
3636         ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable);
3637         if (ret)
3638                 DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n",
3639                           enable ? "enable" : "disable", ret);
3640 }
3641
3642 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)
3643 {
3644         int r;
3645
3646         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
3647                 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
3648                 if (r) {
3649                         pr_err("smu firmware loading failed\n");
3650                         return r;
3651                 }
3652                 *smu_version = adev->pm.fw_version;
3653         }
3654         return 0;
3655 }
3656
3657 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3658 {
3659         int ret;
3660         uint32_t mask = 0;
3661
3662         if (adev->pm.sysfs_initialized)
3663                 return 0;
3664
3665         if (adev->pm.dpm_enabled == 0)
3666                 return 0;
3667
3668         INIT_LIST_HEAD(&adev->pm.pm_attr_list);
3669
3670         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3671                                                                    DRIVER_NAME, adev,
3672                                                                    hwmon_groups);
3673         if (IS_ERR(adev->pm.int_hwmon_dev)) {
3674                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3675                 dev_err(adev->dev,
3676                         "Unable to register hwmon device: %d\n", ret);
3677                 return ret;
3678         }
3679
3680         switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
3681         case SRIOV_VF_MODE_ONE_VF:
3682                 mask = ATTR_FLAG_ONEVF;
3683                 break;
3684         case SRIOV_VF_MODE_MULTI_VF:
3685                 mask = 0;
3686                 break;
3687         case SRIOV_VF_MODE_BARE_METAL:
3688         default:
3689                 mask = ATTR_FLAG_MASK_ALL;
3690                 break;
3691         }
3692
3693         ret = amdgpu_device_attr_create_groups(adev,
3694                                                amdgpu_device_attrs,
3695                                                ARRAY_SIZE(amdgpu_device_attrs),
3696                                                mask,
3697                                                &adev->pm.pm_attr_list);
3698         if (ret)
3699                 return ret;
3700
3701         adev->pm.sysfs_initialized = true;
3702
3703         return 0;
3704 }
3705
3706 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3707 {
3708         if (adev->pm.dpm_enabled == 0)
3709                 return;
3710
3711         if (adev->pm.int_hwmon_dev)
3712                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3713
3714         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
3715 }
3716
3717 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
3718 {
3719         int i = 0;
3720
3721         if (!adev->pm.dpm_enabled)
3722                 return;
3723
3724         if (adev->mode_info.num_crtc)
3725                 amdgpu_display_bandwidth_update(adev);
3726
3727         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3728                 struct amdgpu_ring *ring = adev->rings[i];
3729                 if (ring && ring->sched.ready)
3730                         amdgpu_fence_wait_empty(ring);
3731         }
3732
3733         if (is_support_sw_smu(adev)) {
3734                 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
3735                 smu_handle_task(&adev->smu,
3736                                 smu_dpm->dpm_level,
3737                                 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
3738                                 true);
3739         } else {
3740                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
3741                         if (!amdgpu_device_has_dc_support(adev)) {
3742                                 mutex_lock(&adev->pm.mutex);
3743                                 amdgpu_dpm_get_active_displays(adev);
3744                                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
3745                                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
3746                                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
3747                                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
3748                                 if (adev->pm.pm_display_cfg.vrefresh > 120)
3749                                         adev->pm.pm_display_cfg.min_vblank_time = 0;
3750                                 if (adev->powerplay.pp_funcs->display_configuration_change)
3751                                         adev->powerplay.pp_funcs->display_configuration_change(
3752                                                                         adev->powerplay.pp_handle,
3753                                                                         &adev->pm.pm_display_cfg);
3754                                 mutex_unlock(&adev->pm.mutex);
3755                         }
3756                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
3757                 } else {
3758                         mutex_lock(&adev->pm.mutex);
3759                         amdgpu_dpm_get_active_displays(adev);
3760                         amdgpu_dpm_change_power_state_locked(adev);
3761                         mutex_unlock(&adev->pm.mutex);
3762                 }
3763         }
3764 }
3765
3766 /*
3767  * Debugfs info
3768  */
3769 #if defined(CONFIG_DEBUG_FS)
3770
3771 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3772 {
3773         uint32_t value;
3774         uint64_t value64;
3775         uint32_t query = 0;
3776         int size;
3777
3778         /* GPU Clocks */
3779         size = sizeof(value);
3780         seq_printf(m, "GFX Clocks and Power:\n");
3781         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3782                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3783         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3784                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3785         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3786                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3787         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3788                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3789         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3790                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3791         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3792                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3793         size = sizeof(uint32_t);
3794         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3795                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3796         size = sizeof(value);
3797         seq_printf(m, "\n");
3798
3799         /* GPU Temp */
3800         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3801                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3802
3803         /* GPU Load */
3804         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3805                 seq_printf(m, "GPU Load: %u %%\n", value);
3806         /* MEM Load */
3807         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3808                 seq_printf(m, "MEM Load: %u %%\n", value);
3809
3810         seq_printf(m, "\n");
3811
3812         /* SMC feature mask */
3813         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3814                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3815
3816         if (adev->asic_type > CHIP_VEGA20) {
3817                 /* VCN clocks */
3818                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3819                         if (!value) {
3820                                 seq_printf(m, "VCN: Disabled\n");
3821                         } else {
3822                                 seq_printf(m, "VCN: Enabled\n");
3823                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3824                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3825                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3826                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3827                         }
3828                 }
3829                 seq_printf(m, "\n");
3830         } else {
3831                 /* UVD clocks */
3832                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3833                         if (!value) {
3834                                 seq_printf(m, "UVD: Disabled\n");
3835                         } else {
3836                                 seq_printf(m, "UVD: Enabled\n");
3837                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3838                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3839                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3840                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3841                         }
3842                 }
3843                 seq_printf(m, "\n");
3844
3845                 /* VCE clocks */
3846                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3847                         if (!value) {
3848                                 seq_printf(m, "VCE: Disabled\n");
3849                         } else {
3850                                 seq_printf(m, "VCE: Enabled\n");
3851                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3852                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3853                         }
3854                 }
3855         }
3856
3857         return 0;
3858 }
3859
3860 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3861 {
3862         int i;
3863
3864         for (i = 0; clocks[i].flag; i++)
3865                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3866                            (flags & clocks[i].flag) ? "On" : "Off");
3867 }
3868
3869 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
3870 {
3871         struct drm_info_node *node = (struct drm_info_node *) m->private;
3872         struct drm_device *dev = node->minor->dev;
3873         struct amdgpu_device *adev = dev->dev_private;
3874         u32 flags = 0;
3875         int r;
3876
3877         if (adev->in_gpu_reset)
3878                 return -EPERM;
3879
3880         r = pm_runtime_get_sync(dev->dev);
3881         if (r < 0) {
3882                 pm_runtime_put_autosuspend(dev->dev);
3883                 return r;
3884         }
3885
3886         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3887         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3888         amdgpu_parse_cg_state(m, flags);
3889         seq_printf(m, "\n");
3890
3891         if (!adev->pm.dpm_enabled) {
3892                 seq_printf(m, "dpm not enabled\n");
3893                 pm_runtime_mark_last_busy(dev->dev);
3894                 pm_runtime_put_autosuspend(dev->dev);
3895                 return 0;
3896         }
3897
3898         if (!is_support_sw_smu(adev) &&
3899             adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3900                 mutex_lock(&adev->pm.mutex);
3901                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3902                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3903                 else
3904                         seq_printf(m, "Debugfs support not implemented for this asic\n");
3905                 mutex_unlock(&adev->pm.mutex);
3906                 r = 0;
3907         } else {
3908                 r = amdgpu_debugfs_pm_info_pp(m, adev);
3909         }
3910
3911         pm_runtime_mark_last_busy(dev->dev);
3912         pm_runtime_put_autosuspend(dev->dev);
3913
3914         return r;
3915 }
3916
3917 static const struct drm_info_list amdgpu_pm_info_list[] = {
3918         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
3919 };
3920 #endif
3921
3922 int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3923 {
3924 #if defined(CONFIG_DEBUG_FS)
3925         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
3926 #else
3927         return 0;
3928 #endif
3929 }