drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/amdgpu_drm.h>
  25 #include "amdgpu.h"
  26 #include "atomfirmware.h"
  27 #include "amdgpu_atomfirmware.h"
  28 #include "atom.h"
  29 #include "atombios.h"
  30 #include "soc15_hw_ip.h"
  31
  32 bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
  33 {
  34         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  35                                                 firmwareinfo);
  36         uint16_t data_offset;
  37
  38         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  39                                           NULL, NULL, &data_offset)) {
  40                 struct atom_firmware_info_v3_1 *firmware_info =
  41                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  42                                                            data_offset);
  43
  44                 if (le32_to_cpu(firmware_info->firmware_capability) &
  45                     ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION)
  46                         return true;
  47         }
  48         return false;
  49 }
  50
  51 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
  52 {
  53         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  54                                                 firmwareinfo);
  55         uint16_t data_offset;
  56
  57         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  58                                           NULL, NULL, &data_offset)) {
  59                 struct atom_firmware_info_v3_1 *firmware_info =
  60                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  61                                                            data_offset);
  62
  63                 adev->bios_scratch_reg_offset =
  64                         le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
  65         }
  66 }
  67
  68 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
  69 {
  70         struct atom_context *ctx = adev->mode_info.atom_context;
  71         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  72                                                 vram_usagebyfirmware);
  73         struct vram_usagebyfirmware_v2_1 *      firmware_usage;
  74         uint32_t start_addr, size;
  75         uint16_t data_offset;
  76         int usage_bytes = 0;
  77
  78         if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
  79                 firmware_usage = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
  80                 DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",
  81                           le32_to_cpu(firmware_usage->start_address_in_kb),
  82                           le16_to_cpu(firmware_usage->used_by_firmware_in_kb),
  83                           le16_to_cpu(firmware_usage->used_by_driver_in_kb));
  84
  85                 start_addr = le32_to_cpu(firmware_usage->start_address_in_kb);
  86                 size = le16_to_cpu(firmware_usage->used_by_firmware_in_kb);
  87
  88                 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
  89                         (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
  90                         ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
  91                         /* Firmware request VRAM reservation for SR-IOV */
  92                         adev->fw_vram_usage.start_offset = (start_addr &
  93                                 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
  94                         adev->fw_vram_usage.size = size << 10;
  95                         /* Use the default scratch size */
  96                         usage_bytes = 0;
  97                 } else {
  98                         usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) << 10;
  99                 }
 100         }
 101         ctx->scratch_size_bytes = 0;
 102         if (usage_bytes == 0)
 103                 usage_bytes = 20 * 1024;
 104         /* allocate some scratch memory */
 105         ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
 106         if (!ctx->scratch)
 107                 return -ENOMEM;
 108         ctx->scratch_size_bytes = usage_bytes;
 109         return 0;
 110 }
 111
 112 union igp_info {
 113         struct atom_integrated_system_info_v1_11 v11;
 114 };
 115
 116 union umc_info {
 117         struct atom_umc_info_v3_1 v31;
 118 };
 119
 120 union vram_info {
 121         struct atom_vram_info_header_v2_3 v23;
 122         struct atom_vram_info_header_v2_4 v24;
 123         struct atom_vram_info_header_v2_5 v25;
 124 };
 125
 126 union vram_module {
 127         struct atom_vram_module_v9 v9;
 128         struct atom_vram_module_v10 v10;
 129         struct atom_vram_module_v11 v11;
 130 };
 131
 132 static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
 133                                               int atom_mem_type)
 134 {
 135         int vram_type;
 136
 137         if (adev->flags & AMD_IS_APU) {
 138                 switch (atom_mem_type) {
 139                 case Ddr2MemType:
 140                 case LpDdr2MemType:
 141                         vram_type = AMDGPU_VRAM_TYPE_DDR2;
 142                         break;
 143                 case Ddr3MemType:
 144                 case LpDdr3MemType:
 145                         vram_type = AMDGPU_VRAM_TYPE_DDR3;
 146                         break;
 147                 case Ddr4MemType:
 148                 case LpDdr4MemType:
 149                         vram_type = AMDGPU_VRAM_TYPE_DDR4;
 150                         break;
 151                 default:
 152                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 153                         break;
 154                 }
 155         } else {
 156                 switch (atom_mem_type) {
 157                 case ATOM_DGPU_VRAM_TYPE_GDDR5:
 158                         vram_type = AMDGPU_VRAM_TYPE_GDDR5;
 159                         break;
 160                 case ATOM_DGPU_VRAM_TYPE_HBM2:
 161                         vram_type = AMDGPU_VRAM_TYPE_HBM;
 162                         break;
 163                 case ATOM_DGPU_VRAM_TYPE_GDDR6:
 164                         vram_type = AMDGPU_VRAM_TYPE_GDDR6;
 165                         break;
 166                 default:
 167                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 168                         break;
 169                 }
 170         }
 171
 172         return vram_type;
 173 }
 174
 175
 176 int
 177 amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
 178                                   int *vram_width, int *vram_type,
 179                                   int *vram_vendor)
 180 {
 181         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 182         int index, i = 0;
 183         u16 data_offset, size;
 184         union igp_info *igp_info;
 185         union vram_info *vram_info;
 186         union vram_module *vram_module;
 187         u8 frev, crev;
 188         u8 mem_type;
 189         u8 mem_vendor;
 190         u32 mem_channel_number;
 191         u32 mem_channel_width;
 192         u32 module_id;
 193
 194         if (adev->flags & AMD_IS_APU)
 195                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 196                                                     integratedsysteminfo);
 197         else
 198                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 199                                                     vram_info);
 200
 201         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 202                                           index, &size,
 203                                           &frev, &crev, &data_offset)) {
 204                 if (adev->flags & AMD_IS_APU) {
 205                         igp_info = (union igp_info *)
 206                                 (mode_info->atom_context->bios + data_offset);
 207                         switch (crev) {
 208                         case 11:
 209                                 mem_channel_number = igp_info->v11.umachannelnumber;
 210                                 /* channel width is 64 */
 211                                 if (vram_width)
 212                                         *vram_width = mem_channel_number * 64;
 213                                 mem_type = igp_info->v11.memorytype;
 214                                 if (vram_type)
 215                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 216                                 break;
 217                         default:
 218                                 return -EINVAL;
 219                         }
 220                 } else {
 221                         vram_info = (union vram_info *)
 222                                 (mode_info->atom_context->bios + data_offset);
 223                         module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
 224                         switch (crev) {
 225                         case 3:
 226                                 if (module_id > vram_info->v23.vram_module_num)
 227                                         module_id = 0;
 228                                 vram_module = (union vram_module *)vram_info->v23.vram_module;
 229                                 while (i < module_id) {
 230                                         vram_module = (union vram_module *)
 231                                                 ((u8 *)vram_module + vram_module->v9.vram_module_size);
 232                                         i++;
 233                                 }
 234                                 mem_type = vram_module->v9.memory_type;
 235                                 if (vram_type)
 236                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 237                                 mem_channel_number = vram_module->v9.channel_num;
 238                                 mem_channel_width = vram_module->v9.channel_width;
 239                                 if (vram_width)
 240                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 241                                 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 242                                 if (vram_vendor)
 243                                         *vram_vendor = mem_vendor;
 244                                 break;
 245                         case 4:
 246                                 if (module_id > vram_info->v24.vram_module_num)
 247                                         module_id = 0;
 248                                 vram_module = (union vram_module *)vram_info->v24.vram_module;
 249                                 while (i < module_id) {
 250                                         vram_module = (union vram_module *)
 251                                                 ((u8 *)vram_module + vram_module->v10.vram_module_size);
 252                                         i++;
 253                                 }
 254                                 mem_type = vram_module->v10.memory_type;
 255                                 if (vram_type)
 256                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 257                                 mem_channel_number = vram_module->v10.channel_num;
 258                                 mem_channel_width = vram_module->v10.channel_width;
 259                                 if (vram_width)
 260                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 261                                 mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
 262                                 if (vram_vendor)
 263                                         *vram_vendor = mem_vendor;
 264                                 break;
 265                         case 5:
 266                                 if (module_id > vram_info->v25.vram_module_num)
 267                                         module_id = 0;
 268                                 vram_module = (union vram_module *)vram_info->v25.vram_module;
 269                                 while (i < module_id) {
 270                                         vram_module = (union vram_module *)
 271                                                 ((u8 *)vram_module + vram_module->v11.vram_module_size);
 272                                         i++;
 273                                 }
 274                                 mem_type = vram_module->v11.memory_type;
 275                                 if (vram_type)
 276                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 277                                 mem_channel_number = vram_module->v11.channel_num;
 278                                 mem_channel_width = vram_module->v11.channel_width;
 279                                 if (vram_width)
 280                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 281                                 mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
 282                                 if (vram_vendor)
 283                                         *vram_vendor = mem_vendor;
 284                                 break;
 285                         default:
 286                                 return -EINVAL;
 287                         }
 288                 }
 289
 290         }
 291
 292         return 0;
 293 }
 294
 295 /*
 296  * Return true if vbios enabled ecc by default, if umc info table is available
 297  * or false if ecc is not enabled or umc info table is not available
 298  */
 299 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
 300 {
 301         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 302         int index;
 303         u16 data_offset, size;
 304         union umc_info *umc_info;
 305         u8 frev, crev;
 306         bool ecc_default_enabled = false;
 307
 308         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 309                         umc_info);
 310
 311         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 312                                 index, &size, &frev, &crev, &data_offset)) {
 313                 /* support umc_info 3.1+ */
 314                 if ((frev == 3 && crev >= 1) || (frev > 3)) {
 315                         umc_info = (union umc_info *)
 316                                 (mode_info->atom_context->bios + data_offset);
 317                         ecc_default_enabled =
 318                                 (le32_to_cpu(umc_info->v31.umc_config) &
 319                                  UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 320                 }
 321         }
 322
 323         return ecc_default_enabled;
 324 }
 325
 326 union firmware_info {
 327         struct atom_firmware_info_v3_1 v31;
 328         struct atom_firmware_info_v3_2 v32;
 329         struct atom_firmware_info_v3_3 v33;
 330         struct atom_firmware_info_v3_4 v34;
 331 };
 332
 333 /*
 334  * Return true if vbios supports sram ecc or false if not
 335  */
 336 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
 337 {
 338         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 339         int index;
 340         u16 data_offset, size;
 341         union firmware_info *firmware_info;
 342         u8 frev, crev;
 343         bool sram_ecc_supported = false;
 344
 345         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 346                         firmwareinfo);
 347
 348         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
 349                                 index, &size, &frev, &crev, &data_offset)) {
 350                 /* support firmware_info 3.1 + */
 351                 if ((frev == 3 && crev >=1) || (frev > 3)) {
 352                         firmware_info = (union firmware_info *)
 353                                 (mode_info->atom_context->bios + data_offset);
 354                         sram_ecc_supported =
 355                                 (le32_to_cpu(firmware_info->v31.firmware_capability) &
 356                                  ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
 357                 }
 358         }
 359
 360         return sram_ecc_supported;
 361 }
 362
 363 union smu_info {
 364         struct atom_smu_info_v3_1 v31;
 365 };
 366
 367 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
 368 {
 369         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 370         struct amdgpu_pll *spll = &adev->clock.spll;
 371         struct amdgpu_pll *mpll = &adev->clock.mpll;
 372         uint8_t frev, crev;
 373         uint16_t data_offset;
 374         int ret = -EINVAL, index;
 375
 376         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 377                                             firmwareinfo);
 378         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 379                                    &frev, &crev, &data_offset)) {
 380                 union firmware_info *firmware_info =
 381                         (union firmware_info *)(mode_info->atom_context->bios +
 382                                                 data_offset);
 383
 384                 adev->clock.default_sclk =
 385                         le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
 386                 adev->clock.default_mclk =
 387                         le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
 388
 389                 adev->pm.current_sclk = adev->clock.default_sclk;
 390                 adev->pm.current_mclk = adev->clock.default_mclk;
 391
 392                 /* not technically a clock, but... */
 393                 adev->mode_info.firmware_flags =
 394                         le32_to_cpu(firmware_info->v31.firmware_capability);
 395
 396                 ret = 0;
 397         }
 398
 399         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 400                                             smu_info);
 401         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 402                                    &frev, &crev, &data_offset)) {
 403                 union smu_info *smu_info =
 404                         (union smu_info *)(mode_info->atom_context->bios +
 405                                            data_offset);
 406
 407                 /* system clock */
 408                 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
 409
 410                 spll->reference_div = 0;
 411                 spll->min_post_div = 1;
 412                 spll->max_post_div = 1;
 413                 spll->min_ref_div = 2;
 414                 spll->max_ref_div = 0xff;
 415                 spll->min_feedback_div = 4;
 416                 spll->max_feedback_div = 0xff;
 417                 spll->best_vco = 0;
 418
 419                 ret = 0;
 420         }
 421
 422         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 423                                             umc_info);
 424         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 425                                    &frev, &crev, &data_offset)) {
 426                 union umc_info *umc_info =
 427                         (union umc_info *)(mode_info->atom_context->bios +
 428                                            data_offset);
 429
 430                 /* memory clock */
 431                 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
 432
 433                 mpll->reference_div = 0;
 434                 mpll->min_post_div = 1;
 435                 mpll->max_post_div = 1;
 436                 mpll->min_ref_div = 2;
 437                 mpll->max_ref_div = 0xff;
 438                 mpll->min_feedback_div = 4;
 439                 mpll->max_feedback_div = 0xff;
 440                 mpll->best_vco = 0;
 441
 442                 ret = 0;
 443         }
 444
 445         return ret;
 446 }
 447
 448 union gfx_info {
 449         struct  atom_gfx_info_v2_4 v24;
 450 };
 451
 452 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
 453 {
 454         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 455         int index;
 456         uint8_t frev, crev;
 457         uint16_t data_offset;
 458
 459         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 460                                             gfx_info);
 461         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 462                                    &frev, &crev, &data_offset)) {
 463                 union gfx_info *gfx_info = (union gfx_info *)
 464                         (mode_info->atom_context->bios + data_offset);
 465                 switch (crev) {
 466                 case 4:
 467                         adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
 468                         adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
 469                         adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
 470                         adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
 471                         adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
 472                         adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
 473                         adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
 474                         adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
 475                         adev->gfx.config.gs_prim_buffer_depth =
 476                                 le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
 477                         adev->gfx.config.double_offchip_lds_buf =
 478                                 gfx_info->v24.gc_double_offchip_lds_buffer;
 479                         adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
 480                         adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
 481                         adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
 482                         adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
 483                         return 0;
 484                 default:
 485                         return -EINVAL;
 486                 }
 487
 488         }
 489         return -EINVAL;
 490 }
 491
 492 /*
 493  * Check if VBIOS supports GDDR6 training data save/restore
 494  */
 495 static bool gddr6_mem_train_vbios_support(struct amdgpu_device *adev)
 496 {
 497         uint16_t data_offset;
 498         int index;
 499
 500         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 501                                             firmwareinfo);
 502         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
 503                                           NULL, NULL, &data_offset)) {
 504                 struct atom_firmware_info_v3_1 *firmware_info =
 505                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
 506                                                            data_offset);
 507
 508                 DRM_DEBUG("atom firmware capability:0x%08x.\n",
 509                           le32_to_cpu(firmware_info->firmware_capability));
 510
 511                 if (le32_to_cpu(firmware_info->firmware_capability) &
 512                     ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING)
 513                         return true;
 514         }
 515
 516         return false;
 517 }
 518
 519 int amdgpu_mem_train_support(struct amdgpu_device *adev)
 520 {
 521         int ret;
 522         uint32_t major, minor, revision, hw_v;
 523
 524         if (gddr6_mem_train_vbios_support(adev)) {
 525                 amdgpu_discovery_get_ip_version(adev, MP0_HWID, &major, &minor, &revision);
 526                 hw_v = HW_REV(major, minor, revision);
 527                 /*
 528                  * treat 0 revision as a special case since register for MP0 and MMHUB is missing
 529                  * for some Navi10 A0, preventing driver from discovering the hwip information since
 530                  * none of the functions will be initialized, it should not cause any problems
 531                  */
 532                 switch (hw_v) {
 533                 case HW_REV(11, 0, 0):
 534                 case HW_REV(11, 0, 5):
 535                 case HW_REV(11, 0, 7):
 536                         ret = 1;
 537                         break;
 538                 default:
 539                         DRM_ERROR("memory training vbios supports but psp hw(%08x)"
 540                                   " doesn't support!\n", hw_v);
 541                         ret = -1;
 542                         break;
 543                 }
 544         } else {
 545                 ret = 0;
 546                 hw_v = -1;
 547         }
 548
 549
 550         DRM_DEBUG("mp0 hw_v %08x, ret:%d.\n", hw_v, ret);
 551         return ret;
 552 }
 553
 554 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
 555 {
 556         struct atom_context *ctx = adev->mode_info.atom_context;
 557         union firmware_info *firmware_info;
 558         int index;
 559         u16 data_offset, size;
 560         u8 frev, crev;
 561         int fw_reserved_fb_size;
 562
 563         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 564                         firmwareinfo);
 565
 566         if (!amdgpu_atom_parse_data_header(ctx, index, &size,
 567                                 &frev, &crev, &data_offset))
 568                 /* fail to parse data_header */
 569                 return 0;
 570
 571         firmware_info = (union firmware_info *)(ctx->bios + data_offset);
 572
 573         if (frev !=3)
 574                 return -EINVAL;
 575
 576         switch (crev) {
 577         case 4:
 578                 fw_reserved_fb_size =
 579                         (firmware_info->v34.fw_reserved_size_in_kb << 10);
 580                 break;
 581         default:
 582                 fw_reserved_fb_size = 0;
 583                 break;
 584         }
 585
 586         return fw_reserved_fb_size;
 587 }