drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29
  30 #include "sdma0/sdma0_4_0_offset.h"
  31 #include "sdma0/sdma0_4_0_sh_mask.h"
  32 #include "sdma1/sdma1_4_0_offset.h"
  33 #include "sdma1/sdma1_4_0_sh_mask.h"
  34 #include "hdp/hdp_4_0_offset.h"
  35 #include "sdma0/sdma0_4_1_default.h"
  36
  37 #include "soc15_common.h"
  38 #include "soc15.h"
  39 #include "vega10_sdma_pkt_open.h"
  40
  41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
  42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
  43
  44 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
  45 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
  46 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
  47 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
  48 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
  50 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
  51
  52 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
  53 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
  54
  55 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
  56 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
  57 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  58 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  59
  60 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
  61         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
  62         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
  63         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
  64         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  65         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
  66         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  67         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
  68         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
  69         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  70         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
  71         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  72         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
  73         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
  74         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
  75         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
  76         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
  77         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  78         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
  79         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  80         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
  81         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
  82         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  83         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
  84         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  85         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
  86         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
  87 };
  88
  89 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
  90         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
  91         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
  92         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
  93         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)
  94 };
  95
  96 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
  97         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
  98         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
  99         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
 100         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001)
 101 };
 102
 103 static const struct soc15_reg_golden golden_settings_sdma_4_1[] =
 104 {
 105         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 106         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 107         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
 108         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 109         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
 110         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
 111         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 112         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
 113         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 114         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 115         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
 116 };
 117
 118 static const struct soc15_reg_golden golden_settings_sdma_4_2[] =
 119 {
 120         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 121         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 122         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 123         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 124         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 125         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 126         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 127         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 128         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 129         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 130         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
 131         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 132         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 133         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 134         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 135         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 136         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 137         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0)
 138 };
 139
 140 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
 141 {
 142         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
 143         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
 144 };
 145
 146 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
 147                 u32 instance, u32 offset)
 148 {
 149         return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) :
 150                         (adev->reg_offset[SDMA1_HWIP][0][0] + offset));
 151 }
 152
 153 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
 154 {
 155         switch (adev->asic_type) {
 156         case CHIP_VEGA10:
 157                 soc15_program_register_sequence(adev,
 158                                                  golden_settings_sdma_4,
 159                                                  ARRAY_SIZE(golden_settings_sdma_4));
 160                 soc15_program_register_sequence(adev,
 161                                                  golden_settings_sdma_vg10,
 162                                                  ARRAY_SIZE(golden_settings_sdma_vg10));
 163                 break;
 164         case CHIP_VEGA12:
 165                 soc15_program_register_sequence(adev,
 166                                                 golden_settings_sdma_4,
 167                                                 ARRAY_SIZE(golden_settings_sdma_4));
 168                 soc15_program_register_sequence(adev,
 169                                                 golden_settings_sdma_vg12,
 170                                                 ARRAY_SIZE(golden_settings_sdma_vg12));
 171                 break;
 172         case CHIP_VEGA20:
 173                 soc15_program_register_sequence(adev,
 174                                                 golden_settings_sdma_4_2,
 175                                                 ARRAY_SIZE(golden_settings_sdma_4_2));
 176                 break;
 177         case CHIP_RAVEN:
 178                 soc15_program_register_sequence(adev,
 179                                                  golden_settings_sdma_4_1,
 180                                                  ARRAY_SIZE(golden_settings_sdma_4_1));
 181                 soc15_program_register_sequence(adev,
 182                                                  golden_settings_sdma_rv1,
 183                                                  ARRAY_SIZE(golden_settings_sdma_rv1));
 184                 break;
 185         default:
 186                 break;
 187         }
 188 }
 189
 190 /**
 191  * sdma_v4_0_init_microcode - load ucode images from disk
 192  *
 193  * @adev: amdgpu_device pointer
 194  *
 195  * Use the firmware interface to load the ucode images into
 196  * the driver (not loaded into hw).
 197  * Returns 0 on success, error on failure.
 198  */
 199
 200 // emulation only, won't work on real chip
 201 // vega10 real chip need to use PSP to load firmware
 202 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
 203 {
 204         const char *chip_name;
 205         char fw_name[30];
 206         int err = 0, i;
 207         struct amdgpu_firmware_info *info = NULL;
 208         const struct common_firmware_header *header = NULL;
 209         const struct sdma_firmware_header_v1_0 *hdr;
 210
 211         DRM_DEBUG("\n");
 212
 213         switch (adev->asic_type) {
 214         case CHIP_VEGA10:
 215                 chip_name = "vega10";
 216                 break;
 217         case CHIP_VEGA12:
 218                 chip_name = "vega12";
 219                 break;
 220         case CHIP_VEGA20:
 221                 chip_name = "vega20";
 222                 break;
 223         case CHIP_RAVEN:
 224                 chip_name = "raven";
 225                 break;
 226         default:
 227                 BUG();
 228         }
 229
 230         for (i = 0; i < adev->sdma.num_instances; i++) {
 231                 if (i == 0)
 232                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 233                 else
 234                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 235                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 236                 if (err)
 237                         goto out;
 238                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 239                 if (err)
 240                         goto out;
 241                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 242                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 243                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 244                 if (adev->sdma.instance[i].feature_version >= 20)
 245                         adev->sdma.instance[i].burst_nop = true;
 246                 DRM_DEBUG("psp_load == '%s'\n",
 247                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 248
 249                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 250                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 251                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 252                         info->fw = adev->sdma.instance[i].fw;
 253                         header = (const struct common_firmware_header *)info->fw->data;
 254                         adev->firmware.fw_size +=
 255                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 256                 }
 257         }
 258 out:
 259         if (err) {
 260                 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
 261                 for (i = 0; i < adev->sdma.num_instances; i++) {
 262                         release_firmware(adev->sdma.instance[i].fw);
 263                         adev->sdma.instance[i].fw = NULL;
 264                 }
 265         }
 266         return err;
 267 }
 268
 269 /**
 270  * sdma_v4_0_ring_get_rptr - get the current read pointer
 271  *
 272  * @ring: amdgpu ring pointer
 273  *
 274  * Get the current rptr from the hardware (VEGA10+).
 275  */
 276 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
 277 {
 278         u64 *rptr;
 279
 280         /* XXX check if swapping is necessary on BE */
 281         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 282
 283         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 284         return ((*rptr) >> 2);
 285 }
 286
 287 /**
 288  * sdma_v4_0_ring_get_wptr - get the current write pointer
 289  *
 290  * @ring: amdgpu ring pointer
 291  *
 292  * Get the current wptr from the hardware (VEGA10+).
 293  */
 294 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
 295 {
 296         struct amdgpu_device *adev = ring->adev;
 297         u64 wptr;
 298
 299         if (ring->use_doorbell) {
 300                 /* XXX check if swapping is necessary on BE */
 301                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 302                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 303         } else {
 304                 u32 lowbit, highbit;
 305
 306                 lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
 307                 highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
 308
 309                 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
 310                                 ring->me, highbit, lowbit);
 311                 wptr = highbit;
 312                 wptr = wptr << 32;
 313                 wptr |= lowbit;
 314         }
 315
 316         return wptr >> 2;
 317 }
 318
 319 /**
 320  * sdma_v4_0_ring_set_wptr - commit the write pointer
 321  *
 322  * @ring: amdgpu ring pointer
 323  *
 324  * Write the wptr back to the hardware (VEGA10+).
 325  */
 326 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 327 {
 328         struct amdgpu_device *adev = ring->adev;
 329
 330         DRM_DEBUG("Setting write pointer\n");
 331         if (ring->use_doorbell) {
 332                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 333
 334                 DRM_DEBUG("Using doorbell -- "
 335                                 "wptr_offs == 0x%08x "
 336                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 337                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 338                                 ring->wptr_offs,
 339                                 lower_32_bits(ring->wptr << 2),
 340                                 upper_32_bits(ring->wptr << 2));
 341                 /* XXX check if swapping is necessary on BE */
 342                 WRITE_ONCE(*wb, (ring->wptr << 2));
 343                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 344                                 ring->doorbell_index, ring->wptr << 2);
 345                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 346         } else {
 347                 DRM_DEBUG("Not using doorbell -- "
 348                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 349                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 350                                 ring->me,
 351                                 lower_32_bits(ring->wptr << 2),
 352                                 ring->me,
 353                                 upper_32_bits(ring->wptr << 2));
 354                 WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
 355                 WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
 356         }
 357 }
 358
 359 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 360 {
 361         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 362         int i;
 363
 364         for (i = 0; i < count; i++)
 365                 if (sdma && sdma->burst_nop && (i == 0))
 366                         amdgpu_ring_write(ring, ring->funcs->nop |
 367                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 368                 else
 369                         amdgpu_ring_write(ring, ring->funcs->nop);
 370 }
 371
 372 /**
 373  * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
 374  *
 375  * @ring: amdgpu ring pointer
 376  * @ib: IB object to schedule
 377  *
 378  * Schedule an IB in the DMA ring (VEGA10).
 379  */
 380 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
 381                                         struct amdgpu_ib *ib,
 382                                         unsigned vmid, bool ctx_switch)
 383 {
 384         /* IB packet must end on a 8 DW boundary */
 385         sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 386
 387         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 388                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 389         /* base must be 32 byte aligned */
 390         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 391         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 392         amdgpu_ring_write(ring, ib->length_dw);
 393         amdgpu_ring_write(ring, 0);
 394         amdgpu_ring_write(ring, 0);
 395
 396 }
 397
 398 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
 399                                    int mem_space, int hdp,
 400                                    uint32_t addr0, uint32_t addr1,
 401                                    uint32_t ref, uint32_t mask,
 402                                    uint32_t inv)
 403 {
 404         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 405                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
 406                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
 407                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 408         if (mem_space) {
 409                 /* memory */
 410                 amdgpu_ring_write(ring, addr0);
 411                 amdgpu_ring_write(ring, addr1);
 412         } else {
 413                 /* registers */
 414                 amdgpu_ring_write(ring, addr0 << 2);
 415                 amdgpu_ring_write(ring, addr1 << 2);
 416         }
 417         amdgpu_ring_write(ring, ref); /* reference */
 418         amdgpu_ring_write(ring, mask); /* mask */
 419         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 420                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
 421 }
 422
 423 /**
 424  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 425  *
 426  * @ring: amdgpu ring pointer
 427  *
 428  * Emit an hdp flush packet on the requested DMA ring.
 429  */
 430 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 431 {
 432         struct amdgpu_device *adev = ring->adev;
 433         u32 ref_and_mask = 0;
 434         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
 435
 436         if (ring->me == 0)
 437                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 438         else
 439                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 440
 441         sdma_v4_0_wait_reg_mem(ring, 0, 1,
 442                                adev->nbio_funcs->get_hdp_flush_done_offset(adev),
 443                                adev->nbio_funcs->get_hdp_flush_req_offset(adev),
 444                                ref_and_mask, ref_and_mask, 10);
 445 }
 446
 447 /**
 448  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
 449  *
 450  * @ring: amdgpu ring pointer
 451  * @fence: amdgpu fence object
 452  *
 453  * Add a DMA fence packet to the ring to write
 454  * the fence seq number and DMA trap packet to generate
 455  * an interrupt if needed (VEGA10).
 456  */
 457 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 458                                       unsigned flags)
 459 {
 460         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 461         /* write the fence */
 462         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 463         /* zero in first two bits */
 464         BUG_ON(addr & 0x3);
 465         amdgpu_ring_write(ring, lower_32_bits(addr));
 466         amdgpu_ring_write(ring, upper_32_bits(addr));
 467         amdgpu_ring_write(ring, lower_32_bits(seq));
 468
 469         /* optionally write high bits as well */
 470         if (write64bit) {
 471                 addr += 4;
 472                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 473                 /* zero in first two bits */
 474                 BUG_ON(addr & 0x3);
 475                 amdgpu_ring_write(ring, lower_32_bits(addr));
 476                 amdgpu_ring_write(ring, upper_32_bits(addr));
 477                 amdgpu_ring_write(ring, upper_32_bits(seq));
 478         }
 479
 480         /* generate an interrupt */
 481         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 482         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 483 }
 484
 485
 486 /**
 487  * sdma_v4_0_gfx_stop - stop the gfx async dma engines
 488  *
 489  * @adev: amdgpu_device pointer
 490  *
 491  * Stop the gfx async dma ring buffers (VEGA10).
 492  */
 493 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
 494 {
 495         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 496         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 497         u32 rb_cntl, ib_cntl;
 498         int i;
 499
 500         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 501             (adev->mman.buffer_funcs_ring == sdma1))
 502                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
 503
 504         for (i = 0; i < adev->sdma.num_instances; i++) {
 505                 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 506                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 507                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 508                 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 509                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 510                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 511         }
 512
 513         sdma0->ready = false;
 514         sdma1->ready = false;
 515 }
 516
 517 /**
 518  * sdma_v4_0_rlc_stop - stop the compute async dma engines
 519  *
 520  * @adev: amdgpu_device pointer
 521  *
 522  * Stop the compute async dma queues (VEGA10).
 523  */
 524 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
 525 {
 526         /* XXX todo */
 527 }
 528
 529 /**
 530  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 531  *
 532  * @adev: amdgpu_device pointer
 533  * @enable: enable/disable the DMA MEs context switch.
 534  *
 535  * Halt or unhalt the async dma engines context switch (VEGA10).
 536  */
 537 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 538 {
 539         u32 f32_cntl, phase_quantum = 0;
 540         int i;
 541
 542         if (amdgpu_sdma_phase_quantum) {
 543                 unsigned value = amdgpu_sdma_phase_quantum;
 544                 unsigned unit = 0;
 545
 546                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 547                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 548                         value = (value + 1) >> 1;
 549                         unit++;
 550                 }
 551                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 552                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 553                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 554                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 555                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 556                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 557                         WARN_ONCE(1,
 558                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 559                                   value << unit);
 560                 }
 561                 phase_quantum =
 562                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 563                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 564         }
 565
 566         for (i = 0; i < adev->sdma.num_instances; i++) {
 567                 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 568                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 569                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 570                 if (enable && amdgpu_sdma_phase_quantum) {
 571                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 572                                phase_quantum);
 573                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 574                                phase_quantum);
 575                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 576                                phase_quantum);
 577                 }
 578                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 579         }
 580
 581 }
 582
 583 /**
 584  * sdma_v4_0_enable - stop the async dma engines
 585  *
 586  * @adev: amdgpu_device pointer
 587  * @enable: enable/disable the DMA MEs.
 588  *
 589  * Halt or unhalt the async dma engines (VEGA10).
 590  */
 591 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
 592 {
 593         u32 f32_cntl;
 594         int i;
 595
 596         if (enable == false) {
 597                 sdma_v4_0_gfx_stop(adev);
 598                 sdma_v4_0_rlc_stop(adev);
 599         }
 600
 601         for (i = 0; i < adev->sdma.num_instances; i++) {
 602                 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 603                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 604                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 605         }
 606 }
 607
 608 /**
 609  * sdma_v4_0_gfx_resume - setup and start the async dma engines
 610  *
 611  * @adev: amdgpu_device pointer
 612  *
 613  * Set up the gfx DMA ring buffers and enable them (VEGA10).
 614  * Returns 0 for success, error for failure.
 615  */
 616 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
 617 {
 618         struct amdgpu_ring *ring;
 619         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 620         u32 rb_bufsz;
 621         u32 wb_offset;
 622         u32 doorbell;
 623         u32 doorbell_offset;
 624         u32 temp;
 625         u64 wptr_gpu_addr;
 626         int i, r;
 627
 628         for (i = 0; i < adev->sdma.num_instances; i++) {
 629                 ring = &adev->sdma.instance[i].ring;
 630                 wb_offset = (ring->rptr_offs * 4);
 631
 632                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 633
 634                 /* Set ring buffer size in dwords */
 635                 rb_bufsz = order_base_2(ring->ring_size / 4);
 636                 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 637                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 638 #ifdef __BIG_ENDIAN
 639                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 640                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 641                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 642 #endif
 643                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 644
 645                 /* Initialize the ring buffer's read and write pointers */
 646                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 647                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 648                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 649                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 650
 651                 /* set the wb address whether it's enabled or not */
 652                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 653                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 654                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 655                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 656
 657                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 658
 659                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 660                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 661
 662                 ring->wptr = 0;
 663
 664                 /* before programing wptr to a less value, need set minor_ptr_update first */
 665                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 666
 667                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 668                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 669                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 670                 }
 671
 672                 doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 673                 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 674
 675                 if (ring->use_doorbell) {
 676                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 677                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 678                                         OFFSET, ring->doorbell_index);
 679                 } else {
 680                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 681                 }
 682                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 683                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 684                 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 685                                                       ring->doorbell_index);
 686
 687                 if (amdgpu_sriov_vf(adev))
 688                         sdma_v4_0_ring_set_wptr(ring);
 689
 690                 /* set minor_ptr_update to 0 after wptr programed */
 691                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 692
 693                 /* set utc l1 enable flag always to 1 */
 694                 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 695                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 696                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 697
 698                 if (!amdgpu_sriov_vf(adev)) {
 699                         /* unhalt engine */
 700                         temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 701                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 702                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 703                 }
 704
 705                 /* setup the wptr shadow polling */
 706                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 707                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 708                        lower_32_bits(wptr_gpu_addr));
 709                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 710                        upper_32_bits(wptr_gpu_addr));
 711                 wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 712                 if (amdgpu_sriov_vf(adev))
 713                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
 714                 else
 715                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
 716                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
 717
 718                 /* enable DMA RB */
 719                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 720                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 721
 722                 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 723                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 724 #ifdef __BIG_ENDIAN
 725                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 726 #endif
 727                 /* enable DMA IBs */
 728                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 729
 730                 ring->ready = true;
 731
 732                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 733                         sdma_v4_0_ctx_switch_enable(adev, true);
 734                         sdma_v4_0_enable(adev, true);
 735                 }
 736
 737                 r = amdgpu_ring_test_ring(ring);
 738                 if (r) {
 739                         ring->ready = false;
 740                         return r;
 741                 }
 742
 743                 if (adev->mman.buffer_funcs_ring == ring)
 744                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 745
 746         }
 747
 748         return 0;
 749 }
 750
 751 static void
 752 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
 753 {
 754         uint32_t def, data;
 755
 756         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
 757                 /* disable idle interrupt */
 758                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 759                 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 760
 761                 if (data != def)
 762                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 763         } else {
 764                 /* disable idle interrupt */
 765                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 766                 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 767                 if (data != def)
 768                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 769         }
 770 }
 771
 772 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
 773 {
 774         uint32_t def, data;
 775
 776         /* Enable HW based PG. */
 777         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
 778         data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
 779         if (data != def)
 780                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
 781
 782         /* enable interrupt */
 783         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 784         data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 785         if (data != def)
 786                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 787
 788         /* Configure hold time to filter in-valid power on/off request. Use default right now */
 789         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
 790         data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
 791         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
 792         /* Configure switch time for hysteresis purpose. Use default right now */
 793         data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
 794         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
 795         if(data != def)
 796                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
 797 }
 798
 799 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
 800 {
 801         if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
 802                 return;
 803
 804         switch (adev->asic_type) {
 805         case CHIP_RAVEN:
 806                 sdma_v4_1_init_power_gating(adev);
 807                 sdma_v4_1_update_power_gating(adev, true);
 808                 break;
 809         default:
 810                 break;
 811         }
 812 }
 813
 814 /**
 815  * sdma_v4_0_rlc_resume - setup and start the async dma engines
 816  *
 817  * @adev: amdgpu_device pointer
 818  *
 819  * Set up the compute DMA queues and enable them (VEGA10).
 820  * Returns 0 for success, error for failure.
 821  */
 822 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
 823 {
 824         sdma_v4_0_init_pg(adev);
 825
 826         return 0;
 827 }
 828
 829 /**
 830  * sdma_v4_0_load_microcode - load the sDMA ME ucode
 831  *
 832  * @adev: amdgpu_device pointer
 833  *
 834  * Loads the sDMA0/1 ucode.
 835  * Returns 0 for success, -EINVAL if the ucode is not available.
 836  */
 837 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
 838 {
 839         const struct sdma_firmware_header_v1_0 *hdr;
 840         const __le32 *fw_data;
 841         u32 fw_size;
 842         int i, j;
 843
 844         /* halt the MEs */
 845         sdma_v4_0_enable(adev, false);
 846
 847         for (i = 0; i < adev->sdma.num_instances; i++) {
 848                 if (!adev->sdma.instance[i].fw)
 849                         return -EINVAL;
 850
 851                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 852                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 853                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 854
 855                 fw_data = (const __le32 *)
 856                         (adev->sdma.instance[i].fw->data +
 857                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 858
 859                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 860
 861                 for (j = 0; j < fw_size; j++)
 862                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 863
 864                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 865         }
 866
 867         return 0;
 868 }
 869
 870 /**
 871  * sdma_v4_0_start - setup and start the async dma engines
 872  *
 873  * @adev: amdgpu_device pointer
 874  *
 875  * Set up the DMA engines and enable them (VEGA10).
 876  * Returns 0 for success, error for failure.
 877  */
 878 static int sdma_v4_0_start(struct amdgpu_device *adev)
 879 {
 880         int r = 0;
 881
 882         if (amdgpu_sriov_vf(adev)) {
 883                 sdma_v4_0_ctx_switch_enable(adev, false);
 884                 sdma_v4_0_enable(adev, false);
 885
 886                 /* set RB registers */
 887                 r = sdma_v4_0_gfx_resume(adev);
 888                 return r;
 889         }
 890
 891         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 892                 r = sdma_v4_0_load_microcode(adev);
 893                 if (r)
 894                         return r;
 895         }
 896
 897         /* unhalt the MEs */
 898         sdma_v4_0_enable(adev, true);
 899         /* enable sdma ring preemption */
 900         sdma_v4_0_ctx_switch_enable(adev, true);
 901
 902         /* start the gfx rings and rlc compute queues */
 903         r = sdma_v4_0_gfx_resume(adev);
 904         if (r)
 905                 return r;
 906         r = sdma_v4_0_rlc_resume(adev);
 907
 908         return r;
 909 }
 910
 911 /**
 912  * sdma_v4_0_ring_test_ring - simple async dma engine test
 913  *
 914  * @ring: amdgpu_ring structure holding ring information
 915  *
 916  * Test the DMA engine by writing using it to write an
 917  * value to memory. (VEGA10).
 918  * Returns 0 for success, error for failure.
 919  */
 920 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
 921 {
 922         struct amdgpu_device *adev = ring->adev;
 923         unsigned i;
 924         unsigned index;
 925         int r;
 926         u32 tmp;
 927         u64 gpu_addr;
 928
 929         r = amdgpu_device_wb_get(adev, &index);
 930         if (r) {
 931                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 932                 return r;
 933         }
 934
 935         gpu_addr = adev->wb.gpu_addr + (index * 4);
 936         tmp = 0xCAFEDEAD;
 937         adev->wb.wb[index] = cpu_to_le32(tmp);
 938
 939         r = amdgpu_ring_alloc(ring, 5);
 940         if (r) {
 941                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 942                 amdgpu_device_wb_free(adev, index);
 943                 return r;
 944         }
 945
 946         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 947                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 948         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 949         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 950         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 951         amdgpu_ring_write(ring, 0xDEADBEEF);
 952         amdgpu_ring_commit(ring);
 953
 954         for (i = 0; i < adev->usec_timeout; i++) {
 955                 tmp = le32_to_cpu(adev->wb.wb[index]);
 956                 if (tmp == 0xDEADBEEF)
 957                         break;
 958                 DRM_UDELAY(1);
 959         }
 960
 961         if (i < adev->usec_timeout) {
 962                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 963         } else {
 964                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 965                           ring->idx, tmp);
 966                 r = -EINVAL;
 967         }
 968         amdgpu_device_wb_free(adev, index);
 969
 970         return r;
 971 }
 972
 973 /**
 974  * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
 975  *
 976  * @ring: amdgpu_ring structure holding ring information
 977  *
 978  * Test a simple IB in the DMA ring (VEGA10).
 979  * Returns 0 on success, error on failure.
 980  */
 981 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 982 {
 983         struct amdgpu_device *adev = ring->adev;
 984         struct amdgpu_ib ib;
 985         struct dma_fence *f = NULL;
 986         unsigned index;
 987         long r;
 988         u32 tmp = 0;
 989         u64 gpu_addr;
 990
 991         r = amdgpu_device_wb_get(adev, &index);
 992         if (r) {
 993                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 994                 return r;
 995         }
 996
 997         gpu_addr = adev->wb.gpu_addr + (index * 4);
 998         tmp = 0xCAFEDEAD;
 999         adev->wb.wb[index] = cpu_to_le32(tmp);
1000         memset(&ib, 0, sizeof(ib));
1001         r = amdgpu_ib_get(adev, NULL, 256, &ib);
1002         if (r) {
1003                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1004                 goto err0;
1005         }
1006
1007         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1008                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1009         ib.ptr[1] = lower_32_bits(gpu_addr);
1010         ib.ptr[2] = upper_32_bits(gpu_addr);
1011         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1012         ib.ptr[4] = 0xDEADBEEF;
1013         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1014         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1015         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1016         ib.length_dw = 8;
1017
1018         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1019         if (r)
1020                 goto err1;
1021
1022         r = dma_fence_wait_timeout(f, false, timeout);
1023         if (r == 0) {
1024                 DRM_ERROR("amdgpu: IB test timed out\n");
1025                 r = -ETIMEDOUT;
1026                 goto err1;
1027         } else if (r < 0) {
1028                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1029                 goto err1;
1030         }
1031         tmp = le32_to_cpu(adev->wb.wb[index]);
1032         if (tmp == 0xDEADBEEF) {
1033                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
1034                 r = 0;
1035         } else {
1036                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
1037                 r = -EINVAL;
1038         }
1039 err1:
1040         amdgpu_ib_free(adev, &ib, NULL);
1041         dma_fence_put(f);
1042 err0:
1043         amdgpu_device_wb_free(adev, index);
1044         return r;
1045 }
1046
1047
1048 /**
1049  * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1050  *
1051  * @ib: indirect buffer to fill with commands
1052  * @pe: addr of the page entry
1053  * @src: src addr to copy from
1054  * @count: number of page entries to update
1055  *
1056  * Update PTEs by copying them from the GART using sDMA (VEGA10).
1057  */
1058 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1059                                   uint64_t pe, uint64_t src,
1060                                   unsigned count)
1061 {
1062         unsigned bytes = count * 8;
1063
1064         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1065                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1066         ib->ptr[ib->length_dw++] = bytes - 1;
1067         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1068         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1069         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1070         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1071         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1072
1073 }
1074
1075 /**
1076  * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1077  *
1078  * @ib: indirect buffer to fill with commands
1079  * @pe: addr of the page entry
1080  * @addr: dst addr to write into pe
1081  * @count: number of page entries to update
1082  * @incr: increase next addr by incr bytes
1083  * @flags: access flags
1084  *
1085  * Update PTEs by writing them manually using sDMA (VEGA10).
1086  */
1087 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1088                                    uint64_t value, unsigned count,
1089                                    uint32_t incr)
1090 {
1091         unsigned ndw = count * 2;
1092
1093         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1094                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1095         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1096         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1097         ib->ptr[ib->length_dw++] = ndw - 1;
1098         for (; ndw > 0; ndw -= 2) {
1099                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1100                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1101                 value += incr;
1102         }
1103 }
1104
1105 /**
1106  * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1107  *
1108  * @ib: indirect buffer to fill with commands
1109  * @pe: addr of the page entry
1110  * @addr: dst addr to write into pe
1111  * @count: number of page entries to update
1112  * @incr: increase next addr by incr bytes
1113  * @flags: access flags
1114  *
1115  * Update the page tables using sDMA (VEGA10).
1116  */
1117 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1118                                      uint64_t pe,
1119                                      uint64_t addr, unsigned count,
1120                                      uint32_t incr, uint64_t flags)
1121 {
1122         /* for physically contiguous pages (vram) */
1123         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1124         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1125         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1126         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1127         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1128         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1129         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1130         ib->ptr[ib->length_dw++] = incr; /* increment size */
1131         ib->ptr[ib->length_dw++] = 0;
1132         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1133 }
1134
1135 /**
1136  * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1137  *
1138  * @ib: indirect buffer to fill with padding
1139  *
1140  */
1141 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1142 {
1143         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1144         u32 pad_count;
1145         int i;
1146
1147         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1148         for (i = 0; i < pad_count; i++)
1149                 if (sdma && sdma->burst_nop && (i == 0))
1150                         ib->ptr[ib->length_dw++] =
1151                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1152                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1153                 else
1154                         ib->ptr[ib->length_dw++] =
1155                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1156 }
1157
1158
1159 /**
1160  * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1161  *
1162  * @ring: amdgpu_ring pointer
1163  *
1164  * Make sure all previous operations are completed (CIK).
1165  */
1166 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1167 {
1168         uint32_t seq = ring->fence_drv.sync_seq;
1169         uint64_t addr = ring->fence_drv.gpu_addr;
1170
1171         /* wait for idle */
1172         sdma_v4_0_wait_reg_mem(ring, 1, 0,
1173                                addr & 0xfffffffc,
1174                                upper_32_bits(addr) & 0xffffffff,
1175                                seq, 0xffffffff, 4);
1176 }
1177
1178
1179 /**
1180  * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1181  *
1182  * @ring: amdgpu_ring pointer
1183  * @vm: amdgpu_vm pointer
1184  *
1185  * Update the page table base and flush the VM TLB
1186  * using sDMA (VEGA10).
1187  */
1188 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1189                                          unsigned vmid, uint64_t pd_addr)
1190 {
1191         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1192 }
1193
1194 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1195                                      uint32_t reg, uint32_t val)
1196 {
1197         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1198                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1199         amdgpu_ring_write(ring, reg);
1200         amdgpu_ring_write(ring, val);
1201 }
1202
1203 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1204                                          uint32_t val, uint32_t mask)
1205 {
1206         sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1207 }
1208
1209 static int sdma_v4_0_early_init(void *handle)
1210 {
1211         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1212
1213         if (adev->asic_type == CHIP_RAVEN)
1214                 adev->sdma.num_instances = 1;
1215         else
1216                 adev->sdma.num_instances = 2;
1217
1218         sdma_v4_0_set_ring_funcs(adev);
1219         sdma_v4_0_set_buffer_funcs(adev);
1220         sdma_v4_0_set_vm_pte_funcs(adev);
1221         sdma_v4_0_set_irq_funcs(adev);
1222
1223         return 0;
1224 }
1225
1226
1227 static int sdma_v4_0_sw_init(void *handle)
1228 {
1229         struct amdgpu_ring *ring;
1230         int r, i;
1231         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1232
1233         /* SDMA trap event */
1234         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_TRAP,
1235                               &adev->sdma.trap_irq);
1236         if (r)
1237                 return r;
1238
1239         /* SDMA trap event */
1240         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_TRAP,
1241                               &adev->sdma.trap_irq);
1242         if (r)
1243                 return r;
1244
1245         r = sdma_v4_0_init_microcode(adev);
1246         if (r) {
1247                 DRM_ERROR("Failed to load sdma firmware!\n");
1248                 return r;
1249         }
1250
1251         for (i = 0; i < adev->sdma.num_instances; i++) {
1252                 ring = &adev->sdma.instance[i].ring;
1253                 ring->ring_obj = NULL;
1254                 ring->use_doorbell = true;
1255
1256                 DRM_INFO("use_doorbell being set to: [%s]\n",
1257                                 ring->use_doorbell?"true":"false");
1258
1259                 ring->doorbell_index = (i == 0) ?
1260                         (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
1261                         : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
1262
1263                 sprintf(ring->name, "sdma%d", i);
1264                 r = amdgpu_ring_init(adev, ring, 1024,
1265                                      &adev->sdma.trap_irq,
1266                                      (i == 0) ?
1267                                      AMDGPU_SDMA_IRQ_TRAP0 :
1268                                      AMDGPU_SDMA_IRQ_TRAP1);
1269                 if (r)
1270                         return r;
1271         }
1272
1273         return r;
1274 }
1275
1276 static int sdma_v4_0_sw_fini(void *handle)
1277 {
1278         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1279         int i;
1280
1281         for (i = 0; i < adev->sdma.num_instances; i++)
1282                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1283
1284         for (i = 0; i < adev->sdma.num_instances; i++) {
1285                 release_firmware(adev->sdma.instance[i].fw);
1286                 adev->sdma.instance[i].fw = NULL;
1287         }
1288
1289         return 0;
1290 }
1291
1292 static int sdma_v4_0_hw_init(void *handle)
1293 {
1294         int r;
1295         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1296
1297         sdma_v4_0_init_golden_registers(adev);
1298
1299         r = sdma_v4_0_start(adev);
1300
1301         return r;
1302 }
1303
1304 static int sdma_v4_0_hw_fini(void *handle)
1305 {
1306         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1307
1308         if (amdgpu_sriov_vf(adev))
1309                 return 0;
1310
1311         sdma_v4_0_ctx_switch_enable(adev, false);
1312         sdma_v4_0_enable(adev, false);
1313
1314         return 0;
1315 }
1316
1317 static int sdma_v4_0_suspend(void *handle)
1318 {
1319         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1320
1321         return sdma_v4_0_hw_fini(adev);
1322 }
1323
1324 static int sdma_v4_0_resume(void *handle)
1325 {
1326         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1327
1328         return sdma_v4_0_hw_init(adev);
1329 }
1330
1331 static bool sdma_v4_0_is_idle(void *handle)
1332 {
1333         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1334         u32 i;
1335
1336         for (i = 0; i < adev->sdma.num_instances; i++) {
1337                 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1338
1339                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1340                         return false;
1341         }
1342
1343         return true;
1344 }
1345
1346 static int sdma_v4_0_wait_for_idle(void *handle)
1347 {
1348         unsigned i;
1349         u32 sdma0, sdma1;
1350         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1351
1352         for (i = 0; i < adev->usec_timeout; i++) {
1353                 sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1354                 sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1355
1356                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1357                         return 0;
1358                 udelay(1);
1359         }
1360         return -ETIMEDOUT;
1361 }
1362
1363 static int sdma_v4_0_soft_reset(void *handle)
1364 {
1365         /* todo */
1366
1367         return 0;
1368 }
1369
1370 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
1371                                         struct amdgpu_irq_src *source,
1372                                         unsigned type,
1373                                         enum amdgpu_interrupt_state state)
1374 {
1375         u32 sdma_cntl;
1376
1377         u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ?
1378                 sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1379                 sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1380
1381         sdma_cntl = RREG32(reg_offset);
1382         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1383                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1384         WREG32(reg_offset, sdma_cntl);
1385
1386         return 0;
1387 }
1388
1389 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
1390                                       struct amdgpu_irq_src *source,
1391                                       struct amdgpu_iv_entry *entry)
1392 {
1393         DRM_DEBUG("IH: SDMA trap\n");
1394         switch (entry->client_id) {
1395         case SOC15_IH_CLIENTID_SDMA0:
1396                 switch (entry->ring_id) {
1397                 case 0:
1398                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1399                         break;
1400                 case 1:
1401                         /* XXX compute */
1402                         break;
1403                 case 2:
1404                         /* XXX compute */
1405                         break;
1406                 case 3:
1407                         /* XXX page queue*/
1408                         break;
1409                 }
1410                 break;
1411         case SOC15_IH_CLIENTID_SDMA1:
1412                 switch (entry->ring_id) {
1413                 case 0:
1414                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1415                         break;
1416                 case 1:
1417                         /* XXX compute */
1418                         break;
1419                 case 2:
1420                         /* XXX compute */
1421                         break;
1422                 case 3:
1423                         /* XXX page queue*/
1424                         break;
1425                 }
1426                 break;
1427         }
1428         return 0;
1429 }
1430
1431 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1432                                               struct amdgpu_irq_src *source,
1433                                               struct amdgpu_iv_entry *entry)
1434 {
1435         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1436         schedule_work(&adev->reset_work);
1437         return 0;
1438 }
1439
1440
1441 static void sdma_v4_0_update_medium_grain_clock_gating(
1442                 struct amdgpu_device *adev,
1443                 bool enable)
1444 {
1445         uint32_t data, def;
1446
1447         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1448                 /* enable sdma0 clock gating */
1449                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1450                 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1451                           SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1452                           SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1453                           SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1454                           SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1455                           SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1456                           SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1457                           SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1458                 if (def != data)
1459                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1460
1461                 if (adev->sdma.num_instances > 1) {
1462                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1463                         data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1464                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1465                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1466                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1467                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1468                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1469                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1470                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1471                         if (def != data)
1472                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1473                 }
1474         } else {
1475                 /* disable sdma0 clock gating */
1476                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1477                 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1478                          SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1479                          SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1480                          SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1481                          SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1482                          SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1483                          SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1484                          SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1485
1486                 if (def != data)
1487                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1488
1489                 if (adev->sdma.num_instances > 1) {
1490                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1491                         data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1492                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1493                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1494                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1495                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1496                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1497                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1498                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1499                         if (def != data)
1500                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1501                 }
1502         }
1503 }
1504
1505
1506 static void sdma_v4_0_update_medium_grain_light_sleep(
1507                 struct amdgpu_device *adev,
1508                 bool enable)
1509 {
1510         uint32_t data, def;
1511
1512         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1513                 /* 1-not override: enable sdma0 mem light sleep */
1514                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1515                 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1516                 if (def != data)
1517                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1518
1519                 /* 1-not override: enable sdma1 mem light sleep */
1520                 if (adev->sdma.num_instances > 1) {
1521                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1522                         data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1523                         if (def != data)
1524                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1525                 }
1526         } else {
1527                 /* 0-override:disable sdma0 mem light sleep */
1528                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1529                 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1530                 if (def != data)
1531                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1532
1533                 /* 0-override:disable sdma1 mem light sleep */
1534                 if (adev->sdma.num_instances > 1) {
1535                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1536                         data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1537                         if (def != data)
1538                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1539                 }
1540         }
1541 }
1542
1543 static int sdma_v4_0_set_clockgating_state(void *handle,
1544                                           enum amd_clockgating_state state)
1545 {
1546         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1547
1548         if (amdgpu_sriov_vf(adev))
1549                 return 0;
1550
1551         switch (adev->asic_type) {
1552         case CHIP_VEGA10:
1553         case CHIP_VEGA12:
1554         case CHIP_VEGA20:
1555         case CHIP_RAVEN:
1556                 sdma_v4_0_update_medium_grain_clock_gating(adev,
1557                                 state == AMD_CG_STATE_GATE ? true : false);
1558                 sdma_v4_0_update_medium_grain_light_sleep(adev,
1559                                 state == AMD_CG_STATE_GATE ? true : false);
1560                 break;
1561         default:
1562                 break;
1563         }
1564         return 0;
1565 }
1566
1567 static int sdma_v4_0_set_powergating_state(void *handle,
1568                                           enum amd_powergating_state state)
1569 {
1570         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1571
1572         switch (adev->asic_type) {
1573         case CHIP_RAVEN:
1574                 sdma_v4_1_update_power_gating(adev,
1575                                 state == AMD_PG_STATE_GATE ? true : false);
1576                 break;
1577         default:
1578                 break;
1579         }
1580
1581         return 0;
1582 }
1583
1584 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
1585 {
1586         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1587         int data;
1588
1589         if (amdgpu_sriov_vf(adev))
1590                 *flags = 0;
1591
1592         /* AMD_CG_SUPPORT_SDMA_MGCG */
1593         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1594         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1595                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1596
1597         /* AMD_CG_SUPPORT_SDMA_LS */
1598         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1599         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1600                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1601 }
1602
1603 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
1604         .name = "sdma_v4_0",
1605         .early_init = sdma_v4_0_early_init,
1606         .late_init = NULL,
1607         .sw_init = sdma_v4_0_sw_init,
1608         .sw_fini = sdma_v4_0_sw_fini,
1609         .hw_init = sdma_v4_0_hw_init,
1610         .hw_fini = sdma_v4_0_hw_fini,
1611         .suspend = sdma_v4_0_suspend,
1612         .resume = sdma_v4_0_resume,
1613         .is_idle = sdma_v4_0_is_idle,
1614         .wait_for_idle = sdma_v4_0_wait_for_idle,
1615         .soft_reset = sdma_v4_0_soft_reset,
1616         .set_clockgating_state = sdma_v4_0_set_clockgating_state,
1617         .set_powergating_state = sdma_v4_0_set_powergating_state,
1618         .get_clockgating_state = sdma_v4_0_get_clockgating_state,
1619 };
1620
1621 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
1622         .type = AMDGPU_RING_TYPE_SDMA,
1623         .align_mask = 0xf,
1624         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1625         .support_64bit_ptrs = true,
1626         .vmhub = AMDGPU_MMHUB,
1627         .get_rptr = sdma_v4_0_ring_get_rptr,
1628         .get_wptr = sdma_v4_0_ring_get_wptr,
1629         .set_wptr = sdma_v4_0_ring_set_wptr,
1630         .emit_frame_size =
1631                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
1632                 3 + /* hdp invalidate */
1633                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
1634                 /* sdma_v4_0_ring_emit_vm_flush */
1635                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1636                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1637                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
1638         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
1639         .emit_ib = sdma_v4_0_ring_emit_ib,
1640         .emit_fence = sdma_v4_0_ring_emit_fence,
1641         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
1642         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
1643         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
1644         .test_ring = sdma_v4_0_ring_test_ring,
1645         .test_ib = sdma_v4_0_ring_test_ib,
1646         .insert_nop = sdma_v4_0_ring_insert_nop,
1647         .pad_ib = sdma_v4_0_ring_pad_ib,
1648         .emit_wreg = sdma_v4_0_ring_emit_wreg,
1649         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
1650         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1651 };
1652
1653 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
1654 {
1655         int i;
1656
1657         for (i = 0; i < adev->sdma.num_instances; i++) {
1658                 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
1659                 adev->sdma.instance[i].ring.me = i;
1660         }
1661 }
1662
1663 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
1664         .set = sdma_v4_0_set_trap_irq_state,
1665         .process = sdma_v4_0_process_trap_irq,
1666 };
1667
1668 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
1669         .process = sdma_v4_0_process_illegal_inst_irq,
1670 };
1671
1672 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
1673 {
1674         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1675         adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
1676         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
1677 }
1678
1679 /**
1680  * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
1681  *
1682  * @ring: amdgpu_ring structure holding ring information
1683  * @src_offset: src GPU address
1684  * @dst_offset: dst GPU address
1685  * @byte_count: number of bytes to xfer
1686  *
1687  * Copy GPU buffers using the DMA engine (VEGA10/12).
1688  * Used by the amdgpu ttm implementation to move pages if
1689  * registered as the asic copy callback.
1690  */
1691 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
1692                                        uint64_t src_offset,
1693                                        uint64_t dst_offset,
1694                                        uint32_t byte_count)
1695 {
1696         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1697                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1698         ib->ptr[ib->length_dw++] = byte_count - 1;
1699         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1700         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1701         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1702         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1703         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1704 }
1705
1706 /**
1707  * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
1708  *
1709  * @ring: amdgpu_ring structure holding ring information
1710  * @src_data: value to write to buffer
1711  * @dst_offset: dst GPU address
1712  * @byte_count: number of bytes to xfer
1713  *
1714  * Fill GPU buffers using the DMA engine (VEGA10/12).
1715  */
1716 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
1717                                        uint32_t src_data,
1718                                        uint64_t dst_offset,
1719                                        uint32_t byte_count)
1720 {
1721         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1722         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1723         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1724         ib->ptr[ib->length_dw++] = src_data;
1725         ib->ptr[ib->length_dw++] = byte_count - 1;
1726 }
1727
1728 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
1729         .copy_max_bytes = 0x400000,
1730         .copy_num_dw = 7,
1731         .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
1732
1733         .fill_max_bytes = 0x400000,
1734         .fill_num_dw = 5,
1735         .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
1736 };
1737
1738 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
1739 {
1740         if (adev->mman.buffer_funcs == NULL) {
1741                 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
1742                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1743         }
1744 }
1745
1746 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
1747         .copy_pte_num_dw = 7,
1748         .copy_pte = sdma_v4_0_vm_copy_pte,
1749
1750         .write_pte = sdma_v4_0_vm_write_pte,
1751         .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
1752 };
1753
1754 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1755 {
1756         unsigned i;
1757
1758         if (adev->vm_manager.vm_pte_funcs == NULL) {
1759                 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
1760                 for (i = 0; i < adev->sdma.num_instances; i++)
1761                         adev->vm_manager.vm_pte_rings[i] =
1762                                 &adev->sdma.instance[i].ring;
1763
1764                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1765         }
1766 }
1767
1768 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
1769         .type = AMD_IP_BLOCK_TYPE_SDMA,
1770         .major = 4,
1771         .minor = 0,
1772         .rev = 0,
1773         .funcs = &sdma_v4_0_ip_funcs,
1774 };