drivers/gpu/drm/sti/sti_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics SA 2014
   4  * Author: Vincent Abriou <[email protected]> for STMicroelectronics.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/component.h>
   9 #include <linux/debugfs.h>
  10 #include <linux/hdmi.h>
  11 #include <linux/module.h>
  12 #include <linux/of_gpio.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/reset.h>
  15
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_debugfs.h>
  18 #include <drm/drm_drv.h>
  19 #include <drm/drm_edid.h>
  20 #include <drm/drm_file.h>
  21 #include <drm/drm_print.h>
  22 #include <drm/drm_probe_helper.h>
  23
  24 #include <sound/hdmi-codec.h>
  25
  26 #include "sti_hdmi.h"
  27 #include "sti_hdmi_tx3g4c28phy.h"
  28 #include "sti_vtg.h"
  29
  30 #define HDMI_CFG                        0x0000
  31 #define HDMI_INT_EN                     0x0004
  32 #define HDMI_INT_STA                    0x0008
  33 #define HDMI_INT_CLR                    0x000C
  34 #define HDMI_STA                        0x0010
  35 #define HDMI_ACTIVE_VID_XMIN            0x0100
  36 #define HDMI_ACTIVE_VID_XMAX            0x0104
  37 #define HDMI_ACTIVE_VID_YMIN            0x0108
  38 #define HDMI_ACTIVE_VID_YMAX            0x010C
  39 #define HDMI_DFLT_CHL0_DAT              0x0110
  40 #define HDMI_DFLT_CHL1_DAT              0x0114
  41 #define HDMI_DFLT_CHL2_DAT              0x0118
  42 #define HDMI_AUDIO_CFG                  0x0200
  43 #define HDMI_SPDIF_FIFO_STATUS          0x0204
  44 #define HDMI_SW_DI_1_HEAD_WORD          0x0210
  45 #define HDMI_SW_DI_1_PKT_WORD0          0x0214
  46 #define HDMI_SW_DI_1_PKT_WORD1          0x0218
  47 #define HDMI_SW_DI_1_PKT_WORD2          0x021C
  48 #define HDMI_SW_DI_1_PKT_WORD3          0x0220
  49 #define HDMI_SW_DI_1_PKT_WORD4          0x0224
  50 #define HDMI_SW_DI_1_PKT_WORD5          0x0228
  51 #define HDMI_SW_DI_1_PKT_WORD6          0x022C
  52 #define HDMI_SW_DI_CFG                  0x0230
  53 #define HDMI_SAMPLE_FLAT_MASK           0x0244
  54 #define HDMI_AUDN                       0x0400
  55 #define HDMI_AUD_CTS                    0x0404
  56 #define HDMI_SW_DI_2_HEAD_WORD          0x0600
  57 #define HDMI_SW_DI_2_PKT_WORD0          0x0604
  58 #define HDMI_SW_DI_2_PKT_WORD1          0x0608
  59 #define HDMI_SW_DI_2_PKT_WORD2          0x060C
  60 #define HDMI_SW_DI_2_PKT_WORD3          0x0610
  61 #define HDMI_SW_DI_2_PKT_WORD4          0x0614
  62 #define HDMI_SW_DI_2_PKT_WORD5          0x0618
  63 #define HDMI_SW_DI_2_PKT_WORD6          0x061C
  64 #define HDMI_SW_DI_3_HEAD_WORD          0x0620
  65 #define HDMI_SW_DI_3_PKT_WORD0          0x0624
  66 #define HDMI_SW_DI_3_PKT_WORD1          0x0628
  67 #define HDMI_SW_DI_3_PKT_WORD2          0x062C
  68 #define HDMI_SW_DI_3_PKT_WORD3          0x0630
  69 #define HDMI_SW_DI_3_PKT_WORD4          0x0634
  70 #define HDMI_SW_DI_3_PKT_WORD5          0x0638
  71 #define HDMI_SW_DI_3_PKT_WORD6          0x063C
  72
  73 #define HDMI_IFRAME_SLOT_AVI            1
  74 #define HDMI_IFRAME_SLOT_AUDIO          2
  75 #define HDMI_IFRAME_SLOT_VENDOR         3
  76
  77 #define  XCAT(prefix, x, suffix)        prefix ## x ## suffix
  78 #define  HDMI_SW_DI_N_HEAD_WORD(x)      XCAT(HDMI_SW_DI_, x, _HEAD_WORD)
  79 #define  HDMI_SW_DI_N_PKT_WORD0(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD0)
  80 #define  HDMI_SW_DI_N_PKT_WORD1(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD1)
  81 #define  HDMI_SW_DI_N_PKT_WORD2(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD2)
  82 #define  HDMI_SW_DI_N_PKT_WORD3(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD3)
  83 #define  HDMI_SW_DI_N_PKT_WORD4(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD4)
  84 #define  HDMI_SW_DI_N_PKT_WORD5(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD5)
  85 #define  HDMI_SW_DI_N_PKT_WORD6(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD6)
  86
  87 #define HDMI_SW_DI_MAX_WORD             7
  88
  89 #define HDMI_IFRAME_DISABLED            0x0
  90 #define HDMI_IFRAME_SINGLE_SHOT         0x1
  91 #define HDMI_IFRAME_FIELD               0x2
  92 #define HDMI_IFRAME_FRAME               0x3
  93 #define HDMI_IFRAME_MASK                0x3
  94 #define HDMI_IFRAME_CFG_DI_N(x, n)       ((x) << ((n-1)*4)) /* n from 1 to 6 */
  95
  96 #define HDMI_CFG_DEVICE_EN              BIT(0)
  97 #define HDMI_CFG_HDMI_NOT_DVI           BIT(1)
  98 #define HDMI_CFG_HDCP_EN                BIT(2)
  99 #define HDMI_CFG_ESS_NOT_OESS           BIT(3)
 100 #define HDMI_CFG_H_SYNC_POL_NEG         BIT(4)
 101 #define HDMI_CFG_V_SYNC_POL_NEG         BIT(6)
 102 #define HDMI_CFG_422_EN                 BIT(8)
 103 #define HDMI_CFG_FIFO_OVERRUN_CLR       BIT(12)
 104 #define HDMI_CFG_FIFO_UNDERRUN_CLR      BIT(13)
 105 #define HDMI_CFG_SW_RST_EN              BIT(31)
 106
 107 #define HDMI_INT_GLOBAL                 BIT(0)
 108 #define HDMI_INT_SW_RST                 BIT(1)
 109 #define HDMI_INT_PIX_CAP                BIT(3)
 110 #define HDMI_INT_HOT_PLUG               BIT(4)
 111 #define HDMI_INT_DLL_LCK                BIT(5)
 112 #define HDMI_INT_NEW_FRAME              BIT(6)
 113 #define HDMI_INT_GENCTRL_PKT            BIT(7)
 114 #define HDMI_INT_AUDIO_FIFO_XRUN        BIT(8)
 115 #define HDMI_INT_SINK_TERM_PRESENT      BIT(11)
 116
 117 #define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \
 118                         | HDMI_INT_DLL_LCK \
 119                         | HDMI_INT_HOT_PLUG \
 120                         | HDMI_INT_GLOBAL)
 121
 122 #define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \
 123                         | HDMI_INT_AUDIO_FIFO_XRUN \
 124                         | HDMI_INT_GENCTRL_PKT \
 125                         | HDMI_INT_NEW_FRAME \
 126                         | HDMI_INT_DLL_LCK \
 127                         | HDMI_INT_HOT_PLUG \
 128                         | HDMI_INT_PIX_CAP \
 129                         | HDMI_INT_SW_RST \
 130                         | HDMI_INT_GLOBAL)
 131
 132 #define HDMI_STA_SW_RST                 BIT(1)
 133
 134 #define HDMI_AUD_CFG_8CH                BIT(0)
 135 #define HDMI_AUD_CFG_SPDIF_DIV_2        BIT(1)
 136 #define HDMI_AUD_CFG_SPDIF_DIV_3        BIT(2)
 137 #define HDMI_AUD_CFG_SPDIF_CLK_DIV_4    (BIT(1) | BIT(2))
 138 #define HDMI_AUD_CFG_CTS_CLK_256FS      BIT(12)
 139 #define HDMI_AUD_CFG_DTS_INVALID        BIT(16)
 140 #define HDMI_AUD_CFG_ONE_BIT_INVALID    (BIT(18) | BIT(19) | BIT(20) |  BIT(21))
 141 #define HDMI_AUD_CFG_CH12_VALID BIT(28)
 142 #define HDMI_AUD_CFG_CH34_VALID BIT(29)
 143 #define HDMI_AUD_CFG_CH56_VALID BIT(30)
 144 #define HDMI_AUD_CFG_CH78_VALID BIT(31)
 145
 146 /* sample flat mask */
 147 #define HDMI_SAMPLE_FLAT_NO      0
 148 #define HDMI_SAMPLE_FLAT_SP0 BIT(0)
 149 #define HDMI_SAMPLE_FLAT_SP1 BIT(1)
 150 #define HDMI_SAMPLE_FLAT_SP2 BIT(2)
 151 #define HDMI_SAMPLE_FLAT_SP3 BIT(3)
 152 #define HDMI_SAMPLE_FLAT_ALL (HDMI_SAMPLE_FLAT_SP0 | HDMI_SAMPLE_FLAT_SP1 |\
 153                               HDMI_SAMPLE_FLAT_SP2 | HDMI_SAMPLE_FLAT_SP3)
 154
 155 #define HDMI_INFOFRAME_HEADER_TYPE(x)    (((x) & 0xff) <<  0)
 156 #define HDMI_INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) <<  8)
 157 #define HDMI_INFOFRAME_HEADER_LEN(x)     (((x) & 0x0f) << 16)
 158
 159 struct sti_hdmi_connector {
 160         struct drm_connector drm_connector;
 161         struct drm_encoder *encoder;
 162         struct sti_hdmi *hdmi;
 163         struct drm_property *colorspace_property;
 164 };
 165
 166 #define to_sti_hdmi_connector(x) \
 167         container_of(x, struct sti_hdmi_connector, drm_connector)
 168
 169 u32 hdmi_read(struct sti_hdmi *hdmi, int offset)
 170 {
 171         return readl(hdmi->regs + offset);
 172 }
 173
 174 void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset)
 175 {
 176         writel(val, hdmi->regs + offset);
 177 }
 178
 179 /**
 180  * HDMI interrupt handler threaded
 181  *
 182  * @irq: irq number
 183  * @arg: connector structure
 184  */
 185 static irqreturn_t hdmi_irq_thread(int irq, void *arg)
 186 {
 187         struct sti_hdmi *hdmi = arg;
 188
 189         /* Hot plug/unplug IRQ */
 190         if (hdmi->irq_status & HDMI_INT_HOT_PLUG) {
 191                 hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
 192                 if (hdmi->drm_dev)
 193                         drm_helper_hpd_irq_event(hdmi->drm_dev);
 194         }
 195
 196         /* Sw reset and PLL lock are exclusive so we can use the same
 197          * event to signal them
 198          */
 199         if (hdmi->irq_status & (HDMI_INT_SW_RST | HDMI_INT_DLL_LCK)) {
 200                 hdmi->event_received = true;
 201                 wake_up_interruptible(&hdmi->wait_event);
 202         }
 203
 204         /* Audio FIFO underrun IRQ */
 205         if (hdmi->irq_status & HDMI_INT_AUDIO_FIFO_XRUN)
 206                 DRM_INFO("Warning: audio FIFO underrun occurs!\n");
 207
 208         return IRQ_HANDLED;
 209 }
 210
 211 /**
 212  * HDMI interrupt handler
 213  *
 214  * @irq: irq number
 215  * @arg: connector structure
 216  */
 217 static irqreturn_t hdmi_irq(int irq, void *arg)
 218 {
 219         struct sti_hdmi *hdmi = arg;
 220
 221         /* read interrupt status */
 222         hdmi->irq_status = hdmi_read(hdmi, HDMI_INT_STA);
 223
 224         /* clear interrupt status */
 225         hdmi_write(hdmi, hdmi->irq_status, HDMI_INT_CLR);
 226
 227         /* force sync bus write */
 228         hdmi_read(hdmi, HDMI_INT_STA);
 229
 230         return IRQ_WAKE_THREAD;
 231 }
 232
 233 /**
 234  * Set hdmi active area depending on the drm display mode selected
 235  *
 236  * @hdmi: pointer on the hdmi internal structure
 237  */
 238 static void hdmi_active_area(struct sti_hdmi *hdmi)
 239 {
 240         u32 xmin, xmax;
 241         u32 ymin, ymax;
 242
 243         xmin = sti_vtg_get_pixel_number(hdmi->mode, 1);
 244         xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay);
 245         ymin = sti_vtg_get_line_number(hdmi->mode, 0);
 246         ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1);
 247
 248         hdmi_write(hdmi, xmin, HDMI_ACTIVE_VID_XMIN);
 249         hdmi_write(hdmi, xmax, HDMI_ACTIVE_VID_XMAX);
 250         hdmi_write(hdmi, ymin, HDMI_ACTIVE_VID_YMIN);
 251         hdmi_write(hdmi, ymax, HDMI_ACTIVE_VID_YMAX);
 252 }
 253
 254 /**
 255  * Overall hdmi configuration
 256  *
 257  * @hdmi: pointer on the hdmi internal structure
 258  */
 259 static void hdmi_config(struct sti_hdmi *hdmi)
 260 {
 261         u32 conf;
 262
 263         DRM_DEBUG_DRIVER("\n");
 264
 265         /* Clear overrun and underrun fifo */
 266         conf = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR;
 267
 268         /* Select encryption type and the framing mode */
 269         conf |= HDMI_CFG_ESS_NOT_OESS;
 270         if (hdmi->hdmi_monitor)
 271                 conf |= HDMI_CFG_HDMI_NOT_DVI;
 272
 273         /* Set Hsync polarity */
 274         if (hdmi->mode.flags & DRM_MODE_FLAG_NHSYNC) {
 275                 DRM_DEBUG_DRIVER("H Sync Negative\n");
 276                 conf |= HDMI_CFG_H_SYNC_POL_NEG;
 277         }
 278
 279         /* Set Vsync polarity */
 280         if (hdmi->mode.flags & DRM_MODE_FLAG_NVSYNC) {
 281                 DRM_DEBUG_DRIVER("V Sync Negative\n");
 282                 conf |= HDMI_CFG_V_SYNC_POL_NEG;
 283         }
 284
 285         /* Enable HDMI */
 286         conf |= HDMI_CFG_DEVICE_EN;
 287
 288         hdmi_write(hdmi, conf, HDMI_CFG);
 289 }
 290
 291 /*
 292  * Helper to reset info frame
 293  *
 294  * @hdmi: pointer on the hdmi internal structure
 295  * @slot: infoframe to reset
 296  */
 297 static void hdmi_infoframe_reset(struct sti_hdmi *hdmi,
 298                                  u32 slot)
 299 {
 300         u32 val, i;
 301         u32 head_offset, pack_offset;
 302
 303         switch (slot) {
 304         case HDMI_IFRAME_SLOT_AVI:
 305                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI);
 306                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI);
 307                 break;
 308         case HDMI_IFRAME_SLOT_AUDIO:
 309                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO);
 310                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO);
 311                 break;
 312         case HDMI_IFRAME_SLOT_VENDOR:
 313                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR);
 314                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR);
 315                 break;
 316         default:
 317                 DRM_ERROR("unsupported infoframe slot: %#x\n", slot);
 318                 return;
 319         }
 320
 321         /* Disable transmission for the selected slot */
 322         val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
 323         val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot);
 324         hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
 325
 326         /* Reset info frame registers */
 327         hdmi_write(hdmi, 0x0, head_offset);
 328         for (i = 0; i < HDMI_SW_DI_MAX_WORD; i += sizeof(u32))
 329                 hdmi_write(hdmi, 0x0, pack_offset + i);
 330 }
 331
 332 /**
 333  * Helper to concatenate infoframe in 32 bits word
 334  *
 335  * @ptr: pointer on the hdmi internal structure
 336  * @data: infoframe to write
 337  * @size: size to write
 338  */
 339 static inline unsigned int hdmi_infoframe_subpack(const u8 *ptr, size_t size)
 340 {
 341         unsigned long value = 0;
 342         size_t i;
 343
 344         for (i = size; i > 0; i--)
 345                 value = (value << 8) | ptr[i - 1];
 346
 347         return value;
 348 }
 349
 350 /**
 351  * Helper to write info frame
 352  *
 353  * @hdmi: pointer on the hdmi internal structure
 354  * @data: infoframe to write
 355  * @size: size to write
 356  */
 357 static void hdmi_infoframe_write_infopack(struct sti_hdmi *hdmi,
 358                                           const u8 *data,
 359                                           size_t size)
 360 {
 361         const u8 *ptr = data;
 362         u32 val, slot, mode, i;
 363         u32 head_offset, pack_offset;
 364
 365         switch (*ptr) {
 366         case HDMI_INFOFRAME_TYPE_AVI:
 367                 slot = HDMI_IFRAME_SLOT_AVI;
 368                 mode = HDMI_IFRAME_FIELD;
 369                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI);
 370                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI);
 371                 break;
 372         case HDMI_INFOFRAME_TYPE_AUDIO:
 373                 slot = HDMI_IFRAME_SLOT_AUDIO;
 374                 mode = HDMI_IFRAME_FRAME;
 375                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO);
 376                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO);
 377                 break;
 378         case HDMI_INFOFRAME_TYPE_VENDOR:
 379                 slot = HDMI_IFRAME_SLOT_VENDOR;
 380                 mode = HDMI_IFRAME_FRAME;
 381                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR);
 382                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR);
 383                 break;
 384         default:
 385                 DRM_ERROR("unsupported infoframe type: %#x\n", *ptr);
 386                 return;
 387         }
 388
 389         /* Disable transmission slot for updated infoframe */
 390         val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
 391         val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot);
 392         hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
 393
 394         val = HDMI_INFOFRAME_HEADER_TYPE(*ptr++);
 395         val |= HDMI_INFOFRAME_HEADER_VERSION(*ptr++);
 396         val |= HDMI_INFOFRAME_HEADER_LEN(*ptr++);
 397         writel(val, hdmi->regs + head_offset);
 398
 399         /*
 400          * Each subpack contains 4 bytes
 401          * The First Bytes of the first subpacket must contain the checksum
 402          * Packet size is increase by one.
 403          */
 404         size = size - HDMI_INFOFRAME_HEADER_SIZE + 1;
 405         for (i = 0; i < size; i += sizeof(u32)) {
 406                 size_t num;
 407
 408                 num = min_t(size_t, size - i, sizeof(u32));
 409                 val = hdmi_infoframe_subpack(ptr, num);
 410                 ptr += sizeof(u32);
 411                 writel(val, hdmi->regs + pack_offset + i);
 412         }
 413
 414         /* Enable transmission slot for updated infoframe */
 415         val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
 416         val |= HDMI_IFRAME_CFG_DI_N(mode, slot);
 417         hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
 418 }
 419
 420 /**
 421  * Prepare and configure the AVI infoframe
 422  *
 423  * AVI infoframe are transmitted at least once per two video field and
 424  * contains information about HDMI transmission mode such as color space,
 425  * colorimetry, ...
 426  *
 427  * @hdmi: pointer on the hdmi internal structure
 428  *
 429  * Return negative value if error occurs
 430  */
 431 static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi)
 432 {
 433         struct drm_display_mode *mode = &hdmi->mode;
 434         struct hdmi_avi_infoframe infoframe;
 435         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
 436         int ret;
 437
 438         DRM_DEBUG_DRIVER("\n");
 439
 440         ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe,
 441                                                        hdmi->drm_connector, mode);
 442         if (ret < 0) {
 443                 DRM_ERROR("failed to setup AVI infoframe: %d\n", ret);
 444                 return ret;
 445         }
 446
 447         /* fixed infoframe configuration not linked to the mode */
 448         infoframe.colorspace = hdmi->colorspace;
 449         infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
 450         infoframe.colorimetry = HDMI_COLORIMETRY_NONE;
 451
 452         ret = hdmi_avi_infoframe_pack(&infoframe, buffer, sizeof(buffer));
 453         if (ret < 0) {
 454                 DRM_ERROR("failed to pack AVI infoframe: %d\n", ret);
 455                 return ret;
 456         }
 457
 458         hdmi_infoframe_write_infopack(hdmi, buffer, ret);
 459
 460         return 0;
 461 }
 462
 463 /**
 464  * Prepare and configure the AUDIO infoframe
 465  *
 466  * AUDIO infoframe are transmitted once per frame and
 467  * contains information about HDMI transmission mode such as audio codec,
 468  * sample size, ...
 469  *
 470  * @hdmi: pointer on the hdmi internal structure
 471  *
 472  * Return negative value if error occurs
 473  */
 474 static int hdmi_audio_infoframe_config(struct sti_hdmi *hdmi)
 475 {
 476         struct hdmi_audio_params *audio = &hdmi->audio;
 477         u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
 478         int ret, val;
 479
 480         DRM_DEBUG_DRIVER("enter %s, AIF %s\n", __func__,
 481                          audio->enabled ? "enable" : "disable");
 482         if (audio->enabled) {
 483                 /* set audio parameters stored*/
 484                 ret = hdmi_audio_infoframe_pack(&audio->cea, buffer,
 485                                                 sizeof(buffer));
 486                 if (ret < 0) {
 487                         DRM_ERROR("failed to pack audio infoframe: %d\n", ret);
 488                         return ret;
 489                 }
 490                 hdmi_infoframe_write_infopack(hdmi, buffer, ret);
 491         } else {
 492                 /*disable audio info frame transmission */
 493                 val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
 494                 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK,
 495                                              HDMI_IFRAME_SLOT_AUDIO);
 496                 hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
 497         }
 498
 499         return 0;
 500 }
 501
 502 /*
 503  * Prepare and configure the VS infoframe
 504  *
 505  * Vendor Specific infoframe are transmitted once per frame and
 506  * contains vendor specific information.
 507  *
 508  * @hdmi: pointer on the hdmi internal structure
 509  *
 510  * Return negative value if error occurs
 511  */
 512 #define HDMI_VENDOR_INFOFRAME_MAX_SIZE 6
 513 static int hdmi_vendor_infoframe_config(struct sti_hdmi *hdmi)
 514 {
 515         struct drm_display_mode *mode = &hdmi->mode;
 516         struct hdmi_vendor_infoframe infoframe;
 517         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_VENDOR_INFOFRAME_MAX_SIZE];
 518         int ret;
 519
 520         DRM_DEBUG_DRIVER("\n");
 521
 522         ret = drm_hdmi_vendor_infoframe_from_display_mode(&infoframe,
 523                                                           hdmi->drm_connector,
 524                                                           mode);
 525         if (ret < 0) {
 526                 /*
 527                  * Going into that statement does not means vendor infoframe
 528                  * fails. It just informed us that vendor infoframe is not
 529                  * needed for the selected mode. Only  4k or stereoscopic 3D
 530                  * mode requires vendor infoframe. So just simply return 0.
 531                  */
 532                 return 0;
 533         }
 534
 535         ret = hdmi_vendor_infoframe_pack(&infoframe, buffer, sizeof(buffer));
 536         if (ret < 0) {
 537                 DRM_ERROR("failed to pack VS infoframe: %d\n", ret);
 538                 return ret;
 539         }
 540
 541         hdmi_infoframe_write_infopack(hdmi, buffer, ret);
 542
 543         return 0;
 544 }
 545
 546 /**
 547  * Software reset of the hdmi subsystem
 548  *
 549  * @hdmi: pointer on the hdmi internal structure
 550  *
 551  */
 552 #define HDMI_TIMEOUT_SWRESET  100   /*milliseconds */
 553 static void hdmi_swreset(struct sti_hdmi *hdmi)
 554 {
 555         u32 val;
 556
 557         DRM_DEBUG_DRIVER("\n");
 558
 559         /* Enable hdmi_audio clock only during hdmi reset */
 560         if (clk_prepare_enable(hdmi->clk_audio))
 561                 DRM_INFO("Failed to prepare/enable hdmi_audio clk\n");
 562
 563         /* Sw reset */
 564         hdmi->event_received = false;
 565
 566         val = hdmi_read(hdmi, HDMI_CFG);
 567         val |= HDMI_CFG_SW_RST_EN;
 568         hdmi_write(hdmi, val, HDMI_CFG);
 569
 570         /* Wait reset completed */
 571         wait_event_interruptible_timeout(hdmi->wait_event,
 572                                          hdmi->event_received,
 573                                          msecs_to_jiffies
 574                                          (HDMI_TIMEOUT_SWRESET));
 575
 576         /*
 577          * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is
 578          * set to '1' and clk_audio is running.
 579          */
 580         if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_SW_RST) == 0)
 581                 DRM_DEBUG_DRIVER("Warning: HDMI sw reset timeout occurs\n");
 582
 583         val = hdmi_read(hdmi, HDMI_CFG);
 584         val &= ~HDMI_CFG_SW_RST_EN;
 585         hdmi_write(hdmi, val, HDMI_CFG);
 586
 587         /* Disable hdmi_audio clock. Not used anymore for drm purpose */
 588         clk_disable_unprepare(hdmi->clk_audio);
 589 }
 590
 591 #define DBGFS_PRINT_STR(str1, str2) seq_printf(s, "%-24s %s\n", str1, str2)
 592 #define DBGFS_PRINT_INT(str1, int2) seq_printf(s, "%-24s %d\n", str1, int2)
 593 #define DBGFS_DUMP(str, reg) seq_printf(s, "%s  %-25s 0x%08X", str, #reg, \
 594                                         hdmi_read(hdmi, reg))
 595 #define DBGFS_DUMP_DI(reg, slot) DBGFS_DUMP("\n", reg(slot))
 596
 597 static void hdmi_dbg_cfg(struct seq_file *s, int val)
 598 {
 599         int tmp;
 600
 601         seq_putc(s, '\t');
 602         tmp = val & HDMI_CFG_HDMI_NOT_DVI;
 603         DBGFS_PRINT_STR("mode:", tmp ? "HDMI" : "DVI");
 604         seq_puts(s, "\t\t\t\t\t");
 605         tmp = val & HDMI_CFG_HDCP_EN;
 606         DBGFS_PRINT_STR("HDCP:", tmp ? "enable" : "disable");
 607         seq_puts(s, "\t\t\t\t\t");
 608         tmp = val & HDMI_CFG_ESS_NOT_OESS;
 609         DBGFS_PRINT_STR("HDCP mode:", tmp ? "ESS enable" : "OESS enable");
 610         seq_puts(s, "\t\t\t\t\t");
 611         tmp = val & HDMI_CFG_H_SYNC_POL_NEG;
 612         DBGFS_PRINT_STR("Hsync polarity:", tmp ? "inverted" : "normal");
 613         seq_puts(s, "\t\t\t\t\t");
 614         tmp = val & HDMI_CFG_V_SYNC_POL_NEG;
 615         DBGFS_PRINT_STR("Vsync polarity:", tmp ? "inverted" : "normal");
 616         seq_puts(s, "\t\t\t\t\t");
 617         tmp = val & HDMI_CFG_422_EN;
 618         DBGFS_PRINT_STR("YUV422 format:", tmp ? "enable" : "disable");
 619 }
 620
 621 static void hdmi_dbg_sta(struct seq_file *s, int val)
 622 {
 623         int tmp;
 624
 625         seq_putc(s, '\t');
 626         tmp = (val & HDMI_STA_DLL_LCK);
 627         DBGFS_PRINT_STR("pll:", tmp ? "locked" : "not locked");
 628         seq_puts(s, "\t\t\t\t\t");
 629         tmp = (val & HDMI_STA_HOT_PLUG);
 630         DBGFS_PRINT_STR("hdmi cable:", tmp ? "connected" : "not connected");
 631 }
 632
 633 static void hdmi_dbg_sw_di_cfg(struct seq_file *s, int val)
 634 {
 635         int tmp;
 636         char *const en_di[] = {"no transmission",
 637                                "single transmission",
 638                                "once every field",
 639                                "once every frame"};
 640
 641         seq_putc(s, '\t');
 642         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 1));
 643         DBGFS_PRINT_STR("Data island 1:", en_di[tmp]);
 644         seq_puts(s, "\t\t\t\t\t");
 645         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 2)) >> 4;
 646         DBGFS_PRINT_STR("Data island 2:", en_di[tmp]);
 647         seq_puts(s, "\t\t\t\t\t");
 648         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 3)) >> 8;
 649         DBGFS_PRINT_STR("Data island 3:", en_di[tmp]);
 650         seq_puts(s, "\t\t\t\t\t");
 651         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 4)) >> 12;
 652         DBGFS_PRINT_STR("Data island 4:", en_di[tmp]);
 653         seq_puts(s, "\t\t\t\t\t");
 654         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 5)) >> 16;
 655         DBGFS_PRINT_STR("Data island 5:", en_di[tmp]);
 656         seq_puts(s, "\t\t\t\t\t");
 657         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 6)) >> 20;
 658         DBGFS_PRINT_STR("Data island 6:", en_di[tmp]);
 659 }
 660
 661 static int hdmi_dbg_show(struct seq_file *s, void *data)
 662 {
 663         struct drm_info_node *node = s->private;
 664         struct sti_hdmi *hdmi = (struct sti_hdmi *)node->info_ent->data;
 665
 666         seq_printf(s, "HDMI: (vaddr = 0x%p)", hdmi->regs);
 667         DBGFS_DUMP("\n", HDMI_CFG);
 668         hdmi_dbg_cfg(s, hdmi_read(hdmi, HDMI_CFG));
 669         DBGFS_DUMP("", HDMI_INT_EN);
 670         DBGFS_DUMP("\n", HDMI_STA);
 671         hdmi_dbg_sta(s, hdmi_read(hdmi, HDMI_STA));
 672         DBGFS_DUMP("", HDMI_ACTIVE_VID_XMIN);
 673         seq_putc(s, '\t');
 674         DBGFS_PRINT_INT("Xmin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMIN));
 675         DBGFS_DUMP("", HDMI_ACTIVE_VID_XMAX);
 676         seq_putc(s, '\t');
 677         DBGFS_PRINT_INT("Xmax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMAX));
 678         DBGFS_DUMP("", HDMI_ACTIVE_VID_YMIN);
 679         seq_putc(s, '\t');
 680         DBGFS_PRINT_INT("Ymin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMIN));
 681         DBGFS_DUMP("", HDMI_ACTIVE_VID_YMAX);
 682         seq_putc(s, '\t');
 683         DBGFS_PRINT_INT("Ymax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMAX));
 684         DBGFS_DUMP("", HDMI_SW_DI_CFG);
 685         hdmi_dbg_sw_di_cfg(s, hdmi_read(hdmi, HDMI_SW_DI_CFG));
 686
 687         DBGFS_DUMP("\n", HDMI_AUDIO_CFG);
 688         DBGFS_DUMP("\n", HDMI_SPDIF_FIFO_STATUS);
 689         DBGFS_DUMP("\n", HDMI_AUDN);
 690
 691         seq_printf(s, "\n AVI Infoframe (Data Island slot N=%d):",
 692                    HDMI_IFRAME_SLOT_AVI);
 693         DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AVI);
 694         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AVI);
 695         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AVI);
 696         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AVI);
 697         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AVI);
 698         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AVI);
 699         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AVI);
 700         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AVI);
 701         seq_printf(s, "\n\n AUDIO Infoframe (Data Island slot N=%d):",
 702                    HDMI_IFRAME_SLOT_AUDIO);
 703         DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AUDIO);
 704         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AUDIO);
 705         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AUDIO);
 706         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AUDIO);
 707         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AUDIO);
 708         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AUDIO);
 709         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AUDIO);
 710         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AUDIO);
 711         seq_printf(s, "\n\n VENDOR SPECIFIC Infoframe (Data Island slot N=%d):",
 712                    HDMI_IFRAME_SLOT_VENDOR);
 713         DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_VENDOR);
 714         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_VENDOR);
 715         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_VENDOR);
 716         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_VENDOR);
 717         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_VENDOR);
 718         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_VENDOR);
 719         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_VENDOR);
 720         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_VENDOR);
 721         seq_putc(s, '\n');
 722         return 0;
 723 }
 724
 725 static struct drm_info_list hdmi_debugfs_files[] = {
 726         { "hdmi", hdmi_dbg_show, 0, NULL },
 727 };
 728
 729 static int hdmi_debugfs_init(struct sti_hdmi *hdmi, struct drm_minor *minor)
 730 {
 731         unsigned int i;
 732
 733         for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_files); i++)
 734                 hdmi_debugfs_files[i].data = hdmi;
 735
 736         return drm_debugfs_create_files(hdmi_debugfs_files,
 737                                         ARRAY_SIZE(hdmi_debugfs_files),
 738                                         minor->debugfs_root, minor);
 739 }
 740
 741 static void sti_hdmi_disable(struct drm_bridge *bridge)
 742 {
 743         struct sti_hdmi *hdmi = bridge->driver_private;
 744
 745         u32 val = hdmi_read(hdmi, HDMI_CFG);
 746
 747         if (!hdmi->enabled)
 748                 return;
 749
 750         DRM_DEBUG_DRIVER("\n");
 751
 752         /* Disable HDMI */
 753         val &= ~HDMI_CFG_DEVICE_EN;
 754         hdmi_write(hdmi, val, HDMI_CFG);
 755
 756         hdmi_write(hdmi, 0xffffffff, HDMI_INT_CLR);
 757
 758         /* Stop the phy */
 759         hdmi->phy_ops->stop(hdmi);
 760
 761         /* Reset info frame transmission */
 762         hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AVI);
 763         hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AUDIO);
 764         hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_VENDOR);
 765
 766         /* Set the default channel data to be a dark red */
 767         hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL0_DAT);
 768         hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL1_DAT);
 769         hdmi_write(hdmi, 0x0060, HDMI_DFLT_CHL2_DAT);
 770
 771         /* Disable/unprepare hdmi clock */
 772         clk_disable_unprepare(hdmi->clk_phy);
 773         clk_disable_unprepare(hdmi->clk_tmds);
 774         clk_disable_unprepare(hdmi->clk_pix);
 775
 776         hdmi->enabled = false;
 777
 778         cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID);
 779 }
 780
 781 /**
 782  * sti_hdmi_audio_get_non_coherent_n() - get N parameter for non-coherent
 783  * clocks. None-coherent clocks means that audio and TMDS clocks have not the
 784  * same source (drifts between clocks). In this case assumption is that CTS is
 785  * automatically calculated by hardware.
 786  *
 787  * @audio_fs: audio frame clock frequency in Hz
 788  *
 789  * Values computed are based on table described in HDMI specification 1.4b
 790  *
 791  * Returns n value.
 792  */
 793 static int sti_hdmi_audio_get_non_coherent_n(unsigned int audio_fs)
 794 {
 795         unsigned int n;
 796
 797         switch (audio_fs) {
 798         case 32000:
 799                 n = 4096;
 800                 break;
 801         case 44100:
 802                 n = 6272;
 803                 break;
 804         case 48000:
 805                 n = 6144;
 806                 break;
 807         case 88200:
 808                 n = 6272 * 2;
 809                 break;
 810         case 96000:
 811                 n = 6144 * 2;
 812                 break;
 813         case 176400:
 814                 n = 6272 * 4;
 815                 break;
 816         case 192000:
 817                 n = 6144 * 4;
 818                 break;
 819         default:
 820                 /* Not pre-defined, recommended value: 128 * fs / 1000 */
 821                 n = (audio_fs * 128) / 1000;
 822         }
 823
 824         return n;
 825 }
 826
 827 static int hdmi_audio_configure(struct sti_hdmi *hdmi)
 828 {
 829         int audio_cfg, n;
 830         struct hdmi_audio_params *params = &hdmi->audio;
 831         struct hdmi_audio_infoframe *info = &params->cea;
 832
 833         DRM_DEBUG_DRIVER("\n");
 834
 835         if (!hdmi->enabled)
 836                 return 0;
 837
 838         /* update N parameter */
 839         n = sti_hdmi_audio_get_non_coherent_n(params->sample_rate);
 840
 841         DRM_DEBUG_DRIVER("Audio rate = %d Hz, TMDS clock = %d Hz, n = %d\n",
 842                          params->sample_rate, hdmi->mode.clock * 1000, n);
 843         hdmi_write(hdmi, n, HDMI_AUDN);
 844
 845         /* update HDMI registers according to configuration */
 846         audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID |
 847                     HDMI_AUD_CFG_ONE_BIT_INVALID;
 848
 849         switch (info->channels) {
 850         case 8:
 851                 audio_cfg |= HDMI_AUD_CFG_CH78_VALID;
 852         case 6:
 853                 audio_cfg |= HDMI_AUD_CFG_CH56_VALID;
 854         case 4:
 855                 audio_cfg |= HDMI_AUD_CFG_CH34_VALID | HDMI_AUD_CFG_8CH;
 856         case 2:
 857                 audio_cfg |= HDMI_AUD_CFG_CH12_VALID;
 858                 break;
 859         default:
 860                 DRM_ERROR("ERROR: Unsupported number of channels (%d)!\n",
 861                           info->channels);
 862                 return -EINVAL;
 863         }
 864
 865         hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG);
 866
 867         return hdmi_audio_infoframe_config(hdmi);
 868 }
 869
 870 static void sti_hdmi_pre_enable(struct drm_bridge *bridge)
 871 {
 872         struct sti_hdmi *hdmi = bridge->driver_private;
 873
 874         DRM_DEBUG_DRIVER("\n");
 875
 876         if (hdmi->enabled)
 877                 return;
 878
 879         /* Prepare/enable clocks */
 880         if (clk_prepare_enable(hdmi->clk_pix))
 881                 DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n");
 882         if (clk_prepare_enable(hdmi->clk_tmds))
 883                 DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n");
 884         if (clk_prepare_enable(hdmi->clk_phy))
 885                 DRM_ERROR("Failed to prepare/enable hdmi_rejec_pll clk\n");
 886
 887         hdmi->enabled = true;
 888
 889         /* Program hdmi serializer and start phy */
 890         if (!hdmi->phy_ops->start(hdmi)) {
 891                 DRM_ERROR("Unable to start hdmi phy\n");
 892                 return;
 893         }
 894
 895         /* Program hdmi active area */
 896         hdmi_active_area(hdmi);
 897
 898         /* Enable working interrupts */
 899         hdmi_write(hdmi, HDMI_WORKING_INT, HDMI_INT_EN);
 900
 901         /* Program hdmi config */
 902         hdmi_config(hdmi);
 903
 904         /* Program AVI infoframe */
 905         if (hdmi_avi_infoframe_config(hdmi))
 906                 DRM_ERROR("Unable to configure AVI infoframe\n");
 907
 908         if (hdmi->audio.enabled) {
 909                 if (hdmi_audio_configure(hdmi))
 910                         DRM_ERROR("Unable to configure audio\n");
 911         } else {
 912                 hdmi_audio_infoframe_config(hdmi);
 913         }
 914
 915         /* Program VS infoframe */
 916         if (hdmi_vendor_infoframe_config(hdmi))
 917                 DRM_ERROR("Unable to configure VS infoframe\n");
 918
 919         /* Sw reset */
 920         hdmi_swreset(hdmi);
 921 }
 922
 923 static void sti_hdmi_set_mode(struct drm_bridge *bridge,
 924                               const struct drm_display_mode *mode,
 925                               const struct drm_display_mode *adjusted_mode)
 926 {
 927         struct sti_hdmi *hdmi = bridge->driver_private;
 928         int ret;
 929
 930         DRM_DEBUG_DRIVER("\n");
 931
 932         /* Copy the drm display mode in the connector local structure */
 933         memcpy(&hdmi->mode, mode, sizeof(struct drm_display_mode));
 934
 935         /* Update clock framerate according to the selected mode */
 936         ret = clk_set_rate(hdmi->clk_pix, mode->clock * 1000);
 937         if (ret < 0) {
 938                 DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n",
 939                           mode->clock * 1000);
 940                 return;
 941         }
 942         ret = clk_set_rate(hdmi->clk_phy, mode->clock * 1000);
 943         if (ret < 0) {
 944                 DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n",
 945                           mode->clock * 1000);
 946                 return;
 947         }
 948 }
 949
 950 static void sti_hdmi_bridge_nope(struct drm_bridge *bridge)
 951 {
 952         /* do nothing */
 953 }
 954
 955 static const struct drm_bridge_funcs sti_hdmi_bridge_funcs = {
 956         .pre_enable = sti_hdmi_pre_enable,
 957         .enable = sti_hdmi_bridge_nope,
 958         .disable = sti_hdmi_disable,
 959         .post_disable = sti_hdmi_bridge_nope,
 960         .mode_set = sti_hdmi_set_mode,
 961 };
 962
 963 static int sti_hdmi_connector_get_modes(struct drm_connector *connector)
 964 {
 965         struct sti_hdmi_connector *hdmi_connector
 966                 = to_sti_hdmi_connector(connector);
 967         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
 968         struct edid *edid;
 969         int count;
 970
 971         DRM_DEBUG_DRIVER("\n");
 972
 973         edid = drm_get_edid(connector, hdmi->ddc_adapt);
 974         if (!edid)
 975                 goto fail;
 976
 977         hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 978         DRM_DEBUG_KMS("%s : %dx%d cm\n",
 979                       (hdmi->hdmi_monitor ? "hdmi monitor" : "dvi monitor"),
 980                       edid->width_cm, edid->height_cm);
 981         cec_notifier_set_phys_addr_from_edid(hdmi->notifier, edid);
 982
 983         count = drm_add_edid_modes(connector, edid);
 984         drm_connector_update_edid_property(connector, edid);
 985
 986         kfree(edid);
 987         return count;
 988
 989 fail:
 990         DRM_ERROR("Can't read HDMI EDID\n");
 991         return 0;
 992 }
 993
 994 #define CLK_TOLERANCE_HZ 50
 995
 996 static int sti_hdmi_connector_mode_valid(struct drm_connector *connector,
 997                                         struct drm_display_mode *mode)
 998 {
 999         int target = mode->clock * 1000;
1000         int target_min = target - CLK_TOLERANCE_HZ;
1001         int target_max = target + CLK_TOLERANCE_HZ;
1002         int result;
1003         struct sti_hdmi_connector *hdmi_connector
1004                 = to_sti_hdmi_connector(connector);
1005         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1006
1007
1008         result = clk_round_rate(hdmi->clk_pix, target);
1009
1010         DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
1011                          target, result);
1012
1013         if ((result < target_min) || (result > target_max)) {
1014                 DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target);
1015                 return MODE_BAD;
1016         }
1017
1018         return MODE_OK;
1019 }
1020
1021 static const
1022 struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs = {
1023         .get_modes = sti_hdmi_connector_get_modes,
1024         .mode_valid = sti_hdmi_connector_mode_valid,
1025 };
1026
1027 /* get detection status of display device */
1028 static enum drm_connector_status
1029 sti_hdmi_connector_detect(struct drm_connector *connector, bool force)
1030 {
1031         struct sti_hdmi_connector *hdmi_connector
1032                 = to_sti_hdmi_connector(connector);
1033         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1034
1035         DRM_DEBUG_DRIVER("\n");
1036
1037         if (hdmi->hpd) {
1038                 DRM_DEBUG_DRIVER("hdmi cable connected\n");
1039                 return connector_status_connected;
1040         }
1041
1042         DRM_DEBUG_DRIVER("hdmi cable disconnected\n");
1043         cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID);
1044         return connector_status_disconnected;
1045 }
1046
1047 static void sti_hdmi_connector_init_property(struct drm_device *drm_dev,
1048                                              struct drm_connector *connector)
1049 {
1050         struct sti_hdmi_connector *hdmi_connector
1051                 = to_sti_hdmi_connector(connector);
1052         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1053         struct drm_property *prop;
1054
1055         /* colorspace property */
1056         hdmi->colorspace = DEFAULT_COLORSPACE_MODE;
1057         prop = drm_property_create_enum(drm_dev, 0, "colorspace",
1058                                         colorspace_mode_names,
1059                                         ARRAY_SIZE(colorspace_mode_names));
1060         if (!prop) {
1061                 DRM_ERROR("fails to create colorspace property\n");
1062                 return;
1063         }
1064         hdmi_connector->colorspace_property = prop;
1065         drm_object_attach_property(&connector->base, prop, hdmi->colorspace);
1066 }
1067
1068 static int
1069 sti_hdmi_connector_set_property(struct drm_connector *connector,
1070                                 struct drm_connector_state *state,
1071                                 struct drm_property *property,
1072                                 uint64_t val)
1073 {
1074         struct sti_hdmi_connector *hdmi_connector
1075                 = to_sti_hdmi_connector(connector);
1076         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1077
1078         if (property == hdmi_connector->colorspace_property) {
1079                 hdmi->colorspace = val;
1080                 return 0;
1081         }
1082
1083         DRM_ERROR("failed to set hdmi connector property\n");
1084         return -EINVAL;
1085 }
1086
1087 static int
1088 sti_hdmi_connector_get_property(struct drm_connector *connector,
1089                                 const struct drm_connector_state *state,
1090                                 struct drm_property *property,
1091                                 uint64_t *val)
1092 {
1093         struct sti_hdmi_connector *hdmi_connector
1094                 = to_sti_hdmi_connector(connector);
1095         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1096
1097         if (property == hdmi_connector->colorspace_property) {
1098                 *val = hdmi->colorspace;
1099                 return 0;
1100         }
1101
1102         DRM_ERROR("failed to get hdmi connector property\n");
1103         return -EINVAL;
1104 }
1105
1106 static int sti_hdmi_late_register(struct drm_connector *connector)
1107 {
1108         struct sti_hdmi_connector *hdmi_connector
1109                 = to_sti_hdmi_connector(connector);
1110         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1111
1112         if (hdmi_debugfs_init(hdmi, hdmi->drm_dev->primary)) {
1113                 DRM_ERROR("HDMI debugfs setup failed\n");
1114                 return -EINVAL;
1115         }
1116
1117         return 0;
1118 }
1119
1120 static const struct drm_connector_funcs sti_hdmi_connector_funcs = {
1121         .fill_modes = drm_helper_probe_single_connector_modes,
1122         .detect = sti_hdmi_connector_detect,
1123         .destroy = drm_connector_cleanup,
1124         .reset = drm_atomic_helper_connector_reset,
1125         .atomic_set_property = sti_hdmi_connector_set_property,
1126         .atomic_get_property = sti_hdmi_connector_get_property,
1127         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1128         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1129         .late_register = sti_hdmi_late_register,
1130 };
1131
1132 static struct drm_encoder *sti_hdmi_find_encoder(struct drm_device *dev)
1133 {
1134         struct drm_encoder *encoder;
1135
1136         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1137                 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1138                         return encoder;
1139         }
1140
1141         return NULL;
1142 }
1143
1144 static void hdmi_audio_shutdown(struct device *dev, void *data)
1145 {
1146         struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1147         int audio_cfg;
1148
1149         DRM_DEBUG_DRIVER("\n");
1150
1151         /* disable audio */
1152         audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID |
1153                     HDMI_AUD_CFG_ONE_BIT_INVALID;
1154         hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG);
1155
1156         hdmi->audio.enabled = false;
1157         hdmi_audio_infoframe_config(hdmi);
1158 }
1159
1160 static int hdmi_audio_hw_params(struct device *dev,
1161                                 void *data,
1162                                 struct hdmi_codec_daifmt *daifmt,
1163                                 struct hdmi_codec_params *params)
1164 {
1165         struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1166         int ret;
1167
1168         DRM_DEBUG_DRIVER("\n");
1169
1170         if ((daifmt->fmt != HDMI_I2S) || daifmt->bit_clk_inv ||
1171             daifmt->frame_clk_inv || daifmt->bit_clk_master ||
1172             daifmt->frame_clk_master) {
1173                 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1174                         daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1175                         daifmt->bit_clk_master,
1176                         daifmt->frame_clk_master);
1177                 return -EINVAL;
1178         }
1179
1180         hdmi->audio.sample_width = params->sample_width;
1181         hdmi->audio.sample_rate = params->sample_rate;
1182         hdmi->audio.cea = params->cea;
1183
1184         hdmi->audio.enabled = true;
1185
1186         ret = hdmi_audio_configure(hdmi);
1187         if (ret < 0)
1188                 return ret;
1189
1190         return 0;
1191 }
1192
1193 static int hdmi_audio_digital_mute(struct device *dev, void *data, bool enable)
1194 {
1195         struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1196
1197         DRM_DEBUG_DRIVER("%s\n", enable ? "enable" : "disable");
1198
1199         if (enable)
1200                 hdmi_write(hdmi, HDMI_SAMPLE_FLAT_ALL, HDMI_SAMPLE_FLAT_MASK);
1201         else
1202                 hdmi_write(hdmi, HDMI_SAMPLE_FLAT_NO, HDMI_SAMPLE_FLAT_MASK);
1203
1204         return 0;
1205 }
1206
1207 static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1208 {
1209         struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1210         struct drm_connector *connector = hdmi->drm_connector;
1211
1212         DRM_DEBUG_DRIVER("\n");
1213         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1214
1215         return 0;
1216 }
1217
1218 static const struct hdmi_codec_ops audio_codec_ops = {
1219         .hw_params = hdmi_audio_hw_params,
1220         .audio_shutdown = hdmi_audio_shutdown,
1221         .digital_mute = hdmi_audio_digital_mute,
1222         .get_eld = hdmi_audio_get_eld,
1223 };
1224
1225 static int sti_hdmi_register_audio_driver(struct device *dev,
1226                                           struct sti_hdmi *hdmi)
1227 {
1228         struct hdmi_codec_pdata codec_data = {
1229                 .ops = &audio_codec_ops,
1230                 .max_i2s_channels = 8,
1231                 .i2s = 1,
1232         };
1233
1234         DRM_DEBUG_DRIVER("\n");
1235
1236         hdmi->audio.enabled = false;
1237
1238         hdmi->audio_pdev = platform_device_register_data(
1239                 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1240                 &codec_data, sizeof(codec_data));
1241
1242         if (IS_ERR(hdmi->audio_pdev))
1243                 return PTR_ERR(hdmi->audio_pdev);
1244
1245         DRM_INFO("%s Driver bound %s\n", HDMI_CODEC_DRV_NAME, dev_name(dev));
1246
1247         return 0;
1248 }
1249
1250 static int sti_hdmi_bind(struct device *dev, struct device *master, void *data)
1251 {
1252         struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1253         struct drm_device *drm_dev = data;
1254         struct drm_encoder *encoder;
1255         struct sti_hdmi_connector *connector;
1256         struct drm_connector *drm_connector;
1257         struct drm_bridge *bridge;
1258         int err;
1259
1260         /* Set the drm device handle */
1261         hdmi->drm_dev = drm_dev;
1262
1263         encoder = sti_hdmi_find_encoder(drm_dev);
1264         if (!encoder)
1265                 return -EINVAL;
1266
1267         connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
1268         if (!connector)
1269                 return -EINVAL;
1270
1271         connector->hdmi = hdmi;
1272
1273         bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
1274         if (!bridge)
1275                 return -EINVAL;
1276
1277         bridge->driver_private = hdmi;
1278         bridge->funcs = &sti_hdmi_bridge_funcs;
1279         drm_bridge_attach(encoder, bridge, NULL);
1280
1281         connector->encoder = encoder;
1282
1283         drm_connector = (struct drm_connector *)connector;
1284
1285         drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
1286
1287         drm_connector_init(drm_dev, drm_connector,
1288                         &sti_hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
1289         drm_connector_helper_add(drm_connector,
1290                         &sti_hdmi_connector_helper_funcs);
1291
1292         /* initialise property */
1293         sti_hdmi_connector_init_property(drm_dev, drm_connector);
1294
1295         hdmi->drm_connector = drm_connector;
1296
1297         err = drm_connector_attach_encoder(drm_connector, encoder);
1298         if (err) {
1299                 DRM_ERROR("Failed to attach a connector to a encoder\n");
1300                 goto err_sysfs;
1301         }
1302
1303         err = sti_hdmi_register_audio_driver(dev, hdmi);
1304         if (err) {
1305                 DRM_ERROR("Failed to attach an audio codec\n");
1306                 goto err_sysfs;
1307         }
1308
1309         /* Initialize audio infoframe */
1310         err = hdmi_audio_infoframe_init(&hdmi->audio.cea);
1311         if (err) {
1312                 DRM_ERROR("Failed to init audio infoframe\n");
1313                 goto err_sysfs;
1314         }
1315
1316         /* Enable default interrupts */
1317         hdmi_write(hdmi, HDMI_DEFAULT_INT, HDMI_INT_EN);
1318
1319         return 0;
1320
1321 err_sysfs:
1322         hdmi->drm_connector = NULL;
1323         return -EINVAL;
1324 }
1325
1326 static void sti_hdmi_unbind(struct device *dev,
1327                 struct device *master, void *data)
1328 {
1329 }
1330
1331 static const struct component_ops sti_hdmi_ops = {
1332         .bind = sti_hdmi_bind,
1333         .unbind = sti_hdmi_unbind,
1334 };
1335
1336 static const struct of_device_id hdmi_of_match[] = {
1337         {
1338                 .compatible = "st,stih407-hdmi",
1339                 .data = &tx3g4c28phy_ops,
1340         }, {
1341                 /* end node */
1342         }
1343 };
1344 MODULE_DEVICE_TABLE(of, hdmi_of_match);
1345
1346 static int sti_hdmi_probe(struct platform_device *pdev)
1347 {
1348         struct device *dev = &pdev->dev;
1349         struct sti_hdmi *hdmi;
1350         struct device_node *np = dev->of_node;
1351         struct resource *res;
1352         struct device_node *ddc;
1353         int ret;
1354
1355         DRM_INFO("%s\n", __func__);
1356
1357         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1358         if (!hdmi)
1359                 return -ENOMEM;
1360
1361         ddc = of_parse_phandle(pdev->dev.of_node, "ddc", 0);
1362         if (ddc) {
1363                 hdmi->ddc_adapt = of_get_i2c_adapter_by_node(ddc);
1364                 of_node_put(ddc);
1365                 if (!hdmi->ddc_adapt)
1366                         return -EPROBE_DEFER;
1367         }
1368
1369         hdmi->dev = pdev->dev;
1370
1371         /* Get resources */
1372         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi-reg");
1373         if (!res) {
1374                 DRM_ERROR("Invalid hdmi resource\n");
1375                 ret = -ENOMEM;
1376                 goto release_adapter;
1377         }
1378         hdmi->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
1379         if (!hdmi->regs) {
1380                 ret = -ENOMEM;
1381                 goto release_adapter;
1382         }
1383
1384         hdmi->phy_ops = (struct hdmi_phy_ops *)
1385                 of_match_node(hdmi_of_match, np)->data;
1386
1387         /* Get clock resources */
1388         hdmi->clk_pix = devm_clk_get(dev, "pix");
1389         if (IS_ERR(hdmi->clk_pix)) {
1390                 DRM_ERROR("Cannot get hdmi_pix clock\n");
1391                 ret = PTR_ERR(hdmi->clk_pix);
1392                 goto release_adapter;
1393         }
1394
1395         hdmi->clk_tmds = devm_clk_get(dev, "tmds");
1396         if (IS_ERR(hdmi->clk_tmds)) {
1397                 DRM_ERROR("Cannot get hdmi_tmds clock\n");
1398                 ret = PTR_ERR(hdmi->clk_tmds);
1399                 goto release_adapter;
1400         }
1401
1402         hdmi->clk_phy = devm_clk_get(dev, "phy");
1403         if (IS_ERR(hdmi->clk_phy)) {
1404                 DRM_ERROR("Cannot get hdmi_phy clock\n");
1405                 ret = PTR_ERR(hdmi->clk_phy);
1406                 goto release_adapter;
1407         }
1408
1409         hdmi->clk_audio = devm_clk_get(dev, "audio");
1410         if (IS_ERR(hdmi->clk_audio)) {
1411                 DRM_ERROR("Cannot get hdmi_audio clock\n");
1412                 ret = PTR_ERR(hdmi->clk_audio);
1413                 goto release_adapter;
1414         }
1415
1416         hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
1417
1418         init_waitqueue_head(&hdmi->wait_event);
1419
1420         hdmi->irq = platform_get_irq_byname(pdev, "irq");
1421         if (hdmi->irq < 0) {
1422                 DRM_ERROR("Cannot get HDMI irq\n");
1423                 ret = hdmi->irq;
1424                 goto release_adapter;
1425         }
1426
1427         ret = devm_request_threaded_irq(dev, hdmi->irq, hdmi_irq,
1428                         hdmi_irq_thread, IRQF_ONESHOT, dev_name(dev), hdmi);
1429         if (ret) {
1430                 DRM_ERROR("Failed to register HDMI interrupt\n");
1431                 goto release_adapter;
1432         }
1433
1434         hdmi->notifier = cec_notifier_get(&pdev->dev);
1435         if (!hdmi->notifier)
1436                 goto release_adapter;
1437
1438         hdmi->reset = devm_reset_control_get(dev, "hdmi");
1439         /* Take hdmi out of reset */
1440         if (!IS_ERR(hdmi->reset))
1441                 reset_control_deassert(hdmi->reset);
1442
1443         platform_set_drvdata(pdev, hdmi);
1444
1445         return component_add(&pdev->dev, &sti_hdmi_ops);
1446
1447  release_adapter:
1448         i2c_put_adapter(hdmi->ddc_adapt);
1449
1450         return ret;
1451 }
1452
1453 static int sti_hdmi_remove(struct platform_device *pdev)
1454 {
1455         struct sti_hdmi *hdmi = dev_get_drvdata(&pdev->dev);
1456
1457         cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID);
1458
1459         i2c_put_adapter(hdmi->ddc_adapt);
1460         if (hdmi->audio_pdev)
1461                 platform_device_unregister(hdmi->audio_pdev);
1462         component_del(&pdev->dev, &sti_hdmi_ops);
1463
1464         cec_notifier_put(hdmi->notifier);
1465         return 0;
1466 }
1467
1468 struct platform_driver sti_hdmi_driver = {
1469         .driver = {
1470                 .name = "sti-hdmi",
1471                 .owner = THIS_MODULE,
1472                 .of_match_table = hdmi_of_match,
1473         },
1474         .probe = sti_hdmi_probe,
1475         .remove = sti_hdmi_remove,
1476 };
1477
1478 MODULE_AUTHOR("Benjamin Gaignard <[email protected]>");
1479 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
1480 MODULE_LICENSE("GPL");