drivers/acpi/cppc_acpi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
   4  *
   5  * (C) Copyright 2014, 2015 Linaro Ltd.
   6  * Author: Ashwin Chaugule <[email protected]>
   7  *
   8  * CPPC describes a few methods for controlling CPU performance using
   9  * information from a per CPU table called CPC. This table is described in
  10  * the ACPI v5.0+ specification. The table consists of a list of
  11  * registers which may be memory mapped or hardware registers and also may
  12  * include some static integer values.
  13  *
  14  * CPU performance is on an abstract continuous scale as against a discretized
  15  * P-state scale which is tied to CPU frequency only. In brief, the basic
  16  * operation involves:
  17  *
  18  * - OS makes a CPU performance request. (Can provide min and max bounds)
  19  *
  20  * - Platform (such as BMC) is free to optimize request within requested bounds
  21  *   depending on power/thermal budgets etc.
  22  *
  23  * - Platform conveys its decision back to OS
  24  *
  25  * The communication between OS and platform occurs through another medium
  26  * called (PCC) Platform Communication Channel. This is a generic mailbox like
  27  * mechanism which includes doorbell semantics to indicate register updates.
  28  * See drivers/mailbox/pcc.c for details on PCC.
  29  *
  30  * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
  31  * above specifications.
  32  */
  33
  34 #define pr_fmt(fmt)     "ACPI CPPC: " fmt
  35
  36 #include <linux/cpufreq.h>
  37 #include <linux/delay.h>
  38 #include <linux/iopoll.h>
  39 #include <linux/ktime.h>
  40 #include <linux/rwsem.h>
  41 #include <linux/wait.h>
  42 #include <linux/topology.h>
  43
  44 #include <acpi/cppc_acpi.h>
  45
  46 struct cppc_pcc_data {
  47         struct mbox_chan *pcc_channel;
  48         void __iomem *pcc_comm_addr;
  49         bool pcc_channel_acquired;
  50         unsigned int deadline_us;
  51         unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
  52
  53         bool pending_pcc_write_cmd;     /* Any pending/batched PCC write cmds? */
  54         bool platform_owns_pcc;         /* Ownership of PCC subspace */
  55         unsigned int pcc_write_cnt;     /* Running count of PCC write commands */
  56
  57         /*
  58          * Lock to provide controlled access to the PCC channel.
  59          *
  60          * For performance critical usecases(currently cppc_set_perf)
  61          *      We need to take read_lock and check if channel belongs to OSPM
  62          * before reading or writing to PCC subspace
  63          *      We need to take write_lock before transferring the channel
  64          * ownership to the platform via a Doorbell
  65          *      This allows us to batch a number of CPPC requests if they happen
  66          * to originate in about the same time
  67          *
  68          * For non-performance critical usecases(init)
  69          *      Take write_lock for all purposes which gives exclusive access
  70          */
  71         struct rw_semaphore pcc_lock;
  72
  73         /* Wait queue for CPUs whose requests were batched */
  74         wait_queue_head_t pcc_write_wait_q;
  75         ktime_t last_cmd_cmpl_time;
  76         ktime_t last_mpar_reset;
  77         int mpar_count;
  78         int refcount;
  79 };
  80
  81 /* Array to represent the PCC channel per subspace ID */
  82 static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
  83 /* The cpu_pcc_subspace_idx contains per CPU subspace ID */
  84 static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
  85
  86 /*
  87  * The cpc_desc structure contains the ACPI register details
  88  * as described in the per CPU _CPC tables. The details
  89  * include the type of register (e.g. PCC, System IO, FFH etc.)
  90  * and destination addresses which lets us READ/WRITE CPU performance
  91  * information using the appropriate I/O methods.
  92  */
  93 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
  94
  95 /* pcc mapped address + header size + offset within PCC subspace */
  96 #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
  97                                                 0x8 + (offs))
  98
  99 /* Check if a CPC register is in PCC */
 100 #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER &&             \
 101                                 (cpc)->cpc_entry.reg.space_id ==        \
 102                                 ACPI_ADR_SPACE_PLATFORM_COMM)
 103
 104 /* Evaluates to True if reg is a NULL register descriptor */
 105 #define IS_NULL_REG(reg) ((reg)->space_id ==  ACPI_ADR_SPACE_SYSTEM_MEMORY && \
 106                                 (reg)->address == 0 &&                  \
 107                                 (reg)->bit_width == 0 &&                \
 108                                 (reg)->bit_offset == 0 &&               \
 109                                 (reg)->access_width == 0)
 110
 111 /* Evaluates to True if an optional cpc field is supported */
 112 #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ?          \
 113                                 !!(cpc)->cpc_entry.int_value :          \
 114                                 !IS_NULL_REG(&(cpc)->cpc_entry.reg))
 115 /*
 116  * Arbitrary Retries in case the remote processor is slow to respond
 117  * to PCC commands. Keeping it high enough to cover emulators where
 118  * the processors run painfully slow.
 119  */
 120 #define NUM_RETRIES 500ULL
 121
 122 struct cppc_attr {
 123         struct attribute attr;
 124         ssize_t (*show)(struct kobject *kobj,
 125                         struct attribute *attr, char *buf);
 126         ssize_t (*store)(struct kobject *kobj,
 127                         struct attribute *attr, const char *c, ssize_t count);
 128 };
 129
 130 #define define_one_cppc_ro(_name)               \
 131 static struct cppc_attr _name =                 \
 132 __ATTR(_name, 0444, show_##_name, NULL)
 133
 134 #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
 135
 136 #define show_cppc_data(access_fn, struct_name, member_name)             \
 137         static ssize_t show_##member_name(struct kobject *kobj,         \
 138                                         struct attribute *attr, char *buf) \
 139         {                                                               \
 140                 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);           \
 141                 struct struct_name st_name = {0};                       \
 142                 int ret;                                                \
 143                                                                         \
 144                 ret = access_fn(cpc_ptr->cpu_id, &st_name);             \
 145                 if (ret)                                                \
 146                         return ret;                                     \
 147                                                                         \
 148                 return scnprintf(buf, PAGE_SIZE, "%llu\n",              \
 149                                 (u64)st_name.member_name);              \
 150         }                                                               \
 151         define_one_cppc_ro(member_name)
 152
 153 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
 154 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
 155 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
 156 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
 157 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
 158 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
 159
 160 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
 161 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
 162
 163 static ssize_t show_feedback_ctrs(struct kobject *kobj,
 164                 struct attribute *attr, char *buf)
 165 {
 166         struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
 167         struct cppc_perf_fb_ctrs fb_ctrs = {0};
 168         int ret;
 169
 170         ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
 171         if (ret)
 172                 return ret;
 173
 174         return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n",
 175                         fb_ctrs.reference, fb_ctrs.delivered);
 176 }
 177 define_one_cppc_ro(feedback_ctrs);
 178
 179 static struct attribute *cppc_attrs[] = {
 180         &feedback_ctrs.attr,
 181         &reference_perf.attr,
 182         &wraparound_time.attr,
 183         &highest_perf.attr,
 184         &lowest_perf.attr,
 185         &lowest_nonlinear_perf.attr,
 186         &nominal_perf.attr,
 187         &nominal_freq.attr,
 188         &lowest_freq.attr,
 189         NULL
 190 };
 191
 192 static struct kobj_type cppc_ktype = {
 193         .sysfs_ops = &kobj_sysfs_ops,
 194         .default_attrs = cppc_attrs,
 195 };
 196
 197 static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
 198 {
 199         int ret, status;
 200         struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
 201         struct acpi_pcct_shared_memory __iomem *generic_comm_base =
 202                 pcc_ss_data->pcc_comm_addr;
 203
 204         if (!pcc_ss_data->platform_owns_pcc)
 205                 return 0;
 206
 207         /*
 208          * Poll PCC status register every 3us(delay_us) for maximum of
 209          * deadline_us(timeout_us) until PCC command complete bit is set(cond)
 210          */
 211         ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,
 212                                         status & PCC_CMD_COMPLETE_MASK, 3,
 213                                         pcc_ss_data->deadline_us);
 214
 215         if (likely(!ret)) {
 216                 pcc_ss_data->platform_owns_pcc = false;
 217                 if (chk_err_bit && (status & PCC_ERROR_MASK))
 218                         ret = -EIO;
 219         }
 220
 221         if (unlikely(ret))
 222                 pr_err("PCC check channel failed for ss: %d. ret=%d\n",
 223                        pcc_ss_id, ret);
 224
 225         return ret;
 226 }
 227
 228 /*
 229  * This function transfers the ownership of the PCC to the platform
 230  * So it must be called while holding write_lock(pcc_lock)
 231  */
 232 static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
 233 {
 234         int ret = -EIO, i;
 235         struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
 236         struct acpi_pcct_shared_memory __iomem *generic_comm_base =
 237                 pcc_ss_data->pcc_comm_addr;
 238         unsigned int time_delta;
 239
 240         /*
 241          * For CMD_WRITE we know for a fact the caller should have checked
 242          * the channel before writing to PCC space
 243          */
 244         if (cmd == CMD_READ) {
 245                 /*
 246                  * If there are pending cpc_writes, then we stole the channel
 247                  * before write completion, so first send a WRITE command to
 248                  * platform
 249                  */
 250                 if (pcc_ss_data->pending_pcc_write_cmd)
 251                         send_pcc_cmd(pcc_ss_id, CMD_WRITE);
 252
 253                 ret = check_pcc_chan(pcc_ss_id, false);
 254                 if (ret)
 255                         goto end;
 256         } else /* CMD_WRITE */
 257                 pcc_ss_data->pending_pcc_write_cmd = FALSE;
 258
 259         /*
 260          * Handle the Minimum Request Turnaround Time(MRTT)
 261          * "The minimum amount of time that OSPM must wait after the completion
 262          * of a command before issuing the next command, in microseconds"
 263          */
 264         if (pcc_ss_data->pcc_mrtt) {
 265                 time_delta = ktime_us_delta(ktime_get(),
 266                                             pcc_ss_data->last_cmd_cmpl_time);
 267                 if (pcc_ss_data->pcc_mrtt > time_delta)
 268                         udelay(pcc_ss_data->pcc_mrtt - time_delta);
 269         }
 270
 271         /*
 272          * Handle the non-zero Maximum Periodic Access Rate(MPAR)
 273          * "The maximum number of periodic requests that the subspace channel can
 274          * support, reported in commands per minute. 0 indicates no limitation."
 275          *
 276          * This parameter should be ideally zero or large enough so that it can
 277          * handle maximum number of requests that all the cores in the system can
 278          * collectively generate. If it is not, we will follow the spec and just
 279          * not send the request to the platform after hitting the MPAR limit in
 280          * any 60s window
 281          */
 282         if (pcc_ss_data->pcc_mpar) {
 283                 if (pcc_ss_data->mpar_count == 0) {
 284                         time_delta = ktime_ms_delta(ktime_get(),
 285                                                     pcc_ss_data->last_mpar_reset);
 286                         if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
 287                                 pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",
 288                                          pcc_ss_id);
 289                                 ret = -EIO;
 290                                 goto end;
 291                         }
 292                         pcc_ss_data->last_mpar_reset = ktime_get();
 293                         pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
 294                 }
 295                 pcc_ss_data->mpar_count--;
 296         }
 297
 298         /* Write to the shared comm region. */
 299         writew_relaxed(cmd, &generic_comm_base->command);
 300
 301         /* Flip CMD COMPLETE bit */
 302         writew_relaxed(0, &generic_comm_base->status);
 303
 304         pcc_ss_data->platform_owns_pcc = true;
 305
 306         /* Ring doorbell */
 307         ret = mbox_send_message(pcc_ss_data->pcc_channel, &cmd);
 308         if (ret < 0) {
 309                 pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
 310                        pcc_ss_id, cmd, ret);
 311                 goto end;
 312         }
 313
 314         /* wait for completion and check for PCC errro bit */
 315         ret = check_pcc_chan(pcc_ss_id, true);
 316
 317         if (pcc_ss_data->pcc_mrtt)
 318                 pcc_ss_data->last_cmd_cmpl_time = ktime_get();
 319
 320         if (pcc_ss_data->pcc_channel->mbox->txdone_irq)
 321                 mbox_chan_txdone(pcc_ss_data->pcc_channel, ret);
 322         else
 323                 mbox_client_txdone(pcc_ss_data->pcc_channel, ret);
 324
 325 end:
 326         if (cmd == CMD_WRITE) {
 327                 if (unlikely(ret)) {
 328                         for_each_possible_cpu(i) {
 329                                 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
 330
 331                                 if (!desc)
 332                                         continue;
 333
 334                                 if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
 335                                         desc->write_cmd_status = ret;
 336                         }
 337                 }
 338                 pcc_ss_data->pcc_write_cnt++;
 339                 wake_up_all(&pcc_ss_data->pcc_write_wait_q);
 340         }
 341
 342         return ret;
 343 }
 344
 345 static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
 346 {
 347         if (ret < 0)
 348                 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
 349                                 *(u16 *)msg, ret);
 350         else
 351                 pr_debug("TX completed. CMD sent:%x, ret:%d\n",
 352                                 *(u16 *)msg, ret);
 353 }
 354
 355 static struct mbox_client cppc_mbox_cl = {
 356         .tx_done = cppc_chan_tx_done,
 357         .knows_txdone = true,
 358 };
 359
 360 static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
 361 {
 362         int result = -EFAULT;
 363         acpi_status status = AE_OK;
 364         struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
 365         struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
 366         struct acpi_buffer state = {0, NULL};
 367         union acpi_object  *psd = NULL;
 368         struct acpi_psd_package *pdomain;
 369
 370         status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
 371                                             &buffer, ACPI_TYPE_PACKAGE);
 372         if (status == AE_NOT_FOUND)     /* _PSD is optional */
 373                 return 0;
 374         if (ACPI_FAILURE(status))
 375                 return -ENODEV;
 376
 377         psd = buffer.pointer;
 378         if (!psd || psd->package.count != 1) {
 379                 pr_debug("Invalid _PSD data\n");
 380                 goto end;
 381         }
 382
 383         pdomain = &(cpc_ptr->domain_info);
 384
 385         state.length = sizeof(struct acpi_psd_package);
 386         state.pointer = pdomain;
 387
 388         status = acpi_extract_package(&(psd->package.elements[0]),
 389                 &format, &state);
 390         if (ACPI_FAILURE(status)) {
 391                 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
 392                 goto end;
 393         }
 394
 395         if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
 396                 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
 397                 goto end;
 398         }
 399
 400         if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
 401                 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
 402                 goto end;
 403         }
 404
 405         if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
 406             pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
 407             pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
 408                 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
 409                 goto end;
 410         }
 411
 412         result = 0;
 413 end:
 414         kfree(buffer.pointer);
 415         return result;
 416 }
 417
 418 bool acpi_cpc_valid(void)
 419 {
 420         struct cpc_desc *cpc_ptr;
 421         int cpu;
 422
 423         for_each_possible_cpu(cpu) {
 424                 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
 425                 if (!cpc_ptr)
 426                         return false;
 427         }
 428
 429         return true;
 430 }
 431 EXPORT_SYMBOL_GPL(acpi_cpc_valid);
 432
 433 /**
 434  * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu
 435  * @cpu: Find all CPUs that share a domain with cpu.
 436  * @cpu_data: Pointer to CPU specific CPPC data including PSD info.
 437  *
 438  *      Return: 0 for success or negative value for err.
 439  */
 440 int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data)
 441 {
 442         struct cpc_desc *cpc_ptr, *match_cpc_ptr;
 443         struct acpi_psd_package *match_pdomain;
 444         struct acpi_psd_package *pdomain;
 445         int count_target, i;
 446
 447         /*
 448          * Now that we have _PSD data from all CPUs, let's setup P-state
 449          * domain info.
 450          */
 451         cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
 452         if (!cpc_ptr)
 453                 return -EFAULT;
 454
 455         pdomain = &(cpc_ptr->domain_info);
 456         cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
 457         if (pdomain->num_processors <= 1)
 458                 return 0;
 459
 460         /* Validate the Domain info */
 461         count_target = pdomain->num_processors;
 462         if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
 463                 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL;
 464         else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
 465                 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW;
 466         else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
 467                 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY;
 468
 469         for_each_possible_cpu(i) {
 470                 if (i == cpu)
 471                         continue;
 472
 473                 match_cpc_ptr = per_cpu(cpc_desc_ptr, i);
 474                 if (!match_cpc_ptr)
 475                         goto err_fault;
 476
 477                 match_pdomain = &(match_cpc_ptr->domain_info);
 478                 if (match_pdomain->domain != pdomain->domain)
 479                         continue;
 480
 481                 /* Here i and cpu are in the same domain */
 482                 if (match_pdomain->num_processors != count_target)
 483                         goto err_fault;
 484
 485                 if (pdomain->coord_type != match_pdomain->coord_type)
 486                         goto err_fault;
 487
 488                 cpumask_set_cpu(i, cpu_data->shared_cpu_map);
 489         }
 490
 491         return 0;
 492
 493 err_fault:
 494         /* Assume no coordination on any error parsing domain info */
 495         cpumask_clear(cpu_data->shared_cpu_map);
 496         cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
 497         cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE;
 498
 499         return -EFAULT;
 500 }
 501 EXPORT_SYMBOL_GPL(acpi_get_psd_map);
 502
 503 static int register_pcc_channel(int pcc_ss_idx)
 504 {
 505         struct acpi_pcct_hw_reduced *cppc_ss;
 506         u64 usecs_lat;
 507
 508         if (pcc_ss_idx >= 0) {
 509                 pcc_data[pcc_ss_idx]->pcc_channel =
 510                         pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
 511
 512                 if (IS_ERR(pcc_data[pcc_ss_idx]->pcc_channel)) {
 513                         pr_err("Failed to find PCC channel for subspace %d\n",
 514                                pcc_ss_idx);
 515                         return -ENODEV;
 516                 }
 517
 518                 /*
 519                  * The PCC mailbox controller driver should
 520                  * have parsed the PCCT (global table of all
 521                  * PCC channels) and stored pointers to the
 522                  * subspace communication region in con_priv.
 523                  */
 524                 cppc_ss = (pcc_data[pcc_ss_idx]->pcc_channel)->con_priv;
 525
 526                 if (!cppc_ss) {
 527                         pr_err("No PCC subspace found for %d CPPC\n",
 528                                pcc_ss_idx);
 529                         return -ENODEV;
 530                 }
 531
 532                 /*
 533                  * cppc_ss->latency is just a Nominal value. In reality
 534                  * the remote processor could be much slower to reply.
 535                  * So add an arbitrary amount of wait on top of Nominal.
 536                  */
 537                 usecs_lat = NUM_RETRIES * cppc_ss->latency;
 538                 pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
 539                 pcc_data[pcc_ss_idx]->pcc_mrtt = cppc_ss->min_turnaround_time;
 540                 pcc_data[pcc_ss_idx]->pcc_mpar = cppc_ss->max_access_rate;
 541                 pcc_data[pcc_ss_idx]->pcc_nominal = cppc_ss->latency;
 542
 543                 pcc_data[pcc_ss_idx]->pcc_comm_addr =
 544                         acpi_os_ioremap(cppc_ss->base_address, cppc_ss->length);
 545                 if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
 546                         pr_err("Failed to ioremap PCC comm region mem for %d\n",
 547                                pcc_ss_idx);
 548                         return -ENOMEM;
 549                 }
 550
 551                 /* Set flag so that we don't come here for each CPU. */
 552                 pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
 553         }
 554
 555         return 0;
 556 }
 557
 558 /**
 559  * cpc_ffh_supported() - check if FFH reading supported
 560  *
 561  * Check if the architecture has support for functional fixed hardware
 562  * read/write capability.
 563  *
 564  * Return: true for supported, false for not supported
 565  */
 566 bool __weak cpc_ffh_supported(void)
 567 {
 568         return false;
 569 }
 570
 571 /**
 572  * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
 573  *
 574  * Check and allocate the cppc_pcc_data memory.
 575  * In some processor configurations it is possible that same subspace
 576  * is shared between multiple CPUs. This is seen especially in CPUs
 577  * with hardware multi-threading support.
 578  *
 579  * Return: 0 for success, errno for failure
 580  */
 581 static int pcc_data_alloc(int pcc_ss_id)
 582 {
 583         if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
 584                 return -EINVAL;
 585
 586         if (pcc_data[pcc_ss_id]) {
 587                 pcc_data[pcc_ss_id]->refcount++;
 588         } else {
 589                 pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data),
 590                                               GFP_KERNEL);
 591                 if (!pcc_data[pcc_ss_id])
 592                         return -ENOMEM;
 593                 pcc_data[pcc_ss_id]->refcount++;
 594         }
 595
 596         return 0;
 597 }
 598
 599 /* Check if CPPC revision + num_ent combination is supported */
 600 static bool is_cppc_supported(int revision, int num_ent)
 601 {
 602         int expected_num_ent;
 603
 604         switch (revision) {
 605         case CPPC_V2_REV:
 606                 expected_num_ent = CPPC_V2_NUM_ENT;
 607                 break;
 608         case CPPC_V3_REV:
 609                 expected_num_ent = CPPC_V3_NUM_ENT;
 610                 break;
 611         default:
 612                 pr_debug("Firmware exports unsupported CPPC revision: %d\n",
 613                         revision);
 614                 return false;
 615         }
 616
 617         if (expected_num_ent != num_ent) {
 618                 pr_debug("Firmware exports %d entries. Expected: %d for CPPC rev:%d\n",
 619                         num_ent, expected_num_ent, revision);
 620                 return false;
 621         }
 622
 623         return true;
 624 }
 625
 626 /*
 627  * An example CPC table looks like the following.
 628  *
 629  *      Name(_CPC, Package()
 630  *                      {
 631  *                      17,
 632  *                      NumEntries
 633  *                      1,
 634  *                      // Revision
 635  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)},
 636  *                      // Highest Performance
 637  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)},
 638  *                      // Nominal Performance
 639  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)},
 640  *                      // Lowest Nonlinear Performance
 641  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)},
 642  *                      // Lowest Performance
 643  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)},
 644  *                      // Guaranteed Performance Register
 645  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)},
 646  *                      // Desired Performance Register
 647  *                      ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)},
 648  *                      ..
 649  *                      ..
 650  *                      ..
 651  *
 652  *              }
 653  * Each Register() encodes how to access that specific register.
 654  * e.g. a sample PCC entry has the following encoding:
 655  *
 656  *      Register (
 657  *              PCC,
 658  *              AddressSpaceKeyword
 659  *              8,
 660  *              //RegisterBitWidth
 661  *              8,
 662  *              //RegisterBitOffset
 663  *              0x30,
 664  *              //RegisterAddress
 665  *              9
 666  *              //AccessSize (subspace ID)
 667  *              0
 668  *              )
 669  *      }
 670  */
 671
 672 #ifndef init_freq_invariance_cppc
 673 static inline void init_freq_invariance_cppc(void) { }
 674 #endif
 675
 676 /**
 677  * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
 678  * @pr: Ptr to acpi_processor containing this CPU's logical ID.
 679  *
 680  *      Return: 0 for success or negative value for err.
 681  */
 682 int acpi_cppc_processor_probe(struct acpi_processor *pr)
 683 {
 684         struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
 685         union acpi_object *out_obj, *cpc_obj;
 686         struct cpc_desc *cpc_ptr;
 687         struct cpc_reg *gas_t;
 688         struct device *cpu_dev;
 689         acpi_handle handle = pr->handle;
 690         unsigned int num_ent, i, cpc_rev;
 691         int pcc_subspace_id = -1;
 692         acpi_status status;
 693         int ret = -EFAULT;
 694
 695         /* Parse the ACPI _CPC table for this CPU. */
 696         status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
 697                         ACPI_TYPE_PACKAGE);
 698         if (ACPI_FAILURE(status)) {
 699                 ret = -ENODEV;
 700                 goto out_buf_free;
 701         }
 702
 703         out_obj = (union acpi_object *) output.pointer;
 704
 705         cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
 706         if (!cpc_ptr) {
 707                 ret = -ENOMEM;
 708                 goto out_buf_free;
 709         }
 710
 711         /* First entry is NumEntries. */
 712         cpc_obj = &out_obj->package.elements[0];
 713         if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 714                 num_ent = cpc_obj->integer.value;
 715         } else {
 716                 pr_debug("Unexpected entry type(%d) for NumEntries\n",
 717                                 cpc_obj->type);
 718                 goto out_free;
 719         }
 720         cpc_ptr->num_entries = num_ent;
 721
 722         /* Second entry should be revision. */
 723         cpc_obj = &out_obj->package.elements[1];
 724         if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 725                 cpc_rev = cpc_obj->integer.value;
 726         } else {
 727                 pr_debug("Unexpected entry type(%d) for Revision\n",
 728                                 cpc_obj->type);
 729                 goto out_free;
 730         }
 731         cpc_ptr->version = cpc_rev;
 732
 733         if (!is_cppc_supported(cpc_rev, num_ent))
 734                 goto out_free;
 735
 736         /* Iterate through remaining entries in _CPC */
 737         for (i = 2; i < num_ent; i++) {
 738                 cpc_obj = &out_obj->package.elements[i];
 739
 740                 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 741                         cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
 742                         cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
 743                 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
 744                         gas_t = (struct cpc_reg *)
 745                                 cpc_obj->buffer.pointer;
 746
 747                         /*
 748                          * The PCC Subspace index is encoded inside
 749                          * the CPC table entries. The same PCC index
 750                          * will be used for all the PCC entries,
 751                          * so extract it only once.
 752                          */
 753                         if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
 754                                 if (pcc_subspace_id < 0) {
 755                                         pcc_subspace_id = gas_t->access_width;
 756                                         if (pcc_data_alloc(pcc_subspace_id))
 757                                                 goto out_free;
 758                                 } else if (pcc_subspace_id != gas_t->access_width) {
 759                                         pr_debug("Mismatched PCC ids.\n");
 760                                         goto out_free;
 761                                 }
 762                         } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
 763                                 if (gas_t->address) {
 764                                         void __iomem *addr;
 765
 766                                         addr = ioremap(gas_t->address, gas_t->bit_width/8);
 767                                         if (!addr)
 768                                                 goto out_free;
 769                                         cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
 770                                 }
 771                         } else {
 772                                 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
 773                                         /* Support only PCC ,SYS MEM and FFH type regs */
 774                                         pr_debug("Unsupported register type: %d\n", gas_t->space_id);
 775                                         goto out_free;
 776                                 }
 777                         }
 778
 779                         cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
 780                         memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
 781                 } else {
 782                         pr_debug("Err in entry:%d in CPC table of CPU:%d\n", i, pr->id);
 783                         goto out_free;
 784                 }
 785         }
 786         per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
 787
 788         /*
 789          * Initialize the remaining cpc_regs as unsupported.
 790          * Example: In case FW exposes CPPC v2, the below loop will initialize
 791          * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported
 792          */
 793         for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) {
 794                 cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER;
 795                 cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0;
 796         }
 797
 798
 799         /* Store CPU Logical ID */
 800         cpc_ptr->cpu_id = pr->id;
 801
 802         /* Parse PSD data for this CPU */
 803         ret = acpi_get_psd(cpc_ptr, handle);
 804         if (ret)
 805                 goto out_free;
 806
 807         /* Register PCC channel once for all PCC subspace ID. */
 808         if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
 809                 ret = register_pcc_channel(pcc_subspace_id);
 810                 if (ret)
 811                         goto out_free;
 812
 813                 init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
 814                 init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
 815         }
 816
 817         /* Everything looks okay */
 818         pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
 819
 820         /* Add per logical CPU nodes for reading its feedback counters. */
 821         cpu_dev = get_cpu_device(pr->id);
 822         if (!cpu_dev) {
 823                 ret = -EINVAL;
 824                 goto out_free;
 825         }
 826
 827         /* Plug PSD data into this CPU's CPC descriptor. */
 828         per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
 829
 830         ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
 831                         "acpi_cppc");
 832         if (ret) {
 833                 per_cpu(cpc_desc_ptr, pr->id) = NULL;
 834                 kobject_put(&cpc_ptr->kobj);
 835                 goto out_free;
 836         }
 837
 838         init_freq_invariance_cppc();
 839
 840         kfree(output.pointer);
 841         return 0;
 842
 843 out_free:
 844         /* Free all the mapped sys mem areas for this CPU */
 845         for (i = 2; i < cpc_ptr->num_entries; i++) {
 846                 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
 847
 848                 if (addr)
 849                         iounmap(addr);
 850         }
 851         kfree(cpc_ptr);
 852
 853 out_buf_free:
 854         kfree(output.pointer);
 855         return ret;
 856 }
 857 EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
 858
 859 /**
 860  * acpi_cppc_processor_exit - Cleanup CPC structs.
 861  * @pr: Ptr to acpi_processor containing this CPU's logical ID.
 862  *
 863  * Return: Void
 864  */
 865 void acpi_cppc_processor_exit(struct acpi_processor *pr)
 866 {
 867         struct cpc_desc *cpc_ptr;
 868         unsigned int i;
 869         void __iomem *addr;
 870         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
 871
 872         if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
 873                 if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
 874                         pcc_data[pcc_ss_id]->refcount--;
 875                         if (!pcc_data[pcc_ss_id]->refcount) {
 876                                 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
 877                                 kfree(pcc_data[pcc_ss_id]);
 878                                 pcc_data[pcc_ss_id] = NULL;
 879                         }
 880                 }
 881         }
 882
 883         cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
 884         if (!cpc_ptr)
 885                 return;
 886
 887         /* Free all the mapped sys mem areas for this CPU */
 888         for (i = 2; i < cpc_ptr->num_entries; i++) {
 889                 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
 890                 if (addr)
 891                         iounmap(addr);
 892         }
 893
 894         kobject_put(&cpc_ptr->kobj);
 895         kfree(cpc_ptr);
 896 }
 897 EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
 898
 899 /**
 900  * cpc_read_ffh() - Read FFH register
 901  * @cpunum:     CPU number to read
 902  * @reg:        cppc register information
 903  * @val:        place holder for return value
 904  *
 905  * Read bit_width bits from a specified address and bit_offset
 906  *
 907  * Return: 0 for success and error code
 908  */
 909 int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
 910 {
 911         return -ENOTSUPP;
 912 }
 913
 914 /**
 915  * cpc_write_ffh() - Write FFH register
 916  * @cpunum:     CPU number to write
 917  * @reg:        cppc register information
 918  * @val:        value to write
 919  *
 920  * Write value of bit_width bits to a specified address and bit_offset
 921  *
 922  * Return: 0 for success and error code
 923  */
 924 int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
 925 {
 926         return -ENOTSUPP;
 927 }
 928
 929 /*
 930  * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
 931  * as fast as possible. We have already mapped the PCC subspace during init, so
 932  * we can directly write to it.
 933  */
 934
 935 static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
 936 {
 937         int ret_val = 0;
 938         void __iomem *vaddr = NULL;
 939         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
 940         struct cpc_reg *reg = &reg_res->cpc_entry.reg;
 941
 942         if (reg_res->type == ACPI_TYPE_INTEGER) {
 943                 *val = reg_res->cpc_entry.int_value;
 944                 return ret_val;
 945         }
 946
 947         *val = 0;
 948         if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
 949                 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
 950         else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
 951                 vaddr = reg_res->sys_mem_vaddr;
 952         else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
 953                 return cpc_read_ffh(cpu, reg, val);
 954         else
 955                 return acpi_os_read_memory((acpi_physical_address)reg->address,
 956                                 val, reg->bit_width);
 957
 958         switch (reg->bit_width) {
 959         case 8:
 960                 *val = readb_relaxed(vaddr);
 961                 break;
 962         case 16:
 963                 *val = readw_relaxed(vaddr);
 964                 break;
 965         case 32:
 966                 *val = readl_relaxed(vaddr);
 967                 break;
 968         case 64:
 969                 *val = readq_relaxed(vaddr);
 970                 break;
 971         default:
 972                 pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
 973                          reg->bit_width, pcc_ss_id);
 974                 ret_val = -EFAULT;
 975         }
 976
 977         return ret_val;
 978 }
 979
 980 static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
 981 {
 982         int ret_val = 0;
 983         void __iomem *vaddr = NULL;
 984         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
 985         struct cpc_reg *reg = &reg_res->cpc_entry.reg;
 986
 987         if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
 988                 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
 989         else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
 990                 vaddr = reg_res->sys_mem_vaddr;
 991         else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
 992                 return cpc_write_ffh(cpu, reg, val);
 993         else
 994                 return acpi_os_write_memory((acpi_physical_address)reg->address,
 995                                 val, reg->bit_width);
 996
 997         switch (reg->bit_width) {
 998         case 8:
 999                 writeb_relaxed(val, vaddr);
1000                 break;
1001         case 16:
1002                 writew_relaxed(val, vaddr);
1003                 break;
1004         case 32:
1005                 writel_relaxed(val, vaddr);
1006                 break;
1007         case 64:
1008                 writeq_relaxed(val, vaddr);
1009                 break;
1010         default:
1011                 pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
1012                          reg->bit_width, pcc_ss_id);
1013                 ret_val = -EFAULT;
1014                 break;
1015         }
1016
1017         return ret_val;
1018 }
1019
1020 /**
1021  * cppc_get_desired_perf - Get the value of desired performance register.
1022  * @cpunum: CPU from which to get desired performance.
1023  * @desired_perf: address of a variable to store the returned desired performance
1024  *
1025  * Return: 0 for success, -EIO otherwise.
1026  */
1027 int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
1028 {
1029         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1030         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1031         struct cpc_register_resource *desired_reg;
1032         struct cppc_pcc_data *pcc_ss_data = NULL;
1033
1034         desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1035
1036         if (CPC_IN_PCC(desired_reg)) {
1037                 int ret = 0;
1038
1039                 if (pcc_ss_id < 0)
1040                         return -EIO;
1041
1042                 pcc_ss_data = pcc_data[pcc_ss_id];
1043
1044                 down_write(&pcc_ss_data->pcc_lock);
1045
1046                 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
1047                         cpc_read(cpunum, desired_reg, desired_perf);
1048                 else
1049                         ret = -EIO;
1050
1051                 up_write(&pcc_ss_data->pcc_lock);
1052
1053                 return ret;
1054         }
1055
1056         cpc_read(cpunum, desired_reg, desired_perf);
1057
1058         return 0;
1059 }
1060 EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
1061
1062 /**
1063  * cppc_get_perf_caps - Get a CPU's performance capabilities.
1064  * @cpunum: CPU from which to get capabilities info.
1065  * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
1066  *
1067  * Return: 0 for success with perf_caps populated else -ERRNO.
1068  */
1069 int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1070 {
1071         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1072         struct cpc_register_resource *highest_reg, *lowest_reg,
1073                 *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg,
1074                 *low_freq_reg = NULL, *nom_freq_reg = NULL;
1075         u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0;
1076         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1077         struct cppc_pcc_data *pcc_ss_data = NULL;
1078         int ret = 0, regs_in_pcc = 0;
1079
1080         if (!cpc_desc) {
1081                 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1082                 return -ENODEV;
1083         }
1084
1085         highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
1086         lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
1087         lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
1088         nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1089         low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ];
1090         nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ];
1091         guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF];
1092
1093         /* Are any of the regs PCC ?*/
1094         if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
1095                 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) ||
1096                 CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) {
1097                 if (pcc_ss_id < 0) {
1098                         pr_debug("Invalid pcc_ss_id\n");
1099                         return -ENODEV;
1100                 }
1101                 pcc_ss_data = pcc_data[pcc_ss_id];
1102                 regs_in_pcc = 1;
1103                 down_write(&pcc_ss_data->pcc_lock);
1104                 /* Ring doorbell once to update PCC subspace */
1105                 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1106                         ret = -EIO;
1107                         goto out_err;
1108                 }
1109         }
1110
1111         cpc_read(cpunum, highest_reg, &high);
1112         perf_caps->highest_perf = high;
1113
1114         cpc_read(cpunum, lowest_reg, &low);
1115         perf_caps->lowest_perf = low;
1116
1117         cpc_read(cpunum, nominal_reg, &nom);
1118         perf_caps->nominal_perf = nom;
1119
1120         if (guaranteed_reg->type != ACPI_TYPE_BUFFER  ||
1121             IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) {
1122                 perf_caps->guaranteed_perf = 0;
1123         } else {
1124                 cpc_read(cpunum, guaranteed_reg, &guaranteed);
1125                 perf_caps->guaranteed_perf = guaranteed;
1126         }
1127
1128         cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
1129         perf_caps->lowest_nonlinear_perf = min_nonlinear;
1130
1131         if (!high || !low || !nom || !min_nonlinear)
1132                 ret = -EFAULT;
1133
1134         /* Read optional lowest and nominal frequencies if present */
1135         if (CPC_SUPPORTED(low_freq_reg))
1136                 cpc_read(cpunum, low_freq_reg, &low_f);
1137
1138         if (CPC_SUPPORTED(nom_freq_reg))
1139                 cpc_read(cpunum, nom_freq_reg, &nom_f);
1140
1141         perf_caps->lowest_freq = low_f;
1142         perf_caps->nominal_freq = nom_f;
1143
1144
1145 out_err:
1146         if (regs_in_pcc)
1147                 up_write(&pcc_ss_data->pcc_lock);
1148         return ret;
1149 }
1150 EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1151
1152 /**
1153  * cppc_get_perf_ctrs - Read a CPU's performance feedback counters.
1154  * @cpunum: CPU from which to read counters.
1155  * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1156  *
1157  * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1158  */
1159 int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1160 {
1161         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1162         struct cpc_register_resource *delivered_reg, *reference_reg,
1163                 *ref_perf_reg, *ctr_wrap_reg;
1164         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1165         struct cppc_pcc_data *pcc_ss_data = NULL;
1166         u64 delivered, reference, ref_perf, ctr_wrap_time;
1167         int ret = 0, regs_in_pcc = 0;
1168
1169         if (!cpc_desc) {
1170                 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1171                 return -ENODEV;
1172         }
1173
1174         delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1175         reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1176         ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1177         ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1178
1179         /*
1180          * If reference perf register is not supported then we should
1181          * use the nominal perf value
1182          */
1183         if (!CPC_SUPPORTED(ref_perf_reg))
1184                 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1185
1186         /* Are any of the regs PCC ?*/
1187         if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1188                 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
1189                 if (pcc_ss_id < 0) {
1190                         pr_debug("Invalid pcc_ss_id\n");
1191                         return -ENODEV;
1192                 }
1193                 pcc_ss_data = pcc_data[pcc_ss_id];
1194                 down_write(&pcc_ss_data->pcc_lock);
1195                 regs_in_pcc = 1;
1196                 /* Ring doorbell once to update PCC subspace */
1197                 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1198                         ret = -EIO;
1199                         goto out_err;
1200                 }
1201         }
1202
1203         cpc_read(cpunum, delivered_reg, &delivered);
1204         cpc_read(cpunum, reference_reg, &reference);
1205         cpc_read(cpunum, ref_perf_reg, &ref_perf);
1206
1207         /*
1208          * Per spec, if ctr_wrap_time optional register is unsupported, then the
1209          * performance counters are assumed to never wrap during the lifetime of
1210          * platform
1211          */
1212         ctr_wrap_time = (u64)(~((u64)0));
1213         if (CPC_SUPPORTED(ctr_wrap_reg))
1214                 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1215
1216         if (!delivered || !reference || !ref_perf) {
1217                 ret = -EFAULT;
1218                 goto out_err;
1219         }
1220
1221         perf_fb_ctrs->delivered = delivered;
1222         perf_fb_ctrs->reference = reference;
1223         perf_fb_ctrs->reference_perf = ref_perf;
1224         perf_fb_ctrs->wraparound_time = ctr_wrap_time;
1225 out_err:
1226         if (regs_in_pcc)
1227                 up_write(&pcc_ss_data->pcc_lock);
1228         return ret;
1229 }
1230 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1231
1232 /**
1233  * cppc_set_perf - Set a CPU's performance controls.
1234  * @cpu: CPU for which to set performance controls.
1235  * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1236  *
1237  * Return: 0 for success, -ERRNO otherwise.
1238  */
1239 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1240 {
1241         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1242         struct cpc_register_resource *desired_reg;
1243         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1244         struct cppc_pcc_data *pcc_ss_data = NULL;
1245         int ret = 0;
1246
1247         if (!cpc_desc) {
1248                 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1249                 return -ENODEV;
1250         }
1251
1252         desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1253
1254         /*
1255          * This is Phase-I where we want to write to CPC registers
1256          * -> We want all CPUs to be able to execute this phase in parallel
1257          *
1258          * Since read_lock can be acquired by multiple CPUs simultaneously we
1259          * achieve that goal here
1260          */
1261         if (CPC_IN_PCC(desired_reg)) {
1262                 if (pcc_ss_id < 0) {
1263                         pr_debug("Invalid pcc_ss_id\n");
1264                         return -ENODEV;
1265                 }
1266                 pcc_ss_data = pcc_data[pcc_ss_id];
1267                 down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
1268                 if (pcc_ss_data->platform_owns_pcc) {
1269                         ret = check_pcc_chan(pcc_ss_id, false);
1270                         if (ret) {
1271                                 up_read(&pcc_ss_data->pcc_lock);
1272                                 return ret;
1273                         }
1274                 }
1275                 /*
1276                  * Update the pending_write to make sure a PCC CMD_READ will not
1277                  * arrive and steal the channel during the switch to write lock
1278                  */
1279                 pcc_ss_data->pending_pcc_write_cmd = true;
1280                 cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
1281                 cpc_desc->write_cmd_status = 0;
1282         }
1283
1284         /*
1285          * Skip writing MIN/MAX until Linux knows how to come up with
1286          * useful values.
1287          */
1288         cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
1289
1290         if (CPC_IN_PCC(desired_reg))
1291                 up_read(&pcc_ss_data->pcc_lock);        /* END Phase-I */
1292         /*
1293          * This is Phase-II where we transfer the ownership of PCC to Platform
1294          *
1295          * Short Summary: Basically if we think of a group of cppc_set_perf
1296          * requests that happened in short overlapping interval. The last CPU to
1297          * come out of Phase-I will enter Phase-II and ring the doorbell.
1298          *
1299          * We have the following requirements for Phase-II:
1300          *     1. We want to execute Phase-II only when there are no CPUs
1301          * currently executing in Phase-I
1302          *     2. Once we start Phase-II we want to avoid all other CPUs from
1303          * entering Phase-I.
1304          *     3. We want only one CPU among all those who went through Phase-I
1305          * to run phase-II
1306          *
1307          * If write_trylock fails to get the lock and doesn't transfer the
1308          * PCC ownership to the platform, then one of the following will be TRUE
1309          *     1. There is at-least one CPU in Phase-I which will later execute
1310          * write_trylock, so the CPUs in Phase-I will be responsible for
1311          * executing the Phase-II.
1312          *     2. Some other CPU has beaten this CPU to successfully execute the
1313          * write_trylock and has already acquired the write_lock. We know for a
1314          * fact it (other CPU acquiring the write_lock) couldn't have happened
1315          * before this CPU's Phase-I as we held the read_lock.
1316          *     3. Some other CPU executing pcc CMD_READ has stolen the
1317          * down_write, in which case, send_pcc_cmd will check for pending
1318          * CMD_WRITE commands by checking the pending_pcc_write_cmd.
1319          * So this CPU can be certain that its request will be delivered
1320          *    So in all cases, this CPU knows that its request will be delivered
1321          * by another CPU and can return
1322          *
1323          * After getting the down_write we still need to check for
1324          * pending_pcc_write_cmd to take care of the following scenario
1325          *    The thread running this code could be scheduled out between
1326          * Phase-I and Phase-II. Before it is scheduled back on, another CPU
1327          * could have delivered the request to Platform by triggering the
1328          * doorbell and transferred the ownership of PCC to platform. So this
1329          * avoids triggering an unnecessary doorbell and more importantly before
1330          * triggering the doorbell it makes sure that the PCC channel ownership
1331          * is still with OSPM.
1332          *   pending_pcc_write_cmd can also be cleared by a different CPU, if
1333          * there was a pcc CMD_READ waiting on down_write and it steals the lock
1334          * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this
1335          * case during a CMD_READ and if there are pending writes it delivers
1336          * the write command before servicing the read command
1337          */
1338         if (CPC_IN_PCC(desired_reg)) {
1339                 if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
1340                         /* Update only if there are pending write commands */
1341                         if (pcc_ss_data->pending_pcc_write_cmd)
1342                                 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1343                         up_write(&pcc_ss_data->pcc_lock);       /* END Phase-II */
1344                 } else
1345                         /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
1346                         wait_event(pcc_ss_data->pcc_write_wait_q,
1347                                    cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
1348
1349                 /* send_pcc_cmd updates the status in case of failure */
1350                 ret = cpc_desc->write_cmd_status;
1351         }
1352         return ret;
1353 }
1354 EXPORT_SYMBOL_GPL(cppc_set_perf);
1355
1356 /**
1357  * cppc_get_transition_latency - returns frequency transition latency in ns
1358  *
1359  * ACPI CPPC does not explicitly specify how a platform can specify the
1360  * transition latency for performance change requests. The closest we have
1361  * is the timing information from the PCCT tables which provides the info
1362  * on the number and frequency of PCC commands the platform can handle.
1363  */
1364 unsigned int cppc_get_transition_latency(int cpu_num)
1365 {
1366         /*
1367          * Expected transition latency is based on the PCCT timing values
1368          * Below are definition from ACPI spec:
1369          * pcc_nominal- Expected latency to process a command, in microseconds
1370          * pcc_mpar   - The maximum number of periodic requests that the subspace
1371          *              channel can support, reported in commands per minute. 0
1372          *              indicates no limitation.
1373          * pcc_mrtt   - The minimum amount of time that OSPM must wait after the
1374          *              completion of a command before issuing the next command,
1375          *              in microseconds.
1376          */
1377         unsigned int latency_ns = 0;
1378         struct cpc_desc *cpc_desc;
1379         struct cpc_register_resource *desired_reg;
1380         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
1381         struct cppc_pcc_data *pcc_ss_data;
1382
1383         cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
1384         if (!cpc_desc)
1385                 return CPUFREQ_ETERNAL;
1386
1387         desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1388         if (!CPC_IN_PCC(desired_reg))
1389                 return CPUFREQ_ETERNAL;
1390
1391         if (pcc_ss_id < 0)
1392                 return CPUFREQ_ETERNAL;
1393
1394         pcc_ss_data = pcc_data[pcc_ss_id];
1395         if (pcc_ss_data->pcc_mpar)
1396                 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
1397
1398         latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
1399         latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
1400
1401         return latency_ns;
1402 }
1403 EXPORT_SYMBOL_GPL(cppc_get_transition_latency);