drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "smuio/smuio_11_0_0_offset.h"
  39 #include "smuio/smuio_11_0_0_sh_mask.h"
  40 #include "navi10_enum.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "soc15_common.h"
  47 #include "clearstate_gfx10.h"
  48 #include "v10_structs.h"
  49 #include "gfx_v10_0.h"
  50 #include "nbio_v2_3.h"
  51
  52 /**
  53  * Navi10 has two graphic rings to share each graphic pipe.
  54  * 1. Primary ring
  55  * 2. Async ring
  56  */
  57 #define GFX10_NUM_GFX_RINGS_NV1X        1
  58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  59 #define GFX10_MEC_HPD_SIZE      2048
  60
  61 #define F32_CE_PROGRAM_RAM_SIZE         65536
  62 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  63
  64 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  70
  71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  73
  74 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  76 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
  97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
  98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
  99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 101
 102 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 103 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 104 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 105 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 106 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 107 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 108 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 109 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 110 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 111 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 112 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 113 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 114
 115 //CC_GC_SA_UNIT_DISABLE
 116 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 117 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 118 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 119 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 120 //GC_USER_SA_UNIT_DISABLE
 121 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 122 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 123 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 124 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 125 //PA_SC_ENHANCE_3
 126 #define mmPA_SC_ENHANCE_3                       0x1085
 127 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 128 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 129 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 130
 131 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 132 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 133
 134 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 135 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 136 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 137 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 138 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 139 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 140
 141 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 142 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 143 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 144 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 145 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 146 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 147 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 148 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 149 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 150 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 151 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 152
 153 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 154 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 155 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 156 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 157 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 158 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 159
 160 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 161 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 162 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 163 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 164 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 165 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 166
 167 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 168 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 169 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 170 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 171 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 172 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 173
 174 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 175 {
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 216 };
 217
 218 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 219 {
 220         /* Pending on emulation bring up */
 221 };
 222
 223 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 224 {
 225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1277 };
1278
1279 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1280 {
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1319 };
1320
1321 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1322 {
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1363 };
1364
1365 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1366 {
1367         static void *scratch_reg0;
1368         static void *scratch_reg1;
1369         static void *scratch_reg2;
1370         static void *scratch_reg3;
1371         static void *spare_int;
1372         static uint32_t grbm_cntl;
1373         static uint32_t grbm_idx;
1374         uint32_t i = 0;
1375         uint32_t retries = 50000;
1376
1377         scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1378         scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1379         scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
1380         scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
1381         spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1382
1383         grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1384         grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1385
1386         if (amdgpu_sriov_runtime(adev)) {
1387                 pr_err("shouldn't call rlcg write register during runtime\n");
1388                 return;
1389         }
1390
1391         writel(v, scratch_reg0);
1392         writel(offset | 0x80000000, scratch_reg1);
1393         writel(1, spare_int);
1394         for (i = 0; i < retries; i++) {
1395                 u32 tmp;
1396
1397                 tmp = readl(scratch_reg1);
1398                 if (!(tmp & 0x80000000))
1399                         break;
1400
1401                 udelay(10);
1402         }
1403
1404         if (i >= retries)
1405                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1406 }
1407
1408 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1409 {
1410         /* Pending on emulation bring up */
1411 };
1412
1413 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1414 {
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2035 };
2036
2037 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2038 {
2039         /* Pending on emulation bring up */
2040 };
2041
2042 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2043 {
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3096 };
3097
3098 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3099 {
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3138 };
3139
3140 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3141 {
3142         /* Pending on emulation bring up */
3143 };
3144
3145 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3146 {
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
3185 };
3186
3187 #define DEFAULT_SH_MEM_CONFIG \
3188         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3189          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3190          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3191          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3192
3193
3194 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3195 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3196 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3197 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3198 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3199                                  struct amdgpu_cu_info *cu_info);
3200 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3201 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3202                                    u32 sh_num, u32 instance);
3203 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3204
3205 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3206 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3207 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3208 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3209 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3210 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3211 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3212 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3213 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3214
3215 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3216 {
3217         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3218         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3219                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3220         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3221         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3222         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3223         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3224         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3225         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3226 }
3227
3228 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3229                                  struct amdgpu_ring *ring)
3230 {
3231         struct amdgpu_device *adev = kiq_ring->adev;
3232         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3233         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3234         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3235
3236         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3237         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3238         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3239                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3240                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3241                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3242                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3243                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3244                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3245                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3246                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3247                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3248         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3249         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3250         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3251         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3252         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3253 }
3254
3255 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3256                                    struct amdgpu_ring *ring,
3257                                    enum amdgpu_unmap_queues_action action,
3258                                    u64 gpu_addr, u64 seq)
3259 {
3260         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3261
3262         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3263         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3264                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3265                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3266                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3267                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3268         amdgpu_ring_write(kiq_ring,
3269                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3270
3271         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3272                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3273                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3274                 amdgpu_ring_write(kiq_ring, seq);
3275         } else {
3276                 amdgpu_ring_write(kiq_ring, 0);
3277                 amdgpu_ring_write(kiq_ring, 0);
3278                 amdgpu_ring_write(kiq_ring, 0);
3279         }
3280 }
3281
3282 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3283                                    struct amdgpu_ring *ring,
3284                                    u64 addr,
3285                                    u64 seq)
3286 {
3287         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3288
3289         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3290         amdgpu_ring_write(kiq_ring,
3291                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3292                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3293                           PACKET3_QUERY_STATUS_COMMAND(2));
3294         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3295                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3296                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3297         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3298         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3299         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3300         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3301 }
3302
3303 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3304                                 uint16_t pasid, uint32_t flush_type,
3305                                 bool all_hub)
3306 {
3307         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3308         amdgpu_ring_write(kiq_ring,
3309                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3310                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3311                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3312                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3313 }
3314
3315 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3316         .kiq_set_resources = gfx10_kiq_set_resources,
3317         .kiq_map_queues = gfx10_kiq_map_queues,
3318         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3319         .kiq_query_status = gfx10_kiq_query_status,
3320         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3321         .set_resources_size = 8,
3322         .map_queues_size = 7,
3323         .unmap_queues_size = 6,
3324         .query_status_size = 7,
3325         .invalidate_tlbs_size = 2,
3326 };
3327
3328 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3329 {
3330         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3331 }
3332
3333 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3334 {
3335         switch (adev->asic_type) {
3336         case CHIP_NAVI10:
3337                 soc15_program_register_sequence(adev,
3338                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3339                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3340                 break;
3341         case CHIP_NAVI14:
3342                 soc15_program_register_sequence(adev,
3343                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3344                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3345                 break;
3346         case CHIP_NAVI12:
3347                 soc15_program_register_sequence(adev,
3348                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3349                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3350                 break;
3351         default:
3352                 break;
3353         }
3354 }
3355
3356 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3357 {
3358         switch (adev->asic_type) {
3359         case CHIP_NAVI10:
3360                 soc15_program_register_sequence(adev,
3361                                                 golden_settings_gc_10_1,
3362                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3363                 soc15_program_register_sequence(adev,
3364                                                 golden_settings_gc_10_0_nv10,
3365                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3366                 break;
3367         case CHIP_NAVI14:
3368                 soc15_program_register_sequence(adev,
3369                                                 golden_settings_gc_10_1_1,
3370                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3371                 soc15_program_register_sequence(adev,
3372                                                 golden_settings_gc_10_1_nv14,
3373                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3374                 break;
3375         case CHIP_NAVI12:
3376                 soc15_program_register_sequence(adev,
3377                                                 golden_settings_gc_10_1_2,
3378                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3379                 soc15_program_register_sequence(adev,
3380                                                 golden_settings_gc_10_1_2_nv12,
3381                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3382                 break;
3383         case CHIP_SIENNA_CICHLID:
3384                 soc15_program_register_sequence(adev,
3385                                                 golden_settings_gc_10_3,
3386                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3387                 soc15_program_register_sequence(adev,
3388                                                 golden_settings_gc_10_3_sienna_cichlid,
3389                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3390                 break;
3391         case CHIP_NAVY_FLOUNDER:
3392                 soc15_program_register_sequence(adev,
3393                                                 golden_settings_gc_10_3_2,
3394                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3395                 break;
3396
3397         default:
3398                 break;
3399         }
3400         gfx_v10_0_init_spm_golden_registers(adev);
3401 }
3402
3403 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3404 {
3405         adev->gfx.scratch.num_reg = 8;
3406         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3407         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3408 }
3409
3410 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3411                                        bool wc, uint32_t reg, uint32_t val)
3412 {
3413         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3414         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3415                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3416         amdgpu_ring_write(ring, reg);
3417         amdgpu_ring_write(ring, 0);
3418         amdgpu_ring_write(ring, val);
3419 }
3420
3421 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3422                                   int mem_space, int opt, uint32_t addr0,
3423                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3424                                   uint32_t inv)
3425 {
3426         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3427         amdgpu_ring_write(ring,
3428                           /* memory (1) or register (0) */
3429                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3430                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3431                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3432                            WAIT_REG_MEM_ENGINE(eng_sel)));
3433
3434         if (mem_space)
3435                 BUG_ON(addr0 & 0x3); /* Dword align */
3436         amdgpu_ring_write(ring, addr0);
3437         amdgpu_ring_write(ring, addr1);
3438         amdgpu_ring_write(ring, ref);
3439         amdgpu_ring_write(ring, mask);
3440         amdgpu_ring_write(ring, inv); /* poll interval */
3441 }
3442
3443 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3444 {
3445         struct amdgpu_device *adev = ring->adev;
3446         uint32_t scratch;
3447         uint32_t tmp = 0;
3448         unsigned i;
3449         int r;
3450
3451         r = amdgpu_gfx_scratch_get(adev, &scratch);
3452         if (r) {
3453                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3454                 return r;
3455         }
3456
3457         WREG32(scratch, 0xCAFEDEAD);
3458
3459         r = amdgpu_ring_alloc(ring, 3);
3460         if (r) {
3461                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3462                           ring->idx, r);
3463                 amdgpu_gfx_scratch_free(adev, scratch);
3464                 return r;
3465         }
3466
3467         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3468         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3469         amdgpu_ring_write(ring, 0xDEADBEEF);
3470         amdgpu_ring_commit(ring);
3471
3472         for (i = 0; i < adev->usec_timeout; i++) {
3473                 tmp = RREG32(scratch);
3474                 if (tmp == 0xDEADBEEF)
3475                         break;
3476                 if (amdgpu_emu_mode == 1)
3477                         msleep(1);
3478                 else
3479                         udelay(1);
3480         }
3481
3482         if (i >= adev->usec_timeout)
3483                 r = -ETIMEDOUT;
3484
3485         amdgpu_gfx_scratch_free(adev, scratch);
3486
3487         return r;
3488 }
3489
3490 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3491 {
3492         struct amdgpu_device *adev = ring->adev;
3493         struct amdgpu_ib ib;
3494         struct dma_fence *f = NULL;
3495         unsigned index;
3496         uint64_t gpu_addr;
3497         uint32_t tmp;
3498         long r;
3499
3500         r = amdgpu_device_wb_get(adev, &index);
3501         if (r)
3502                 return r;
3503
3504         gpu_addr = adev->wb.gpu_addr + (index * 4);
3505         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3506         memset(&ib, 0, sizeof(ib));
3507         r = amdgpu_ib_get(adev, NULL, 16,
3508                                         AMDGPU_IB_POOL_DIRECT, &ib);
3509         if (r)
3510                 goto err1;
3511
3512         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3513         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3514         ib.ptr[2] = lower_32_bits(gpu_addr);
3515         ib.ptr[3] = upper_32_bits(gpu_addr);
3516         ib.ptr[4] = 0xDEADBEEF;
3517         ib.length_dw = 5;
3518
3519         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3520         if (r)
3521                 goto err2;
3522
3523         r = dma_fence_wait_timeout(f, false, timeout);
3524         if (r == 0) {
3525                 r = -ETIMEDOUT;
3526                 goto err2;
3527         } else if (r < 0) {
3528                 goto err2;
3529         }
3530
3531         tmp = adev->wb.wb[index];
3532         if (tmp == 0xDEADBEEF)
3533                 r = 0;
3534         else
3535                 r = -EINVAL;
3536 err2:
3537         amdgpu_ib_free(adev, &ib, NULL);
3538         dma_fence_put(f);
3539 err1:
3540         amdgpu_device_wb_free(adev, index);
3541         return r;
3542 }
3543
3544 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3545 {
3546         release_firmware(adev->gfx.pfp_fw);
3547         adev->gfx.pfp_fw = NULL;
3548         release_firmware(adev->gfx.me_fw);
3549         adev->gfx.me_fw = NULL;
3550         release_firmware(adev->gfx.ce_fw);
3551         adev->gfx.ce_fw = NULL;
3552         release_firmware(adev->gfx.rlc_fw);
3553         adev->gfx.rlc_fw = NULL;
3554         release_firmware(adev->gfx.mec_fw);
3555         adev->gfx.mec_fw = NULL;
3556         release_firmware(adev->gfx.mec2_fw);
3557         adev->gfx.mec2_fw = NULL;
3558
3559         kfree(adev->gfx.rlc.register_list_format);
3560 }
3561
3562 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3563 {
3564         adev->gfx.cp_fw_write_wait = false;
3565
3566         switch (adev->asic_type) {
3567         case CHIP_NAVI10:
3568         case CHIP_NAVI12:
3569         case CHIP_NAVI14:
3570                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3571                     (adev->gfx.me_feature_version >= 27) &&
3572                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3573                     (adev->gfx.pfp_feature_version >= 27) &&
3574                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3575                     (adev->gfx.mec_feature_version >= 27))
3576                         adev->gfx.cp_fw_write_wait = true;
3577                 break;
3578         case CHIP_SIENNA_CICHLID:
3579         case CHIP_NAVY_FLOUNDER:
3580                 adev->gfx.cp_fw_write_wait = true;
3581                 break;
3582         default:
3583                 break;
3584         }
3585
3586         if (!adev->gfx.cp_fw_write_wait)
3587                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3588 }
3589
3590
3591 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3592 {
3593         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3594
3595         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3596         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3597         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3598         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3599         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3600         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3601         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3602         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3603         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3604         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3605         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3606         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3607         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3608         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3609                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3610 }
3611
3612 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3613 {
3614         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3615
3616         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3617         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3618         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3619         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3620         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3621 }
3622
3623 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3624 {
3625         bool ret = false;
3626
3627         switch (adev->pdev->revision) {
3628         case 0xc2:
3629         case 0xc3:
3630                 ret = true;
3631                 break;
3632         default:
3633                 ret = false;
3634                 break;
3635         }
3636
3637         return ret ;
3638 }
3639
3640 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3641 {
3642         switch (adev->asic_type) {
3643         case CHIP_NAVI10:
3644                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3645                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3646                 break;
3647         case CHIP_NAVY_FLOUNDER:
3648                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3649                 break;
3650         default:
3651                 break;
3652         }
3653 }
3654
3655 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3656 {
3657         const char *chip_name;
3658         char fw_name[40];
3659         char wks[10];
3660         int err;
3661         struct amdgpu_firmware_info *info = NULL;
3662         const struct common_firmware_header *header = NULL;
3663         const struct gfx_firmware_header_v1_0 *cp_hdr;
3664         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3665         unsigned int *tmp = NULL;
3666         unsigned int i = 0;
3667         uint16_t version_major;
3668         uint16_t version_minor;
3669
3670         DRM_DEBUG("\n");
3671
3672         memset(wks, 0, sizeof(wks));
3673         switch (adev->asic_type) {
3674         case CHIP_NAVI10:
3675                 chip_name = "navi10";
3676                 break;
3677         case CHIP_NAVI14:
3678                 chip_name = "navi14";
3679                 if (!(adev->pdev->device == 0x7340 &&
3680                       adev->pdev->revision != 0x00))
3681                         snprintf(wks, sizeof(wks), "_wks");
3682                 break;
3683         case CHIP_NAVI12:
3684                 chip_name = "navi12";
3685                 break;
3686         case CHIP_SIENNA_CICHLID:
3687                 chip_name = "sienna_cichlid";
3688                 break;
3689         case CHIP_NAVY_FLOUNDER:
3690                 chip_name = "navy_flounder";
3691                 break;
3692         default:
3693                 BUG();
3694         }
3695
3696         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3697         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3698         if (err)
3699                 goto out;
3700         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3701         if (err)
3702                 goto out;
3703         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3704         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3705         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3706
3707         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3708         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3709         if (err)
3710                 goto out;
3711         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3712         if (err)
3713                 goto out;
3714         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3715         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3716         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3717
3718         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3719         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3720         if (err)
3721                 goto out;
3722         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3723         if (err)
3724                 goto out;
3725         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3726         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3727         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3728
3729         if (!amdgpu_sriov_vf(adev)) {
3730                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3731                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3732                 if (err)
3733                         goto out;
3734                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3735                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3736                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3737                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3738
3739                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3740                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3741                 adev->gfx.rlc.save_and_restore_offset =
3742                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3743                 adev->gfx.rlc.clear_state_descriptor_offset =
3744                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3745                 adev->gfx.rlc.avail_scratch_ram_locations =
3746                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3747                 adev->gfx.rlc.reg_restore_list_size =
3748                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3749                 adev->gfx.rlc.reg_list_format_start =
3750                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3751                 adev->gfx.rlc.reg_list_format_separate_start =
3752                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3753                 adev->gfx.rlc.starting_offsets_start =
3754                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3755                 adev->gfx.rlc.reg_list_format_size_bytes =
3756                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3757                 adev->gfx.rlc.reg_list_size_bytes =
3758                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3759                 adev->gfx.rlc.register_list_format =
3760                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3761                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3762                 if (!adev->gfx.rlc.register_list_format) {
3763                         err = -ENOMEM;
3764                         goto out;
3765                 }
3766
3767                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3768                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3769                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3770                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
3771
3772                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3773
3774                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3775                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3776                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3777                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3778
3779                 if (version_major == 2) {
3780                         if (version_minor >= 1)
3781                                 gfx_v10_0_init_rlc_ext_microcode(adev);
3782                         if (version_minor == 2)
3783                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
3784                 }
3785         }
3786
3787         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3788         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3789         if (err)
3790                 goto out;
3791         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3792         if (err)
3793                 goto out;
3794         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3795         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3796         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3797
3798         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3799         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3800         if (!err) {
3801                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3802                 if (err)
3803                         goto out;
3804                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3805                 adev->gfx.mec2_fw->data;
3806                 adev->gfx.mec2_fw_version =
3807                 le32_to_cpu(cp_hdr->header.ucode_version);
3808                 adev->gfx.mec2_feature_version =
3809                 le32_to_cpu(cp_hdr->ucode_feature_version);
3810         } else {
3811                 err = 0;
3812                 adev->gfx.mec2_fw = NULL;
3813         }
3814
3815         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3816                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3817                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3818                 info->fw = adev->gfx.pfp_fw;
3819                 header = (const struct common_firmware_header *)info->fw->data;
3820                 adev->firmware.fw_size +=
3821                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3822
3823                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3824                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3825                 info->fw = adev->gfx.me_fw;
3826                 header = (const struct common_firmware_header *)info->fw->data;
3827                 adev->firmware.fw_size +=
3828                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3829
3830                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3831                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3832                 info->fw = adev->gfx.ce_fw;
3833                 header = (const struct common_firmware_header *)info->fw->data;
3834                 adev->firmware.fw_size +=
3835                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3836
3837                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3838                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3839                 info->fw = adev->gfx.rlc_fw;
3840                 if (info->fw) {
3841                         header = (const struct common_firmware_header *)info->fw->data;
3842                         adev->firmware.fw_size +=
3843                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3844                 }
3845                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3846                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3847                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3848                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3849                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3850                         info->fw = adev->gfx.rlc_fw;
3851                         adev->firmware.fw_size +=
3852                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3853
3854                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3855                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3856                         info->fw = adev->gfx.rlc_fw;
3857                         adev->firmware.fw_size +=
3858                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
3859
3860                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
3861                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
3862                         info->fw = adev->gfx.rlc_fw;
3863                         adev->firmware.fw_size +=
3864                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
3865
3866                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
3867                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
3868                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
3869                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
3870                                 info->fw = adev->gfx.rlc_fw;
3871                                 adev->firmware.fw_size +=
3872                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
3873
3874                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
3875                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
3876                                 info->fw = adev->gfx.rlc_fw;
3877                                 adev->firmware.fw_size +=
3878                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
3879                         }
3880                 }
3881
3882                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
3883                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
3884                 info->fw = adev->gfx.mec_fw;
3885                 header = (const struct common_firmware_header *)info->fw->data;
3886                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3887                 adev->firmware.fw_size +=
3888                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3889                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3890
3891                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
3892                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
3893                 info->fw = adev->gfx.mec_fw;
3894                 adev->firmware.fw_size +=
3895                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3896
3897                 if (adev->gfx.mec2_fw) {
3898                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
3899                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
3900                         info->fw = adev->gfx.mec2_fw;
3901                         header = (const struct common_firmware_header *)info->fw->data;
3902                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3903                         adev->firmware.fw_size +=
3904                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3905                                       le32_to_cpu(cp_hdr->jt_size) * 4,
3906                                       PAGE_SIZE);
3907                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
3908                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
3909                         info->fw = adev->gfx.mec2_fw;
3910                         adev->firmware.fw_size +=
3911                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
3912                                       PAGE_SIZE);
3913                 }
3914         }
3915
3916         gfx_v10_0_check_fw_write_wait(adev);
3917 out:
3918         if (err) {
3919                 dev_err(adev->dev,
3920                         "gfx10: Failed to load firmware \"%s\"\n",
3921                         fw_name);
3922                 release_firmware(adev->gfx.pfp_fw);
3923                 adev->gfx.pfp_fw = NULL;
3924                 release_firmware(adev->gfx.me_fw);
3925                 adev->gfx.me_fw = NULL;
3926                 release_firmware(adev->gfx.ce_fw);
3927                 adev->gfx.ce_fw = NULL;
3928                 release_firmware(adev->gfx.rlc_fw);
3929                 adev->gfx.rlc_fw = NULL;
3930                 release_firmware(adev->gfx.mec_fw);
3931                 adev->gfx.mec_fw = NULL;
3932                 release_firmware(adev->gfx.mec2_fw);
3933                 adev->gfx.mec2_fw = NULL;
3934         }
3935
3936         gfx_v10_0_check_gfxoff_flag(adev);
3937
3938         return err;
3939 }
3940
3941 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
3942 {
3943         u32 count = 0;
3944         const struct cs_section_def *sect = NULL;
3945         const struct cs_extent_def *ext = NULL;
3946
3947         /* begin clear state */
3948         count += 2;
3949         /* context control state */
3950         count += 3;
3951
3952         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
3953                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3954                         if (sect->id == SECT_CONTEXT)
3955                                 count += 2 + ext->reg_count;
3956                         else
3957                                 return 0;
3958                 }
3959         }
3960
3961         /* set PA_SC_TILE_STEERING_OVERRIDE */
3962         count += 3;
3963         /* end clear state */
3964         count += 2;
3965         /* clear state */
3966         count += 2;
3967
3968         return count;
3969 }
3970
3971 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
3972                                     volatile u32 *buffer)
3973 {
3974         u32 count = 0, i;
3975         const struct cs_section_def *sect = NULL;
3976         const struct cs_extent_def *ext = NULL;
3977         int ctx_reg_offset;
3978
3979         if (adev->gfx.rlc.cs_data == NULL)
3980                 return;
3981         if (buffer == NULL)
3982                 return;
3983
3984         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3985         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3986
3987         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3988         buffer[count++] = cpu_to_le32(0x80000000);
3989         buffer[count++] = cpu_to_le32(0x80000000);
3990
3991         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3992                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3993                         if (sect->id == SECT_CONTEXT) {
3994                                 buffer[count++] =
3995                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
3996                                 buffer[count++] = cpu_to_le32(ext->reg_index -
3997                                                 PACKET3_SET_CONTEXT_REG_START);
3998                                 for (i = 0; i < ext->reg_count; i++)
3999                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4000                         } else {
4001                                 return;
4002                         }
4003                 }
4004         }
4005
4006         ctx_reg_offset =
4007                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4008         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4009         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4010         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4011
4012         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4013         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4014
4015         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4016         buffer[count++] = cpu_to_le32(0);
4017 }
4018
4019 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4020 {
4021         /* clear state block */
4022         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4023                         &adev->gfx.rlc.clear_state_gpu_addr,
4024                         (void **)&adev->gfx.rlc.cs_ptr);
4025
4026         /* jump table block */
4027         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4028                         &adev->gfx.rlc.cp_table_gpu_addr,
4029                         (void **)&adev->gfx.rlc.cp_table_ptr);
4030 }
4031
4032 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4033 {
4034         const struct cs_section_def *cs_data;
4035         int r;
4036
4037         adev->gfx.rlc.cs_data = gfx10_cs_data;
4038
4039         cs_data = adev->gfx.rlc.cs_data;
4040
4041         if (cs_data) {
4042                 /* init clear state block */
4043                 r = amdgpu_gfx_rlc_init_csb(adev);
4044                 if (r)
4045                         return r;
4046         }
4047
4048         /* init spm vmid with 0xf */
4049         if (adev->gfx.rlc.funcs->update_spm_vmid)
4050                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4051
4052         return 0;
4053 }
4054
4055 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4056 {
4057         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4058         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4059 }
4060
4061 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4062 {
4063         int r;
4064
4065         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4066
4067         amdgpu_gfx_graphics_queue_acquire(adev);
4068
4069         r = gfx_v10_0_init_microcode(adev);
4070         if (r)
4071                 DRM_ERROR("Failed to load gfx firmware!\n");
4072
4073         return r;
4074 }
4075
4076 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4077 {
4078         int r;
4079         u32 *hpd;
4080         const __le32 *fw_data = NULL;
4081         unsigned fw_size;
4082         u32 *fw = NULL;
4083         size_t mec_hpd_size;
4084
4085         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4086
4087         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4088
4089         /* take ownership of the relevant compute queues */
4090         amdgpu_gfx_compute_queue_acquire(adev);
4091         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4092
4093         if (mec_hpd_size) {
4094                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4095                                               AMDGPU_GEM_DOMAIN_GTT,
4096                                               &adev->gfx.mec.hpd_eop_obj,
4097                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4098                                               (void **)&hpd);
4099                 if (r) {
4100                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4101                         gfx_v10_0_mec_fini(adev);
4102                         return r;
4103                 }
4104
4105                 memset(hpd, 0, mec_hpd_size);
4106
4107                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4108                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4109         }
4110
4111         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4112                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4113
4114                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4115                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4116                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4117
4118                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4119                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4120                                               &adev->gfx.mec.mec_fw_obj,
4121                                               &adev->gfx.mec.mec_fw_gpu_addr,
4122                                               (void **)&fw);
4123                 if (r) {
4124                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4125                         gfx_v10_0_mec_fini(adev);
4126                         return r;
4127                 }
4128
4129                 memcpy(fw, fw_data, fw_size);
4130
4131                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4132                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4133         }
4134
4135         return 0;
4136 }
4137
4138 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4139 {
4140         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4141                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4142                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4143         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4144 }
4145
4146 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4147                            uint32_t thread, uint32_t regno,
4148                            uint32_t num, uint32_t *out)
4149 {
4150         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4151                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4152                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4153                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4154                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4155         while (num--)
4156                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4157 }
4158
4159 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4160 {
4161         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4162          * field when performing a select_se_sh so it should be
4163          * zero here */
4164         WARN_ON(simd != 0);
4165
4166         /* type 2 wave data */
4167         dst[(*no_fields)++] = 2;
4168         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4169         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4170         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4171         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4172         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4173         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4174         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4175         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4176         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4177         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4178         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4179         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4180         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4181         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4182         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4183 }
4184
4185 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4186                                      uint32_t wave, uint32_t start,
4187                                      uint32_t size, uint32_t *dst)
4188 {
4189         WARN_ON(simd != 0);
4190
4191         wave_read_regs(
4192                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4193                 dst);
4194 }
4195
4196 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4197                                       uint32_t wave, uint32_t thread,
4198                                       uint32_t start, uint32_t size,
4199                                       uint32_t *dst)
4200 {
4201         wave_read_regs(
4202                 adev, wave, thread,
4203                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4204 }
4205
4206 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4207                                                                           u32 me, u32 pipe, u32 q, u32 vm)
4208  {
4209        nv_grbm_select(adev, me, pipe, q, vm);
4210  }
4211
4212
4213 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4214         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4215         .select_se_sh = &gfx_v10_0_select_se_sh,
4216         .read_wave_data = &gfx_v10_0_read_wave_data,
4217         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4218         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4219         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4220         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4221 };
4222
4223 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4224 {
4225         u32 gb_addr_config;
4226
4227         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4228
4229         switch (adev->asic_type) {
4230         case CHIP_NAVI10:
4231         case CHIP_NAVI14:
4232         case CHIP_NAVI12:
4233                 adev->gfx.config.max_hw_contexts = 8;
4234                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4235                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4236                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4237                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4238                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4239                 break;
4240         case CHIP_SIENNA_CICHLID:
4241         case CHIP_NAVY_FLOUNDER:
4242                 adev->gfx.config.max_hw_contexts = 8;
4243                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4244                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4245                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4246                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4247                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4248                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4249                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4250                 break;
4251         default:
4252                 BUG();
4253                 break;
4254         }
4255
4256         adev->gfx.config.gb_addr_config = gb_addr_config;
4257
4258         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4259                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4260                                       GB_ADDR_CONFIG, NUM_PIPES);
4261
4262         adev->gfx.config.max_tile_pipes =
4263                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4264
4265         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4266                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4267                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4268         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4269                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4270                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4271         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4272                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4273                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4274         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4275                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4276                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4277 }
4278
4279 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4280                                    int me, int pipe, int queue)
4281 {
4282         int r;
4283         struct amdgpu_ring *ring;
4284         unsigned int irq_type;
4285
4286         ring = &adev->gfx.gfx_ring[ring_id];
4287
4288         ring->me = me;
4289         ring->pipe = pipe;
4290         ring->queue = queue;
4291
4292         ring->ring_obj = NULL;
4293         ring->use_doorbell = true;
4294
4295         if (!ring_id)
4296                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4297         else
4298                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4299         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4300
4301         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4302         r = amdgpu_ring_init(adev, ring, 1024,
4303                              &adev->gfx.eop_irq, irq_type,
4304                              AMDGPU_RING_PRIO_DEFAULT);
4305         if (r)
4306                 return r;
4307         return 0;
4308 }
4309
4310 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4311                                        int mec, int pipe, int queue)
4312 {
4313         int r;
4314         unsigned irq_type;
4315         struct amdgpu_ring *ring;
4316         unsigned int hw_prio;
4317
4318         ring = &adev->gfx.compute_ring[ring_id];
4319
4320         /* mec0 is me1 */
4321         ring->me = mec + 1;
4322         ring->pipe = pipe;
4323         ring->queue = queue;
4324
4325         ring->ring_obj = NULL;
4326         ring->use_doorbell = true;
4327         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4328         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4329                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4330         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4331
4332         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4333                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4334                 + ring->pipe;
4335         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
4336                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4337         /* type-2 packets are deprecated on MEC, use type-3 instead */
4338         r = amdgpu_ring_init(adev, ring, 1024,
4339                              &adev->gfx.eop_irq, irq_type, hw_prio);
4340         if (r)
4341                 return r;
4342
4343         return 0;
4344 }
4345
4346 static int gfx_v10_0_sw_init(void *handle)
4347 {
4348         int i, j, k, r, ring_id = 0;
4349         struct amdgpu_kiq *kiq;
4350         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4351
4352         switch (adev->asic_type) {
4353         case CHIP_NAVI10:
4354         case CHIP_NAVI14:
4355         case CHIP_NAVI12:
4356                 adev->gfx.me.num_me = 1;
4357                 adev->gfx.me.num_pipe_per_me = 1;
4358                 adev->gfx.me.num_queue_per_pipe = 1;
4359                 adev->gfx.mec.num_mec = 2;
4360                 adev->gfx.mec.num_pipe_per_mec = 4;
4361                 adev->gfx.mec.num_queue_per_pipe = 8;
4362                 break;
4363         case CHIP_SIENNA_CICHLID:
4364         case CHIP_NAVY_FLOUNDER:
4365                 adev->gfx.me.num_me = 1;
4366                 adev->gfx.me.num_pipe_per_me = 1;
4367                 adev->gfx.me.num_queue_per_pipe = 1;
4368                 adev->gfx.mec.num_mec = 2;
4369                 adev->gfx.mec.num_pipe_per_mec = 4;
4370                 adev->gfx.mec.num_queue_per_pipe = 4;
4371                 break;
4372         default:
4373                 adev->gfx.me.num_me = 1;
4374                 adev->gfx.me.num_pipe_per_me = 1;
4375                 adev->gfx.me.num_queue_per_pipe = 1;
4376                 adev->gfx.mec.num_mec = 1;
4377                 adev->gfx.mec.num_pipe_per_mec = 4;
4378                 adev->gfx.mec.num_queue_per_pipe = 8;
4379                 break;
4380         }
4381
4382         /* KIQ event */
4383         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4384                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4385                               &adev->gfx.kiq.irq);
4386         if (r)
4387                 return r;
4388
4389         /* EOP Event */
4390         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4391                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4392                               &adev->gfx.eop_irq);
4393         if (r)
4394                 return r;
4395
4396         /* Privileged reg */
4397         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4398                               &adev->gfx.priv_reg_irq);
4399         if (r)
4400                 return r;
4401
4402         /* Privileged inst */
4403         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4404                               &adev->gfx.priv_inst_irq);
4405         if (r)
4406                 return r;
4407
4408         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4409
4410         gfx_v10_0_scratch_init(adev);
4411
4412         r = gfx_v10_0_me_init(adev);
4413         if (r)
4414                 return r;
4415
4416         r = gfx_v10_0_rlc_init(adev);
4417         if (r) {
4418                 DRM_ERROR("Failed to init rlc BOs!\n");
4419                 return r;
4420         }
4421
4422         r = gfx_v10_0_mec_init(adev);
4423         if (r) {
4424                 DRM_ERROR("Failed to init MEC BOs!\n");
4425                 return r;
4426         }
4427
4428         /* set up the gfx ring */
4429         for (i = 0; i < adev->gfx.me.num_me; i++) {
4430                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4431                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4432                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4433                                         continue;
4434
4435                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4436                                                             i, k, j);
4437                                 if (r)
4438                                         return r;
4439                                 ring_id++;
4440                         }
4441                 }
4442         }
4443
4444         ring_id = 0;
4445         /* set up the compute queues - allocate horizontally across pipes */
4446         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4447                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4448                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4449                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4450                                                                      j))
4451                                         continue;
4452
4453                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4454                                                                 i, k, j);
4455                                 if (r)
4456                                         return r;
4457
4458                                 ring_id++;
4459                         }
4460                 }
4461         }
4462
4463         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4464         if (r) {
4465                 DRM_ERROR("Failed to init KIQ BOs!\n");
4466                 return r;
4467         }
4468
4469         kiq = &adev->gfx.kiq;
4470         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4471         if (r)
4472                 return r;
4473
4474         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4475         if (r)
4476                 return r;
4477
4478         /* allocate visible FB for rlc auto-loading fw */
4479         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4480                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4481                 if (r)
4482                         return r;
4483         }
4484
4485         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4486
4487         gfx_v10_0_gpu_early_init(adev);
4488
4489         return 0;
4490 }
4491
4492 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4493 {
4494         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4495                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4496                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4497 }
4498
4499 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4500 {
4501         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4502                               &adev->gfx.ce.ce_fw_gpu_addr,
4503                               (void **)&adev->gfx.ce.ce_fw_ptr);
4504 }
4505
4506 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4507 {
4508         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4509                               &adev->gfx.me.me_fw_gpu_addr,
4510                               (void **)&adev->gfx.me.me_fw_ptr);
4511 }
4512
4513 static int gfx_v10_0_sw_fini(void *handle)
4514 {
4515         int i;
4516         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4517
4518         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4519                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4520         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4521                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4522
4523         amdgpu_gfx_mqd_sw_fini(adev);
4524         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4525         amdgpu_gfx_kiq_fini(adev);
4526
4527         gfx_v10_0_pfp_fini(adev);
4528         gfx_v10_0_ce_fini(adev);
4529         gfx_v10_0_me_fini(adev);
4530         gfx_v10_0_rlc_fini(adev);
4531         gfx_v10_0_mec_fini(adev);
4532
4533         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4534                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4535
4536         gfx_v10_0_free_microcode(adev);
4537
4538         return 0;
4539 }
4540
4541 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4542                                    u32 sh_num, u32 instance)
4543 {
4544         u32 data;
4545
4546         if (instance == 0xffffffff)
4547                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4548                                      INSTANCE_BROADCAST_WRITES, 1);
4549         else
4550                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4551                                      instance);
4552
4553         if (se_num == 0xffffffff)
4554                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4555                                      1);
4556         else
4557                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4558
4559         if (sh_num == 0xffffffff)
4560                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4561                                      1);
4562         else
4563                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4564
4565         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4566 }
4567
4568 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4569 {
4570         u32 data, mask;
4571
4572         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4573         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4574
4575         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4576         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4577
4578         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4579                                          adev->gfx.config.max_sh_per_se);
4580
4581         return (~data) & mask;
4582 }
4583
4584 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4585 {
4586         int i, j;
4587         u32 data;
4588         u32 active_rbs = 0;
4589         u32 bitmap;
4590         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4591                                         adev->gfx.config.max_sh_per_se;
4592
4593         mutex_lock(&adev->grbm_idx_mutex);
4594         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4595                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4596                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4597                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
4598                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4599                                 continue;
4600                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4601                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4602                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4603                                                rb_bitmap_width_per_sh);
4604                 }
4605         }
4606         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4607         mutex_unlock(&adev->grbm_idx_mutex);
4608
4609         adev->gfx.config.backend_enable_mask = active_rbs;
4610         adev->gfx.config.num_rbs = hweight32(active_rbs);
4611 }
4612
4613 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4614 {
4615         uint32_t num_sc;
4616         uint32_t enabled_rb_per_sh;
4617         uint32_t active_rb_bitmap;
4618         uint32_t num_rb_per_sc;
4619         uint32_t num_packer_per_sc;
4620         uint32_t pa_sc_tile_steering_override;
4621
4622         /* for ASICs that integrates GFX v10.3
4623          * pa_sc_tile_steering_override should be set to 0 */
4624         if (adev->asic_type == CHIP_SIENNA_CICHLID ||
4625             adev->asic_type == CHIP_NAVY_FLOUNDER)
4626                 return 0;
4627
4628         /* init num_sc */
4629         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4630                         adev->gfx.config.num_sc_per_sh;
4631         /* init num_rb_per_sc */
4632         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4633         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4634         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4635         /* init num_packer_per_sc */
4636         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4637
4638         pa_sc_tile_steering_override = 0;
4639         pa_sc_tile_steering_override |=
4640                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4641                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4642         pa_sc_tile_steering_override |=
4643                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4644                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4645         pa_sc_tile_steering_override |=
4646                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4647                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4648
4649         return pa_sc_tile_steering_override;
4650 }
4651
4652 #define DEFAULT_SH_MEM_BASES    (0x6000)
4653
4654 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4655 {
4656         int i;
4657         uint32_t sh_mem_bases;
4658
4659         /*
4660          * Configure apertures:
4661          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4662          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4663          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4664          */
4665         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4666
4667         mutex_lock(&adev->srbm_mutex);
4668         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4669                 nv_grbm_select(adev, 0, 0, 0, i);
4670                 /* CP and shaders */
4671                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4672                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4673         }
4674         nv_grbm_select(adev, 0, 0, 0, 0);
4675         mutex_unlock(&adev->srbm_mutex);
4676
4677         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4678            acccess. These should be enabled by FW for target VMIDs. */
4679         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4680                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4681                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4682                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4683                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4684         }
4685 }
4686
4687 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4688 {
4689         int vmid;
4690
4691         /*
4692          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4693          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4694          * the driver can enable them for graphics. VMID0 should maintain
4695          * access so that HWS firmware can save/restore entries.
4696          */
4697         for (vmid = 1; vmid < 16; vmid++) {
4698                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4699                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4700                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4701                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4702         }
4703 }
4704
4705
4706 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4707 {
4708         int i, j, k;
4709         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4710         u32 tmp, wgp_active_bitmap = 0;
4711         u32 gcrd_targets_disable_tcp = 0;
4712         u32 utcl_invreq_disable = 0;
4713         /*
4714          * GCRD_TARGETS_DISABLE field contains
4715          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4716          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4717          */
4718         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4719                 2 * max_wgp_per_sh + /* TCP */
4720                 max_wgp_per_sh + /* SQC */
4721                 4); /* GL1C */
4722         /*
4723          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4724          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4725          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4726          */
4727         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4728                 2 * max_wgp_per_sh + /* TCP */
4729                 2 * max_wgp_per_sh + /* SQC */
4730                 4 + /* RMI */
4731                 1); /* SQG */
4732
4733         if (adev->asic_type == CHIP_NAVI10 ||
4734             adev->asic_type == CHIP_NAVI14 ||
4735             adev->asic_type == CHIP_NAVI12) {
4736                 mutex_lock(&adev->grbm_idx_mutex);
4737                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4738                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4739                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4740                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4741                                 /*
4742                                  * Set corresponding TCP bits for the inactive WGPs in
4743                                  * GCRD_SA_TARGETS_DISABLE
4744                                  */
4745                                 gcrd_targets_disable_tcp = 0;
4746                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4747                                 utcl_invreq_disable = 0;
4748
4749                                 for (k = 0; k < max_wgp_per_sh; k++) {
4750                                         if (!(wgp_active_bitmap & (1 << k))) {
4751                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
4752                                                 utcl_invreq_disable |= (3 << (2 * k)) |
4753                                                         (3 << (2 * (max_wgp_per_sh + k)));
4754                                         }
4755                                 }
4756
4757                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4758                                 /* only override TCP & SQC bits */
4759                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4760                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4761                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4762
4763                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4764                                 /* only override TCP bits */
4765                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4766                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4767                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4768                         }
4769                 }
4770
4771                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4772                 mutex_unlock(&adev->grbm_idx_mutex);
4773         }
4774 }
4775
4776 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4777 {
4778         /* TCCs are global (not instanced). */
4779         uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4780                                RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4781
4782         adev->gfx.config.tcc_disabled_mask =
4783                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4784                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4785 }
4786
4787 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4788 {
4789         u32 tmp;
4790         int i;
4791
4792         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4793
4794         gfx_v10_0_setup_rb(adev);
4795         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4796         gfx_v10_0_get_tcc_info(adev);
4797         adev->gfx.config.pa_sc_tile_steering_override =
4798                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4799
4800         /* XXX SH_MEM regs */
4801         /* where to put LDS, scratch, GPUVM in FSA64 space */
4802         mutex_lock(&adev->srbm_mutex);
4803         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4804                 nv_grbm_select(adev, 0, 0, 0, i);
4805                 /* CP and shaders */
4806                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4807                 if (i != 0) {
4808                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4809                                 (adev->gmc.private_aperture_start >> 48));
4810                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4811                                 (adev->gmc.shared_aperture_start >> 48));
4812                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4813                 }
4814         }
4815         nv_grbm_select(adev, 0, 0, 0, 0);
4816
4817         mutex_unlock(&adev->srbm_mutex);
4818
4819         gfx_v10_0_init_compute_vmid(adev);
4820         gfx_v10_0_init_gds_vmid(adev);
4821
4822 }
4823
4824 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4825                                                bool enable)
4826 {
4827         u32 tmp;
4828
4829         if (amdgpu_sriov_vf(adev))
4830                 return;
4831
4832         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
4833
4834         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
4835                             enable ? 1 : 0);
4836         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
4837                             enable ? 1 : 0);
4838         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
4839                             enable ? 1 : 0);
4840         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
4841                             enable ? 1 : 0);
4842
4843         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
4844 }
4845
4846 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
4847 {
4848         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4849
4850         /* csib */
4851         if (adev->asic_type == CHIP_NAVI12) {
4852                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
4853                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4854                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
4855                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4856                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4857         } else {
4858                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
4859                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4860                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
4861                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4862                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4863         }
4864         return 0;
4865 }
4866
4867 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
4868 {
4869         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4870
4871         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
4872         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
4873 }
4874
4875 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
4876 {
4877         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4878         udelay(50);
4879         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4880         udelay(50);
4881 }
4882
4883 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
4884                                              bool enable)
4885 {
4886         uint32_t rlc_pg_cntl;
4887
4888         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
4889
4890         if (!enable) {
4891                 /* RLC_PG_CNTL[23] = 0 (default)
4892                  * RLC will wait for handshake acks with SMU
4893                  * GFXOFF will be enabled
4894                  * RLC_PG_CNTL[23] = 1
4895                  * RLC will not issue any message to SMU
4896                  * hence no handshake between SMU & RLC
4897                  * GFXOFF will be disabled
4898                  */
4899                 rlc_pg_cntl |= 0x800000;
4900         } else
4901                 rlc_pg_cntl &= ~0x800000;
4902         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
4903 }
4904
4905 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
4906 {
4907         /* TODO: enable rlc & smu handshake until smu
4908          * and gfxoff feature works as expected */
4909         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
4910                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
4911
4912         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
4913         udelay(50);
4914 }
4915
4916 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
4917 {
4918         uint32_t tmp;
4919
4920         /* enable Save Restore Machine */
4921         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
4922         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
4923         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
4924         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
4925 }
4926
4927 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
4928 {
4929         const struct rlc_firmware_header_v2_0 *hdr;
4930         const __le32 *fw_data;
4931         unsigned i, fw_size;
4932
4933         if (!adev->gfx.rlc_fw)
4934                 return -EINVAL;
4935
4936         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4937         amdgpu_ucode_print_rlc_hdr(&hdr->header);
4938
4939         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4940                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4941         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4942
4943         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
4944                      RLCG_UCODE_LOADING_START_ADDRESS);
4945
4946         for (i = 0; i < fw_size; i++)
4947                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
4948                              le32_to_cpup(fw_data++));
4949
4950         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4951
4952         return 0;
4953 }
4954
4955 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
4956 {
4957         int r;
4958
4959         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4960
4961                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4962                 if (r)
4963                         return r;
4964
4965                 gfx_v10_0_init_csb(adev);
4966
4967                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
4968                         gfx_v10_0_rlc_enable_srm(adev);
4969         } else {
4970                 if (amdgpu_sriov_vf(adev)) {
4971                         gfx_v10_0_init_csb(adev);
4972                         return 0;
4973                 }
4974
4975                 adev->gfx.rlc.funcs->stop(adev);
4976
4977                 /* disable CG */
4978                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
4979
4980                 /* disable PG */
4981                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
4982
4983                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4984                         /* legacy rlc firmware loading */
4985                         r = gfx_v10_0_rlc_load_microcode(adev);
4986                         if (r)
4987                                 return r;
4988                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4989                         /* rlc backdoor autoload firmware */
4990                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
4991                         if (r)
4992                                 return r;
4993                 }
4994
4995                 gfx_v10_0_init_csb(adev);
4996
4997                 adev->gfx.rlc.funcs->start(adev);
4998
4999                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5000                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5001                         if (r)
5002                                 return r;
5003                 }
5004         }
5005         return 0;
5006 }
5007
5008 static struct {
5009         FIRMWARE_ID     id;
5010         unsigned int    offset;
5011         unsigned int    size;
5012 } rlc_autoload_info[FIRMWARE_ID_MAX];
5013
5014 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5015 {
5016         int ret;
5017         RLC_TABLE_OF_CONTENT *rlc_toc;
5018
5019         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5020                                         AMDGPU_GEM_DOMAIN_GTT,
5021                                         &adev->gfx.rlc.rlc_toc_bo,
5022                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5023                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5024         if (ret) {
5025                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5026                 return ret;
5027         }
5028
5029         /* Copy toc from psp sos fw to rlc toc buffer */
5030         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5031
5032         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5033         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5034                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5035                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5036                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5037                         /* Offset needs 4KB alignment */
5038                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5039                 }
5040
5041                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5042                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5043                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5044
5045                 rlc_toc++;
5046         }
5047
5048         return 0;
5049 }
5050
5051 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5052 {
5053         uint32_t total_size = 0;
5054         FIRMWARE_ID id;
5055         int ret;
5056
5057         ret = gfx_v10_0_parse_rlc_toc(adev);
5058         if (ret) {
5059                 dev_err(adev->dev, "failed to parse rlc toc\n");
5060                 return 0;
5061         }
5062
5063         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5064                 total_size += rlc_autoload_info[id].size;
5065
5066         /* In case the offset in rlc toc ucode is aligned */
5067         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5068                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5069                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5070
5071         return total_size;
5072 }
5073
5074 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5075 {
5076         int r;
5077         uint32_t total_size;
5078
5079         total_size = gfx_v10_0_calc_toc_total_size(adev);
5080
5081         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5082                                       AMDGPU_GEM_DOMAIN_GTT,
5083                                       &adev->gfx.rlc.rlc_autoload_bo,
5084                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5085                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5086         if (r) {
5087                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5088                 return r;
5089         }
5090
5091         return 0;
5092 }
5093
5094 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5095 {
5096         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5097                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5098                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5099         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5100                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5101                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5102 }
5103
5104 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5105                                                        FIRMWARE_ID id,
5106                                                        const void *fw_data,
5107                                                        uint32_t fw_size)
5108 {
5109         uint32_t toc_offset;
5110         uint32_t toc_fw_size;
5111         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5112
5113         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5114                 return;
5115
5116         toc_offset = rlc_autoload_info[id].offset;
5117         toc_fw_size = rlc_autoload_info[id].size;
5118
5119         if (fw_size == 0)
5120                 fw_size = toc_fw_size;
5121
5122         if (fw_size > toc_fw_size)
5123                 fw_size = toc_fw_size;
5124
5125         memcpy(ptr + toc_offset, fw_data, fw_size);
5126
5127         if (fw_size < toc_fw_size)
5128                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5129 }
5130
5131 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5132 {
5133         void *data;
5134         uint32_t size;
5135
5136         data = adev->gfx.rlc.rlc_toc_buf;
5137         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5138
5139         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5140                                                    FIRMWARE_ID_RLC_TOC,
5141                                                    data, size);
5142 }
5143
5144 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5145 {
5146         const __le32 *fw_data;
5147         uint32_t fw_size;
5148         const struct gfx_firmware_header_v1_0 *cp_hdr;
5149         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5150
5151         /* pfp ucode */
5152         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5153                 adev->gfx.pfp_fw->data;
5154         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5155                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5156         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5157         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5158                                                    FIRMWARE_ID_CP_PFP,
5159                                                    fw_data, fw_size);
5160
5161         /* ce ucode */
5162         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5163                 adev->gfx.ce_fw->data;
5164         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5165                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5166         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5167         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5168                                                    FIRMWARE_ID_CP_CE,
5169                                                    fw_data, fw_size);
5170
5171         /* me ucode */
5172         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5173                 adev->gfx.me_fw->data;
5174         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5175                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5176         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5177         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5178                                                    FIRMWARE_ID_CP_ME,
5179                                                    fw_data, fw_size);
5180
5181         /* rlc ucode */
5182         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5183                 adev->gfx.rlc_fw->data;
5184         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5185                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5186         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5187         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5188                                                    FIRMWARE_ID_RLC_G_UCODE,
5189                                                    fw_data, fw_size);
5190
5191         /* mec1 ucode */
5192         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5193                 adev->gfx.mec_fw->data;
5194         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5195                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5196         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5197                 cp_hdr->jt_size * 4;
5198         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5199                                                    FIRMWARE_ID_CP_MEC,
5200                                                    fw_data, fw_size);
5201         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5202 }
5203
5204 /* Temporarily put sdma part here */
5205 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5206 {
5207         const __le32 *fw_data;
5208         uint32_t fw_size;
5209         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5210         int i;
5211
5212         for (i = 0; i < adev->sdma.num_instances; i++) {
5213                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5214                         adev->sdma.instance[i].fw->data;
5215                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5216                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5217                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5218
5219                 if (i == 0) {
5220                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5221                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5222                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5223                                 FIRMWARE_ID_SDMA0_JT,
5224                                 (uint32_t *)fw_data +
5225                                 sdma_hdr->jt_offset,
5226                                 sdma_hdr->jt_size * 4);
5227                 } else if (i == 1) {
5228                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5229                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5230                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5231                                 FIRMWARE_ID_SDMA1_JT,
5232                                 (uint32_t *)fw_data +
5233                                 sdma_hdr->jt_offset,
5234                                 sdma_hdr->jt_size * 4);
5235                 }
5236         }
5237 }
5238
5239 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5240 {
5241         uint32_t rlc_g_offset, rlc_g_size, tmp;
5242         uint64_t gpu_addr;
5243
5244         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5245         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5246         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5247
5248         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5249         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5250         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5251
5252         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5253         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5254         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5255
5256         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5257         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5258                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5259                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5260                 return -EINVAL;
5261         }
5262
5263         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5264         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5265                 DRM_ERROR("RLC ROM should halt itself\n");
5266                 return -EINVAL;
5267         }
5268
5269         return 0;
5270 }
5271
5272 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5273 {
5274         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5275         uint32_t tmp;
5276         int i;
5277         uint64_t addr;
5278
5279         /* Trigger an invalidation of the L1 instruction caches */
5280         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5281         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5282         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5283
5284         /* Wait for invalidation complete */
5285         for (i = 0; i < usec_timeout; i++) {
5286                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5287                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5288                         INVALIDATE_CACHE_COMPLETE))
5289                         break;
5290                 udelay(1);
5291         }
5292
5293         if (i >= usec_timeout) {
5294                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5295                 return -EINVAL;
5296         }
5297
5298         /* Program me ucode address into intruction cache address register */
5299         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5300                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5301         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5302                         lower_32_bits(addr) & 0xFFFFF000);
5303         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5304                         upper_32_bits(addr));
5305
5306         return 0;
5307 }
5308
5309 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5310 {
5311         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5312         uint32_t tmp;
5313         int i;
5314         uint64_t addr;
5315
5316         /* Trigger an invalidation of the L1 instruction caches */
5317         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5318         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5319         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5320
5321         /* Wait for invalidation complete */
5322         for (i = 0; i < usec_timeout; i++) {
5323                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5324                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5325                         INVALIDATE_CACHE_COMPLETE))
5326                         break;
5327                 udelay(1);
5328         }
5329
5330         if (i >= usec_timeout) {
5331                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5332                 return -EINVAL;
5333         }
5334
5335         /* Program ce ucode address into intruction cache address register */
5336         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5337                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5338         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5339                         lower_32_bits(addr) & 0xFFFFF000);
5340         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5341                         upper_32_bits(addr));
5342
5343         return 0;
5344 }
5345
5346 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5347 {
5348         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5349         uint32_t tmp;
5350         int i;
5351         uint64_t addr;
5352
5353         /* Trigger an invalidation of the L1 instruction caches */
5354         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5355         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5356         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5357
5358         /* Wait for invalidation complete */
5359         for (i = 0; i < usec_timeout; i++) {
5360                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5361                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5362                         INVALIDATE_CACHE_COMPLETE))
5363                         break;
5364                 udelay(1);
5365         }
5366
5367         if (i >= usec_timeout) {
5368                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5369                 return -EINVAL;
5370         }
5371
5372         /* Program pfp ucode address into intruction cache address register */
5373         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5374                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5375         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5376                         lower_32_bits(addr) & 0xFFFFF000);
5377         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5378                         upper_32_bits(addr));
5379
5380         return 0;
5381 }
5382
5383 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5384 {
5385         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5386         uint32_t tmp;
5387         int i;
5388         uint64_t addr;
5389
5390         /* Trigger an invalidation of the L1 instruction caches */
5391         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5392         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5393         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5394
5395         /* Wait for invalidation complete */
5396         for (i = 0; i < usec_timeout; i++) {
5397                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5398                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5399                         INVALIDATE_CACHE_COMPLETE))
5400                         break;
5401                 udelay(1);
5402         }
5403
5404         if (i >= usec_timeout) {
5405                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5406                 return -EINVAL;
5407         }
5408
5409         /* Program mec1 ucode address into intruction cache address register */
5410         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5411                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5412         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5413                         lower_32_bits(addr) & 0xFFFFF000);
5414         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5415                         upper_32_bits(addr));
5416
5417         return 0;
5418 }
5419
5420 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5421 {
5422         uint32_t cp_status;
5423         uint32_t bootload_status;
5424         int i, r;
5425
5426         for (i = 0; i < adev->usec_timeout; i++) {
5427                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5428                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5429                 if ((cp_status == 0) &&
5430                     (REG_GET_FIELD(bootload_status,
5431                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5432                         break;
5433                 }
5434                 udelay(1);
5435         }
5436
5437         if (i >= adev->usec_timeout) {
5438                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5439                 return -ETIMEDOUT;
5440         }
5441
5442         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5443                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5444                 if (r)
5445                         return r;
5446
5447                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5448                 if (r)
5449                         return r;
5450
5451                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5452                 if (r)
5453                         return r;
5454
5455                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5456                 if (r)
5457                         return r;
5458         }
5459
5460         return 0;
5461 }
5462
5463 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5464 {
5465         int i;
5466         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5467
5468         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5469         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5470         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5471
5472         if (adev->asic_type == CHIP_NAVI12) {
5473                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5474         } else {
5475                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5476         }
5477
5478         for (i = 0; i < adev->usec_timeout; i++) {
5479                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5480                         break;
5481                 udelay(1);
5482         }
5483
5484         if (i >= adev->usec_timeout)
5485                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5486
5487         return 0;
5488 }
5489
5490 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5491 {
5492         int r;
5493         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5494         const __le32 *fw_data;
5495         unsigned i, fw_size;
5496         uint32_t tmp;
5497         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5498
5499         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5500                 adev->gfx.pfp_fw->data;
5501
5502         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5503
5504         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5505                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5506         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5507
5508         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5509                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5510                                       &adev->gfx.pfp.pfp_fw_obj,
5511                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5512                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5513         if (r) {
5514                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5515                 gfx_v10_0_pfp_fini(adev);
5516                 return r;
5517         }
5518
5519         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5520
5521         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5522         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5523
5524         /* Trigger an invalidation of the L1 instruction caches */
5525         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5526         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5527         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5528
5529         /* Wait for invalidation complete */
5530         for (i = 0; i < usec_timeout; i++) {
5531                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5532                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5533                         INVALIDATE_CACHE_COMPLETE))
5534                         break;
5535                 udelay(1);
5536         }
5537
5538         if (i >= usec_timeout) {
5539                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5540                 return -EINVAL;
5541         }
5542
5543         if (amdgpu_emu_mode == 1)
5544                 adev->nbio.funcs->hdp_flush(adev, NULL);
5545
5546         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5547         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5548         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5549         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5550         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5551         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5552         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5553                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5554         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5555                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5556
5557         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5558
5559         for (i = 0; i < pfp_hdr->jt_size; i++)
5560                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5561                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5562
5563         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5564
5565         return 0;
5566 }
5567
5568 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5569 {
5570         int r;
5571         const struct gfx_firmware_header_v1_0 *ce_hdr;
5572         const __le32 *fw_data;
5573         unsigned i, fw_size;
5574         uint32_t tmp;
5575         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5576
5577         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5578                 adev->gfx.ce_fw->data;
5579
5580         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5581
5582         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5583                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5584         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5585
5586         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5587                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5588                                       &adev->gfx.ce.ce_fw_obj,
5589                                       &adev->gfx.ce.ce_fw_gpu_addr,
5590                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5591         if (r) {
5592                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5593                 gfx_v10_0_ce_fini(adev);
5594                 return r;
5595         }
5596
5597         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5598
5599         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5600         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5601
5602         /* Trigger an invalidation of the L1 instruction caches */
5603         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5604         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5605         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5606
5607         /* Wait for invalidation complete */
5608         for (i = 0; i < usec_timeout; i++) {
5609                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5610                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5611                         INVALIDATE_CACHE_COMPLETE))
5612                         break;
5613                 udelay(1);
5614         }
5615
5616         if (i >= usec_timeout) {
5617                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5618                 return -EINVAL;
5619         }
5620
5621         if (amdgpu_emu_mode == 1)
5622                 adev->nbio.funcs->hdp_flush(adev, NULL);
5623
5624         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5625         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5626         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5627         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5628         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5629         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5630                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5631         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5632                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5633
5634         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5635
5636         for (i = 0; i < ce_hdr->jt_size; i++)
5637                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5638                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5639
5640         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5641
5642         return 0;
5643 }
5644
5645 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5646 {
5647         int r;
5648         const struct gfx_firmware_header_v1_0 *me_hdr;
5649         const __le32 *fw_data;
5650         unsigned i, fw_size;
5651         uint32_t tmp;
5652         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5653
5654         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5655                 adev->gfx.me_fw->data;
5656
5657         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5658
5659         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5660                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5661         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5662
5663         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5664                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5665                                       &adev->gfx.me.me_fw_obj,
5666                                       &adev->gfx.me.me_fw_gpu_addr,
5667                                       (void **)&adev->gfx.me.me_fw_ptr);
5668         if (r) {
5669                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5670                 gfx_v10_0_me_fini(adev);
5671                 return r;
5672         }
5673
5674         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5675
5676         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5677         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5678
5679         /* Trigger an invalidation of the L1 instruction caches */
5680         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5681         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5682         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5683
5684         /* Wait for invalidation complete */
5685         for (i = 0; i < usec_timeout; i++) {
5686                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5687                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5688                         INVALIDATE_CACHE_COMPLETE))
5689                         break;
5690                 udelay(1);
5691         }
5692
5693         if (i >= usec_timeout) {
5694                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5695                 return -EINVAL;
5696         }
5697
5698         if (amdgpu_emu_mode == 1)
5699                 adev->nbio.funcs->hdp_flush(adev, NULL);
5700
5701         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5702         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5703         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5704         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5705         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5706         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5707                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5708         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5709                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5710
5711         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5712
5713         for (i = 0; i < me_hdr->jt_size; i++)
5714                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5715                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5716
5717         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5718
5719         return 0;
5720 }
5721
5722 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5723 {
5724         int r;
5725
5726         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5727                 return -EINVAL;
5728
5729         gfx_v10_0_cp_gfx_enable(adev, false);
5730
5731         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5732         if (r) {
5733                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5734                 return r;
5735         }
5736
5737         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5738         if (r) {
5739                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5740                 return r;
5741         }
5742
5743         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5744         if (r) {
5745                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5746                 return r;
5747         }
5748
5749         return 0;
5750 }
5751
5752 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5753 {
5754         struct amdgpu_ring *ring;
5755         const struct cs_section_def *sect = NULL;
5756         const struct cs_extent_def *ext = NULL;
5757         int r, i;
5758         int ctx_reg_offset;
5759
5760         /* init the CP */
5761         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5762                      adev->gfx.config.max_hw_contexts - 1);
5763         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5764
5765         gfx_v10_0_cp_gfx_enable(adev, true);
5766
5767         ring = &adev->gfx.gfx_ring[0];
5768         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5769         if (r) {
5770                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5771                 return r;
5772         }
5773
5774         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5775         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5776
5777         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5778         amdgpu_ring_write(ring, 0x80000000);
5779         amdgpu_ring_write(ring, 0x80000000);
5780
5781         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5782                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5783                         if (sect->id == SECT_CONTEXT) {
5784                                 amdgpu_ring_write(ring,
5785                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5786                                                           ext->reg_count));
5787                                 amdgpu_ring_write(ring, ext->reg_index -
5788                                                   PACKET3_SET_CONTEXT_REG_START);
5789                                 for (i = 0; i < ext->reg_count; i++)
5790                                         amdgpu_ring_write(ring, ext->extent[i]);
5791                         }
5792                 }
5793         }
5794
5795         ctx_reg_offset =
5796                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5797         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5798         amdgpu_ring_write(ring, ctx_reg_offset);
5799         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5800
5801         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5802         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5803
5804         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5805         amdgpu_ring_write(ring, 0);
5806
5807         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5808         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5809         amdgpu_ring_write(ring, 0x8000);
5810         amdgpu_ring_write(ring, 0x8000);
5811
5812         amdgpu_ring_commit(ring);
5813
5814         /* submit cs packet to copy state 0 to next available state */
5815         if (adev->gfx.num_gfx_rings > 1) {
5816                 /* maximum supported gfx ring is 2 */
5817                 ring = &adev->gfx.gfx_ring[1];
5818                 r = amdgpu_ring_alloc(ring, 2);
5819                 if (r) {
5820                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5821                         return r;
5822                 }
5823
5824                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5825                 amdgpu_ring_write(ring, 0);
5826
5827                 amdgpu_ring_commit(ring);
5828         }
5829         return 0;
5830 }
5831
5832 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5833                                          CP_PIPE_ID pipe)
5834 {
5835         u32 tmp;
5836
5837         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
5838         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
5839
5840         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
5841 }
5842
5843 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
5844                                           struct amdgpu_ring *ring)
5845 {
5846         u32 tmp;
5847
5848         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
5849         if (ring->use_doorbell) {
5850                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5851                                     DOORBELL_OFFSET, ring->doorbell_index);
5852                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5853                                     DOORBELL_EN, 1);
5854         } else {
5855                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5856                                     DOORBELL_EN, 0);
5857         }
5858         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
5859         switch (adev->asic_type) {
5860         case CHIP_SIENNA_CICHLID:
5861         case CHIP_NAVY_FLOUNDER:
5862                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5863                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
5864                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5865
5866                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5867                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
5868                 break;
5869         default:
5870                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5871                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
5872                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5873
5874                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5875                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
5876                 break;
5877         }
5878 }
5879
5880 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
5881 {
5882         struct amdgpu_ring *ring;
5883         u32 tmp;
5884         u32 rb_bufsz;
5885         u64 rb_addr, rptr_addr, wptr_gpu_addr;
5886         u32 i;
5887
5888         /* Set the write pointer delay */
5889         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
5890
5891         /* set the RB to use vmid 0 */
5892         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
5893
5894         /* Init gfx ring 0 for pipe 0 */
5895         mutex_lock(&adev->srbm_mutex);
5896         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5897
5898         /* Set ring buffer size */
5899         ring = &adev->gfx.gfx_ring[0];
5900         rb_bufsz = order_base_2(ring->ring_size / 8);
5901         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
5902         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
5903 #ifdef __BIG_ENDIAN
5904         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
5905 #endif
5906         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5907
5908         /* Initialize the ring buffer's write pointers */
5909         ring->wptr = 0;
5910         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
5911         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
5912
5913         /* set the wb address wether it's enabled or not */
5914         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5915         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
5916         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5917                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5918
5919         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5920         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5921                      lower_32_bits(wptr_gpu_addr));
5922         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5923                      upper_32_bits(wptr_gpu_addr));
5924
5925         mdelay(1);
5926         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5927
5928         rb_addr = ring->gpu_addr >> 8;
5929         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
5930         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
5931
5932         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
5933
5934         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5935         mutex_unlock(&adev->srbm_mutex);
5936
5937         /* Init gfx ring 1 for pipe 1 */
5938         if (adev->gfx.num_gfx_rings > 1) {
5939                 mutex_lock(&adev->srbm_mutex);
5940                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
5941                 /* maximum supported gfx ring is 2 */
5942                 ring = &adev->gfx.gfx_ring[1];
5943                 rb_bufsz = order_base_2(ring->ring_size / 8);
5944                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
5945                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
5946                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5947                 /* Initialize the ring buffer's write pointers */
5948                 ring->wptr = 0;
5949                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
5950                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
5951                 /* Set the wb address wether it's enabled or not */
5952                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5953                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
5954                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5955                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5956                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5957                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5958                              lower_32_bits(wptr_gpu_addr));
5959                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5960                              upper_32_bits(wptr_gpu_addr));
5961
5962                 mdelay(1);
5963                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5964
5965                 rb_addr = ring->gpu_addr >> 8;
5966                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
5967                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
5968                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
5969
5970                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5971                 mutex_unlock(&adev->srbm_mutex);
5972         }
5973         /* Switch to pipe 0 */
5974         mutex_lock(&adev->srbm_mutex);
5975         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5976         mutex_unlock(&adev->srbm_mutex);
5977
5978         /* start the ring */
5979         gfx_v10_0_cp_gfx_start(adev);
5980
5981         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5982                 ring = &adev->gfx.gfx_ring[i];
5983                 ring->sched.ready = true;
5984         }
5985
5986         return 0;
5987 }
5988
5989 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
5990 {
5991         if (enable) {
5992                 switch (adev->asic_type) {
5993                 case CHIP_SIENNA_CICHLID:
5994                 case CHIP_NAVY_FLOUNDER:
5995                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
5996                         break;
5997                 default:
5998                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
5999                         break;
6000                 }
6001         } else {
6002                 switch (adev->asic_type) {
6003                 case CHIP_SIENNA_CICHLID:
6004                 case CHIP_NAVY_FLOUNDER:
6005                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6006                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6007                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6008                         break;
6009                 default:
6010                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6011                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6012                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6013                         break;
6014                 }
6015                 adev->gfx.kiq.ring.sched.ready = false;
6016         }
6017         udelay(50);
6018 }
6019
6020 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6021 {
6022         const struct gfx_firmware_header_v1_0 *mec_hdr;
6023         const __le32 *fw_data;
6024         unsigned i;
6025         u32 tmp;
6026         u32 usec_timeout = 50000; /* Wait for 50 ms */
6027
6028         if (!adev->gfx.mec_fw)
6029                 return -EINVAL;
6030
6031         gfx_v10_0_cp_compute_enable(adev, false);
6032
6033         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6034         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6035
6036         fw_data = (const __le32 *)
6037                 (adev->gfx.mec_fw->data +
6038                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6039
6040         /* Trigger an invalidation of the L1 instruction caches */
6041         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6042         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6043         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6044
6045         /* Wait for invalidation complete */
6046         for (i = 0; i < usec_timeout; i++) {
6047                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6048                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6049                                        INVALIDATE_CACHE_COMPLETE))
6050                         break;
6051                 udelay(1);
6052         }
6053
6054         if (i >= usec_timeout) {
6055                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6056                 return -EINVAL;
6057         }
6058
6059         if (amdgpu_emu_mode == 1)
6060                 adev->nbio.funcs->hdp_flush(adev, NULL);
6061
6062         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6063         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6064         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6065         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6066         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6067
6068         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6069                      0xFFFFF000);
6070         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6071                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6072
6073         /* MEC1 */
6074         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6075
6076         for (i = 0; i < mec_hdr->jt_size; i++)
6077                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6078                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6079
6080         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6081
6082         /*
6083          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6084          * different microcode than MEC1.
6085          */
6086
6087         return 0;
6088 }
6089
6090 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6091 {
6092         uint32_t tmp;
6093         struct amdgpu_device *adev = ring->adev;
6094
6095         /* tell RLC which is KIQ queue */
6096         switch (adev->asic_type) {
6097         case CHIP_SIENNA_CICHLID:
6098         case CHIP_NAVY_FLOUNDER:
6099                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6100                 tmp &= 0xffffff00;
6101                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6102                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6103                 tmp |= 0x80;
6104                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6105                 break;
6106         default:
6107                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6108                 tmp &= 0xffffff00;
6109                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6110                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6111                 tmp |= 0x80;
6112                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6113                 break;
6114         }
6115 }
6116
6117 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6118 {
6119         struct amdgpu_device *adev = ring->adev;
6120         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6121         uint64_t hqd_gpu_addr, wb_gpu_addr;
6122         uint32_t tmp;
6123         uint32_t rb_bufsz;
6124
6125         /* set up gfx hqd wptr */
6126         mqd->cp_gfx_hqd_wptr = 0;
6127         mqd->cp_gfx_hqd_wptr_hi = 0;
6128
6129         /* set the pointer to the MQD */
6130         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6131         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6132
6133         /* set up mqd control */
6134         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6135         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6136         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6137         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6138         mqd->cp_gfx_mqd_control = tmp;
6139
6140         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6141         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6142         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6143         mqd->cp_gfx_hqd_vmid = 0;
6144
6145         /* set up default queue priority level
6146          * 0x0 = low priority, 0x1 = high priority */
6147         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6148         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6149         mqd->cp_gfx_hqd_queue_priority = tmp;
6150
6151         /* set up time quantum */
6152         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6153         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6154         mqd->cp_gfx_hqd_quantum = tmp;
6155
6156         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6157         hqd_gpu_addr = ring->gpu_addr >> 8;
6158         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6159         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6160
6161         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6162         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6163         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6164         mqd->cp_gfx_hqd_rptr_addr_hi =
6165                 upper_32_bits(wb_gpu_addr) & 0xffff;
6166
6167         /* set up rb_wptr_poll addr */
6168         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6169         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6170         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6171
6172         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6173         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6174         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6175         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6176         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6177 #ifdef __BIG_ENDIAN
6178         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6179 #endif
6180         mqd->cp_gfx_hqd_cntl = tmp;
6181
6182         /* set up cp_doorbell_control */
6183         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6184         if (ring->use_doorbell) {
6185                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6186                                     DOORBELL_OFFSET, ring->doorbell_index);
6187                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6188                                     DOORBELL_EN, 1);
6189         } else
6190                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6191                                     DOORBELL_EN, 0);
6192         mqd->cp_rb_doorbell_control = tmp;
6193
6194         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6195         ring->wptr = 0;
6196         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6197
6198         /* active the queue */
6199         mqd->cp_gfx_hqd_active = 1;
6200
6201         return 0;
6202 }
6203
6204 #ifdef BRING_UP_DEBUG
6205 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6206 {
6207         struct amdgpu_device *adev = ring->adev;
6208         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6209
6210         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6211         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6212         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6213
6214         /* set GFX_MQD_BASE */
6215         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6216         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6217
6218         /* set GFX_MQD_CONTROL */
6219         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6220
6221         /* set GFX_HQD_VMID to 0 */
6222         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6223
6224         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6225                         mqd->cp_gfx_hqd_queue_priority);
6226         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6227
6228         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6229         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6230         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6231
6232         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6233         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6234         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6235
6236         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6237         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6238
6239         /* set RB_WPTR_POLL_ADDR */
6240         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6241         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6242
6243         /* set RB_DOORBELL_CONTROL */
6244         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6245
6246         /* active the queue */
6247         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6248
6249         return 0;
6250 }
6251 #endif
6252
6253 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6254 {
6255         struct amdgpu_device *adev = ring->adev;
6256         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6257         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6258
6259         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6260                 memset((void *)mqd, 0, sizeof(*mqd));
6261                 mutex_lock(&adev->srbm_mutex);
6262                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6263                 gfx_v10_0_gfx_mqd_init(ring);
6264 #ifdef BRING_UP_DEBUG
6265                 gfx_v10_0_gfx_queue_init_register(ring);
6266 #endif
6267                 nv_grbm_select(adev, 0, 0, 0, 0);
6268                 mutex_unlock(&adev->srbm_mutex);
6269                 if (adev->gfx.me.mqd_backup[mqd_idx])
6270                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6271         } else if (amdgpu_in_reset(adev)) {
6272                 /* reset mqd with the backup copy */
6273                 if (adev->gfx.me.mqd_backup[mqd_idx])
6274                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6275                 /* reset the ring */
6276                 ring->wptr = 0;
6277                 adev->wb.wb[ring->wptr_offs] = 0;
6278                 amdgpu_ring_clear_ring(ring);
6279 #ifdef BRING_UP_DEBUG
6280                 mutex_lock(&adev->srbm_mutex);
6281                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6282                 gfx_v10_0_gfx_queue_init_register(ring);
6283                 nv_grbm_select(adev, 0, 0, 0, 0);
6284                 mutex_unlock(&adev->srbm_mutex);
6285 #endif
6286         } else {
6287                 amdgpu_ring_clear_ring(ring);
6288         }
6289
6290         return 0;
6291 }
6292
6293 #ifndef BRING_UP_DEBUG
6294 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6295 {
6296         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6297         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6298         int r, i;
6299
6300         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6301                 return -EINVAL;
6302
6303         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6304                                         adev->gfx.num_gfx_rings);
6305         if (r) {
6306                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6307                 return r;
6308         }
6309
6310         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6311                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6312
6313         return amdgpu_ring_test_helper(kiq_ring);
6314 }
6315 #endif
6316
6317 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6318 {
6319         int r, i;
6320         struct amdgpu_ring *ring;
6321
6322         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6323                 ring = &adev->gfx.gfx_ring[i];
6324
6325                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6326                 if (unlikely(r != 0))
6327                         goto done;
6328
6329                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6330                 if (!r) {
6331                         r = gfx_v10_0_gfx_init_queue(ring);
6332                         amdgpu_bo_kunmap(ring->mqd_obj);
6333                         ring->mqd_ptr = NULL;
6334                 }
6335                 amdgpu_bo_unreserve(ring->mqd_obj);
6336                 if (r)
6337                         goto done;
6338         }
6339 #ifndef BRING_UP_DEBUG
6340         r = gfx_v10_0_kiq_enable_kgq(adev);
6341         if (r)
6342                 goto done;
6343 #endif
6344         r = gfx_v10_0_cp_gfx_start(adev);
6345         if (r)
6346                 goto done;
6347
6348         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6349                 ring = &adev->gfx.gfx_ring[i];
6350                 ring->sched.ready = true;
6351         }
6352 done:
6353         return r;
6354 }
6355
6356 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6357 {
6358         struct amdgpu_device *adev = ring->adev;
6359
6360         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6361                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
6362                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6363                         mqd->cp_hqd_queue_priority =
6364                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6365                 }
6366         }
6367 }
6368
6369 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6370 {
6371         struct amdgpu_device *adev = ring->adev;
6372         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6373         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6374         uint32_t tmp;
6375
6376         mqd->header = 0xC0310800;
6377         mqd->compute_pipelinestat_enable = 0x00000001;
6378         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6379         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6380         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6381         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6382         mqd->compute_misc_reserved = 0x00000003;
6383
6384         eop_base_addr = ring->eop_gpu_addr >> 8;
6385         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6386         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6387
6388         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6389         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6390         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6391                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6392
6393         mqd->cp_hqd_eop_control = tmp;
6394
6395         /* enable doorbell? */
6396         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6397
6398         if (ring->use_doorbell) {
6399                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6400                                     DOORBELL_OFFSET, ring->doorbell_index);
6401                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6402                                     DOORBELL_EN, 1);
6403                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6404                                     DOORBELL_SOURCE, 0);
6405                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6406                                     DOORBELL_HIT, 0);
6407         } else {
6408                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6409                                     DOORBELL_EN, 0);
6410         }
6411
6412         mqd->cp_hqd_pq_doorbell_control = tmp;
6413
6414         /* disable the queue if it's active */
6415         ring->wptr = 0;
6416         mqd->cp_hqd_dequeue_request = 0;
6417         mqd->cp_hqd_pq_rptr = 0;
6418         mqd->cp_hqd_pq_wptr_lo = 0;
6419         mqd->cp_hqd_pq_wptr_hi = 0;
6420
6421         /* set the pointer to the MQD */
6422         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6423         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6424
6425         /* set MQD vmid to 0 */
6426         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6427         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6428         mqd->cp_mqd_control = tmp;
6429
6430         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6431         hqd_gpu_addr = ring->gpu_addr >> 8;
6432         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6433         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6434
6435         /* set up the HQD, this is similar to CP_RB0_CNTL */
6436         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6437         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6438                             (order_base_2(ring->ring_size / 4) - 1));
6439         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6440                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6441 #ifdef __BIG_ENDIAN
6442         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6443 #endif
6444         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6445         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6446         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6447         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6448         mqd->cp_hqd_pq_control = tmp;
6449
6450         /* set the wb address whether it's enabled or not */
6451         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6452         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6453         mqd->cp_hqd_pq_rptr_report_addr_hi =
6454                 upper_32_bits(wb_gpu_addr) & 0xffff;
6455
6456         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6457         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6458         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6459         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6460
6461         tmp = 0;
6462         /* enable the doorbell if requested */
6463         if (ring->use_doorbell) {
6464                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6465                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6466                                 DOORBELL_OFFSET, ring->doorbell_index);
6467
6468                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6469                                     DOORBELL_EN, 1);
6470                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6471                                     DOORBELL_SOURCE, 0);
6472                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6473                                     DOORBELL_HIT, 0);
6474         }
6475
6476         mqd->cp_hqd_pq_doorbell_control = tmp;
6477
6478         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6479         ring->wptr = 0;
6480         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6481
6482         /* set the vmid for the queue */
6483         mqd->cp_hqd_vmid = 0;
6484
6485         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6486         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6487         mqd->cp_hqd_persistent_state = tmp;
6488
6489         /* set MIN_IB_AVAIL_SIZE */
6490         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6491         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6492         mqd->cp_hqd_ib_control = tmp;
6493
6494         /* set static priority for a compute queue/ring */
6495         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6496
6497         /* map_queues packet doesn't need activate the queue,
6498          * so only kiq need set this field.
6499          */
6500         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6501                 mqd->cp_hqd_active = 1;
6502
6503         return 0;
6504 }
6505
6506 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6507 {
6508         struct amdgpu_device *adev = ring->adev;
6509         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6510         int j;
6511
6512         /* inactivate the queue */
6513         if (amdgpu_sriov_vf(adev))
6514                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6515
6516         /* disable wptr polling */
6517         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6518
6519         /* write the EOP addr */
6520         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6521                mqd->cp_hqd_eop_base_addr_lo);
6522         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6523                mqd->cp_hqd_eop_base_addr_hi);
6524
6525         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6526         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6527                mqd->cp_hqd_eop_control);
6528
6529         /* enable doorbell? */
6530         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6531                mqd->cp_hqd_pq_doorbell_control);
6532
6533         /* disable the queue if it's active */
6534         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6535                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6536                 for (j = 0; j < adev->usec_timeout; j++) {
6537                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6538                                 break;
6539                         udelay(1);
6540                 }
6541                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6542                        mqd->cp_hqd_dequeue_request);
6543                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6544                        mqd->cp_hqd_pq_rptr);
6545                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6546                        mqd->cp_hqd_pq_wptr_lo);
6547                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6548                        mqd->cp_hqd_pq_wptr_hi);
6549         }
6550
6551         /* set the pointer to the MQD */
6552         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6553                mqd->cp_mqd_base_addr_lo);
6554         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6555                mqd->cp_mqd_base_addr_hi);
6556
6557         /* set MQD vmid to 0 */
6558         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6559                mqd->cp_mqd_control);
6560
6561         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6562         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6563                mqd->cp_hqd_pq_base_lo);
6564         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6565                mqd->cp_hqd_pq_base_hi);
6566
6567         /* set up the HQD, this is similar to CP_RB0_CNTL */
6568         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6569                mqd->cp_hqd_pq_control);
6570
6571         /* set the wb address whether it's enabled or not */
6572         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6573                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6574         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6575                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6576
6577         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6578         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6579                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6580         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6581                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6582
6583         /* enable the doorbell if requested */
6584         if (ring->use_doorbell) {
6585                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6586                         (adev->doorbell_index.kiq * 2) << 2);
6587                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6588                         (adev->doorbell_index.userqueue_end * 2) << 2);
6589         }
6590
6591         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6592                mqd->cp_hqd_pq_doorbell_control);
6593
6594         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6595         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6596                mqd->cp_hqd_pq_wptr_lo);
6597         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6598                mqd->cp_hqd_pq_wptr_hi);
6599
6600         /* set the vmid for the queue */
6601         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6602
6603         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6604                mqd->cp_hqd_persistent_state);
6605
6606         /* activate the queue */
6607         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6608                mqd->cp_hqd_active);
6609
6610         if (ring->use_doorbell)
6611                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6612
6613         return 0;
6614 }
6615
6616 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6617 {
6618         struct amdgpu_device *adev = ring->adev;
6619         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6620         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6621
6622         gfx_v10_0_kiq_setting(ring);
6623
6624         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6625                 /* reset MQD to a clean status */
6626                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6627                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6628
6629                 /* reset ring buffer */
6630                 ring->wptr = 0;
6631                 amdgpu_ring_clear_ring(ring);
6632
6633                 mutex_lock(&adev->srbm_mutex);
6634                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6635                 gfx_v10_0_kiq_init_register(ring);
6636                 nv_grbm_select(adev, 0, 0, 0, 0);
6637                 mutex_unlock(&adev->srbm_mutex);
6638         } else {
6639                 memset((void *)mqd, 0, sizeof(*mqd));
6640                 mutex_lock(&adev->srbm_mutex);
6641                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6642                 gfx_v10_0_compute_mqd_init(ring);
6643                 gfx_v10_0_kiq_init_register(ring);
6644                 nv_grbm_select(adev, 0, 0, 0, 0);
6645                 mutex_unlock(&adev->srbm_mutex);
6646
6647                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6648                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6649         }
6650
6651         return 0;
6652 }
6653
6654 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6655 {
6656         struct amdgpu_device *adev = ring->adev;
6657         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6658         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6659
6660         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6661                 memset((void *)mqd, 0, sizeof(*mqd));
6662                 mutex_lock(&adev->srbm_mutex);
6663                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6664                 gfx_v10_0_compute_mqd_init(ring);
6665                 nv_grbm_select(adev, 0, 0, 0, 0);
6666                 mutex_unlock(&adev->srbm_mutex);
6667
6668                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6669                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6670         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6671                 /* reset MQD to a clean status */
6672                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6673                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6674
6675                 /* reset ring buffer */
6676                 ring->wptr = 0;
6677                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6678                 amdgpu_ring_clear_ring(ring);
6679         } else {
6680                 amdgpu_ring_clear_ring(ring);
6681         }
6682
6683         return 0;
6684 }
6685
6686 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6687 {
6688         struct amdgpu_ring *ring;
6689         int r;
6690
6691         ring = &adev->gfx.kiq.ring;
6692
6693         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6694         if (unlikely(r != 0))
6695                 return r;
6696
6697         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6698         if (unlikely(r != 0))
6699                 return r;
6700
6701         gfx_v10_0_kiq_init_queue(ring);
6702         amdgpu_bo_kunmap(ring->mqd_obj);
6703         ring->mqd_ptr = NULL;
6704         amdgpu_bo_unreserve(ring->mqd_obj);
6705         ring->sched.ready = true;
6706         return 0;
6707 }
6708
6709 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6710 {
6711         struct amdgpu_ring *ring = NULL;
6712         int r = 0, i;
6713
6714         gfx_v10_0_cp_compute_enable(adev, true);
6715
6716         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6717                 ring = &adev->gfx.compute_ring[i];
6718
6719                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6720                 if (unlikely(r != 0))
6721                         goto done;
6722                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6723                 if (!r) {
6724                         r = gfx_v10_0_kcq_init_queue(ring);
6725                         amdgpu_bo_kunmap(ring->mqd_obj);
6726                         ring->mqd_ptr = NULL;
6727                 }
6728                 amdgpu_bo_unreserve(ring->mqd_obj);
6729                 if (r)
6730                         goto done;
6731         }
6732
6733         r = amdgpu_gfx_enable_kcq(adev);
6734 done:
6735         return r;
6736 }
6737
6738 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6739 {
6740         int r, i;
6741         struct amdgpu_ring *ring;
6742
6743         if (!(adev->flags & AMD_IS_APU))
6744                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6745
6746         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6747                 /* legacy firmware loading */
6748                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6749                 if (r)
6750                         return r;
6751
6752                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6753                 if (r)
6754                         return r;
6755         }
6756
6757         r = gfx_v10_0_kiq_resume(adev);
6758         if (r)
6759                 return r;
6760
6761         r = gfx_v10_0_kcq_resume(adev);
6762         if (r)
6763                 return r;
6764
6765         if (!amdgpu_async_gfx_ring) {
6766                 r = gfx_v10_0_cp_gfx_resume(adev);
6767                 if (r)
6768                         return r;
6769         } else {
6770                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6771                 if (r)
6772                         return r;
6773         }
6774
6775         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6776                 ring = &adev->gfx.gfx_ring[i];
6777                 r = amdgpu_ring_test_helper(ring);
6778                 if (r)
6779                         return r;
6780         }
6781
6782         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6783                 ring = &adev->gfx.compute_ring[i];
6784                 r = amdgpu_ring_test_helper(ring);
6785                 if (r)
6786                         return r;
6787         }
6788
6789         return 0;
6790 }
6791
6792 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6793 {
6794         gfx_v10_0_cp_gfx_enable(adev, enable);
6795         gfx_v10_0_cp_compute_enable(adev, enable);
6796 }
6797
6798 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6799 {
6800         uint32_t data, pattern = 0xDEADBEEF;
6801
6802         /* check if mmVGT_ESGS_RING_SIZE_UMD
6803          * has been remapped to mmVGT_ESGS_RING_SIZE */
6804         switch (adev->asic_type) {
6805         case CHIP_SIENNA_CICHLID:
6806         case CHIP_NAVY_FLOUNDER:
6807                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6808                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6809                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6810
6811                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6812                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
6813                         return true;
6814                 } else {
6815                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6816                         return false;
6817                 }
6818                 break;
6819         default:
6820                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6821                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6822                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6823
6824                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6825                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6826                         return true;
6827                 } else {
6828                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6829                         return false;
6830                 }
6831                 break;
6832         }
6833 }
6834
6835 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6836 {
6837         uint32_t data;
6838
6839         /* initialize cam_index to 0
6840          * index will auto-inc after each data writting */
6841         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6842
6843         switch (adev->asic_type) {
6844         case CHIP_SIENNA_CICHLID:
6845         case CHIP_NAVY_FLOUNDER:
6846                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6847                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6848                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6849                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
6850                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6851                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6852                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6853
6854                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6855                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6856                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6857                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
6858                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6859                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6860                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6861
6862                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6863                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6864                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6865                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
6866                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6867                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6868                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6869
6870                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6871                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6872                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6873                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
6874                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6875                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6876                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6877
6878                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6879                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6880                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6881                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
6882                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6883                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6884                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6885
6886                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6887                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6888                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6889                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
6890                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6891                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6892                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6893
6894                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6895                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6896                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6897                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
6898                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6899                 break;
6900         default:
6901                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6902                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6903                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6904                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
6905                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6906                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6907                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6908
6909                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6910                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6911                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6912                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
6913                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6914                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6915                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6916
6917                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6918                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6919                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6920                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
6921                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6922                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6923                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6924
6925                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6926                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6927                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6928                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
6929                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6930                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6931                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6932
6933                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6934                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6935                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6936                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
6937                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6938                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6939                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6940
6941                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6942                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6943                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6944                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
6945                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6946                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6947                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6948
6949                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6950                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6951                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6952                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
6953                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6954                 break;
6955         }
6956
6957         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6958         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6959 }
6960
6961 static int gfx_v10_0_hw_init(void *handle)
6962 {
6963         int r;
6964         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6965
6966         if (!amdgpu_emu_mode)
6967                 gfx_v10_0_init_golden_registers(adev);
6968
6969         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6970                 /**
6971                  * For gfx 10, rlc firmware loading relies on smu firmware is
6972                  * loaded firstly, so in direct type, it has to load smc ucode
6973                  * here before rlc.
6974                  */
6975                 if (adev->smu.ppt_funcs != NULL) {
6976                         r = smu_load_microcode(&adev->smu);
6977                         if (r)
6978                                 return r;
6979
6980                         r = smu_check_fw_status(&adev->smu);
6981                         if (r) {
6982                                 pr_err("SMC firmware status is not correct\n");
6983                                 return r;
6984                         }
6985                 }
6986         }
6987
6988         /* if GRBM CAM not remapped, set up the remapping */
6989         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
6990                 gfx_v10_0_setup_grbm_cam_remapping(adev);
6991
6992         gfx_v10_0_constants_init(adev);
6993
6994         r = gfx_v10_0_rlc_resume(adev);
6995         if (r)
6996                 return r;
6997
6998         /*
6999          * init golden registers and rlc resume may override some registers,
7000          * reconfig them here
7001          */
7002         gfx_v10_0_tcp_harvest(adev);
7003
7004         r = gfx_v10_0_cp_resume(adev);
7005         if (r)
7006                 return r;
7007
7008         if (adev->asic_type == CHIP_SIENNA_CICHLID)
7009                 gfx_v10_3_program_pbb_mode(adev);
7010
7011         return r;
7012 }
7013
7014 #ifndef BRING_UP_DEBUG
7015 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7016 {
7017         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7018         struct amdgpu_ring *kiq_ring = &kiq->ring;
7019         int i;
7020
7021         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7022                 return -EINVAL;
7023
7024         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7025                                         adev->gfx.num_gfx_rings))
7026                 return -ENOMEM;
7027
7028         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7029                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7030                                            PREEMPT_QUEUES, 0, 0);
7031
7032         return amdgpu_ring_test_helper(kiq_ring);
7033 }
7034 #endif
7035
7036 static int gfx_v10_0_hw_fini(void *handle)
7037 {
7038         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7039         int r;
7040         uint32_t tmp;
7041
7042         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7043         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7044
7045         if (!adev->in_pci_err_recovery) {
7046 #ifndef BRING_UP_DEBUG
7047                 if (amdgpu_async_gfx_ring) {
7048                         r = gfx_v10_0_kiq_disable_kgq(adev);
7049                         if (r)
7050                                 DRM_ERROR("KGQ disable failed\n");
7051                 }
7052 #endif
7053                 if (amdgpu_gfx_disable_kcq(adev))
7054                         DRM_ERROR("KCQ disable failed\n");
7055         }
7056
7057         if (amdgpu_sriov_vf(adev)) {
7058                 gfx_v10_0_cp_gfx_enable(adev, false);
7059                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7060                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7061                 tmp &= 0xffffff00;
7062                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7063
7064                 return 0;
7065         }
7066         gfx_v10_0_cp_enable(adev, false);
7067         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7068
7069         return 0;
7070 }
7071
7072 static int gfx_v10_0_suspend(void *handle)
7073 {
7074         return gfx_v10_0_hw_fini(handle);
7075 }
7076
7077 static int gfx_v10_0_resume(void *handle)
7078 {
7079         return gfx_v10_0_hw_init(handle);
7080 }
7081
7082 static bool gfx_v10_0_is_idle(void *handle)
7083 {
7084         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7085
7086         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7087                                 GRBM_STATUS, GUI_ACTIVE))
7088                 return false;
7089         else
7090                 return true;
7091 }
7092
7093 static int gfx_v10_0_wait_for_idle(void *handle)
7094 {
7095         unsigned i;
7096         u32 tmp;
7097         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7098
7099         for (i = 0; i < adev->usec_timeout; i++) {
7100                 /* read MC_STATUS */
7101                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7102                         GRBM_STATUS__GUI_ACTIVE_MASK;
7103
7104                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7105                         return 0;
7106                 udelay(1);
7107         }
7108         return -ETIMEDOUT;
7109 }
7110
7111 static int gfx_v10_0_soft_reset(void *handle)
7112 {
7113         u32 grbm_soft_reset = 0;
7114         u32 tmp;
7115         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7116
7117         /* GRBM_STATUS */
7118         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7119         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7120                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7121                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7122                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7123                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7124                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7125                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7126                                                 1);
7127                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7128                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7129                                                 1);
7130         }
7131
7132         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7133                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7134                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7135                                                 1);
7136         }
7137
7138         /* GRBM_STATUS2 */
7139         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7140         switch (adev->asic_type) {
7141         case CHIP_SIENNA_CICHLID:
7142         case CHIP_NAVY_FLOUNDER:
7143                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7144                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7145                                                         GRBM_SOFT_RESET,
7146                                                         SOFT_RESET_RLC,
7147                                                         1);
7148                 break;
7149         default:
7150                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7151                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7152                                                         GRBM_SOFT_RESET,
7153                                                         SOFT_RESET_RLC,
7154                                                         1);
7155                 break;
7156         }
7157
7158         if (grbm_soft_reset) {
7159                 /* stop the rlc */
7160                 gfx_v10_0_rlc_stop(adev);
7161
7162                 /* Disable GFX parsing/prefetching */
7163                 gfx_v10_0_cp_gfx_enable(adev, false);
7164
7165                 /* Disable MEC parsing/prefetching */
7166                 gfx_v10_0_cp_compute_enable(adev, false);
7167
7168                 if (grbm_soft_reset) {
7169                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7170                         tmp |= grbm_soft_reset;
7171                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7172                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7173                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7174
7175                         udelay(50);
7176
7177                         tmp &= ~grbm_soft_reset;
7178                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7179                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7180                 }
7181
7182                 /* Wait a little for things to settle down */
7183                 udelay(50);
7184         }
7185         return 0;
7186 }
7187
7188 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7189 {
7190         uint64_t clock;
7191
7192         amdgpu_gfx_off_ctrl(adev, false);
7193         mutex_lock(&adev->gfx.gpu_clock_mutex);
7194         clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7195                 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7196         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7197         amdgpu_gfx_off_ctrl(adev, true);
7198         return clock;
7199 }
7200
7201 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7202                                            uint32_t vmid,
7203                                            uint32_t gds_base, uint32_t gds_size,
7204                                            uint32_t gws_base, uint32_t gws_size,
7205                                            uint32_t oa_base, uint32_t oa_size)
7206 {
7207         struct amdgpu_device *adev = ring->adev;
7208
7209         /* GDS Base */
7210         gfx_v10_0_write_data_to_reg(ring, 0, false,
7211                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7212                                     gds_base);
7213
7214         /* GDS Size */
7215         gfx_v10_0_write_data_to_reg(ring, 0, false,
7216                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7217                                     gds_size);
7218
7219         /* GWS */
7220         gfx_v10_0_write_data_to_reg(ring, 0, false,
7221                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7222                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7223
7224         /* OA */
7225         gfx_v10_0_write_data_to_reg(ring, 0, false,
7226                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7227                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7228 }
7229
7230 static int gfx_v10_0_early_init(void *handle)
7231 {
7232         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7233
7234         switch (adev->asic_type) {
7235         case CHIP_NAVI10:
7236         case CHIP_NAVI14:
7237         case CHIP_NAVI12:
7238                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7239                 break;
7240         case CHIP_SIENNA_CICHLID:
7241         case CHIP_NAVY_FLOUNDER:
7242                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7243                 break;
7244         default:
7245                 break;
7246         }
7247
7248         adev->gfx.num_compute_rings = amdgpu_num_kcq;
7249
7250         gfx_v10_0_set_kiq_pm4_funcs(adev);
7251         gfx_v10_0_set_ring_funcs(adev);
7252         gfx_v10_0_set_irq_funcs(adev);
7253         gfx_v10_0_set_gds_init(adev);
7254         gfx_v10_0_set_rlc_funcs(adev);
7255
7256         return 0;
7257 }
7258
7259 static int gfx_v10_0_late_init(void *handle)
7260 {
7261         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7262         int r;
7263
7264         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7265         if (r)
7266                 return r;
7267
7268         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7269         if (r)
7270                 return r;
7271
7272         return 0;
7273 }
7274
7275 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7276 {
7277         uint32_t rlc_cntl;
7278
7279         /* if RLC is not enabled, do nothing */
7280         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7281         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7282 }
7283
7284 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7285 {
7286         uint32_t data;
7287         unsigned i;
7288
7289         data = RLC_SAFE_MODE__CMD_MASK;
7290         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7291
7292         switch (adev->asic_type) {
7293         case CHIP_SIENNA_CICHLID:
7294         case CHIP_NAVY_FLOUNDER:
7295                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7296
7297                 /* wait for RLC_SAFE_MODE */
7298                 for (i = 0; i < adev->usec_timeout; i++) {
7299                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7300                                            RLC_SAFE_MODE, CMD))
7301                                 break;
7302                         udelay(1);
7303                 }
7304                 break;
7305         default:
7306                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7307
7308                 /* wait for RLC_SAFE_MODE */
7309                 for (i = 0; i < adev->usec_timeout; i++) {
7310                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7311                                            RLC_SAFE_MODE, CMD))
7312                                 break;
7313                         udelay(1);
7314                 }
7315                 break;
7316         }
7317 }
7318
7319 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7320 {
7321         uint32_t data;
7322
7323         data = RLC_SAFE_MODE__CMD_MASK;
7324         switch (adev->asic_type) {
7325         case CHIP_SIENNA_CICHLID:
7326         case CHIP_NAVY_FLOUNDER:
7327                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7328                 break;
7329         default:
7330                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7331                 break;
7332         }
7333 }
7334
7335 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7336                                                       bool enable)
7337 {
7338         uint32_t data, def;
7339
7340         /* It is disabled by HW by default */
7341         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7342                 /* 0 - Disable some blocks' MGCG */
7343                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7344                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7345                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7346                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7347
7348                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7349                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7350                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7351                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7352                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7353                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7354
7355                 if (def != data)
7356                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7357
7358                 /* MGLS is a global flag to control all MGLS in GFX */
7359                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7360                         /* 2 - RLC memory Light sleep */
7361                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7362                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7363                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7364                                 if (def != data)
7365                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7366                         }
7367                         /* 3 - CP memory Light sleep */
7368                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7369                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7370                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7371                                 if (def != data)
7372                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7373                         }
7374                 }
7375         } else {
7376                 /* 1 - MGCG_OVERRIDE */
7377                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7378                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7379                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7380                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7381                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7382                 if (def != data)
7383                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7384
7385                 /* 2 - disable MGLS in CP */
7386                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7387                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7388                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7389                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7390                 }
7391
7392                 /* 3 - disable MGLS in RLC */
7393                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7394                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7395                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7396                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7397                 }
7398
7399         }
7400 }
7401
7402 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7403                                            bool enable)
7404 {
7405         uint32_t data, def;
7406
7407         /* Enable 3D CGCG/CGLS */
7408         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7409                 /* write cmd to clear cgcg/cgls ov */
7410                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7411                 /* unset CGCG override */
7412                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7413                 /* update CGCG and CGLS override bits */
7414                 if (def != data)
7415                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7416                 /* enable 3Dcgcg FSM(0x0000363f) */
7417                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7418                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7419                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7420                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7421                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7422                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7423                 if (def != data)
7424                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7425
7426                 /* set IDLE_POLL_COUNT(0x00900100) */
7427                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7428                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7429                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7430                 if (def != data)
7431                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7432         } else {
7433                 /* Disable CGCG/CGLS */
7434                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7435                 /* disable cgcg, cgls should be disabled */
7436                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7437                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7438                 /* disable cgcg and cgls in FSM */
7439                 if (def != data)
7440                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7441         }
7442 }
7443
7444 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7445                                                       bool enable)
7446 {
7447         uint32_t def, data;
7448
7449         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7450                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7451                 /* unset CGCG override */
7452                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7453                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7454                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7455                 else
7456                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7457                 /* update CGCG and CGLS override bits */
7458                 if (def != data)
7459                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7460
7461                 /* enable cgcg FSM(0x0000363F) */
7462                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7463                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7464                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7465                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7466                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7467                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7468                 if (def != data)
7469                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7470
7471                 /* set IDLE_POLL_COUNT(0x00900100) */
7472                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7473                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7474                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7475                 if (def != data)
7476                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7477         } else {
7478                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7479                 /* reset CGCG/CGLS bits */
7480                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7481                 /* disable cgcg and cgls in FSM */
7482                 if (def != data)
7483                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7484         }
7485 }
7486
7487 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7488                                             bool enable)
7489 {
7490         amdgpu_gfx_rlc_enter_safe_mode(adev);
7491
7492         if (enable) {
7493                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7494                  * ===  MGCG + MGLS ===
7495                  */
7496                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7497                 /* ===  CGCG /CGLS for GFX 3D Only === */
7498                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7499                 /* ===  CGCG + CGLS === */
7500                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7501         } else {
7502                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7503                  * ===  CGCG + CGLS ===
7504                  */
7505                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7506                 /* ===  CGCG /CGLS for GFX 3D Only === */
7507                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7508                 /* ===  MGCG + MGLS === */
7509                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7510         }
7511
7512         if (adev->cg_flags &
7513             (AMD_CG_SUPPORT_GFX_MGCG |
7514              AMD_CG_SUPPORT_GFX_CGLS |
7515              AMD_CG_SUPPORT_GFX_CGCG |
7516              AMD_CG_SUPPORT_GFX_3D_CGCG |
7517              AMD_CG_SUPPORT_GFX_3D_CGLS))
7518                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7519
7520         amdgpu_gfx_rlc_exit_safe_mode(adev);
7521
7522         return 0;
7523 }
7524
7525 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7526 {
7527         u32 reg, data;
7528
7529         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7530         if (amdgpu_sriov_is_pp_one_vf(adev))
7531                 data = RREG32_NO_KIQ(reg);
7532         else
7533                 data = RREG32(reg);
7534
7535         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7536         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7537
7538         if (amdgpu_sriov_is_pp_one_vf(adev))
7539                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7540         else
7541                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7542 }
7543
7544 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7545                                         uint32_t offset,
7546                                         struct soc15_reg_rlcg *entries, int arr_size)
7547 {
7548         int i;
7549         uint32_t reg;
7550
7551         if (!entries)
7552                 return false;
7553
7554         for (i = 0; i < arr_size; i++) {
7555                 const struct soc15_reg_rlcg *entry;
7556
7557                 entry = &entries[i];
7558                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7559                 if (offset == reg)
7560                         return true;
7561         }
7562
7563         return false;
7564 }
7565
7566 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7567 {
7568         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7569 }
7570
7571 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7572         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7573         .set_safe_mode = gfx_v10_0_set_safe_mode,
7574         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7575         .init = gfx_v10_0_rlc_init,
7576         .get_csb_size = gfx_v10_0_get_csb_size,
7577         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7578         .resume = gfx_v10_0_rlc_resume,
7579         .stop = gfx_v10_0_rlc_stop,
7580         .reset = gfx_v10_0_rlc_reset,
7581         .start = gfx_v10_0_rlc_start,
7582         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7583 };
7584
7585 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7586         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7587         .set_safe_mode = gfx_v10_0_set_safe_mode,
7588         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7589         .init = gfx_v10_0_rlc_init,
7590         .get_csb_size = gfx_v10_0_get_csb_size,
7591         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7592         .resume = gfx_v10_0_rlc_resume,
7593         .stop = gfx_v10_0_rlc_stop,
7594         .reset = gfx_v10_0_rlc_reset,
7595         .start = gfx_v10_0_rlc_start,
7596         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7597         .rlcg_wreg = gfx_v10_rlcg_wreg,
7598         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7599 };
7600
7601 static int gfx_v10_0_set_powergating_state(void *handle,
7602                                           enum amd_powergating_state state)
7603 {
7604         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7605         bool enable = (state == AMD_PG_STATE_GATE);
7606
7607         if (amdgpu_sriov_vf(adev))
7608                 return 0;
7609
7610         switch (adev->asic_type) {
7611         case CHIP_NAVI10:
7612         case CHIP_NAVI14:
7613         case CHIP_NAVI12:
7614         case CHIP_SIENNA_CICHLID:
7615         case CHIP_NAVY_FLOUNDER:
7616                 amdgpu_gfx_off_ctrl(adev, enable);
7617                 break;
7618         default:
7619                 break;
7620         }
7621         return 0;
7622 }
7623
7624 static int gfx_v10_0_set_clockgating_state(void *handle,
7625                                           enum amd_clockgating_state state)
7626 {
7627         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7628
7629         if (amdgpu_sriov_vf(adev))
7630                 return 0;
7631
7632         switch (adev->asic_type) {
7633         case CHIP_NAVI10:
7634         case CHIP_NAVI14:
7635         case CHIP_NAVI12:
7636         case CHIP_SIENNA_CICHLID:
7637         case CHIP_NAVY_FLOUNDER:
7638                 gfx_v10_0_update_gfx_clock_gating(adev,
7639                                                  state == AMD_CG_STATE_GATE);
7640                 break;
7641         default:
7642                 break;
7643         }
7644         return 0;
7645 }
7646
7647 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7648 {
7649         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7650         int data;
7651
7652         /* AMD_CG_SUPPORT_GFX_MGCG */
7653         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7654         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7655                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
7656
7657         /* AMD_CG_SUPPORT_GFX_CGCG */
7658         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
7659         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7660                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
7661
7662         /* AMD_CG_SUPPORT_GFX_CGLS */
7663         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7664                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
7665
7666         /* AMD_CG_SUPPORT_GFX_RLC_LS */
7667         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
7668         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7669                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7670
7671         /* AMD_CG_SUPPORT_GFX_CP_LS */
7672         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
7673         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7674                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7675
7676         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
7677         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
7678         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7679                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7680
7681         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
7682         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7683                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7684 }
7685
7686 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7687 {
7688         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7689 }
7690
7691 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7692 {
7693         struct amdgpu_device *adev = ring->adev;
7694         u64 wptr;
7695
7696         /* XXX check if swapping is necessary on BE */
7697         if (ring->use_doorbell) {
7698                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
7699         } else {
7700                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
7701                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
7702         }
7703
7704         return wptr;
7705 }
7706
7707 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7708 {
7709         struct amdgpu_device *adev = ring->adev;
7710
7711         if (ring->use_doorbell) {
7712                 /* XXX check if swapping is necessary on BE */
7713                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7714                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7715         } else {
7716                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
7717                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
7718         }
7719 }
7720
7721 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
7722 {
7723         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
7724 }
7725
7726 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
7727 {
7728         u64 wptr;
7729
7730         /* XXX check if swapping is necessary on BE */
7731         if (ring->use_doorbell)
7732                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
7733         else
7734                 BUG();
7735         return wptr;
7736 }
7737
7738 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
7739 {
7740         struct amdgpu_device *adev = ring->adev;
7741
7742         /* XXX check if swapping is necessary on BE */
7743         if (ring->use_doorbell) {
7744                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7745                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7746         } else {
7747                 BUG(); /* only DOORBELL method supported on gfx10 now */
7748         }
7749 }
7750
7751 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
7752 {
7753         struct amdgpu_device *adev = ring->adev;
7754         u32 ref_and_mask, reg_mem_engine;
7755         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
7756
7757         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
7758                 switch (ring->me) {
7759                 case 1:
7760                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
7761                         break;
7762                 case 2:
7763                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
7764                         break;
7765                 default:
7766                         return;
7767                 }
7768                 reg_mem_engine = 0;
7769         } else {
7770                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
7771                 reg_mem_engine = 1; /* pfp */
7772         }
7773
7774         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
7775                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
7776                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
7777                                ref_and_mask, ref_and_mask, 0x20);
7778 }
7779
7780 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
7781                                        struct amdgpu_job *job,
7782                                        struct amdgpu_ib *ib,
7783                                        uint32_t flags)
7784 {
7785         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7786         u32 header, control = 0;
7787
7788         if (ib->flags & AMDGPU_IB_FLAG_CE)
7789                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
7790         else
7791                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
7792
7793         control |= ib->length_dw | (vmid << 24);
7794
7795         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
7796                 control |= INDIRECT_BUFFER_PRE_ENB(1);
7797
7798                 if (flags & AMDGPU_IB_PREEMPTED)
7799                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
7800
7801                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
7802                         gfx_v10_0_ring_emit_de_meta(ring,
7803                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7804         }
7805
7806         amdgpu_ring_write(ring, header);
7807         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7808         amdgpu_ring_write(ring,
7809 #ifdef __BIG_ENDIAN
7810                 (2 << 0) |
7811 #endif
7812                 lower_32_bits(ib->gpu_addr));
7813         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7814         amdgpu_ring_write(ring, control);
7815 }
7816
7817 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
7818                                            struct amdgpu_job *job,
7819                                            struct amdgpu_ib *ib,
7820                                            uint32_t flags)
7821 {
7822         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7823         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
7824
7825         /* Currently, there is a high possibility to get wave ID mismatch
7826          * between ME and GDS, leading to a hw deadlock, because ME generates
7827          * different wave IDs than the GDS expects. This situation happens
7828          * randomly when at least 5 compute pipes use GDS ordered append.
7829          * The wave IDs generated by ME are also wrong after suspend/resume.
7830          * Those are probably bugs somewhere else in the kernel driver.
7831          *
7832          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
7833          * GDS to 0 for this ring (me/pipe).
7834          */
7835         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
7836                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
7837                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
7838                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
7839         }
7840
7841         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
7842         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7843         amdgpu_ring_write(ring,
7844 #ifdef __BIG_ENDIAN
7845                                 (2 << 0) |
7846 #endif
7847                                 lower_32_bits(ib->gpu_addr));
7848         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7849         amdgpu_ring_write(ring, control);
7850 }
7851
7852 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
7853                                      u64 seq, unsigned flags)
7854 {
7855         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
7856         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
7857
7858         /* RELEASE_MEM - flush caches, send int */
7859         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
7860         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
7861                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
7862                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
7863                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
7864                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
7865                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
7866                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
7867         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
7868                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
7869
7870         /*
7871          * the address should be Qword aligned if 64bit write, Dword
7872          * aligned if only send 32bit data low (discard data high)
7873          */
7874         if (write64bit)
7875                 BUG_ON(addr & 0x7);
7876         else
7877                 BUG_ON(addr & 0x3);
7878         amdgpu_ring_write(ring, lower_32_bits(addr));
7879         amdgpu_ring_write(ring, upper_32_bits(addr));
7880         amdgpu_ring_write(ring, lower_32_bits(seq));
7881         amdgpu_ring_write(ring, upper_32_bits(seq));
7882         amdgpu_ring_write(ring, 0);
7883 }
7884
7885 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
7886 {
7887         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
7888         uint32_t seq = ring->fence_drv.sync_seq;
7889         uint64_t addr = ring->fence_drv.gpu_addr;
7890
7891         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
7892                                upper_32_bits(addr), seq, 0xffffffff, 4);
7893 }
7894
7895 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
7896                                          unsigned vmid, uint64_t pd_addr)
7897 {
7898         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
7899
7900         /* compute doesn't have PFP */
7901         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
7902                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
7903                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
7904                 amdgpu_ring_write(ring, 0x0);
7905         }
7906 }
7907
7908 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
7909                                           u64 seq, unsigned int flags)
7910 {
7911         struct amdgpu_device *adev = ring->adev;
7912
7913         /* we only allocate 32bit for each seq wb address */
7914         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
7915
7916         /* write fence seq to the "addr" */
7917         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7918         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7919                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
7920         amdgpu_ring_write(ring, lower_32_bits(addr));
7921         amdgpu_ring_write(ring, upper_32_bits(addr));
7922         amdgpu_ring_write(ring, lower_32_bits(seq));
7923
7924         if (flags & AMDGPU_FENCE_FLAG_INT) {
7925                 /* set register to trigger INT */
7926                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7927                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7928                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
7929                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
7930                 amdgpu_ring_write(ring, 0);
7931                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
7932         }
7933 }
7934
7935 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
7936 {
7937         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
7938         amdgpu_ring_write(ring, 0);
7939 }
7940
7941 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
7942                                          uint32_t flags)
7943 {
7944         uint32_t dw2 = 0;
7945
7946         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
7947                 gfx_v10_0_ring_emit_ce_meta(ring,
7948                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7949
7950         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
7951         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
7952                 /* set load_global_config & load_global_uconfig */
7953                 dw2 |= 0x8001;
7954                 /* set load_cs_sh_regs */
7955                 dw2 |= 0x01000000;
7956                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
7957                 dw2 |= 0x10002;
7958
7959                 /* set load_ce_ram if preamble presented */
7960                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
7961                         dw2 |= 0x10000000;
7962         } else {
7963                 /* still load_ce_ram if this is the first time preamble presented
7964                  * although there is no context switch happens.
7965                  */
7966                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
7967                         dw2 |= 0x10000000;
7968         }
7969
7970         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
7971         amdgpu_ring_write(ring, dw2);
7972         amdgpu_ring_write(ring, 0);
7973 }
7974
7975 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
7976 {
7977         unsigned ret;
7978
7979         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
7980         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
7981         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
7982         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
7983         ret = ring->wptr & ring->buf_mask;
7984         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
7985
7986         return ret;
7987 }
7988
7989 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
7990 {
7991         unsigned cur;
7992         BUG_ON(offset > ring->buf_mask);
7993         BUG_ON(ring->ring[offset] != 0x55aa55aa);
7994
7995         cur = (ring->wptr - 1) & ring->buf_mask;
7996         if (likely(cur > offset))
7997                 ring->ring[offset] = cur - offset;
7998         else
7999                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8000 }
8001
8002 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8003 {
8004         int i, r = 0;
8005         struct amdgpu_device *adev = ring->adev;
8006         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8007         struct amdgpu_ring *kiq_ring = &kiq->ring;
8008         unsigned long flags;
8009
8010         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8011                 return -EINVAL;
8012
8013         spin_lock_irqsave(&kiq->ring_lock, flags);
8014
8015         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8016                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8017                 return -ENOMEM;
8018         }
8019
8020         /* assert preemption condition */
8021         amdgpu_ring_set_preempt_cond_exec(ring, false);
8022
8023         /* assert IB preemption, emit the trailing fence */
8024         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8025                                    ring->trail_fence_gpu_addr,
8026                                    ++ring->trail_seq);
8027         amdgpu_ring_commit(kiq_ring);
8028
8029         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8030
8031         /* poll the trailing fence */
8032         for (i = 0; i < adev->usec_timeout; i++) {
8033                 if (ring->trail_seq ==
8034                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8035                         break;
8036                 udelay(1);
8037         }
8038
8039         if (i >= adev->usec_timeout) {
8040                 r = -EINVAL;
8041                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8042         }
8043
8044         /* deassert preemption condition */
8045         amdgpu_ring_set_preempt_cond_exec(ring, true);
8046         return r;
8047 }
8048
8049 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8050 {
8051         struct amdgpu_device *adev = ring->adev;
8052         struct v10_ce_ib_state ce_payload = {0};
8053         uint64_t csa_addr;
8054         int cnt;
8055
8056         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8057         csa_addr = amdgpu_csa_vaddr(ring->adev);
8058
8059         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8060         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8061                                  WRITE_DATA_DST_SEL(8) |
8062                                  WR_CONFIRM) |
8063                                  WRITE_DATA_CACHE_POLICY(0));
8064         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8065                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8066         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8067                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8068
8069         if (resume)
8070                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8071                                            offsetof(struct v10_gfx_meta_data,
8072                                                     ce_payload),
8073                                            sizeof(ce_payload) >> 2);
8074         else
8075                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8076                                            sizeof(ce_payload) >> 2);
8077 }
8078
8079 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8080 {
8081         struct amdgpu_device *adev = ring->adev;
8082         struct v10_de_ib_state de_payload = {0};
8083         uint64_t csa_addr, gds_addr;
8084         int cnt;
8085
8086         csa_addr = amdgpu_csa_vaddr(ring->adev);
8087         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8088                          PAGE_SIZE);
8089         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8090         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8091
8092         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8093         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8094         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8095                                  WRITE_DATA_DST_SEL(8) |
8096                                  WR_CONFIRM) |
8097                                  WRITE_DATA_CACHE_POLICY(0));
8098         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8099                               offsetof(struct v10_gfx_meta_data, de_payload)));
8100         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8101                               offsetof(struct v10_gfx_meta_data, de_payload)));
8102
8103         if (resume)
8104                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8105                                            offsetof(struct v10_gfx_meta_data,
8106                                                     de_payload),
8107                                            sizeof(de_payload) >> 2);
8108         else
8109                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8110                                            sizeof(de_payload) >> 2);
8111 }
8112
8113 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8114                                     bool secure)
8115 {
8116         uint32_t v = secure ? FRAME_TMZ : 0;
8117
8118         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8119         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8120 }
8121
8122 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8123                                      uint32_t reg_val_offs)
8124 {
8125         struct amdgpu_device *adev = ring->adev;
8126
8127         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8128         amdgpu_ring_write(ring, 0 |     /* src: register*/
8129                                 (5 << 8) |      /* dst: memory */
8130                                 (1 << 20));     /* write confirm */
8131         amdgpu_ring_write(ring, reg);
8132         amdgpu_ring_write(ring, 0);
8133         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8134                                 reg_val_offs * 4));
8135         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8136                                 reg_val_offs * 4));
8137 }
8138
8139 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8140                                    uint32_t val)
8141 {
8142         uint32_t cmd = 0;
8143
8144         switch (ring->funcs->type) {
8145         case AMDGPU_RING_TYPE_GFX:
8146                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8147                 break;
8148         case AMDGPU_RING_TYPE_KIQ:
8149                 cmd = (1 << 16); /* no inc addr */
8150                 break;
8151         default:
8152                 cmd = WR_CONFIRM;
8153                 break;
8154         }
8155         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8156         amdgpu_ring_write(ring, cmd);
8157         amdgpu_ring_write(ring, reg);
8158         amdgpu_ring_write(ring, 0);
8159         amdgpu_ring_write(ring, val);
8160 }
8161
8162 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8163                                         uint32_t val, uint32_t mask)
8164 {
8165         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8166 }
8167
8168 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8169                                                    uint32_t reg0, uint32_t reg1,
8170                                                    uint32_t ref, uint32_t mask)
8171 {
8172         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8173         struct amdgpu_device *adev = ring->adev;
8174         bool fw_version_ok = false;
8175
8176         fw_version_ok = adev->gfx.cp_fw_write_wait;
8177
8178         if (fw_version_ok)
8179                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8180                                        ref, mask, 0x20);
8181         else
8182                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8183                                                            ref, mask);
8184 }
8185
8186 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8187                                          unsigned vmid)
8188 {
8189         struct amdgpu_device *adev = ring->adev;
8190         uint32_t value = 0;
8191
8192         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8193         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8194         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8195         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8196         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8197 }
8198
8199 static void
8200 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8201                                       uint32_t me, uint32_t pipe,
8202                                       enum amdgpu_interrupt_state state)
8203 {
8204         uint32_t cp_int_cntl, cp_int_cntl_reg;
8205
8206         if (!me) {
8207                 switch (pipe) {
8208                 case 0:
8209                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8210                         break;
8211                 case 1:
8212                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8213                         break;
8214                 default:
8215                         DRM_DEBUG("invalid pipe %d\n", pipe);
8216                         return;
8217                 }
8218         } else {
8219                 DRM_DEBUG("invalid me %d\n", me);
8220                 return;
8221         }
8222
8223         switch (state) {
8224         case AMDGPU_IRQ_STATE_DISABLE:
8225                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8226                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8227                                             TIME_STAMP_INT_ENABLE, 0);
8228                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8229                 break;
8230         case AMDGPU_IRQ_STATE_ENABLE:
8231                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8232                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8233                                             TIME_STAMP_INT_ENABLE, 1);
8234                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8235                 break;
8236         default:
8237                 break;
8238         }
8239 }
8240
8241 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8242                                                      int me, int pipe,
8243                                                      enum amdgpu_interrupt_state state)
8244 {
8245         u32 mec_int_cntl, mec_int_cntl_reg;
8246
8247         /*
8248          * amdgpu controls only the first MEC. That's why this function only
8249          * handles the setting of interrupts for this specific MEC. All other
8250          * pipes' interrupts are set by amdkfd.
8251          */
8252
8253         if (me == 1) {
8254                 switch (pipe) {
8255                 case 0:
8256                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8257                         break;
8258                 case 1:
8259                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8260                         break;
8261                 case 2:
8262                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8263                         break;
8264                 case 3:
8265                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8266                         break;
8267                 default:
8268                         DRM_DEBUG("invalid pipe %d\n", pipe);
8269                         return;
8270                 }
8271         } else {
8272                 DRM_DEBUG("invalid me %d\n", me);
8273                 return;
8274         }
8275
8276         switch (state) {
8277         case AMDGPU_IRQ_STATE_DISABLE:
8278                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8279                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8280                                              TIME_STAMP_INT_ENABLE, 0);
8281                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8282                 break;
8283         case AMDGPU_IRQ_STATE_ENABLE:
8284                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8285                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8286                                              TIME_STAMP_INT_ENABLE, 1);
8287                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8288                 break;
8289         default:
8290                 break;
8291         }
8292 }
8293
8294 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8295                                             struct amdgpu_irq_src *src,
8296                                             unsigned type,
8297                                             enum amdgpu_interrupt_state state)
8298 {
8299         switch (type) {
8300         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8301                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8302                 break;
8303         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8304                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8305                 break;
8306         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8307                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8308                 break;
8309         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8310                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8311                 break;
8312         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8313                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8314                 break;
8315         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8316                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8317                 break;
8318         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8319                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8320                 break;
8321         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8322                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8323                 break;
8324         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8325                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8326                 break;
8327         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8328                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8329                 break;
8330         default:
8331                 break;
8332         }
8333         return 0;
8334 }
8335
8336 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8337                              struct amdgpu_irq_src *source,
8338                              struct amdgpu_iv_entry *entry)
8339 {
8340         int i;
8341         u8 me_id, pipe_id, queue_id;
8342         struct amdgpu_ring *ring;
8343
8344         DRM_DEBUG("IH: CP EOP\n");
8345         me_id = (entry->ring_id & 0x0c) >> 2;
8346         pipe_id = (entry->ring_id & 0x03) >> 0;
8347         queue_id = (entry->ring_id & 0x70) >> 4;
8348
8349         switch (me_id) {
8350         case 0:
8351                 if (pipe_id == 0)
8352                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8353                 else
8354                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8355                 break;
8356         case 1:
8357         case 2:
8358                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8359                         ring = &adev->gfx.compute_ring[i];
8360                         /* Per-queue interrupt is supported for MEC starting from VI.
8361                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8362                           */
8363                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8364                                 amdgpu_fence_process(ring);
8365                 }
8366                 break;
8367         }
8368         return 0;
8369 }
8370
8371 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8372                                               struct amdgpu_irq_src *source,
8373                                               unsigned type,
8374                                               enum amdgpu_interrupt_state state)
8375 {
8376         switch (state) {
8377         case AMDGPU_IRQ_STATE_DISABLE:
8378         case AMDGPU_IRQ_STATE_ENABLE:
8379                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8380                                PRIV_REG_INT_ENABLE,
8381                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8382                 break;
8383         default:
8384                 break;
8385         }
8386
8387         return 0;
8388 }
8389
8390 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8391                                                struct amdgpu_irq_src *source,
8392                                                unsigned type,
8393                                                enum amdgpu_interrupt_state state)
8394 {
8395         switch (state) {
8396         case AMDGPU_IRQ_STATE_DISABLE:
8397         case AMDGPU_IRQ_STATE_ENABLE:
8398                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8399                                PRIV_INSTR_INT_ENABLE,
8400                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8401         default:
8402                 break;
8403         }
8404
8405         return 0;
8406 }
8407
8408 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8409                                         struct amdgpu_iv_entry *entry)
8410 {
8411         u8 me_id, pipe_id, queue_id;
8412         struct amdgpu_ring *ring;
8413         int i;
8414
8415         me_id = (entry->ring_id & 0x0c) >> 2;
8416         pipe_id = (entry->ring_id & 0x03) >> 0;
8417         queue_id = (entry->ring_id & 0x70) >> 4;
8418
8419         switch (me_id) {
8420         case 0:
8421                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8422                         ring = &adev->gfx.gfx_ring[i];
8423                         /* we only enabled 1 gfx queue per pipe for now */
8424                         if (ring->me == me_id && ring->pipe == pipe_id)
8425                                 drm_sched_fault(&ring->sched);
8426                 }
8427                 break;
8428         case 1:
8429         case 2:
8430                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8431                         ring = &adev->gfx.compute_ring[i];
8432                         if (ring->me == me_id && ring->pipe == pipe_id &&
8433                             ring->queue == queue_id)
8434                                 drm_sched_fault(&ring->sched);
8435                 }
8436                 break;
8437         default:
8438                 BUG();
8439         }
8440 }
8441
8442 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8443                                   struct amdgpu_irq_src *source,
8444                                   struct amdgpu_iv_entry *entry)
8445 {
8446         DRM_ERROR("Illegal register access in command stream\n");
8447         gfx_v10_0_handle_priv_fault(adev, entry);
8448         return 0;
8449 }
8450
8451 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8452                                    struct amdgpu_irq_src *source,
8453                                    struct amdgpu_iv_entry *entry)
8454 {
8455         DRM_ERROR("Illegal instruction in command stream\n");
8456         gfx_v10_0_handle_priv_fault(adev, entry);
8457         return 0;
8458 }
8459
8460 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8461                                              struct amdgpu_irq_src *src,
8462                                              unsigned int type,
8463                                              enum amdgpu_interrupt_state state)
8464 {
8465         uint32_t tmp, target;
8466         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8467
8468         if (ring->me == 1)
8469                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8470         else
8471                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8472         target += ring->pipe;
8473
8474         switch (type) {
8475         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8476                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8477                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8478                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8479                                             GENERIC2_INT_ENABLE, 0);
8480                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8481
8482                         tmp = RREG32(target);
8483                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8484                                             GENERIC2_INT_ENABLE, 0);
8485                         WREG32(target, tmp);
8486                 } else {
8487                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8488                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8489                                             GENERIC2_INT_ENABLE, 1);
8490                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8491
8492                         tmp = RREG32(target);
8493                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8494                                             GENERIC2_INT_ENABLE, 1);
8495                         WREG32(target, tmp);
8496                 }
8497                 break;
8498         default:
8499                 BUG(); /* kiq only support GENERIC2_INT now */
8500                 break;
8501         }
8502         return 0;
8503 }
8504
8505 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8506                              struct amdgpu_irq_src *source,
8507                              struct amdgpu_iv_entry *entry)
8508 {
8509         u8 me_id, pipe_id, queue_id;
8510         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8511
8512         me_id = (entry->ring_id & 0x0c) >> 2;
8513         pipe_id = (entry->ring_id & 0x03) >> 0;
8514         queue_id = (entry->ring_id & 0x70) >> 4;
8515         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8516                    me_id, pipe_id, queue_id);
8517
8518         amdgpu_fence_process(ring);
8519         return 0;
8520 }
8521
8522 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8523 {
8524         const unsigned int gcr_cntl =
8525                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8526                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8527                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8528                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8529                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8530                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8531                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8532                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8533
8534         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8535         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8536         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8537         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8538         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8539         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8540         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8541         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8542         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8543 }
8544
8545 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8546         .name = "gfx_v10_0",
8547         .early_init = gfx_v10_0_early_init,
8548         .late_init = gfx_v10_0_late_init,
8549         .sw_init = gfx_v10_0_sw_init,
8550         .sw_fini = gfx_v10_0_sw_fini,
8551         .hw_init = gfx_v10_0_hw_init,
8552         .hw_fini = gfx_v10_0_hw_fini,
8553         .suspend = gfx_v10_0_suspend,
8554         .resume = gfx_v10_0_resume,
8555         .is_idle = gfx_v10_0_is_idle,
8556         .wait_for_idle = gfx_v10_0_wait_for_idle,
8557         .soft_reset = gfx_v10_0_soft_reset,
8558         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8559         .set_powergating_state = gfx_v10_0_set_powergating_state,
8560         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8561 };
8562
8563 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8564         .type = AMDGPU_RING_TYPE_GFX,
8565         .align_mask = 0xff,
8566         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8567         .support_64bit_ptrs = true,
8568         .vmhub = AMDGPU_GFXHUB_0,
8569         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8570         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8571         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8572         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8573                 5 + /* COND_EXEC */
8574                 7 + /* PIPELINE_SYNC */
8575                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8576                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8577                 2 + /* VM_FLUSH */
8578                 8 + /* FENCE for VM_FLUSH */
8579                 20 + /* GDS switch */
8580                 4 + /* double SWITCH_BUFFER,
8581                      * the first COND_EXEC jump to the place
8582                      * just prior to this double SWITCH_BUFFER
8583                      */
8584                 5 + /* COND_EXEC */
8585                 7 + /* HDP_flush */
8586                 4 + /* VGT_flush */
8587                 14 + /* CE_META */
8588                 31 + /* DE_META */
8589                 3 + /* CNTX_CTRL */
8590                 5 + /* HDP_INVL */
8591                 8 + 8 + /* FENCE x2 */
8592                 2 + /* SWITCH_BUFFER */
8593                 8, /* gfx_v10_0_emit_mem_sync */
8594         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8595         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8596         .emit_fence = gfx_v10_0_ring_emit_fence,
8597         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8598         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8599         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8600         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8601         .test_ring = gfx_v10_0_ring_test_ring,
8602         .test_ib = gfx_v10_0_ring_test_ib,
8603         .insert_nop = amdgpu_ring_insert_nop,
8604         .pad_ib = amdgpu_ring_generic_pad_ib,
8605         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8606         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8607         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8608         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8609         .preempt_ib = gfx_v10_0_ring_preempt_ib,
8610         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8611         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8612         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8613         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8614         .soft_recovery = gfx_v10_0_ring_soft_recovery,
8615         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8616 };
8617
8618 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8619         .type = AMDGPU_RING_TYPE_COMPUTE,
8620         .align_mask = 0xff,
8621         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8622         .support_64bit_ptrs = true,
8623         .vmhub = AMDGPU_GFXHUB_0,
8624         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8625         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8626         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8627         .emit_frame_size =
8628                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8629                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8630                 5 + /* hdp invalidate */
8631                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8632                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8633                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8634                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8635                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8636                 8, /* gfx_v10_0_emit_mem_sync */
8637         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8638         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8639         .emit_fence = gfx_v10_0_ring_emit_fence,
8640         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8641         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8642         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8643         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8644         .test_ring = gfx_v10_0_ring_test_ring,
8645         .test_ib = gfx_v10_0_ring_test_ib,
8646         .insert_nop = amdgpu_ring_insert_nop,
8647         .pad_ib = amdgpu_ring_generic_pad_ib,
8648         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8649         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8650         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8651         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8652 };
8653
8654 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8655         .type = AMDGPU_RING_TYPE_KIQ,
8656         .align_mask = 0xff,
8657         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8658         .support_64bit_ptrs = true,
8659         .vmhub = AMDGPU_GFXHUB_0,
8660         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8661         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8662         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8663         .emit_frame_size =
8664                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8665                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8666                 5 + /*hdp invalidate */
8667                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8668                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8669                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8670                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8671                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8672         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8673         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8674         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8675         .test_ring = gfx_v10_0_ring_test_ring,
8676         .test_ib = gfx_v10_0_ring_test_ib,
8677         .insert_nop = amdgpu_ring_insert_nop,
8678         .pad_ib = amdgpu_ring_generic_pad_ib,
8679         .emit_rreg = gfx_v10_0_ring_emit_rreg,
8680         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8681         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8682         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8683 };
8684
8685 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8686 {
8687         int i;
8688
8689         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8690
8691         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8692                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8693
8694         for (i = 0; i < adev->gfx.num_compute_rings; i++)
8695                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8696 }
8697
8698 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8699         .set = gfx_v10_0_set_eop_interrupt_state,
8700         .process = gfx_v10_0_eop_irq,
8701 };
8702
8703 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8704         .set = gfx_v10_0_set_priv_reg_fault_state,
8705         .process = gfx_v10_0_priv_reg_irq,
8706 };
8707
8708 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8709         .set = gfx_v10_0_set_priv_inst_fault_state,
8710         .process = gfx_v10_0_priv_inst_irq,
8711 };
8712
8713 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
8714         .set = gfx_v10_0_kiq_set_interrupt_state,
8715         .process = gfx_v10_0_kiq_irq,
8716 };
8717
8718 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
8719 {
8720         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
8721         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
8722
8723         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
8724         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
8725
8726         adev->gfx.priv_reg_irq.num_types = 1;
8727         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
8728
8729         adev->gfx.priv_inst_irq.num_types = 1;
8730         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
8731 }
8732
8733 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
8734 {
8735         switch (adev->asic_type) {
8736         case CHIP_NAVI10:
8737         case CHIP_NAVI14:
8738         case CHIP_SIENNA_CICHLID:
8739         case CHIP_NAVY_FLOUNDER:
8740                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
8741                 break;
8742         case CHIP_NAVI12:
8743                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
8744                 break;
8745         default:
8746                 break;
8747         }
8748 }
8749
8750 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
8751 {
8752         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
8753                             adev->gfx.config.max_sh_per_se *
8754                             adev->gfx.config.max_shader_engines;
8755
8756         adev->gds.gds_size = 0x10000;
8757         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
8758         adev->gds.gws_size = 64;
8759         adev->gds.oa_size = 16;
8760 }
8761
8762 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
8763                                                           u32 bitmap)
8764 {
8765         u32 data;
8766
8767         if (!bitmap)
8768                 return;
8769
8770         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8771         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8772
8773         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
8774 }
8775
8776 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
8777 {
8778         u32 data, wgp_bitmask;
8779         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
8780         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
8781
8782         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8783         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8784
8785         wgp_bitmask =
8786                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
8787
8788         return (~data) & wgp_bitmask;
8789 }
8790
8791 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
8792 {
8793         u32 wgp_idx, wgp_active_bitmap;
8794         u32 cu_bitmap_per_wgp, cu_active_bitmap;
8795
8796         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
8797         cu_active_bitmap = 0;
8798
8799         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
8800                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
8801                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
8802                 if (wgp_active_bitmap & (1 << wgp_idx))
8803                         cu_active_bitmap |= cu_bitmap_per_wgp;
8804         }
8805
8806         return cu_active_bitmap;
8807 }
8808
8809 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
8810                                  struct amdgpu_cu_info *cu_info)
8811 {
8812         int i, j, k, counter, active_cu_number = 0;
8813         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
8814         unsigned disable_masks[4 * 2];
8815
8816         if (!adev || !cu_info)
8817                 return -EINVAL;
8818
8819         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
8820
8821         mutex_lock(&adev->grbm_idx_mutex);
8822         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
8823                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
8824                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
8825                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
8826                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
8827                                 continue;
8828                         mask = 1;
8829                         ao_bitmap = 0;
8830                         counter = 0;
8831                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
8832                         if (i < 4 && j < 2)
8833                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
8834                                         adev, disable_masks[i * 2 + j]);
8835                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
8836                         cu_info->bitmap[i][j] = bitmap;
8837
8838                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
8839                                 if (bitmap & mask) {
8840                                         if (counter < adev->gfx.config.max_cu_per_sh)
8841                                                 ao_bitmap |= mask;
8842                                         counter++;
8843                                 }
8844                                 mask <<= 1;
8845                         }
8846                         active_cu_number += counter;
8847                         if (i < 2 && j < 2)
8848                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
8849                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
8850                 }
8851         }
8852         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8853         mutex_unlock(&adev->grbm_idx_mutex);
8854
8855         cu_info->number = active_cu_number;
8856         cu_info->ao_cu_mask = ao_cu_mask;
8857         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
8858
8859         return 0;
8860 }
8861
8862 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
8863 {
8864         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
8865
8866         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
8867         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
8868         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
8869
8870         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
8871         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
8872         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
8873
8874         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
8875                                                 adev->gfx.config.max_shader_engines);
8876         disabled_sa = efuse_setting | vbios_setting;
8877         disabled_sa &= max_sa_mask;
8878
8879         return disabled_sa;
8880 }
8881
8882 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
8883 {
8884         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
8885         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
8886
8887         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
8888
8889         max_sa_per_se = adev->gfx.config.max_sh_per_se;
8890         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
8891         max_shader_engines = adev->gfx.config.max_shader_engines;
8892
8893         for (se_index = 0; max_shader_engines > se_index; se_index++) {
8894                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
8895                 disabled_sa_per_se &= max_sa_per_se_mask;
8896                 if (disabled_sa_per_se == max_sa_per_se_mask) {
8897                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
8898                         break;
8899                 }
8900         }
8901 }
8902
8903 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
8904 {
8905         .type = AMD_IP_BLOCK_TYPE_GFX,
8906         .major = 10,
8907         .minor = 0,
8908         .rev = 0,
8909         .funcs = &gfx_v10_0_ip_funcs,
8910 };