drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drm_drv.h>
  24 #include <linux/vmalloc.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_psp.h"
  27 #include "amdgpu_ucode.h"
  28 #include "soc15_common.h"
  29 #include "psp_v13_0.h"
  30
  31 #include "mp/mp_13_0_2_offset.h"
  32 #include "mp/mp_13_0_2_sh_mask.h"
  33
  34 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
  35 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
  36 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
  37 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
  38 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
  39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
  40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
  41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
  42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
  43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
  44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
  45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
  46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
  47 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
  48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
  49 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");
  50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");
  51 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin");
  52 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin");
  53 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");
  54 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
  55
  56 /* For large FW files the time to complete can be very long */
  57 #define USBC_PD_POLLING_LIMIT_S 240
  58
  59 /* Read USB-PD from LFB */
  60 #define GFX_CMD_USB_PD_USE_LFB 0x480
  61
  62 /* Retry times for vmbx ready wait */
  63 #define PSP_VMBX_POLLING_LIMIT 3000
  64
  65 /* VBIOS gfl defines */
  66 #define MBOX_READY_MASK 0x80000000
  67 #define MBOX_STATUS_MASK 0x0000FFFF
  68 #define MBOX_COMMAND_MASK 0x00FF0000
  69 #define MBOX_READY_FLAG 0x80000000
  70 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
  71 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
  72 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
  73
  74 /* memory training timeout define */
  75 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
  76
  77 static int psp_v13_0_init_microcode(struct psp_context *psp)
  78 {
  79         struct amdgpu_device *adev = psp->adev;
  80         char ucode_prefix[30];
  81         int err = 0;
  82
  83         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
  84
  85         switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
  86         case IP_VERSION(13, 0, 2):
  87                 err = psp_init_sos_microcode(psp, ucode_prefix);
  88                 if (err)
  89                         return err;
  90                 /* It's not necessary to load ras ta on Guest side */
  91                 if (!amdgpu_sriov_vf(adev)) {
  92                         err = psp_init_ta_microcode(psp, ucode_prefix);
  93                         if (err)
  94                                 return err;
  95                 }
  96                 break;
  97         case IP_VERSION(13, 0, 1):
  98         case IP_VERSION(13, 0, 3):
  99         case IP_VERSION(13, 0, 5):
 100         case IP_VERSION(13, 0, 8):
 101         case IP_VERSION(13, 0, 11):
 102         case IP_VERSION(14, 0, 0):
 103                 err = psp_init_toc_microcode(psp, ucode_prefix);
 104                 if (err)
 105                         return err;
 106                 err = psp_init_ta_microcode(psp, ucode_prefix);
 107                 if (err)
 108                         return err;
 109                 break;
 110         case IP_VERSION(13, 0, 0):
 111         case IP_VERSION(13, 0, 6):
 112         case IP_VERSION(13, 0, 7):
 113         case IP_VERSION(13, 0, 10):
 114                 err = psp_init_sos_microcode(psp, ucode_prefix);
 115                 if (err)
 116                         return err;
 117                 /* It's not necessary to load ras ta on Guest side */
 118                 err = psp_init_ta_microcode(psp, ucode_prefix);
 119                 if (err)
 120                         return err;
 121                 break;
 122         default:
 123                 BUG();
 124         }
 125
 126         return 0;
 127 }
 128
 129 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
 130 {
 131         struct amdgpu_device *adev = psp->adev;
 132         uint32_t sol_reg;
 133
 134         sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
 135
 136         return sol_reg != 0x0;
 137 }
 138
 139 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp)
 140 {
 141         struct amdgpu_device *adev = psp->adev;
 142         int retry_loop, ret;
 143
 144         for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) {
 145                 /* Wait for bootloader to signify that is
 146                    ready having bit 31 of C2PMSG_33 set to 1 */
 147                 ret = psp_wait_for(
 148                         psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33),
 149                         0x80000000, 0xffffffff, false);
 150
 151                 if (ret == 0)
 152                         break;
 153         }
 154
 155         if (ret)
 156                 dev_warn(adev->dev, "Bootloader wait timed out");
 157
 158         return ret;
 159 }
 160
 161 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
 162 {
 163         struct amdgpu_device *adev = psp->adev;
 164         int retry_loop, retry_cnt, ret;
 165
 166         retry_cnt =
 167                 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) ?
 168                         PSP_VMBX_POLLING_LIMIT :
 169                         10;
 170         /* Wait for bootloader to signify that it is ready having bit 31 of
 171          * C2PMSG_35 set to 1. All other bits are expected to be cleared.
 172          * If there is an error in processing command, bits[7:0] will be set.
 173          * This is applicable for PSP v13.0.6 and newer.
 174          */
 175         for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) {
 176                 ret = psp_wait_for(
 177                         psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 178                         0x80000000, 0xffffffff, false);
 179
 180                 if (ret == 0)
 181                         return 0;
 182         }
 183
 184         return ret;
 185 }
 186
 187 static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp)
 188 {
 189         struct amdgpu_device *adev = psp->adev;
 190
 191         if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) {
 192                 psp_v13_0_wait_for_vmbx_ready(psp);
 193
 194                 return psp_v13_0_wait_for_bootloader(psp);
 195         }
 196
 197         return 0;
 198 }
 199
 200 static int psp_v13_0_bootloader_load_component(struct psp_context       *psp,
 201                                                struct psp_bin_desc      *bin_desc,
 202                                                enum psp_bootloader_cmd  bl_cmd)
 203 {
 204         int ret;
 205         uint32_t psp_gfxdrv_command_reg = 0;
 206         struct amdgpu_device *adev = psp->adev;
 207
 208         /* Check tOS sign of life register to confirm sys driver and sOS
 209          * are already been loaded.
 210          */
 211         if (psp_v13_0_is_sos_alive(psp))
 212                 return 0;
 213
 214         ret = psp_v13_0_wait_for_bootloader(psp);
 215         if (ret)
 216                 return ret;
 217
 218         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 219
 220         /* Copy PSP KDB binary to memory */
 221         memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
 222
 223         /* Provide the PSP KDB to bootloader */
 224         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 225                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 226         psp_gfxdrv_command_reg = bl_cmd;
 227         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 228                psp_gfxdrv_command_reg);
 229
 230         ret = psp_v13_0_wait_for_bootloader(psp);
 231
 232         return ret;
 233 }
 234
 235 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
 236 {
 237         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
 238 }
 239
 240 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
 241 {
 242         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
 243 }
 244
 245 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
 246 {
 247         return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
 248 }
 249
 250 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
 251 {
 252         return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
 253 }
 254
 255 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
 256 {
 257         return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
 258 }
 259
 260 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
 261 {
 262         return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
 263 }
 264
 265 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp)
 266 {
 267         return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
 268 }
 269
 270 static inline void psp_v13_0_init_sos_version(struct psp_context *psp)
 271 {
 272         struct amdgpu_device *adev = psp->adev;
 273
 274         psp->sos.fw_version = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_58);
 275 }
 276
 277 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
 278 {
 279         int ret;
 280         unsigned int psp_gfxdrv_command_reg = 0;
 281         struct amdgpu_device *adev = psp->adev;
 282
 283         /* Check sOS sign of life register to confirm sys driver and sOS
 284          * are already been loaded.
 285          */
 286         if (psp_v13_0_is_sos_alive(psp)) {
 287                 psp_v13_0_init_sos_version(psp);
 288                 return 0;
 289         }
 290
 291         ret = psp_v13_0_wait_for_bootloader(psp);
 292         if (ret)
 293                 return ret;
 294
 295         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 296
 297         /* Copy Secure OS binary to PSP memory */
 298         memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
 299
 300         /* Provide the PSP secure OS to bootloader */
 301         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 302                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 303         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 304         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 305                psp_gfxdrv_command_reg);
 306
 307         /* there might be handshake issue with hardware which needs delay */
 308         mdelay(20);
 309         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
 310                            RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
 311                            0, true);
 312
 313         if (!ret)
 314                 psp_v13_0_init_sos_version(psp);
 315
 316         return ret;
 317 }
 318
 319 static int psp_v13_0_ring_stop(struct psp_context *psp,
 320                                enum psp_ring_type ring_type)
 321 {
 322         int ret = 0;
 323         struct amdgpu_device *adev = psp->adev;
 324
 325         if (amdgpu_sriov_vf(adev)) {
 326                 /* Write the ring destroy command*/
 327                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 328                              GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 329                 /* there might be handshake issue with hardware which needs delay */
 330                 mdelay(20);
 331                 /* Wait for response flag (bit 31) */
 332                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 333                                    0x80000000, 0x80000000, false);
 334         } else {
 335                 /* Write the ring destroy command*/
 336                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
 337                              GFX_CTRL_CMD_ID_DESTROY_RINGS);
 338                 /* there might be handshake issue with hardware which needs delay */
 339                 mdelay(20);
 340                 /* Wait for response flag (bit 31) */
 341                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 342                                    0x80000000, 0x80000000, false);
 343         }
 344
 345         return ret;
 346 }
 347
 348 static int psp_v13_0_ring_create(struct psp_context *psp,
 349                                  enum psp_ring_type ring_type)
 350 {
 351         int ret = 0;
 352         unsigned int psp_ring_reg = 0;
 353         struct psp_ring *ring = &psp->km_ring;
 354         struct amdgpu_device *adev = psp->adev;
 355
 356         if (amdgpu_sriov_vf(adev)) {
 357                 ret = psp_v13_0_ring_stop(psp, ring_type);
 358                 if (ret) {
 359                         DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
 360                         return ret;
 361                 }
 362
 363                 /* Write low address of the ring to C2PMSG_102 */
 364                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 365                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
 366                 /* Write high address of the ring to C2PMSG_103 */
 367                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 368                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
 369
 370                 /* Write the ring initialization command to C2PMSG_101 */
 371                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 372                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 373
 374                 /* there might be handshake issue with hardware which needs delay */
 375                 mdelay(20);
 376
 377                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 378                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 379                                    0x80000000, 0x8000FFFF, false);
 380
 381         } else {
 382                 /* Wait for sOS ready for ring creation */
 383                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 384                                    0x80000000, 0x80000000, false);
 385                 if (ret) {
 386                         DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
 387                         return ret;
 388                 }
 389
 390                 /* Write low address of the ring to C2PMSG_69 */
 391                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 392                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
 393                 /* Write high address of the ring to C2PMSG_70 */
 394                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 395                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
 396                 /* Write size of ring to C2PMSG_71 */
 397                 psp_ring_reg = ring->ring_size;
 398                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
 399                 /* Write the ring initialization command to C2PMSG_64 */
 400                 psp_ring_reg = ring_type;
 401                 psp_ring_reg = psp_ring_reg << 16;
 402                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
 403
 404                 /* there might be handshake issue with hardware which needs delay */
 405                 mdelay(20);
 406
 407                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 408                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 409                                    0x80000000, 0x8000FFFF, false);
 410         }
 411
 412         return ret;
 413 }
 414
 415 static int psp_v13_0_ring_destroy(struct psp_context *psp,
 416                                   enum psp_ring_type ring_type)
 417 {
 418         int ret = 0;
 419         struct psp_ring *ring = &psp->km_ring;
 420         struct amdgpu_device *adev = psp->adev;
 421
 422         ret = psp_v13_0_ring_stop(psp, ring_type);
 423         if (ret)
 424                 DRM_ERROR("Fail to stop psp ring\n");
 425
 426         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 427                               &ring->ring_mem_mc_addr,
 428                               (void **)&ring->ring_mem);
 429
 430         return ret;
 431 }
 432
 433 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
 434 {
 435         uint32_t data;
 436         struct amdgpu_device *adev = psp->adev;
 437
 438         if (amdgpu_sriov_vf(adev))
 439                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
 440         else
 441                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
 442
 443         return data;
 444 }
 445
 446 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 447 {
 448         struct amdgpu_device *adev = psp->adev;
 449
 450         if (amdgpu_sriov_vf(adev)) {
 451                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
 452                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 453                              GFX_CTRL_CMD_ID_CONSUME_CMD);
 454         } else
 455                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
 456 }
 457
 458 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
 459 {
 460         int ret;
 461         int i;
 462         uint32_t data_32;
 463         int max_wait;
 464         struct amdgpu_device *adev = psp->adev;
 465
 466         data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
 467         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
 468         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
 469
 470         max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
 471         for (i = 0; i < max_wait; i++) {
 472                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 473                                    0x80000000, 0x80000000, false);
 474                 if (ret == 0)
 475                         break;
 476         }
 477         if (i < max_wait)
 478                 ret = 0;
 479         else
 480                 ret = -ETIME;
 481
 482         dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
 483                   (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
 484                   (ret == 0) ? "succeed" : "failed",
 485                   i, adev->usec_timeout/1000);
 486         return ret;
 487 }
 488
 489
 490 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
 491 {
 492         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 493         uint32_t *pcache = (uint32_t *)ctx->sys_cache;
 494         struct amdgpu_device *adev = psp->adev;
 495         uint32_t p2c_header[4];
 496         uint32_t sz;
 497         void *buf;
 498         int ret, idx;
 499
 500         if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
 501                 dev_dbg(adev->dev, "Memory training is not supported.\n");
 502                 return 0;
 503         } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
 504                 dev_err(adev->dev, "Memory training initialization failure.\n");
 505                 return -EINVAL;
 506         }
 507
 508         if (psp_v13_0_is_sos_alive(psp)) {
 509                 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
 510                 return 0;
 511         }
 512
 513         amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
 514         dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
 515                   pcache[0], pcache[1], pcache[2], pcache[3],
 516                   p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
 517
 518         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 519                 dev_dbg(adev->dev, "Short training depends on restore.\n");
 520                 ops |= PSP_MEM_TRAIN_RESTORE;
 521         }
 522
 523         if ((ops & PSP_MEM_TRAIN_RESTORE) &&
 524             pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 525                 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
 526                 ops |= PSP_MEM_TRAIN_SAVE;
 527         }
 528
 529         if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 530             !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 531               pcache[3] == p2c_header[3])) {
 532                 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
 533                 ops |= PSP_MEM_TRAIN_SAVE;
 534         }
 535
 536         if ((ops & PSP_MEM_TRAIN_SAVE) &&
 537             p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 538                 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
 539                 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
 540         }
 541
 542         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 543                 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
 544                 ops |= PSP_MEM_TRAIN_SAVE;
 545         }
 546
 547         dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
 548
 549         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 550                 /*
 551                  * Long training will encroach a certain amount on the bottom of VRAM;
 552                  * save the content from the bottom of VRAM to system memory
 553                  * before training, and restore it after training to avoid
 554                  * VRAM corruption.
 555                  */
 556                 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
 557
 558                 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
 559                         dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
 560                                   adev->gmc.visible_vram_size,
 561                                   adev->mman.aper_base_kaddr);
 562                         return -EINVAL;
 563                 }
 564
 565                 buf = vmalloc(sz);
 566                 if (!buf) {
 567                         dev_err(adev->dev, "failed to allocate system memory.\n");
 568                         return -ENOMEM;
 569                 }
 570
 571                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 572                         memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
 573                         ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
 574                         if (ret) {
 575                                 DRM_ERROR("Send long training msg failed.\n");
 576                                 vfree(buf);
 577                                 drm_dev_exit(idx);
 578                                 return ret;
 579                         }
 580
 581                         memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
 582                         adev->hdp.funcs->flush_hdp(adev, NULL);
 583                         vfree(buf);
 584                         drm_dev_exit(idx);
 585                 } else {
 586                         vfree(buf);
 587                         return -ENODEV;
 588                 }
 589         }
 590
 591         if (ops & PSP_MEM_TRAIN_SAVE) {
 592                 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
 593         }
 594
 595         if (ops & PSP_MEM_TRAIN_RESTORE) {
 596                 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
 597         }
 598
 599         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 600                 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
 601                                                          PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
 602                 if (ret) {
 603                         dev_err(adev->dev, "send training msg failed.\n");
 604                         return ret;
 605                 }
 606         }
 607         ctx->training_cnt++;
 608         return 0;
 609 }
 610
 611 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
 612 {
 613         struct amdgpu_device *adev = psp->adev;
 614         uint32_t reg_status;
 615         int ret, i = 0;
 616
 617         /*
 618          * LFB address which is aligned to 1MB address and has to be
 619          * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
 620          * register
 621          */
 622         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
 623
 624         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 625                              0x80000000, 0x80000000, false);
 626         if (ret)
 627                 return ret;
 628
 629         /* Fireup interrupt so PSP can pick up the address */
 630         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
 631
 632         /* FW load takes very long time */
 633         do {
 634                 msleep(1000);
 635                 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
 636
 637                 if (reg_status & 0x80000000)
 638                         goto done;
 639
 640         } while (++i < USBC_PD_POLLING_LIMIT_S);
 641
 642         return -ETIME;
 643 done:
 644
 645         if ((reg_status & 0xFFFF) != 0) {
 646                 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
 647                                 reg_status & 0xFFFF);
 648                 return -EIO;
 649         }
 650
 651         return 0;
 652 }
 653
 654 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
 655 {
 656         struct amdgpu_device *adev = psp->adev;
 657         int ret;
 658
 659         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 660
 661         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 662                                      0x80000000, 0x80000000, false);
 663         if (!ret)
 664                 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
 665
 666         return ret;
 667 }
 668
 669 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
 670 {
 671         uint32_t reg_status = 0, reg_val = 0;
 672         struct amdgpu_device *adev = psp->adev;
 673         int ret;
 674
 675         /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
 676         reg_val |= (cmd << 16);
 677         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115,  reg_val);
 678
 679         /* Ring the doorbell */
 680         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
 681
 682         if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
 683                 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 684                                                  MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
 685         else
 686                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 687                                    MBOX_READY_FLAG, MBOX_READY_MASK, false);
 688         if (ret) {
 689                 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
 690                 return ret;
 691         }
 692
 693         reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 694         if ((reg_status & 0xFFFF) != 0) {
 695                 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
 696                                 cmd, reg_status & 0xFFFF);
 697                 return -EIO;
 698         }
 699
 700         return 0;
 701 }
 702
 703 static int psp_v13_0_update_spirom(struct psp_context *psp,
 704                                    uint64_t fw_pri_mc_addr)
 705 {
 706         struct amdgpu_device *adev = psp->adev;
 707         int ret;
 708
 709         /* Confirm PSP is ready to start */
 710         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 711                            MBOX_READY_FLAG, MBOX_READY_MASK, false);
 712         if (ret) {
 713                 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
 714                 return ret;
 715         }
 716
 717         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
 718
 719         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
 720         if (ret)
 721                 return ret;
 722
 723         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
 724
 725         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
 726         if (ret)
 727                 return ret;
 728
 729         psp->vbflash_done = true;
 730
 731         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
 732         if (ret)
 733                 return ret;
 734
 735         return 0;
 736 }
 737
 738 static int psp_v13_0_vbflash_status(struct psp_context *psp)
 739 {
 740         struct amdgpu_device *adev = psp->adev;
 741
 742         return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 743 }
 744
 745 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp)
 746 {
 747         struct amdgpu_device *adev = psp->adev;
 748
 749         if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) {
 750                 uint32_t  reg_data;
 751                 /* MP1 fatal error: trigger PSP dram read to unhalt PSP
 752                  * during MP1 triggered sync flood.
 753                  */
 754                 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
 755                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10);
 756
 757                 /* delay 1000ms for the mode1 reset for fatal error
 758                  * to be recovered back.
 759                  */
 760                 msleep(1000);
 761         }
 762
 763         return 0;
 764 }
 765
 766
 767 static void psp_v13_0_boot_error_reporting(struct amdgpu_device *adev,
 768                                            uint32_t inst,
 769                                            uint32_t boot_error)
 770 {
 771         uint32_t socket_id;
 772         uint32_t aid_id;
 773         uint32_t hbm_id;
 774         uint32_t reg_data;
 775
 776         socket_id = REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, SOCKET_ID);
 777         aid_id = REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, AID_ID);
 778         hbm_id = REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, HBM_ID);
 779
 780         reg_data = RREG32_SOC15(MP0, inst, regMP0_SMN_C2PMSG_109);
 781         dev_info(adev->dev, "socket: %d, aid: %d, firmware boot failed, fw status is 0x%x\n",
 782                  socket_id, aid_id, reg_data);
 783
 784         if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_MEM_TRAINING))
 785                 dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, memory training failed\n",
 786                          socket_id, aid_id, hbm_id);
 787
 788         if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_FW_LOAD))
 789                 dev_info(adev->dev, "socket: %d, aid: %d, firmware load failed at boot time\n",
 790                          socket_id, aid_id);
 791
 792         if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_WAFL_LINK_TRAINING))
 793                 dev_info(adev->dev, "socket: %d, aid: %d, wafl link training failed\n",
 794                          socket_id, aid_id);
 795
 796         if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_XGMI_LINK_TRAINING))
 797                 dev_info(adev->dev, "socket: %d, aid: %d, xgmi link training failed\n",
 798                          socket_id, aid_id);
 799
 800         if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_USR_CP_LINK_TRAINING))
 801                 dev_info(adev->dev, "socket: %d, aid: %d, usr cp link training failed\n",
 802                          socket_id, aid_id);
 803
 804         if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_USR_DP_LINK_TRAINING))
 805                 dev_info(adev->dev, "socket: %d, aid: %d, usr dp link training failed\n",
 806                          socket_id, aid_id);
 807
 808         if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_HBM_MEM_TEST))
 809                 dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, hbm memory test failed\n",
 810                          socket_id, aid_id, hbm_id);
 811
 812         if (REG_GET_FIELD(boot_error, MP0_SMN_C2PMSG_126, GPU_ERR_HBM_BIST_TEST))
 813                 dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, hbm bist test failed\n",
 814                          socket_id, aid_id, hbm_id);
 815 }
 816
 817 static int psp_v13_0_query_boot_status(struct psp_context *psp)
 818 {
 819         struct amdgpu_device *adev = psp->adev;
 820         int inst_mask = adev->aid_mask;
 821         uint32_t reg_data;
 822         uint32_t i;
 823         int ret = 0;
 824
 825         if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))
 826                 return 0;
 827
 828         if (RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_59) < 0x00a10109)
 829                 return 0;
 830
 831         for_each_inst(i, inst_mask) {
 832                 reg_data = RREG32_SOC15(MP0, i, regMP0_SMN_C2PMSG_126);
 833                 if (!REG_GET_FIELD(reg_data, MP0_SMN_C2PMSG_126, BOOT_STATUS)) {
 834                         psp_v13_0_boot_error_reporting(adev, i, reg_data);
 835                         ret = -EINVAL;
 836                         break;
 837                 }
 838         }
 839
 840         return ret;
 841 }
 842
 843 static const struct psp_funcs psp_v13_0_funcs = {
 844         .init_microcode = psp_v13_0_init_microcode,
 845         .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state,
 846         .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
 847         .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
 848         .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
 849         .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
 850         .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
 851         .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
 852         .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv,
 853         .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
 854         .ring_create = psp_v13_0_ring_create,
 855         .ring_stop = psp_v13_0_ring_stop,
 856         .ring_destroy = psp_v13_0_ring_destroy,
 857         .ring_get_wptr = psp_v13_0_ring_get_wptr,
 858         .ring_set_wptr = psp_v13_0_ring_set_wptr,
 859         .mem_training = psp_v13_0_memory_training,
 860         .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
 861         .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
 862         .update_spirom = psp_v13_0_update_spirom,
 863         .vbflash_stat = psp_v13_0_vbflash_status,
 864         .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk,
 865         .query_boot_status = psp_v13_0_query_boot_status,
 866 };
 867
 868 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
 869 {
 870         psp->funcs = &psp_v13_0_funcs;
 871 }