drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drm_edid.h>
  25 #include <drm/drm_fourcc.h>
  26 #include <drm/drm_modeset_helper.h>
  27 #include <drm/drm_modeset_helper_vtables.h>
  28 #include <drm/drm_vblank.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_pm.h"
  32 #include "amdgpu_i2c.h"
  33 #include "vid.h"
  34 #include "atom.h"
  35 #include "amdgpu_atombios.h"
  36 #include "atombios_crtc.h"
  37 #include "atombios_encoders.h"
  38 #include "amdgpu_pll.h"
  39 #include "amdgpu_connectors.h"
  40 #include "amdgpu_display.h"
  41 #include "dce_v10_0.h"
  42
  43 #include "dce/dce_10_0_d.h"
  44 #include "dce/dce_10_0_sh_mask.h"
  45 #include "dce/dce_10_0_enum.h"
  46 #include "oss/oss_3_0_d.h"
  47 #include "oss/oss_3_0_sh_mask.h"
  48 #include "gmc/gmc_8_1_d.h"
  49 #include "gmc/gmc_8_1_sh_mask.h"
  50
  51 #include "ivsrcid/ivsrcid_vislands30.h"
  52
  53 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
  54 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
  55
  56 static const u32 crtc_offsets[] = {
  57         CRTC0_REGISTER_OFFSET,
  58         CRTC1_REGISTER_OFFSET,
  59         CRTC2_REGISTER_OFFSET,
  60         CRTC3_REGISTER_OFFSET,
  61         CRTC4_REGISTER_OFFSET,
  62         CRTC5_REGISTER_OFFSET,
  63         CRTC6_REGISTER_OFFSET
  64 };
  65
  66 static const u32 hpd_offsets[] = {
  67         HPD0_REGISTER_OFFSET,
  68         HPD1_REGISTER_OFFSET,
  69         HPD2_REGISTER_OFFSET,
  70         HPD3_REGISTER_OFFSET,
  71         HPD4_REGISTER_OFFSET,
  72         HPD5_REGISTER_OFFSET
  73 };
  74
  75 static const uint32_t dig_offsets[] = {
  76         DIG0_REGISTER_OFFSET,
  77         DIG1_REGISTER_OFFSET,
  78         DIG2_REGISTER_OFFSET,
  79         DIG3_REGISTER_OFFSET,
  80         DIG4_REGISTER_OFFSET,
  81         DIG5_REGISTER_OFFSET,
  82         DIG6_REGISTER_OFFSET
  83 };
  84
  85 static const struct {
  86         uint32_t        reg;
  87         uint32_t        vblank;
  88         uint32_t        vline;
  89         uint32_t        hpd;
  90
  91 } interrupt_status_offsets[] = { {
  92         .reg = mmDISP_INTERRUPT_STATUS,
  93         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  94         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  95         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  96 }, {
  97         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  98         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  99         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
 100         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
 101 }, {
 102         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
 103         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
 104         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
 105         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 106 }, {
 107         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 108         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 109         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 110         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 111 }, {
 112         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 113         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 114         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 115         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 116 }, {
 117         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 118         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 119         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 120         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 121 } };
 122
 123 static const u32 golden_settings_tonga_a11[] = {
 124         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 125         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 126         mmFBC_MISC, 0x1f311fff, 0x12300000,
 127         mmHDMI_CONTROL, 0x31000111, 0x00000011,
 128 };
 129
 130 static const u32 tonga_mgcg_cgcg_init[] = {
 131         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 132         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 133 };
 134
 135 static const u32 golden_settings_fiji_a10[] = {
 136         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 137         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 138         mmFBC_MISC, 0x1f311fff, 0x12300000,
 139         mmHDMI_CONTROL, 0x31000111, 0x00000011,
 140 };
 141
 142 static const u32 fiji_mgcg_cgcg_init[] = {
 143         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 144         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 145 };
 146
 147 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
 148 {
 149         switch (adev->asic_type) {
 150         case CHIP_FIJI:
 151                 amdgpu_device_program_register_sequence(adev,
 152                                                         fiji_mgcg_cgcg_init,
 153                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 154                 amdgpu_device_program_register_sequence(adev,
 155                                                         golden_settings_fiji_a10,
 156                                                         ARRAY_SIZE(golden_settings_fiji_a10));
 157                 break;
 158         case CHIP_TONGA:
 159                 amdgpu_device_program_register_sequence(adev,
 160                                                         tonga_mgcg_cgcg_init,
 161                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 162                 amdgpu_device_program_register_sequence(adev,
 163                                                         golden_settings_tonga_a11,
 164                                                         ARRAY_SIZE(golden_settings_tonga_a11));
 165                 break;
 166         default:
 167                 break;
 168         }
 169 }
 170
 171 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
 172                                      u32 block_offset, u32 reg)
 173 {
 174         unsigned long flags;
 175         u32 r;
 176
 177         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 178         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 179         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 180         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 181
 182         return r;
 183 }
 184
 185 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
 186                                       u32 block_offset, u32 reg, u32 v)
 187 {
 188         unsigned long flags;
 189
 190         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 191         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 192         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 193         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 194 }
 195
 196 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 197 {
 198         if (crtc >= adev->mode_info.num_crtc)
 199                 return 0;
 200         else
 201                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 202 }
 203
 204 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 205 {
 206         unsigned i;
 207
 208         /* Enable pflip interrupts */
 209         for (i = 0; i < adev->mode_info.num_crtc; i++)
 210                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 211 }
 212
 213 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 214 {
 215         unsigned i;
 216
 217         /* Disable pflip interrupts */
 218         for (i = 0; i < adev->mode_info.num_crtc; i++)
 219                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 220 }
 221
 222 /**
 223  * dce_v10_0_page_flip - pageflip callback.
 224  *
 225  * @adev: amdgpu_device pointer
 226  * @crtc_id: crtc to cleanup pageflip on
 227  * @crtc_base: new address of the crtc (GPU MC address)
 228  * @async: asynchronous flip
 229  *
 230  * Triggers the actual pageflip by updating the primary
 231  * surface base address.
 232  */
 233 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
 234                                 int crtc_id, u64 crtc_base, bool async)
 235 {
 236         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 237         struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
 238         u32 tmp;
 239
 240         /* flip at hsync for async, default is vsync */
 241         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
 242         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
 243                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
 244         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 245         /* update pitch */
 246         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
 247                fb->pitches[0] / fb->format->cpp[0]);
 248         /* update the primary scanout address */
 249         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 250                upper_32_bits(crtc_base));
 251         /* writing to the low address triggers the update */
 252         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 253                lower_32_bits(crtc_base));
 254         /* post the write */
 255         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 256 }
 257
 258 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 259                                         u32 *vbl, u32 *position)
 260 {
 261         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 262                 return -EINVAL;
 263
 264         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 265         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 266
 267         return 0;
 268 }
 269
 270 /**
 271  * dce_v10_0_hpd_sense - hpd sense callback.
 272  *
 273  * @adev: amdgpu_device pointer
 274  * @hpd: hpd (hotplug detect) pin
 275  *
 276  * Checks if a digital monitor is connected (evergreen+).
 277  * Returns true if connected, false if not connected.
 278  */
 279 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
 280                                enum amdgpu_hpd_id hpd)
 281 {
 282         bool connected = false;
 283
 284         if (hpd >= adev->mode_info.num_hpd)
 285                 return connected;
 286
 287         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
 288             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 289                 connected = true;
 290
 291         return connected;
 292 }
 293
 294 /**
 295  * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
 296  *
 297  * @adev: amdgpu_device pointer
 298  * @hpd: hpd (hotplug detect) pin
 299  *
 300  * Set the polarity of the hpd pin (evergreen+).
 301  */
 302 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
 303                                       enum amdgpu_hpd_id hpd)
 304 {
 305         u32 tmp;
 306         bool connected = dce_v10_0_hpd_sense(adev, hpd);
 307
 308         if (hpd >= adev->mode_info.num_hpd)
 309                 return;
 310
 311         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
 312         if (connected)
 313                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 314         else
 315                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 316         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
 317 }
 318
 319 /**
 320  * dce_v10_0_hpd_init - hpd setup callback.
 321  *
 322  * @adev: amdgpu_device pointer
 323  *
 324  * Setup the hpd pins used by the card (evergreen+).
 325  * Enable the pin, set the polarity, and enable the hpd interrupts.
 326  */
 327 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
 328 {
 329         struct drm_device *dev = adev_to_drm(adev);
 330         struct drm_connector *connector;
 331         struct drm_connector_list_iter iter;
 332         u32 tmp;
 333
 334         drm_connector_list_iter_begin(dev, &iter);
 335         drm_for_each_connector_iter(connector, &iter) {
 336                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 337
 338                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 339                         continue;
 340
 341                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 342                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 343                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 344                          * aux dp channel on imac and help (but not completely fix)
 345                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 346                          * also avoid interrupt storms during dpms.
 347                          */
 348                         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 349                         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
 350                         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 351                         continue;
 352                 }
 353
 354                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 355                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 356                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 357
 358                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 359                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 360                                     DC_HPD_CONNECT_INT_DELAY,
 361                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 362                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 363                                     DC_HPD_DISCONNECT_INT_DELAY,
 364                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 365                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 366
 367                 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 368                 amdgpu_irq_get(adev, &adev->hpd_irq,
 369                                amdgpu_connector->hpd.hpd);
 370         }
 371         drm_connector_list_iter_end(&iter);
 372 }
 373
 374 /**
 375  * dce_v10_0_hpd_fini - hpd tear down callback.
 376  *
 377  * @adev: amdgpu_device pointer
 378  *
 379  * Tear down the hpd pins used by the card (evergreen+).
 380  * Disable the hpd interrupts.
 381  */
 382 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
 383 {
 384         struct drm_device *dev = adev_to_drm(adev);
 385         struct drm_connector *connector;
 386         struct drm_connector_list_iter iter;
 387         u32 tmp;
 388
 389         drm_connector_list_iter_begin(dev, &iter);
 390         drm_for_each_connector_iter(connector, &iter) {
 391                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 392
 393                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 394                         continue;
 395
 396                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 397                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 398                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 399
 400                 amdgpu_irq_put(adev, &adev->hpd_irq,
 401                                amdgpu_connector->hpd.hpd);
 402         }
 403         drm_connector_list_iter_end(&iter);
 404 }
 405
 406 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 407 {
 408         return mmDC_GPIO_HPD_A;
 409 }
 410
 411 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
 412 {
 413         u32 crtc_hung = 0;
 414         u32 crtc_status[6];
 415         u32 i, j, tmp;
 416
 417         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 418                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 419                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 420                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 421                         crtc_hung |= (1 << i);
 422                 }
 423         }
 424
 425         for (j = 0; j < 10; j++) {
 426                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 427                         if (crtc_hung & (1 << i)) {
 428                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 429                                 if (tmp != crtc_status[i])
 430                                         crtc_hung &= ~(1 << i);
 431                         }
 432                 }
 433                 if (crtc_hung == 0)
 434                         return false;
 435                 udelay(100);
 436         }
 437
 438         return true;
 439 }
 440
 441 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
 442                                            bool render)
 443 {
 444         u32 tmp;
 445
 446         /* Lockout access through VGA aperture*/
 447         tmp = RREG32(mmVGA_HDP_CONTROL);
 448         if (render)
 449                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 450         else
 451                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 452         WREG32(mmVGA_HDP_CONTROL, tmp);
 453
 454         /* disable VGA render */
 455         tmp = RREG32(mmVGA_RENDER_CONTROL);
 456         if (render)
 457                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 458         else
 459                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 460         WREG32(mmVGA_RENDER_CONTROL, tmp);
 461 }
 462
 463 static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
 464 {
 465         int num_crtc = 0;
 466
 467         switch (adev->asic_type) {
 468         case CHIP_FIJI:
 469         case CHIP_TONGA:
 470                 num_crtc = 6;
 471                 break;
 472         default:
 473                 num_crtc = 0;
 474         }
 475         return num_crtc;
 476 }
 477
 478 void dce_v10_0_disable_dce(struct amdgpu_device *adev)
 479 {
 480         /*Disable VGA render and enabled crtc, if has DCE engine*/
 481         if (amdgpu_atombios_has_dce_engine_info(adev)) {
 482                 u32 tmp;
 483                 int crtc_enabled, i;
 484
 485                 dce_v10_0_set_vga_render_state(adev, false);
 486
 487                 /*Disable crtc*/
 488                 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
 489                         crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 490                                                                          CRTC_CONTROL, CRTC_MASTER_EN);
 491                         if (crtc_enabled) {
 492                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 493                                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 494                                 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 495                                 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 496                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 497                         }
 498                 }
 499         }
 500 }
 501
 502 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
 503 {
 504         struct drm_device *dev = encoder->dev;
 505         struct amdgpu_device *adev = drm_to_adev(dev);
 506         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 507         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 508         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 509         int bpc = 0;
 510         u32 tmp = 0;
 511         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 512
 513         if (connector) {
 514                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 515                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 516                 dither = amdgpu_connector->dither;
 517         }
 518
 519         /* LVDS/eDP FMT is set up by atom */
 520         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 521                 return;
 522
 523         /* not needed for analog */
 524         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 525             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 526                 return;
 527
 528         if (bpc == 0)
 529                 return;
 530
 531         switch (bpc) {
 532         case 6:
 533                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 534                         /* XXX sort out optimal dither settings */
 535                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 536                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 537                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 538                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 539                 } else {
 540                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 541                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 542                 }
 543                 break;
 544         case 8:
 545                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 546                         /* XXX sort out optimal dither settings */
 547                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 548                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 549                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 550                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 551                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 552                 } else {
 553                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 554                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 555                 }
 556                 break;
 557         case 10:
 558                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 559                         /* XXX sort out optimal dither settings */
 560                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 561                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 562                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 563                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 564                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 565                 } else {
 566                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 567                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 568                 }
 569                 break;
 570         default:
 571                 /* not needed */
 572                 break;
 573         }
 574
 575         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 576 }
 577
 578
 579 /* display watermark setup */
 580 /**
 581  * dce_v10_0_line_buffer_adjust - Set up the line buffer
 582  *
 583  * @adev: amdgpu_device pointer
 584  * @amdgpu_crtc: the selected display controller
 585  * @mode: the current display mode on the selected display
 586  * controller
 587  *
 588  * Setup up the line buffer allocation for
 589  * the selected display controller (CIK).
 590  * Returns the line buffer size in pixels.
 591  */
 592 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
 593                                        struct amdgpu_crtc *amdgpu_crtc,
 594                                        struct drm_display_mode *mode)
 595 {
 596         u32 tmp, buffer_alloc, i, mem_cfg;
 597         u32 pipe_offset = amdgpu_crtc->crtc_id;
 598         /*
 599          * Line Buffer Setup
 600          * There are 6 line buffers, one for each display controllers.
 601          * There are 3 partitions per LB. Select the number of partitions
 602          * to enable based on the display width.  For display widths larger
 603          * than 4096, you need use to use 2 display controllers and combine
 604          * them using the stereo blender.
 605          */
 606         if (amdgpu_crtc->base.enabled && mode) {
 607                 if (mode->crtc_hdisplay < 1920) {
 608                         mem_cfg = 1;
 609                         buffer_alloc = 2;
 610                 } else if (mode->crtc_hdisplay < 2560) {
 611                         mem_cfg = 2;
 612                         buffer_alloc = 2;
 613                 } else if (mode->crtc_hdisplay < 4096) {
 614                         mem_cfg = 0;
 615                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 616                 } else {
 617                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 618                         mem_cfg = 0;
 619                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 620                 }
 621         } else {
 622                 mem_cfg = 1;
 623                 buffer_alloc = 0;
 624         }
 625
 626         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 627         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 628         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 629
 630         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 631         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 632         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 633
 634         for (i = 0; i < adev->usec_timeout; i++) {
 635                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 636                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 637                         break;
 638                 udelay(1);
 639         }
 640
 641         if (amdgpu_crtc->base.enabled && mode) {
 642                 switch (mem_cfg) {
 643                 case 0:
 644                 default:
 645                         return 4096 * 2;
 646                 case 1:
 647                         return 1920 * 2;
 648                 case 2:
 649                         return 2560 * 2;
 650                 }
 651         }
 652
 653         /* controller not enabled, so no lb used */
 654         return 0;
 655 }
 656
 657 /**
 658  * cik_get_number_of_dram_channels - get the number of dram channels
 659  *
 660  * @adev: amdgpu_device pointer
 661  *
 662  * Look up the number of video ram channels (CIK).
 663  * Used for display watermark bandwidth calculations
 664  * Returns the number of dram channels
 665  */
 666 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 667 {
 668         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 669
 670         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 671         case 0:
 672         default:
 673                 return 1;
 674         case 1:
 675                 return 2;
 676         case 2:
 677                 return 4;
 678         case 3:
 679                 return 8;
 680         case 4:
 681                 return 3;
 682         case 5:
 683                 return 6;
 684         case 6:
 685                 return 10;
 686         case 7:
 687                 return 12;
 688         case 8:
 689                 return 16;
 690         }
 691 }
 692
 693 struct dce10_wm_params {
 694         u32 dram_channels; /* number of dram channels */
 695         u32 yclk;          /* bandwidth per dram data pin in kHz */
 696         u32 sclk;          /* engine clock in kHz */
 697         u32 disp_clk;      /* display clock in kHz */
 698         u32 src_width;     /* viewport width */
 699         u32 active_time;   /* active display time in ns */
 700         u32 blank_time;    /* blank time in ns */
 701         bool interlaced;    /* mode is interlaced */
 702         fixed20_12 vsc;    /* vertical scale ratio */
 703         u32 num_heads;     /* number of active crtcs */
 704         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 705         u32 lb_size;       /* line buffer allocated to pipe */
 706         u32 vtaps;         /* vertical scaler taps */
 707 };
 708
 709 /**
 710  * dce_v10_0_dram_bandwidth - get the dram bandwidth
 711  *
 712  * @wm: watermark calculation data
 713  *
 714  * Calculate the raw dram bandwidth (CIK).
 715  * Used for display watermark bandwidth calculations
 716  * Returns the dram bandwidth in MBytes/s
 717  */
 718 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
 719 {
 720         /* Calculate raw DRAM Bandwidth */
 721         fixed20_12 dram_efficiency; /* 0.7 */
 722         fixed20_12 yclk, dram_channels, bandwidth;
 723         fixed20_12 a;
 724
 725         a.full = dfixed_const(1000);
 726         yclk.full = dfixed_const(wm->yclk);
 727         yclk.full = dfixed_div(yclk, a);
 728         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 729         a.full = dfixed_const(10);
 730         dram_efficiency.full = dfixed_const(7);
 731         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 732         bandwidth.full = dfixed_mul(dram_channels, yclk);
 733         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 734
 735         return dfixed_trunc(bandwidth);
 736 }
 737
 738 /**
 739  * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
 740  *
 741  * @wm: watermark calculation data
 742  *
 743  * Calculate the dram bandwidth used for display (CIK).
 744  * Used for display watermark bandwidth calculations
 745  * Returns the dram bandwidth for display in MBytes/s
 746  */
 747 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 748 {
 749         /* Calculate DRAM Bandwidth and the part allocated to display. */
 750         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 751         fixed20_12 yclk, dram_channels, bandwidth;
 752         fixed20_12 a;
 753
 754         a.full = dfixed_const(1000);
 755         yclk.full = dfixed_const(wm->yclk);
 756         yclk.full = dfixed_div(yclk, a);
 757         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 758         a.full = dfixed_const(10);
 759         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 760         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 761         bandwidth.full = dfixed_mul(dram_channels, yclk);
 762         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 763
 764         return dfixed_trunc(bandwidth);
 765 }
 766
 767 /**
 768  * dce_v10_0_data_return_bandwidth - get the data return bandwidth
 769  *
 770  * @wm: watermark calculation data
 771  *
 772  * Calculate the data return bandwidth used for display (CIK).
 773  * Used for display watermark bandwidth calculations
 774  * Returns the data return bandwidth in MBytes/s
 775  */
 776 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
 777 {
 778         /* Calculate the display Data return Bandwidth */
 779         fixed20_12 return_efficiency; /* 0.8 */
 780         fixed20_12 sclk, bandwidth;
 781         fixed20_12 a;
 782
 783         a.full = dfixed_const(1000);
 784         sclk.full = dfixed_const(wm->sclk);
 785         sclk.full = dfixed_div(sclk, a);
 786         a.full = dfixed_const(10);
 787         return_efficiency.full = dfixed_const(8);
 788         return_efficiency.full = dfixed_div(return_efficiency, a);
 789         a.full = dfixed_const(32);
 790         bandwidth.full = dfixed_mul(a, sclk);
 791         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 792
 793         return dfixed_trunc(bandwidth);
 794 }
 795
 796 /**
 797  * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
 798  *
 799  * @wm: watermark calculation data
 800  *
 801  * Calculate the dmif bandwidth used for display (CIK).
 802  * Used for display watermark bandwidth calculations
 803  * Returns the dmif bandwidth in MBytes/s
 804  */
 805 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
 806 {
 807         /* Calculate the DMIF Request Bandwidth */
 808         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 809         fixed20_12 disp_clk, bandwidth;
 810         fixed20_12 a, b;
 811
 812         a.full = dfixed_const(1000);
 813         disp_clk.full = dfixed_const(wm->disp_clk);
 814         disp_clk.full = dfixed_div(disp_clk, a);
 815         a.full = dfixed_const(32);
 816         b.full = dfixed_mul(a, disp_clk);
 817
 818         a.full = dfixed_const(10);
 819         disp_clk_request_efficiency.full = dfixed_const(8);
 820         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 821
 822         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
 823
 824         return dfixed_trunc(bandwidth);
 825 }
 826
 827 /**
 828  * dce_v10_0_available_bandwidth - get the min available bandwidth
 829  *
 830  * @wm: watermark calculation data
 831  *
 832  * Calculate the min available bandwidth used for display (CIK).
 833  * Used for display watermark bandwidth calculations
 834  * Returns the min available bandwidth in MBytes/s
 835  */
 836 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
 837 {
 838         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 839         u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
 840         u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
 841         u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
 842
 843         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 844 }
 845
 846 /**
 847  * dce_v10_0_average_bandwidth - get the average available bandwidth
 848  *
 849  * @wm: watermark calculation data
 850  *
 851  * Calculate the average available bandwidth used for display (CIK).
 852  * Used for display watermark bandwidth calculations
 853  * Returns the average available bandwidth in MBytes/s
 854  */
 855 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
 856 {
 857         /* Calculate the display mode Average Bandwidth
 858          * DisplayMode should contain the source and destination dimensions,
 859          * timing, etc.
 860          */
 861         fixed20_12 bpp;
 862         fixed20_12 line_time;
 863         fixed20_12 src_width;
 864         fixed20_12 bandwidth;
 865         fixed20_12 a;
 866
 867         a.full = dfixed_const(1000);
 868         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 869         line_time.full = dfixed_div(line_time, a);
 870         bpp.full = dfixed_const(wm->bytes_per_pixel);
 871         src_width.full = dfixed_const(wm->src_width);
 872         bandwidth.full = dfixed_mul(src_width, bpp);
 873         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 874         bandwidth.full = dfixed_div(bandwidth, line_time);
 875
 876         return dfixed_trunc(bandwidth);
 877 }
 878
 879 /**
 880  * dce_v10_0_latency_watermark - get the latency watermark
 881  *
 882  * @wm: watermark calculation data
 883  *
 884  * Calculate the latency watermark (CIK).
 885  * Used for display watermark bandwidth calculations
 886  * Returns the latency watermark in ns
 887  */
 888 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
 889 {
 890         /* First calculate the latency in ns */
 891         u32 mc_latency = 2000; /* 2000 ns. */
 892         u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
 893         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 894         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 895         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 896         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 897                 (wm->num_heads * cursor_line_pair_return_time);
 898         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 899         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 900         u32 tmp, dmif_size = 12288;
 901         fixed20_12 a, b, c;
 902
 903         if (wm->num_heads == 0)
 904                 return 0;
 905
 906         a.full = dfixed_const(2);
 907         b.full = dfixed_const(1);
 908         if ((wm->vsc.full > a.full) ||
 909             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 910             (wm->vtaps >= 5) ||
 911             ((wm->vsc.full >= a.full) && wm->interlaced))
 912                 max_src_lines_per_dst_line = 4;
 913         else
 914                 max_src_lines_per_dst_line = 2;
 915
 916         a.full = dfixed_const(available_bandwidth);
 917         b.full = dfixed_const(wm->num_heads);
 918         a.full = dfixed_div(a, b);
 919         tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
 920         tmp = min(dfixed_trunc(a), tmp);
 921
 922         lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
 923
 924         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 925         b.full = dfixed_const(1000);
 926         c.full = dfixed_const(lb_fill_bw);
 927         b.full = dfixed_div(c, b);
 928         a.full = dfixed_div(a, b);
 929         line_fill_time = dfixed_trunc(a);
 930
 931         if (line_fill_time < wm->active_time)
 932                 return latency;
 933         else
 934                 return latency + (line_fill_time - wm->active_time);
 935
 936 }
 937
 938 /**
 939  * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
 940  * average and available dram bandwidth
 941  *
 942  * @wm: watermark calculation data
 943  *
 944  * Check if the display average bandwidth fits in the display
 945  * dram bandwidth (CIK).
 946  * Used for display watermark bandwidth calculations
 947  * Returns true if the display fits, false if not.
 948  */
 949 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 950 {
 951         if (dce_v10_0_average_bandwidth(wm) <=
 952             (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
 953                 return true;
 954         else
 955                 return false;
 956 }
 957
 958 /**
 959  * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
 960  * average and available bandwidth
 961  *
 962  * @wm: watermark calculation data
 963  *
 964  * Check if the display average bandwidth fits in the display
 965  * available bandwidth (CIK).
 966  * Used for display watermark bandwidth calculations
 967  * Returns true if the display fits, false if not.
 968  */
 969 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
 970 {
 971         if (dce_v10_0_average_bandwidth(wm) <=
 972             (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
 973                 return true;
 974         else
 975                 return false;
 976 }
 977
 978 /**
 979  * dce_v10_0_check_latency_hiding - check latency hiding
 980  *
 981  * @wm: watermark calculation data
 982  *
 983  * Check latency hiding (CIK).
 984  * Used for display watermark bandwidth calculations
 985  * Returns true if the display fits, false if not.
 986  */
 987 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
 988 {
 989         u32 lb_partitions = wm->lb_size / wm->src_width;
 990         u32 line_time = wm->active_time + wm->blank_time;
 991         u32 latency_tolerant_lines;
 992         u32 latency_hiding;
 993         fixed20_12 a;
 994
 995         a.full = dfixed_const(1);
 996         if (wm->vsc.full > a.full)
 997                 latency_tolerant_lines = 1;
 998         else {
 999                 if (lb_partitions <= (wm->vtaps + 1))
1000                         latency_tolerant_lines = 1;
1001                 else
1002                         latency_tolerant_lines = 2;
1003         }
1004
1005         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1006
1007         if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1008                 return true;
1009         else
1010                 return false;
1011 }
1012
1013 /**
1014  * dce_v10_0_program_watermarks - program display watermarks
1015  *
1016  * @adev: amdgpu_device pointer
1017  * @amdgpu_crtc: the selected display controller
1018  * @lb_size: line buffer size
1019  * @num_heads: number of display controllers in use
1020  *
1021  * Calculate and program the display watermarks for the
1022  * selected display controller (CIK).
1023  */
1024 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1025                                         struct amdgpu_crtc *amdgpu_crtc,
1026                                         u32 lb_size, u32 num_heads)
1027 {
1028         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1029         struct dce10_wm_params wm_low, wm_high;
1030         u32 active_time;
1031         u32 line_time = 0;
1032         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1033         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1034
1035         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1036                 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1037                                             (u32)mode->clock);
1038                 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1039                                           (u32)mode->clock);
1040                 line_time = min_t(u32, line_time, 65535);
1041
1042                 /* watermark for high clocks */
1043                 if (adev->pm.dpm_enabled) {
1044                         wm_high.yclk =
1045                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1046                         wm_high.sclk =
1047                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1048                 } else {
1049                         wm_high.yclk = adev->pm.current_mclk * 10;
1050                         wm_high.sclk = adev->pm.current_sclk * 10;
1051                 }
1052
1053                 wm_high.disp_clk = mode->clock;
1054                 wm_high.src_width = mode->crtc_hdisplay;
1055                 wm_high.active_time = active_time;
1056                 wm_high.blank_time = line_time - wm_high.active_time;
1057                 wm_high.interlaced = false;
1058                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1059                         wm_high.interlaced = true;
1060                 wm_high.vsc = amdgpu_crtc->vsc;
1061                 wm_high.vtaps = 1;
1062                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1063                         wm_high.vtaps = 2;
1064                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1065                 wm_high.lb_size = lb_size;
1066                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1067                 wm_high.num_heads = num_heads;
1068
1069                 /* set for high clocks */
1070                 latency_watermark_a = min_t(u32, dce_v10_0_latency_watermark(&wm_high), 65535);
1071
1072                 /* possibly force display priority to high */
1073                 /* should really do this at mode validation time... */
1074                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1075                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1076                     !dce_v10_0_check_latency_hiding(&wm_high) ||
1077                     (adev->mode_info.disp_priority == 2)) {
1078                         DRM_DEBUG_KMS("force priority to high\n");
1079                 }
1080
1081                 /* watermark for low clocks */
1082                 if (adev->pm.dpm_enabled) {
1083                         wm_low.yclk =
1084                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1085                         wm_low.sclk =
1086                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1087                 } else {
1088                         wm_low.yclk = adev->pm.current_mclk * 10;
1089                         wm_low.sclk = adev->pm.current_sclk * 10;
1090                 }
1091
1092                 wm_low.disp_clk = mode->clock;
1093                 wm_low.src_width = mode->crtc_hdisplay;
1094                 wm_low.active_time = active_time;
1095                 wm_low.blank_time = line_time - wm_low.active_time;
1096                 wm_low.interlaced = false;
1097                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1098                         wm_low.interlaced = true;
1099                 wm_low.vsc = amdgpu_crtc->vsc;
1100                 wm_low.vtaps = 1;
1101                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1102                         wm_low.vtaps = 2;
1103                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1104                 wm_low.lb_size = lb_size;
1105                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1106                 wm_low.num_heads = num_heads;
1107
1108                 /* set for low clocks */
1109                 latency_watermark_b = min_t(u32, dce_v10_0_latency_watermark(&wm_low), 65535);
1110
1111                 /* possibly force display priority to high */
1112                 /* should really do this at mode validation time... */
1113                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1114                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1115                     !dce_v10_0_check_latency_hiding(&wm_low) ||
1116                     (adev->mode_info.disp_priority == 2)) {
1117                         DRM_DEBUG_KMS("force priority to high\n");
1118                 }
1119                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1120         }
1121
1122         /* select wm A */
1123         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1124         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1125         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1126         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1127         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1128         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1129         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1130         /* select wm B */
1131         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1132         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1133         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1134         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1135         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1136         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1137         /* restore original selection */
1138         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1139
1140         /* save values for DPM */
1141         amdgpu_crtc->line_time = line_time;
1142         amdgpu_crtc->wm_high = latency_watermark_a;
1143         amdgpu_crtc->wm_low = latency_watermark_b;
1144         /* Save number of lines the linebuffer leads before the scanout */
1145         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1146 }
1147
1148 /**
1149  * dce_v10_0_bandwidth_update - program display watermarks
1150  *
1151  * @adev: amdgpu_device pointer
1152  *
1153  * Calculate and program the display watermarks and line
1154  * buffer allocation (CIK).
1155  */
1156 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1157 {
1158         struct drm_display_mode *mode = NULL;
1159         u32 num_heads = 0, lb_size;
1160         int i;
1161
1162         amdgpu_display_update_priority(adev);
1163
1164         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1165                 if (adev->mode_info.crtcs[i]->base.enabled)
1166                         num_heads++;
1167         }
1168         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1169                 mode = &adev->mode_info.crtcs[i]->base.mode;
1170                 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1171                 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1172                                             lb_size, num_heads);
1173         }
1174 }
1175
1176 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1177 {
1178         int i;
1179         u32 offset, tmp;
1180
1181         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1182                 offset = adev->mode_info.audio.pin[i].offset;
1183                 tmp = RREG32_AUDIO_ENDPT(offset,
1184                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1185                 if (((tmp &
1186                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1187                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1188                         adev->mode_info.audio.pin[i].connected = false;
1189                 else
1190                         adev->mode_info.audio.pin[i].connected = true;
1191         }
1192 }
1193
1194 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1195 {
1196         int i;
1197
1198         dce_v10_0_audio_get_connected_pins(adev);
1199
1200         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1201                 if (adev->mode_info.audio.pin[i].connected)
1202                         return &adev->mode_info.audio.pin[i];
1203         }
1204         DRM_ERROR("No connected audio pins found!\n");
1205         return NULL;
1206 }
1207
1208 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1209 {
1210         struct amdgpu_device *adev = drm_to_adev(encoder->dev);
1211         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1212         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1213         u32 tmp;
1214
1215         if (!dig || !dig->afmt || !dig->afmt->pin)
1216                 return;
1217
1218         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1219         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1220         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1221 }
1222
1223 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1224                                                 struct drm_display_mode *mode)
1225 {
1226         struct drm_device *dev = encoder->dev;
1227         struct amdgpu_device *adev = drm_to_adev(dev);
1228         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1229         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1230         struct drm_connector *connector;
1231         struct drm_connector_list_iter iter;
1232         struct amdgpu_connector *amdgpu_connector = NULL;
1233         u32 tmp;
1234         int interlace = 0;
1235
1236         if (!dig || !dig->afmt || !dig->afmt->pin)
1237                 return;
1238
1239         drm_connector_list_iter_begin(dev, &iter);
1240         drm_for_each_connector_iter(connector, &iter) {
1241                 if (connector->encoder == encoder) {
1242                         amdgpu_connector = to_amdgpu_connector(connector);
1243                         break;
1244                 }
1245         }
1246         drm_connector_list_iter_end(&iter);
1247
1248         if (!amdgpu_connector) {
1249                 DRM_ERROR("Couldn't find encoder's connector\n");
1250                 return;
1251         }
1252
1253         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1254                 interlace = 1;
1255         if (connector->latency_present[interlace]) {
1256                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1257                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1258                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1259                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1260         } else {
1261                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1262                                     VIDEO_LIPSYNC, 0);
1263                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1264                                     AUDIO_LIPSYNC, 0);
1265         }
1266         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1267                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1268 }
1269
1270 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1271 {
1272         struct drm_device *dev = encoder->dev;
1273         struct amdgpu_device *adev = drm_to_adev(dev);
1274         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1275         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1276         struct drm_connector *connector;
1277         struct drm_connector_list_iter iter;
1278         struct amdgpu_connector *amdgpu_connector = NULL;
1279         u32 tmp;
1280         u8 *sadb = NULL;
1281         int sad_count;
1282
1283         if (!dig || !dig->afmt || !dig->afmt->pin)
1284                 return;
1285
1286         drm_connector_list_iter_begin(dev, &iter);
1287         drm_for_each_connector_iter(connector, &iter) {
1288                 if (connector->encoder == encoder) {
1289                         amdgpu_connector = to_amdgpu_connector(connector);
1290                         break;
1291                 }
1292         }
1293         drm_connector_list_iter_end(&iter);
1294
1295         if (!amdgpu_connector) {
1296                 DRM_ERROR("Couldn't find encoder's connector\n");
1297                 return;
1298         }
1299
1300         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1301         if (sad_count < 0) {
1302                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1303                 sad_count = 0;
1304         }
1305
1306         /* program the speaker allocation */
1307         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1308                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1309         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1310                             DP_CONNECTION, 0);
1311         /* set HDMI mode */
1312         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1313                             HDMI_CONNECTION, 1);
1314         if (sad_count)
1315                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1316                                     SPEAKER_ALLOCATION, sadb[0]);
1317         else
1318                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1319                                     SPEAKER_ALLOCATION, 5); /* stereo */
1320         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1321                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1322
1323         kfree(sadb);
1324 }
1325
1326 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1327 {
1328         struct drm_device *dev = encoder->dev;
1329         struct amdgpu_device *adev = drm_to_adev(dev);
1330         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1331         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1332         struct drm_connector *connector;
1333         struct drm_connector_list_iter iter;
1334         struct amdgpu_connector *amdgpu_connector = NULL;
1335         struct cea_sad *sads;
1336         int i, sad_count;
1337
1338         static const u16 eld_reg_to_type[][2] = {
1339                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1340                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1341                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1342                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1343                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1344                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1345                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1346                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1347                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1348                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1349                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1350                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1351         };
1352
1353         if (!dig || !dig->afmt || !dig->afmt->pin)
1354                 return;
1355
1356         drm_connector_list_iter_begin(dev, &iter);
1357         drm_for_each_connector_iter(connector, &iter) {
1358                 if (connector->encoder == encoder) {
1359                         amdgpu_connector = to_amdgpu_connector(connector);
1360                         break;
1361                 }
1362         }
1363         drm_connector_list_iter_end(&iter);
1364
1365         if (!amdgpu_connector) {
1366                 DRM_ERROR("Couldn't find encoder's connector\n");
1367                 return;
1368         }
1369
1370         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1371         if (sad_count < 0)
1372                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1373         if (sad_count <= 0)
1374                 return;
1375         BUG_ON(!sads);
1376
1377         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1378                 u32 tmp = 0;
1379                 u8 stereo_freqs = 0;
1380                 int max_channels = -1;
1381                 int j;
1382
1383                 for (j = 0; j < sad_count; j++) {
1384                         struct cea_sad *sad = &sads[j];
1385
1386                         if (sad->format == eld_reg_to_type[i][1]) {
1387                                 if (sad->channels > max_channels) {
1388                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1389                                                             MAX_CHANNELS, sad->channels);
1390                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1391                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1392                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1393                                                             SUPPORTED_FREQUENCIES, sad->freq);
1394                                         max_channels = sad->channels;
1395                                 }
1396
1397                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1398                                         stereo_freqs |= sad->freq;
1399                                 else
1400                                         break;
1401                         }
1402                 }
1403
1404                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1405                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1406                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1407         }
1408
1409         kfree(sads);
1410 }
1411
1412 static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1413                                   struct amdgpu_audio_pin *pin,
1414                                   bool enable)
1415 {
1416         if (!pin)
1417                 return;
1418
1419         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1420                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1421 }
1422
1423 static const u32 pin_offsets[] = {
1424         AUD0_REGISTER_OFFSET,
1425         AUD1_REGISTER_OFFSET,
1426         AUD2_REGISTER_OFFSET,
1427         AUD3_REGISTER_OFFSET,
1428         AUD4_REGISTER_OFFSET,
1429         AUD5_REGISTER_OFFSET,
1430         AUD6_REGISTER_OFFSET,
1431 };
1432
1433 static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1434 {
1435         int i;
1436
1437         if (!amdgpu_audio)
1438                 return 0;
1439
1440         adev->mode_info.audio.enabled = true;
1441
1442         adev->mode_info.audio.num_pins = 7;
1443
1444         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1445                 adev->mode_info.audio.pin[i].channels = -1;
1446                 adev->mode_info.audio.pin[i].rate = -1;
1447                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1448                 adev->mode_info.audio.pin[i].status_bits = 0;
1449                 adev->mode_info.audio.pin[i].category_code = 0;
1450                 adev->mode_info.audio.pin[i].connected = false;
1451                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1452                 adev->mode_info.audio.pin[i].id = i;
1453                 /* disable audio.  it will be set up later */
1454                 /* XXX remove once we switch to ip funcs */
1455                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1456         }
1457
1458         return 0;
1459 }
1460
1461 static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1462 {
1463         int i;
1464
1465         if (!amdgpu_audio)
1466                 return;
1467
1468         if (!adev->mode_info.audio.enabled)
1469                 return;
1470
1471         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1472                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1473
1474         adev->mode_info.audio.enabled = false;
1475 }
1476
1477 /*
1478  * update the N and CTS parameters for a given pixel clock rate
1479  */
1480 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1481 {
1482         struct drm_device *dev = encoder->dev;
1483         struct amdgpu_device *adev = drm_to_adev(dev);
1484         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1485         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1486         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1487         u32 tmp;
1488
1489         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1490         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1491         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1492         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1493         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1494         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1495
1496         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1497         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1498         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1499         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1500         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1501         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1502
1503         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1504         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1505         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1506         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1507         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1508         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1509
1510 }
1511
1512 /*
1513  * build a HDMI Video Info Frame
1514  */
1515 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1516                                                void *buffer, size_t size)
1517 {
1518         struct drm_device *dev = encoder->dev;
1519         struct amdgpu_device *adev = drm_to_adev(dev);
1520         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1521         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1522         uint8_t *frame = buffer + 3;
1523         uint8_t *header = buffer;
1524
1525         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1526                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1527         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1528                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1529         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1530                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1531         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1532                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1533 }
1534
1535 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1536 {
1537         struct drm_device *dev = encoder->dev;
1538         struct amdgpu_device *adev = drm_to_adev(dev);
1539         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1540         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1541         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1542         u32 dto_phase = 24 * 1000;
1543         u32 dto_modulo = clock;
1544         u32 tmp;
1545
1546         if (!dig || !dig->afmt)
1547                 return;
1548
1549         /* XXX two dtos; generally use dto0 for hdmi */
1550         /* Express [24MHz / target pixel clock] as an exact rational
1551          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1552          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1553          */
1554         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1555         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1556                             amdgpu_crtc->crtc_id);
1557         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1558         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1559         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1560 }
1561
1562 /*
1563  * update the info frames with the data from the current display mode
1564  */
1565 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1566                                   struct drm_display_mode *mode)
1567 {
1568         struct drm_device *dev = encoder->dev;
1569         struct amdgpu_device *adev = drm_to_adev(dev);
1570         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1571         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1572         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1573         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1574         struct hdmi_avi_infoframe frame;
1575         ssize_t err;
1576         u32 tmp;
1577         int bpc = 8;
1578
1579         if (!dig || !dig->afmt)
1580                 return;
1581
1582         /* Silent, r600_hdmi_enable will raise WARN for us */
1583         if (!dig->afmt->enabled)
1584                 return;
1585
1586         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1587         if (encoder->crtc) {
1588                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1589                 bpc = amdgpu_crtc->bpc;
1590         }
1591
1592         /* disable audio prior to setting up hw */
1593         dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1594         dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1595
1596         dce_v10_0_audio_set_dto(encoder, mode->clock);
1597
1598         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1599         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1600         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1601
1602         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1603
1604         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1605         switch (bpc) {
1606         case 0:
1607         case 6:
1608         case 8:
1609         case 16:
1610         default:
1611                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1612                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1613                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1614                           connector->name, bpc);
1615                 break;
1616         case 10:
1617                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1618                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1619                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1620                           connector->name);
1621                 break;
1622         case 12:
1623                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1624                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1625                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1626                           connector->name);
1627                 break;
1628         }
1629         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1630
1631         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1632         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1633         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1634         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1635         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1636
1637         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1638         /* enable audio info frames (frames won't be set until audio is enabled) */
1639         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1640         /* required for audio info values to be updated */
1641         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1642         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1643
1644         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1645         /* required for audio info values to be updated */
1646         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1647         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1648
1649         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1650         /* anything other than 0 */
1651         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1652         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1653
1654         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1655
1656         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1657         /* set the default audio delay */
1658         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1659         /* should be suffient for all audio modes and small enough for all hblanks */
1660         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1661         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1662
1663         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1664         /* allow 60958 channel status fields to be updated */
1665         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1666         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1667
1668         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1669         if (bpc > 8)
1670                 /* clear SW CTS value */
1671                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1672         else
1673                 /* select SW CTS value */
1674                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1675         /* allow hw to sent ACR packets when required */
1676         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1677         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1678
1679         dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1680
1681         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1682         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1683         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1684
1685         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1686         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1687         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1688
1689         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1690         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1691         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1692         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1693         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1694         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1695         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1696         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1697
1698         dce_v10_0_audio_write_speaker_allocation(encoder);
1699
1700         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1701                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1702
1703         dce_v10_0_afmt_audio_select_pin(encoder);
1704         dce_v10_0_audio_write_sad_regs(encoder);
1705         dce_v10_0_audio_write_latency_fields(encoder, mode);
1706
1707         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1708         if (err < 0) {
1709                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1710                 return;
1711         }
1712
1713         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1714         if (err < 0) {
1715                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1716                 return;
1717         }
1718
1719         dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1720
1721         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1722         /* enable AVI info frames */
1723         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1724         /* required for audio info values to be updated */
1725         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1726         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1727
1728         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1729         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1730         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1731
1732         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1733         /* send audio packets */
1734         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1735         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1736
1737         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1738         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1739         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1740         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1741
1742         /* enable audio after to setting up hw */
1743         dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1744 }
1745
1746 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1747 {
1748         struct drm_device *dev = encoder->dev;
1749         struct amdgpu_device *adev = drm_to_adev(dev);
1750         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1751         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1752
1753         if (!dig || !dig->afmt)
1754                 return;
1755
1756         /* Silent, r600_hdmi_enable will raise WARN for us */
1757         if (enable && dig->afmt->enabled)
1758                 return;
1759         if (!enable && !dig->afmt->enabled)
1760                 return;
1761
1762         if (!enable && dig->afmt->pin) {
1763                 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1764                 dig->afmt->pin = NULL;
1765         }
1766
1767         dig->afmt->enabled = enable;
1768
1769         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1770                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1771 }
1772
1773 static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
1774 {
1775         int i;
1776
1777         for (i = 0; i < adev->mode_info.num_dig; i++)
1778                 adev->mode_info.afmt[i] = NULL;
1779
1780         /* DCE10 has audio blocks tied to DIG encoders */
1781         for (i = 0; i < adev->mode_info.num_dig; i++) {
1782                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1783                 if (adev->mode_info.afmt[i]) {
1784                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1785                         adev->mode_info.afmt[i]->id = i;
1786                 } else {
1787                         int j;
1788                         for (j = 0; j < i; j++) {
1789                                 kfree(adev->mode_info.afmt[j]);
1790                                 adev->mode_info.afmt[j] = NULL;
1791                         }
1792                         return -ENOMEM;
1793                 }
1794         }
1795         return 0;
1796 }
1797
1798 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1799 {
1800         int i;
1801
1802         for (i = 0; i < adev->mode_info.num_dig; i++) {
1803                 kfree(adev->mode_info.afmt[i]);
1804                 adev->mode_info.afmt[i] = NULL;
1805         }
1806 }
1807
1808 static const u32 vga_control_regs[6] = {
1809         mmD1VGA_CONTROL,
1810         mmD2VGA_CONTROL,
1811         mmD3VGA_CONTROL,
1812         mmD4VGA_CONTROL,
1813         mmD5VGA_CONTROL,
1814         mmD6VGA_CONTROL,
1815 };
1816
1817 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
1818 {
1819         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1820         struct drm_device *dev = crtc->dev;
1821         struct amdgpu_device *adev = drm_to_adev(dev);
1822         u32 vga_control;
1823
1824         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1825         if (enable)
1826                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1827         else
1828                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1829 }
1830
1831 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
1832 {
1833         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1834         struct drm_device *dev = crtc->dev;
1835         struct amdgpu_device *adev = drm_to_adev(dev);
1836
1837         if (enable)
1838                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1839         else
1840                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1841 }
1842
1843 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
1844                                      struct drm_framebuffer *fb,
1845                                      int x, int y, int atomic)
1846 {
1847         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1848         struct drm_device *dev = crtc->dev;
1849         struct amdgpu_device *adev = drm_to_adev(dev);
1850         struct drm_framebuffer *target_fb;
1851         struct drm_gem_object *obj;
1852         struct amdgpu_bo *abo;
1853         uint64_t fb_location, tiling_flags;
1854         uint32_t fb_format, fb_pitch_pixels;
1855         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1856         u32 pipe_config;
1857         u32 tmp, viewport_w, viewport_h;
1858         int r;
1859         bool bypass_lut = false;
1860
1861         /* no fb bound */
1862         if (!atomic && !crtc->primary->fb) {
1863                 DRM_DEBUG_KMS("No FB bound\n");
1864                 return 0;
1865         }
1866
1867         if (atomic)
1868                 target_fb = fb;
1869         else
1870                 target_fb = crtc->primary->fb;
1871
1872         /* If atomic, assume fb object is pinned & idle & fenced and
1873          * just update base pointers
1874          */
1875         obj = target_fb->obj[0];
1876         abo = gem_to_amdgpu_bo(obj);
1877         r = amdgpu_bo_reserve(abo, false);
1878         if (unlikely(r != 0))
1879                 return r;
1880
1881         if (!atomic) {
1882                 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1883                 if (unlikely(r != 0)) {
1884                         amdgpu_bo_unreserve(abo);
1885                         return -EINVAL;
1886                 }
1887         }
1888         fb_location = amdgpu_bo_gpu_offset(abo);
1889
1890         amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1891         amdgpu_bo_unreserve(abo);
1892
1893         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1894
1895         switch (target_fb->format->format) {
1896         case DRM_FORMAT_C8:
1897                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1898                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1899                 break;
1900         case DRM_FORMAT_XRGB4444:
1901         case DRM_FORMAT_ARGB4444:
1902                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1903                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1904 #ifdef __BIG_ENDIAN
1905                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1906                                         ENDIAN_8IN16);
1907 #endif
1908                 break;
1909         case DRM_FORMAT_XRGB1555:
1910         case DRM_FORMAT_ARGB1555:
1911                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1912                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1913 #ifdef __BIG_ENDIAN
1914                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1915                                         ENDIAN_8IN16);
1916 #endif
1917                 break;
1918         case DRM_FORMAT_BGRX5551:
1919         case DRM_FORMAT_BGRA5551:
1920                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1921                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1922 #ifdef __BIG_ENDIAN
1923                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1924                                         ENDIAN_8IN16);
1925 #endif
1926                 break;
1927         case DRM_FORMAT_RGB565:
1928                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1929                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1930 #ifdef __BIG_ENDIAN
1931                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1932                                         ENDIAN_8IN16);
1933 #endif
1934                 break;
1935         case DRM_FORMAT_XRGB8888:
1936         case DRM_FORMAT_ARGB8888:
1937                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1938                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1939 #ifdef __BIG_ENDIAN
1940                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1941                                         ENDIAN_8IN32);
1942 #endif
1943                 break;
1944         case DRM_FORMAT_XRGB2101010:
1945         case DRM_FORMAT_ARGB2101010:
1946                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1947                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1948 #ifdef __BIG_ENDIAN
1949                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1950                                         ENDIAN_8IN32);
1951 #endif
1952                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1953                 bypass_lut = true;
1954                 break;
1955         case DRM_FORMAT_BGRX1010102:
1956         case DRM_FORMAT_BGRA1010102:
1957                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1958                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
1959 #ifdef __BIG_ENDIAN
1960                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1961                                         ENDIAN_8IN32);
1962 #endif
1963                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1964                 bypass_lut = true;
1965                 break;
1966         case DRM_FORMAT_XBGR8888:
1967         case DRM_FORMAT_ABGR8888:
1968                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1969                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1970                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
1971                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
1972 #ifdef __BIG_ENDIAN
1973                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1974                                         ENDIAN_8IN32);
1975 #endif
1976                 break;
1977         default:
1978                 DRM_ERROR("Unsupported screen format %p4cc\n",
1979                           &target_fb->format->format);
1980                 return -EINVAL;
1981         }
1982
1983         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1984                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1985
1986                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1987                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1988                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1989                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1990                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1991
1992                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
1993                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
1994                                           ARRAY_2D_TILED_THIN1);
1995                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
1996                                           tile_split);
1997                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
1998                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
1999                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2000                                           mtaspect);
2001                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2002                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2003         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2004                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2005                                           ARRAY_1D_TILED_THIN1);
2006         }
2007
2008         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2009                                   pipe_config);
2010
2011         dce_v10_0_vga_enable(crtc, false);
2012
2013         /* Make sure surface address is updated at vertical blank rather than
2014          * horizontal blank
2015          */
2016         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2017         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2018                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2019         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2020
2021         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2022                upper_32_bits(fb_location));
2023         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2024                upper_32_bits(fb_location));
2025         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2026                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2027         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2028                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2029         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2030         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2031
2032         /*
2033          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2034          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2035          * retain the full precision throughout the pipeline.
2036          */
2037         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2038         if (bypass_lut)
2039                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2040         else
2041                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2042         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2043
2044         if (bypass_lut)
2045                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2046
2047         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2048         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2049         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2050         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2051         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2052         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2053
2054         fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2055         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2056
2057         dce_v10_0_grph_enable(crtc, true);
2058
2059         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2060                target_fb->height);
2061
2062         x &= ~3;
2063         y &= ~1;
2064         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2065                (x << 16) | y);
2066         viewport_w = crtc->mode.hdisplay;
2067         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2068         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2069                (viewport_w << 16) | viewport_h);
2070
2071         /* set pageflip to happen anywhere in vblank interval */
2072         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2073
2074         if (!atomic && fb && fb != crtc->primary->fb) {
2075                 abo = gem_to_amdgpu_bo(fb->obj[0]);
2076                 r = amdgpu_bo_reserve(abo, true);
2077                 if (unlikely(r != 0))
2078                         return r;
2079                 amdgpu_bo_unpin(abo);
2080                 amdgpu_bo_unreserve(abo);
2081         }
2082
2083         /* Bytes per pixel may have changed */
2084         dce_v10_0_bandwidth_update(adev);
2085
2086         return 0;
2087 }
2088
2089 static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2090                                      struct drm_display_mode *mode)
2091 {
2092         struct drm_device *dev = crtc->dev;
2093         struct amdgpu_device *adev = drm_to_adev(dev);
2094         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2095         u32 tmp;
2096
2097         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2098         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2099                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2100         else
2101                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2102         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2103 }
2104
2105 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2106 {
2107         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2108         struct drm_device *dev = crtc->dev;
2109         struct amdgpu_device *adev = drm_to_adev(dev);
2110         u16 *r, *g, *b;
2111         int i;
2112         u32 tmp;
2113
2114         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2115
2116         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2117         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2118         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2119         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2120
2121         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2122         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2123         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2124
2125         tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2126         tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2127         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2128
2129         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2130         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2131         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2132         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2133
2134         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2135
2136         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2137         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2138         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2139
2140         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2141         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2142         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2143
2144         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2145         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2146
2147         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2148         r = crtc->gamma_store;
2149         g = r + crtc->gamma_size;
2150         b = g + crtc->gamma_size;
2151         for (i = 0; i < 256; i++) {
2152                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2153                        ((*r++ & 0xffc0) << 14) |
2154                        ((*g++ & 0xffc0) << 4) |
2155                        (*b++ >> 6));
2156         }
2157
2158         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2159         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2160         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2161         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2162         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2163
2164         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2165         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2166         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2167         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2168
2169         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2170         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2171         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2172         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2173
2174         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2175         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2176         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2177         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2178
2179         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2180         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2181         /* XXX this only needs to be programmed once per crtc at startup,
2182          * not sure where the best place for it is
2183          */
2184         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2185         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2186         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2187 }
2188
2189 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2190 {
2191         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2192         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2193
2194         switch (amdgpu_encoder->encoder_id) {
2195         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2196                 if (dig->linkb)
2197                         return 1;
2198                 else
2199                         return 0;
2200         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2201                 if (dig->linkb)
2202                         return 3;
2203                 else
2204                         return 2;
2205         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2206                 if (dig->linkb)
2207                         return 5;
2208                 else
2209                         return 4;
2210         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2211                 return 6;
2212         default:
2213                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2214                 return 0;
2215         }
2216 }
2217
2218 /**
2219  * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2220  *
2221  * @crtc: drm crtc
2222  *
2223  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2224  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2225  * monitors a dedicated PPLL must be used.  If a particular board has
2226  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2227  * as there is no need to program the PLL itself.  If we are not able to
2228  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2229  * avoid messing up an existing monitor.
2230  *
2231  * Asic specific PLL information
2232  *
2233  * DCE 10.x
2234  * Tonga
2235  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2236  * CI
2237  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2238  *
2239  */
2240 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2241 {
2242         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2243         struct drm_device *dev = crtc->dev;
2244         struct amdgpu_device *adev = drm_to_adev(dev);
2245         u32 pll_in_use;
2246         int pll;
2247
2248         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2249                 if (adev->clock.dp_extclk)
2250                         /* skip PPLL programming if using ext clock */
2251                         return ATOM_PPLL_INVALID;
2252                 else {
2253                         /* use the same PPLL for all DP monitors */
2254                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2255                         if (pll != ATOM_PPLL_INVALID)
2256                                 return pll;
2257                 }
2258         } else {
2259                 /* use the same PPLL for all monitors with the same clock */
2260                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2261                 if (pll != ATOM_PPLL_INVALID)
2262                         return pll;
2263         }
2264
2265         /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2266         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2267         if (!(pll_in_use & (1 << ATOM_PPLL2)))
2268                 return ATOM_PPLL2;
2269         if (!(pll_in_use & (1 << ATOM_PPLL1)))
2270                 return ATOM_PPLL1;
2271         if (!(pll_in_use & (1 << ATOM_PPLL0)))
2272                 return ATOM_PPLL0;
2273         DRM_ERROR("unable to allocate a PPLL\n");
2274         return ATOM_PPLL_INVALID;
2275 }
2276
2277 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2278 {
2279         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2280         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2281         uint32_t cur_lock;
2282
2283         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2284         if (lock)
2285                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2286         else
2287                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2288         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2289 }
2290
2291 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2292 {
2293         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2294         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2295         u32 tmp;
2296
2297         tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2298         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2299         WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2300 }
2301
2302 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2303 {
2304         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2305         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2306         u32 tmp;
2307
2308         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2309                upper_32_bits(amdgpu_crtc->cursor_addr));
2310         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2311                lower_32_bits(amdgpu_crtc->cursor_addr));
2312
2313         tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2314         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2315         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2316         WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2317 }
2318
2319 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2320                                         int x, int y)
2321 {
2322         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2323         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2324         int xorigin = 0, yorigin = 0;
2325
2326         amdgpu_crtc->cursor_x = x;
2327         amdgpu_crtc->cursor_y = y;
2328
2329         /* avivo cursor are offset into the total surface */
2330         x += crtc->x;
2331         y += crtc->y;
2332         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2333
2334         if (x < 0) {
2335                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2336                 x = 0;
2337         }
2338         if (y < 0) {
2339                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2340                 y = 0;
2341         }
2342
2343         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2344         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2345         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2346                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2347
2348         return 0;
2349 }
2350
2351 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2352                                       int x, int y)
2353 {
2354         int ret;
2355
2356         dce_v10_0_lock_cursor(crtc, true);
2357         ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2358         dce_v10_0_lock_cursor(crtc, false);
2359
2360         return ret;
2361 }
2362
2363 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2364                                       struct drm_file *file_priv,
2365                                       uint32_t handle,
2366                                       uint32_t width,
2367                                       uint32_t height,
2368                                       int32_t hot_x,
2369                                       int32_t hot_y)
2370 {
2371         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2372         struct drm_gem_object *obj;
2373         struct amdgpu_bo *aobj;
2374         int ret;
2375
2376         if (!handle) {
2377                 /* turn off cursor */
2378                 dce_v10_0_hide_cursor(crtc);
2379                 obj = NULL;
2380                 goto unpin;
2381         }
2382
2383         if ((width > amdgpu_crtc->max_cursor_width) ||
2384             (height > amdgpu_crtc->max_cursor_height)) {
2385                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2386                 return -EINVAL;
2387         }
2388
2389         obj = drm_gem_object_lookup(file_priv, handle);
2390         if (!obj) {
2391                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2392                 return -ENOENT;
2393         }
2394
2395         aobj = gem_to_amdgpu_bo(obj);
2396         ret = amdgpu_bo_reserve(aobj, false);
2397         if (ret != 0) {
2398                 drm_gem_object_put(obj);
2399                 return ret;
2400         }
2401
2402         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2403         amdgpu_bo_unreserve(aobj);
2404         if (ret) {
2405                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2406                 drm_gem_object_put(obj);
2407                 return ret;
2408         }
2409         amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2410
2411         dce_v10_0_lock_cursor(crtc, true);
2412
2413         if (width != amdgpu_crtc->cursor_width ||
2414             height != amdgpu_crtc->cursor_height ||
2415             hot_x != amdgpu_crtc->cursor_hot_x ||
2416             hot_y != amdgpu_crtc->cursor_hot_y) {
2417                 int x, y;
2418
2419                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2420                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2421
2422                 dce_v10_0_cursor_move_locked(crtc, x, y);
2423
2424                 amdgpu_crtc->cursor_width = width;
2425                 amdgpu_crtc->cursor_height = height;
2426                 amdgpu_crtc->cursor_hot_x = hot_x;
2427                 amdgpu_crtc->cursor_hot_y = hot_y;
2428         }
2429
2430         dce_v10_0_show_cursor(crtc);
2431         dce_v10_0_lock_cursor(crtc, false);
2432
2433 unpin:
2434         if (amdgpu_crtc->cursor_bo) {
2435                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2436                 ret = amdgpu_bo_reserve(aobj, true);
2437                 if (likely(ret == 0)) {
2438                         amdgpu_bo_unpin(aobj);
2439                         amdgpu_bo_unreserve(aobj);
2440                 }
2441                 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2442         }
2443
2444         amdgpu_crtc->cursor_bo = obj;
2445         return 0;
2446 }
2447
2448 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2449 {
2450         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2451
2452         if (amdgpu_crtc->cursor_bo) {
2453                 dce_v10_0_lock_cursor(crtc, true);
2454
2455                 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2456                                              amdgpu_crtc->cursor_y);
2457
2458                 dce_v10_0_show_cursor(crtc);
2459
2460                 dce_v10_0_lock_cursor(crtc, false);
2461         }
2462 }
2463
2464 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2465                                     u16 *blue, uint32_t size,
2466                                     struct drm_modeset_acquire_ctx *ctx)
2467 {
2468         dce_v10_0_crtc_load_lut(crtc);
2469
2470         return 0;
2471 }
2472
2473 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2474 {
2475         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2476
2477         drm_crtc_cleanup(crtc);
2478         kfree(amdgpu_crtc);
2479 }
2480
2481 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2482         .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2483         .cursor_move = dce_v10_0_crtc_cursor_move,
2484         .gamma_set = dce_v10_0_crtc_gamma_set,
2485         .set_config = amdgpu_display_crtc_set_config,
2486         .destroy = dce_v10_0_crtc_destroy,
2487         .page_flip_target = amdgpu_display_crtc_page_flip_target,
2488         .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2489         .enable_vblank = amdgpu_enable_vblank_kms,
2490         .disable_vblank = amdgpu_disable_vblank_kms,
2491         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2492 };
2493
2494 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2495 {
2496         struct drm_device *dev = crtc->dev;
2497         struct amdgpu_device *adev = drm_to_adev(dev);
2498         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2499         unsigned type;
2500
2501         switch (mode) {
2502         case DRM_MODE_DPMS_ON:
2503                 amdgpu_crtc->enabled = true;
2504                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2505                 dce_v10_0_vga_enable(crtc, true);
2506                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2507                 dce_v10_0_vga_enable(crtc, false);
2508                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2509                 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2510                                                 amdgpu_crtc->crtc_id);
2511                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2512                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2513                 drm_crtc_vblank_on(crtc);
2514                 dce_v10_0_crtc_load_lut(crtc);
2515                 break;
2516         case DRM_MODE_DPMS_STANDBY:
2517         case DRM_MODE_DPMS_SUSPEND:
2518         case DRM_MODE_DPMS_OFF:
2519                 drm_crtc_vblank_off(crtc);
2520                 if (amdgpu_crtc->enabled) {
2521                         dce_v10_0_vga_enable(crtc, true);
2522                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2523                         dce_v10_0_vga_enable(crtc, false);
2524                 }
2525                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2526                 amdgpu_crtc->enabled = false;
2527                 break;
2528         }
2529         /* adjust pm to dpms */
2530         amdgpu_dpm_compute_clocks(adev);
2531 }
2532
2533 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2534 {
2535         /* disable crtc pair power gating before programming */
2536         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2537         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2538         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2539 }
2540
2541 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2542 {
2543         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2544         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2545 }
2546
2547 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2548 {
2549         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2550         struct drm_device *dev = crtc->dev;
2551         struct amdgpu_device *adev = drm_to_adev(dev);
2552         struct amdgpu_atom_ss ss;
2553         int i;
2554
2555         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2556         if (crtc->primary->fb) {
2557                 int r;
2558                 struct amdgpu_bo *abo;
2559
2560                 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2561                 r = amdgpu_bo_reserve(abo, true);
2562                 if (unlikely(r))
2563                         DRM_ERROR("failed to reserve abo before unpin\n");
2564                 else {
2565                         amdgpu_bo_unpin(abo);
2566                         amdgpu_bo_unreserve(abo);
2567                 }
2568         }
2569         /* disable the GRPH */
2570         dce_v10_0_grph_enable(crtc, false);
2571
2572         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2573
2574         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2575                 if (adev->mode_info.crtcs[i] &&
2576                     adev->mode_info.crtcs[i]->enabled &&
2577                     i != amdgpu_crtc->crtc_id &&
2578                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2579                         /* one other crtc is using this pll don't turn
2580                          * off the pll
2581                          */
2582                         goto done;
2583                 }
2584         }
2585
2586         switch (amdgpu_crtc->pll_id) {
2587         case ATOM_PPLL0:
2588         case ATOM_PPLL1:
2589         case ATOM_PPLL2:
2590                 /* disable the ppll */
2591                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2592                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2593                 break;
2594         default:
2595                 break;
2596         }
2597 done:
2598         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2599         amdgpu_crtc->adjusted_clock = 0;
2600         amdgpu_crtc->encoder = NULL;
2601         amdgpu_crtc->connector = NULL;
2602 }
2603
2604 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2605                                   struct drm_display_mode *mode,
2606                                   struct drm_display_mode *adjusted_mode,
2607                                   int x, int y, struct drm_framebuffer *old_fb)
2608 {
2609         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2610
2611         if (!amdgpu_crtc->adjusted_clock)
2612                 return -EINVAL;
2613
2614         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2615         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2616         dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2617         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2618         amdgpu_atombios_crtc_scaler_setup(crtc);
2619         dce_v10_0_cursor_reset(crtc);
2620         /* update the hw version fpr dpm */
2621         amdgpu_crtc->hw_mode = *adjusted_mode;
2622
2623         return 0;
2624 }
2625
2626 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2627                                      const struct drm_display_mode *mode,
2628                                      struct drm_display_mode *adjusted_mode)
2629 {
2630         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2631         struct drm_device *dev = crtc->dev;
2632         struct drm_encoder *encoder;
2633
2634         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2635         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2636                 if (encoder->crtc == crtc) {
2637                         amdgpu_crtc->encoder = encoder;
2638                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2639                         break;
2640                 }
2641         }
2642         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2643                 amdgpu_crtc->encoder = NULL;
2644                 amdgpu_crtc->connector = NULL;
2645                 return false;
2646         }
2647         if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2648                 return false;
2649         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2650                 return false;
2651         /* pick pll */
2652         amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2653         /* if we can't get a PPLL for a non-DP encoder, fail */
2654         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2655             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2656                 return false;
2657
2658         return true;
2659 }
2660
2661 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2662                                   struct drm_framebuffer *old_fb)
2663 {
2664         return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2665 }
2666
2667 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2668                                          struct drm_framebuffer *fb,
2669                                          int x, int y, enum mode_set_atomic state)
2670 {
2671         return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2672 }
2673
2674 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2675         .dpms = dce_v10_0_crtc_dpms,
2676         .mode_fixup = dce_v10_0_crtc_mode_fixup,
2677         .mode_set = dce_v10_0_crtc_mode_set,
2678         .mode_set_base = dce_v10_0_crtc_set_base,
2679         .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2680         .prepare = dce_v10_0_crtc_prepare,
2681         .commit = dce_v10_0_crtc_commit,
2682         .disable = dce_v10_0_crtc_disable,
2683         .get_scanout_position = amdgpu_crtc_get_scanout_position,
2684 };
2685
2686 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2687 {
2688         struct amdgpu_crtc *amdgpu_crtc;
2689
2690         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2691                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2692         if (amdgpu_crtc == NULL)
2693                 return -ENOMEM;
2694
2695         drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2696
2697         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2698         amdgpu_crtc->crtc_id = index;
2699         adev->mode_info.crtcs[index] = amdgpu_crtc;
2700
2701         amdgpu_crtc->max_cursor_width = 128;
2702         amdgpu_crtc->max_cursor_height = 128;
2703         adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2704         adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2705
2706         switch (amdgpu_crtc->crtc_id) {
2707         case 0:
2708         default:
2709                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2710                 break;
2711         case 1:
2712                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2713                 break;
2714         case 2:
2715                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2716                 break;
2717         case 3:
2718                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2719                 break;
2720         case 4:
2721                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2722                 break;
2723         case 5:
2724                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2725                 break;
2726         }
2727
2728         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2729         amdgpu_crtc->adjusted_clock = 0;
2730         amdgpu_crtc->encoder = NULL;
2731         amdgpu_crtc->connector = NULL;
2732         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2733
2734         return 0;
2735 }
2736
2737 static int dce_v10_0_early_init(void *handle)
2738 {
2739         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2740
2741         adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2742         adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2743
2744         dce_v10_0_set_display_funcs(adev);
2745
2746         adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
2747
2748         switch (adev->asic_type) {
2749         case CHIP_FIJI:
2750         case CHIP_TONGA:
2751                 adev->mode_info.num_hpd = 6;
2752                 adev->mode_info.num_dig = 7;
2753                 break;
2754         default:
2755                 /* FIXME: not supported yet */
2756                 return -EINVAL;
2757         }
2758
2759         dce_v10_0_set_irq_funcs(adev);
2760
2761         return 0;
2762 }
2763
2764 static int dce_v10_0_sw_init(void *handle)
2765 {
2766         int r, i;
2767         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2768
2769         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2770                 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2771                 if (r)
2772                         return r;
2773         }
2774
2775         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2776                 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2777                 if (r)
2778                         return r;
2779         }
2780
2781         /* HPD hotplug */
2782         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2783         if (r)
2784                 return r;
2785
2786         adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2787
2788         adev_to_drm(adev)->mode_config.async_page_flip = true;
2789
2790         adev_to_drm(adev)->mode_config.max_width = 16384;
2791         adev_to_drm(adev)->mode_config.max_height = 16384;
2792
2793         adev_to_drm(adev)->mode_config.preferred_depth = 24;
2794         adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2795
2796         adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2797
2798         r = amdgpu_display_modeset_create_props(adev);
2799         if (r)
2800                 return r;
2801
2802         adev_to_drm(adev)->mode_config.max_width = 16384;
2803         adev_to_drm(adev)->mode_config.max_height = 16384;
2804
2805         /* allocate crtcs */
2806         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2807                 r = dce_v10_0_crtc_init(adev, i);
2808                 if (r)
2809                         return r;
2810         }
2811
2812         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2813                 amdgpu_display_print_display_setup(adev_to_drm(adev));
2814         else
2815                 return -EINVAL;
2816
2817         /* setup afmt */
2818         r = dce_v10_0_afmt_init(adev);
2819         if (r)
2820                 return r;
2821
2822         r = dce_v10_0_audio_init(adev);
2823         if (r)
2824                 return r;
2825
2826         /* Disable vblank IRQs aggressively for power-saving */
2827         /* XXX: can this be enabled for DC? */
2828         adev_to_drm(adev)->vblank_disable_immediate = true;
2829
2830         r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
2831         if (r)
2832                 return r;
2833
2834         INIT_DELAYED_WORK(&adev->hotplug_work,
2835                   amdgpu_display_hotplug_work_func);
2836
2837         drm_kms_helper_poll_init(adev_to_drm(adev));
2838
2839         adev->mode_info.mode_config_initialized = true;
2840         return 0;
2841 }
2842
2843 static int dce_v10_0_sw_fini(void *handle)
2844 {
2845         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2846
2847         kfree(adev->mode_info.bios_hardcoded_edid);
2848
2849         drm_kms_helper_poll_fini(adev_to_drm(adev));
2850
2851         dce_v10_0_audio_fini(adev);
2852
2853         dce_v10_0_afmt_fini(adev);
2854
2855         drm_mode_config_cleanup(adev_to_drm(adev));
2856         adev->mode_info.mode_config_initialized = false;
2857
2858         return 0;
2859 }
2860
2861 static int dce_v10_0_hw_init(void *handle)
2862 {
2863         int i;
2864         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2865
2866         dce_v10_0_init_golden_registers(adev);
2867
2868         /* disable vga render */
2869         dce_v10_0_set_vga_render_state(adev, false);
2870         /* init dig PHYs, disp eng pll */
2871         amdgpu_atombios_encoder_init_dig(adev);
2872         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2873
2874         /* initialize hpd */
2875         dce_v10_0_hpd_init(adev);
2876
2877         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2878                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2879         }
2880
2881         dce_v10_0_pageflip_interrupt_init(adev);
2882
2883         return 0;
2884 }
2885
2886 static int dce_v10_0_hw_fini(void *handle)
2887 {
2888         int i;
2889         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2890
2891         dce_v10_0_hpd_fini(adev);
2892
2893         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2894                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2895         }
2896
2897         dce_v10_0_pageflip_interrupt_fini(adev);
2898
2899         flush_delayed_work(&adev->hotplug_work);
2900
2901         return 0;
2902 }
2903
2904 static int dce_v10_0_suspend(void *handle)
2905 {
2906         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2907         int r;
2908
2909         r = amdgpu_display_suspend_helper(adev);
2910         if (r)
2911                 return r;
2912
2913         adev->mode_info.bl_level =
2914                 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2915
2916         return dce_v10_0_hw_fini(handle);
2917 }
2918
2919 static int dce_v10_0_resume(void *handle)
2920 {
2921         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2922         int ret;
2923
2924         amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2925                                                            adev->mode_info.bl_level);
2926
2927         ret = dce_v10_0_hw_init(handle);
2928
2929         /* turn on the BL */
2930         if (adev->mode_info.bl_encoder) {
2931                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2932                                                                   adev->mode_info.bl_encoder);
2933                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2934                                                     bl_level);
2935         }
2936         if (ret)
2937                 return ret;
2938
2939         return amdgpu_display_resume_helper(adev);
2940 }
2941
2942 static bool dce_v10_0_is_idle(void *handle)
2943 {
2944         return true;
2945 }
2946
2947 static int dce_v10_0_wait_for_idle(void *handle)
2948 {
2949         return 0;
2950 }
2951
2952 static bool dce_v10_0_check_soft_reset(void *handle)
2953 {
2954         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2955
2956         return dce_v10_0_is_display_hung(adev);
2957 }
2958
2959 static int dce_v10_0_soft_reset(void *handle)
2960 {
2961         u32 srbm_soft_reset = 0, tmp;
2962         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2963
2964         if (dce_v10_0_is_display_hung(adev))
2965                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2966
2967         if (srbm_soft_reset) {
2968                 tmp = RREG32(mmSRBM_SOFT_RESET);
2969                 tmp |= srbm_soft_reset;
2970                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2971                 WREG32(mmSRBM_SOFT_RESET, tmp);
2972                 tmp = RREG32(mmSRBM_SOFT_RESET);
2973
2974                 udelay(50);
2975
2976                 tmp &= ~srbm_soft_reset;
2977                 WREG32(mmSRBM_SOFT_RESET, tmp);
2978                 tmp = RREG32(mmSRBM_SOFT_RESET);
2979
2980                 /* Wait a little for things to settle down */
2981                 udelay(50);
2982         }
2983         return 0;
2984 }
2985
2986 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2987                                                      int crtc,
2988                                                      enum amdgpu_interrupt_state state)
2989 {
2990         u32 lb_interrupt_mask;
2991
2992         if (crtc >= adev->mode_info.num_crtc) {
2993                 DRM_DEBUG("invalid crtc %d\n", crtc);
2994                 return;
2995         }
2996
2997         switch (state) {
2998         case AMDGPU_IRQ_STATE_DISABLE:
2999                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3000                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3001                                                   VBLANK_INTERRUPT_MASK, 0);
3002                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3003                 break;
3004         case AMDGPU_IRQ_STATE_ENABLE:
3005                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3006                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3007                                                   VBLANK_INTERRUPT_MASK, 1);
3008                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3009                 break;
3010         default:
3011                 break;
3012         }
3013 }
3014
3015 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3016                                                     int crtc,
3017                                                     enum amdgpu_interrupt_state state)
3018 {
3019         u32 lb_interrupt_mask;
3020
3021         if (crtc >= adev->mode_info.num_crtc) {
3022                 DRM_DEBUG("invalid crtc %d\n", crtc);
3023                 return;
3024         }
3025
3026         switch (state) {
3027         case AMDGPU_IRQ_STATE_DISABLE:
3028                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3029                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3030                                                   VLINE_INTERRUPT_MASK, 0);
3031                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3032                 break;
3033         case AMDGPU_IRQ_STATE_ENABLE:
3034                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3035                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3036                                                   VLINE_INTERRUPT_MASK, 1);
3037                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3038                 break;
3039         default:
3040                 break;
3041         }
3042 }
3043
3044 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3045                                        struct amdgpu_irq_src *source,
3046                                        unsigned hpd,
3047                                        enum amdgpu_interrupt_state state)
3048 {
3049         u32 tmp;
3050
3051         if (hpd >= adev->mode_info.num_hpd) {
3052                 DRM_DEBUG("invalid hdp %d\n", hpd);
3053                 return 0;
3054         }
3055
3056         switch (state) {
3057         case AMDGPU_IRQ_STATE_DISABLE:
3058                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3059                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3060                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3061                 break;
3062         case AMDGPU_IRQ_STATE_ENABLE:
3063                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3064                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3065                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3066                 break;
3067         default:
3068                 break;
3069         }
3070
3071         return 0;
3072 }
3073
3074 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3075                                         struct amdgpu_irq_src *source,
3076                                         unsigned type,
3077                                         enum amdgpu_interrupt_state state)
3078 {
3079         switch (type) {
3080         case AMDGPU_CRTC_IRQ_VBLANK1:
3081                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3082                 break;
3083         case AMDGPU_CRTC_IRQ_VBLANK2:
3084                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3085                 break;
3086         case AMDGPU_CRTC_IRQ_VBLANK3:
3087                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3088                 break;
3089         case AMDGPU_CRTC_IRQ_VBLANK4:
3090                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3091                 break;
3092         case AMDGPU_CRTC_IRQ_VBLANK5:
3093                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3094                 break;
3095         case AMDGPU_CRTC_IRQ_VBLANK6:
3096                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3097                 break;
3098         case AMDGPU_CRTC_IRQ_VLINE1:
3099                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3100                 break;
3101         case AMDGPU_CRTC_IRQ_VLINE2:
3102                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3103                 break;
3104         case AMDGPU_CRTC_IRQ_VLINE3:
3105                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3106                 break;
3107         case AMDGPU_CRTC_IRQ_VLINE4:
3108                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3109                 break;
3110         case AMDGPU_CRTC_IRQ_VLINE5:
3111                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3112                 break;
3113         case AMDGPU_CRTC_IRQ_VLINE6:
3114                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3115                 break;
3116         default:
3117                 break;
3118         }
3119         return 0;
3120 }
3121
3122 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3123                                             struct amdgpu_irq_src *src,
3124                                             unsigned type,
3125                                             enum amdgpu_interrupt_state state)
3126 {
3127         u32 reg;
3128
3129         if (type >= adev->mode_info.num_crtc) {
3130                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3131                 return -EINVAL;
3132         }
3133
3134         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3135         if (state == AMDGPU_IRQ_STATE_DISABLE)
3136                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3137                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3138         else
3139                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3140                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3141
3142         return 0;
3143 }
3144
3145 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3146                                   struct amdgpu_irq_src *source,
3147                                   struct amdgpu_iv_entry *entry)
3148 {
3149         unsigned long flags;
3150         unsigned crtc_id;
3151         struct amdgpu_crtc *amdgpu_crtc;
3152         struct amdgpu_flip_work *works;
3153
3154         crtc_id = (entry->src_id - 8) >> 1;
3155         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3156
3157         if (crtc_id >= adev->mode_info.num_crtc) {
3158                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3159                 return -EINVAL;
3160         }
3161
3162         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3163             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3164                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3165                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3166
3167         /* IRQ could occur when in initial stage */
3168         if (amdgpu_crtc == NULL)
3169                 return 0;
3170
3171         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
3172         works = amdgpu_crtc->pflip_works;
3173         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3174                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3175                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3176                                                  amdgpu_crtc->pflip_status,
3177                                                  AMDGPU_FLIP_SUBMITTED);
3178                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3179                 return 0;
3180         }
3181
3182         /* page flip completed. clean up */
3183         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3184         amdgpu_crtc->pflip_works = NULL;
3185
3186         /* wakeup usersapce */
3187         if (works->event)
3188                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3189
3190         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3191
3192         drm_crtc_vblank_put(&amdgpu_crtc->base);
3193         schedule_work(&works->unpin_work);
3194
3195         return 0;
3196 }
3197
3198 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3199                                   int hpd)
3200 {
3201         u32 tmp;
3202
3203         if (hpd >= adev->mode_info.num_hpd) {
3204                 DRM_DEBUG("invalid hdp %d\n", hpd);
3205                 return;
3206         }
3207
3208         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3209         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3210         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3211 }
3212
3213 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3214                                           int crtc)
3215 {
3216         u32 tmp;
3217
3218         if (crtc >= adev->mode_info.num_crtc) {
3219                 DRM_DEBUG("invalid crtc %d\n", crtc);
3220                 return;
3221         }
3222
3223         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3224         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3225         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3226 }
3227
3228 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3229                                          int crtc)
3230 {
3231         u32 tmp;
3232
3233         if (crtc >= adev->mode_info.num_crtc) {
3234                 DRM_DEBUG("invalid crtc %d\n", crtc);
3235                 return;
3236         }
3237
3238         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3239         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3240         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3241 }
3242
3243 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3244                               struct amdgpu_irq_src *source,
3245                               struct amdgpu_iv_entry *entry)
3246 {
3247         unsigned crtc = entry->src_id - 1;
3248         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3249         unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, crtc);
3250
3251         switch (entry->src_data[0]) {
3252         case 0: /* vblank */
3253                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3254                         dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3255                 else
3256                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3257
3258                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3259                         drm_handle_vblank(adev_to_drm(adev), crtc);
3260                 }
3261                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3262
3263                 break;
3264         case 1: /* vline */
3265                 if (disp_int & interrupt_status_offsets[crtc].vline)
3266                         dce_v10_0_crtc_vline_int_ack(adev, crtc);
3267                 else
3268                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3269
3270                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3271
3272                 break;
3273         default:
3274                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3275                 break;
3276         }
3277
3278         return 0;
3279 }
3280
3281 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3282                              struct amdgpu_irq_src *source,
3283                              struct amdgpu_iv_entry *entry)
3284 {
3285         uint32_t disp_int, mask;
3286         unsigned hpd;
3287
3288         if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3289                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3290                 return 0;
3291         }
3292
3293         hpd = entry->src_data[0];
3294         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3295         mask = interrupt_status_offsets[hpd].hpd;
3296
3297         if (disp_int & mask) {
3298                 dce_v10_0_hpd_int_ack(adev, hpd);
3299                 schedule_delayed_work(&adev->hotplug_work, 0);
3300                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3301         }
3302
3303         return 0;
3304 }
3305
3306 static int dce_v10_0_set_clockgating_state(void *handle,
3307                                           enum amd_clockgating_state state)
3308 {
3309         return 0;
3310 }
3311
3312 static int dce_v10_0_set_powergating_state(void *handle,
3313                                           enum amd_powergating_state state)
3314 {
3315         return 0;
3316 }
3317
3318 static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3319         .name = "dce_v10_0",
3320         .early_init = dce_v10_0_early_init,
3321         .late_init = NULL,
3322         .sw_init = dce_v10_0_sw_init,
3323         .sw_fini = dce_v10_0_sw_fini,
3324         .hw_init = dce_v10_0_hw_init,
3325         .hw_fini = dce_v10_0_hw_fini,
3326         .suspend = dce_v10_0_suspend,
3327         .resume = dce_v10_0_resume,
3328         .is_idle = dce_v10_0_is_idle,
3329         .wait_for_idle = dce_v10_0_wait_for_idle,
3330         .check_soft_reset = dce_v10_0_check_soft_reset,
3331         .soft_reset = dce_v10_0_soft_reset,
3332         .set_clockgating_state = dce_v10_0_set_clockgating_state,
3333         .set_powergating_state = dce_v10_0_set_powergating_state,
3334 };
3335
3336 static void
3337 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3338                           struct drm_display_mode *mode,
3339                           struct drm_display_mode *adjusted_mode)
3340 {
3341         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3342
3343         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3344
3345         /* need to call this here rather than in prepare() since we need some crtc info */
3346         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3347
3348         /* set scaler clears this on some chips */
3349         dce_v10_0_set_interleave(encoder->crtc, mode);
3350
3351         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3352                 dce_v10_0_afmt_enable(encoder, true);
3353                 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3354         }
3355 }
3356
3357 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3358 {
3359         struct amdgpu_device *adev = drm_to_adev(encoder->dev);
3360         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3361         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3362
3363         if ((amdgpu_encoder->active_device &
3364              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3365             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3366              ENCODER_OBJECT_ID_NONE)) {
3367                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3368                 if (dig) {
3369                         dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3370                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3371                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3372                 }
3373         }
3374
3375         amdgpu_atombios_scratch_regs_lock(adev, true);
3376
3377         if (connector) {
3378                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3379
3380                 /* select the clock/data port if it uses a router */
3381                 if (amdgpu_connector->router.cd_valid)
3382                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3383
3384                 /* turn eDP panel on for mode set */
3385                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3386                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3387                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3388         }
3389
3390         /* this is needed for the pll/ss setup to work correctly in some cases */
3391         amdgpu_atombios_encoder_set_crtc_source(encoder);
3392         /* set up the FMT blocks */
3393         dce_v10_0_program_fmt(encoder);
3394 }
3395
3396 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3397 {
3398         struct drm_device *dev = encoder->dev;
3399         struct amdgpu_device *adev = drm_to_adev(dev);
3400
3401         /* need to call this here as we need the crtc set up */
3402         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3403         amdgpu_atombios_scratch_regs_lock(adev, false);
3404 }
3405
3406 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3407 {
3408         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3409         struct amdgpu_encoder_atom_dig *dig;
3410
3411         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3412
3413         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3414                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3415                         dce_v10_0_afmt_enable(encoder, false);
3416                 dig = amdgpu_encoder->enc_priv;
3417                 dig->dig_encoder = -1;
3418         }
3419         amdgpu_encoder->active_device = 0;
3420 }
3421
3422 /* these are handled by the primary encoders */
3423 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3424 {
3425
3426 }
3427
3428 static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3429 {
3430
3431 }
3432
3433 static void
3434 dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3435                       struct drm_display_mode *mode,
3436                       struct drm_display_mode *adjusted_mode)
3437 {
3438
3439 }
3440
3441 static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3442 {
3443
3444 }
3445
3446 static void
3447 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3448 {
3449
3450 }
3451
3452 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3453         .dpms = dce_v10_0_ext_dpms,
3454         .prepare = dce_v10_0_ext_prepare,
3455         .mode_set = dce_v10_0_ext_mode_set,
3456         .commit = dce_v10_0_ext_commit,
3457         .disable = dce_v10_0_ext_disable,
3458         /* no detect for TMDS/LVDS yet */
3459 };
3460
3461 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3462         .dpms = amdgpu_atombios_encoder_dpms,
3463         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3464         .prepare = dce_v10_0_encoder_prepare,
3465         .mode_set = dce_v10_0_encoder_mode_set,
3466         .commit = dce_v10_0_encoder_commit,
3467         .disable = dce_v10_0_encoder_disable,
3468         .detect = amdgpu_atombios_encoder_dig_detect,
3469 };
3470
3471 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3472         .dpms = amdgpu_atombios_encoder_dpms,
3473         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3474         .prepare = dce_v10_0_encoder_prepare,
3475         .mode_set = dce_v10_0_encoder_mode_set,
3476         .commit = dce_v10_0_encoder_commit,
3477         .detect = amdgpu_atombios_encoder_dac_detect,
3478 };
3479
3480 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3481 {
3482         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3483         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3484                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3485         kfree(amdgpu_encoder->enc_priv);
3486         drm_encoder_cleanup(encoder);
3487         kfree(amdgpu_encoder);
3488 }
3489
3490 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3491         .destroy = dce_v10_0_encoder_destroy,
3492 };
3493
3494 static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3495                                  uint32_t encoder_enum,
3496                                  uint32_t supported_device,
3497                                  u16 caps)
3498 {
3499         struct drm_device *dev = adev_to_drm(adev);
3500         struct drm_encoder *encoder;
3501         struct amdgpu_encoder *amdgpu_encoder;
3502
3503         /* see if we already added it */
3504         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3505                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3506                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3507                         amdgpu_encoder->devices |= supported_device;
3508                         return;
3509                 }
3510
3511         }
3512
3513         /* add a new one */
3514         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3515         if (!amdgpu_encoder)
3516                 return;
3517
3518         encoder = &amdgpu_encoder->base;
3519         switch (adev->mode_info.num_crtc) {
3520         case 1:
3521                 encoder->possible_crtcs = 0x1;
3522                 break;
3523         case 2:
3524         default:
3525                 encoder->possible_crtcs = 0x3;
3526                 break;
3527         case 4:
3528                 encoder->possible_crtcs = 0xf;
3529                 break;
3530         case 6:
3531                 encoder->possible_crtcs = 0x3f;
3532                 break;
3533         }
3534
3535         amdgpu_encoder->enc_priv = NULL;
3536
3537         amdgpu_encoder->encoder_enum = encoder_enum;
3538         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3539         amdgpu_encoder->devices = supported_device;
3540         amdgpu_encoder->rmx_type = RMX_OFF;
3541         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3542         amdgpu_encoder->is_ext_encoder = false;
3543         amdgpu_encoder->caps = caps;
3544
3545         switch (amdgpu_encoder->encoder_id) {
3546         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3547         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3548                 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3549                                  DRM_MODE_ENCODER_DAC, NULL);
3550                 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3551                 break;
3552         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3553         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3554         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3555         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3556         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3557                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3558                         amdgpu_encoder->rmx_type = RMX_FULL;
3559                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3560                                          DRM_MODE_ENCODER_LVDS, NULL);
3561                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3562                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3563                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3564                                          DRM_MODE_ENCODER_DAC, NULL);
3565                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3566                 } else {
3567                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3568                                          DRM_MODE_ENCODER_TMDS, NULL);
3569                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3570                 }
3571                 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3572                 break;
3573         case ENCODER_OBJECT_ID_SI170B:
3574         case ENCODER_OBJECT_ID_CH7303:
3575         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3576         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3577         case ENCODER_OBJECT_ID_TITFP513:
3578         case ENCODER_OBJECT_ID_VT1623:
3579         case ENCODER_OBJECT_ID_HDMI_SI1930:
3580         case ENCODER_OBJECT_ID_TRAVIS:
3581         case ENCODER_OBJECT_ID_NUTMEG:
3582                 /* these are handled by the primary encoders */
3583                 amdgpu_encoder->is_ext_encoder = true;
3584                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3585                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3586                                          DRM_MODE_ENCODER_LVDS, NULL);
3587                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3588                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3589                                          DRM_MODE_ENCODER_DAC, NULL);
3590                 else
3591                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3592                                          DRM_MODE_ENCODER_TMDS, NULL);
3593                 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3594                 break;
3595         }
3596 }
3597
3598 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3599         .bandwidth_update = &dce_v10_0_bandwidth_update,
3600         .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3601         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3602         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3603         .hpd_sense = &dce_v10_0_hpd_sense,
3604         .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3605         .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3606         .page_flip = &dce_v10_0_page_flip,
3607         .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3608         .add_encoder = &dce_v10_0_encoder_add,
3609         .add_connector = &amdgpu_connector_add,
3610 };
3611
3612 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3613 {
3614         adev->mode_info.funcs = &dce_v10_0_display_funcs;
3615 }
3616
3617 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3618         .set = dce_v10_0_set_crtc_irq_state,
3619         .process = dce_v10_0_crtc_irq,
3620 };
3621
3622 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3623         .set = dce_v10_0_set_pageflip_irq_state,
3624         .process = dce_v10_0_pageflip_irq,
3625 };
3626
3627 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3628         .set = dce_v10_0_set_hpd_irq_state,
3629         .process = dce_v10_0_hpd_irq,
3630 };
3631
3632 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3633 {
3634         if (adev->mode_info.num_crtc > 0)
3635                 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3636         else
3637                 adev->crtc_irq.num_types = 0;
3638         adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3639
3640         adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3641         adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3642
3643         adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3644         adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3645 }
3646
3647 const struct amdgpu_ip_block_version dce_v10_0_ip_block = {
3648         .type = AMD_IP_BLOCK_TYPE_DCE,
3649         .major = 10,
3650         .minor = 0,
3651         .rev = 0,
3652         .funcs = &dce_v10_0_ip_funcs,
3653 };
3654
3655 const struct amdgpu_ip_block_version dce_v10_1_ip_block = {
3656         .type = AMD_IP_BLOCK_TYPE_DCE,
3657         .major = 10,
3658         .minor = 1,
3659         .rev = 0,
3660         .funcs = &dce_v10_0_ip_funcs,
3661 };