drivers/gpu/drm/tilcdc/tilcdc_drv.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <[email protected]>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 /* LCDC DRM driver, based on da8xx-fb */
  19
  20 #include <linux/component.h>
  21 #include <linux/pinctrl/consumer.h>
  22 #include <linux/suspend.h>
  23 #include <drm/drm_atomic.h>
  24 #include <drm/drm_atomic_helper.h>
  25 #include <drm/drm_fb_helper.h>
  26 #include <drm/drm_gem_framebuffer_helper.h>
  27
  28 #include "tilcdc_drv.h"
  29 #include "tilcdc_regs.h"
  30 #include "tilcdc_tfp410.h"
  31 #include "tilcdc_panel.h"
  32 #include "tilcdc_external.h"
  33
  34 static LIST_HEAD(module_list);
  35
  36 static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };
  37
  38 static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
  39                                                DRM_FORMAT_BGR888,
  40                                                DRM_FORMAT_XBGR8888 };
  41
  42 static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
  43                                               DRM_FORMAT_RGB888,
  44                                               DRM_FORMAT_XRGB8888 };
  45
  46 static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
  47                                              DRM_FORMAT_RGB888,
  48                                              DRM_FORMAT_XRGB8888 };
  49
  50 void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
  51                 const struct tilcdc_module_ops *funcs)
  52 {
  53         mod->name = name;
  54         mod->funcs = funcs;
  55         INIT_LIST_HEAD(&mod->list);
  56         list_add(&mod->list, &module_list);
  57 }
  58
  59 void tilcdc_module_cleanup(struct tilcdc_module *mod)
  60 {
  61         list_del(&mod->list);
  62 }
  63
  64 static struct of_device_id tilcdc_of_match[];
  65
  66 static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
  67                 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
  68 {
  69         return drm_gem_fb_create(dev, file_priv, mode_cmd);
  70 }
  71
  72 static int tilcdc_atomic_check(struct drm_device *dev,
  73                                struct drm_atomic_state *state)
  74 {
  75         int ret;
  76
  77         ret = drm_atomic_helper_check_modeset(dev, state);
  78         if (ret)
  79                 return ret;
  80
  81         ret = drm_atomic_helper_check_planes(dev, state);
  82         if (ret)
  83                 return ret;
  84
  85         /*
  86          * tilcdc ->atomic_check can update ->mode_changed if pixel format
  87          * changes, hence will we check modeset changes again.
  88          */
  89         ret = drm_atomic_helper_check_modeset(dev, state);
  90         if (ret)
  91                 return ret;
  92
  93         return ret;
  94 }
  95
  96 static int tilcdc_commit(struct drm_device *dev,
  97                   struct drm_atomic_state *state,
  98                   bool async)
  99 {
 100         int ret;
 101
 102         ret = drm_atomic_helper_prepare_planes(dev, state);
 103         if (ret)
 104                 return ret;
 105
 106         ret = drm_atomic_helper_swap_state(state, true);
 107         if (ret) {
 108                 drm_atomic_helper_cleanup_planes(dev, state);
 109                 return ret;
 110         }
 111
 112         /*
 113          * Everything below can be run asynchronously without the need to grab
 114          * any modeset locks at all under one condition: It must be guaranteed
 115          * that the asynchronous work has either been cancelled (if the driver
 116          * supports it, which at least requires that the framebuffers get
 117          * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
 118          * before the new state gets committed on the software side with
 119          * drm_atomic_helper_swap_state().
 120          *
 121          * This scheme allows new atomic state updates to be prepared and
 122          * checked in parallel to the asynchronous completion of the previous
 123          * update. Which is important since compositors need to figure out the
 124          * composition of the next frame right after having submitted the
 125          * current layout.
 126          */
 127
 128         drm_atomic_helper_commit_modeset_disables(dev, state);
 129
 130         drm_atomic_helper_commit_planes(dev, state, 0);
 131
 132         drm_atomic_helper_commit_modeset_enables(dev, state);
 133
 134         drm_atomic_helper_wait_for_vblanks(dev, state);
 135
 136         drm_atomic_helper_cleanup_planes(dev, state);
 137
 138         return 0;
 139 }
 140
 141 static const struct drm_mode_config_funcs mode_config_funcs = {
 142         .fb_create = tilcdc_fb_create,
 143         .atomic_check = tilcdc_atomic_check,
 144         .atomic_commit = tilcdc_commit,
 145 };
 146
 147 static void modeset_init(struct drm_device *dev)
 148 {
 149         struct tilcdc_drm_private *priv = dev->dev_private;
 150         struct tilcdc_module *mod;
 151
 152         list_for_each_entry(mod, &module_list, list) {
 153                 DBG("loading module: %s", mod->name);
 154                 mod->funcs->modeset_init(mod, dev);
 155         }
 156
 157         dev->mode_config.min_width = 0;
 158         dev->mode_config.min_height = 0;
 159         dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
 160         dev->mode_config.max_height = 2048;
 161         dev->mode_config.funcs = &mode_config_funcs;
 162 }
 163
 164 #ifdef CONFIG_CPU_FREQ
 165 static int cpufreq_transition(struct notifier_block *nb,
 166                                      unsigned long val, void *data)
 167 {
 168         struct tilcdc_drm_private *priv = container_of(nb,
 169                         struct tilcdc_drm_private, freq_transition);
 170
 171         if (val == CPUFREQ_POSTCHANGE)
 172                 tilcdc_crtc_update_clk(priv->crtc);
 173
 174         return 0;
 175 }
 176 #endif
 177
 178 /*
 179  * DRM operations:
 180  */
 181
 182 static void tilcdc_fini(struct drm_device *dev)
 183 {
 184         struct tilcdc_drm_private *priv = dev->dev_private;
 185
 186         if (priv->crtc)
 187                 tilcdc_crtc_shutdown(priv->crtc);
 188
 189         if (priv->is_registered)
 190                 drm_dev_unregister(dev);
 191
 192         drm_kms_helper_poll_fini(dev);
 193         drm_irq_uninstall(dev);
 194         drm_mode_config_cleanup(dev);
 195         tilcdc_remove_external_device(dev);
 196
 197 #ifdef CONFIG_CPU_FREQ
 198         if (priv->freq_transition.notifier_call)
 199                 cpufreq_unregister_notifier(&priv->freq_transition,
 200                                             CPUFREQ_TRANSITION_NOTIFIER);
 201 #endif
 202
 203         if (priv->clk)
 204                 clk_put(priv->clk);
 205
 206         if (priv->mmio)
 207                 iounmap(priv->mmio);
 208
 209         if (priv->wq) {
 210                 flush_workqueue(priv->wq);
 211                 destroy_workqueue(priv->wq);
 212         }
 213
 214         dev->dev_private = NULL;
 215
 216         pm_runtime_disable(dev->dev);
 217
 218         drm_dev_put(dev);
 219 }
 220
 221 static int tilcdc_init(struct drm_driver *ddrv, struct device *dev)
 222 {
 223         struct drm_device *ddev;
 224         struct platform_device *pdev = to_platform_device(dev);
 225         struct device_node *node = dev->of_node;
 226         struct tilcdc_drm_private *priv;
 227         struct resource *res;
 228         u32 bpp = 0;
 229         int ret;
 230
 231         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 232         if (!priv)
 233                 return -ENOMEM;
 234
 235         ddev = drm_dev_alloc(ddrv, dev);
 236         if (IS_ERR(ddev))
 237                 return PTR_ERR(ddev);
 238
 239         ddev->dev_private = priv;
 240         platform_set_drvdata(pdev, ddev);
 241         drm_mode_config_init(ddev);
 242
 243         priv->is_componentized =
 244                 tilcdc_get_external_components(dev, NULL) > 0;
 245
 246         priv->wq = alloc_ordered_workqueue("tilcdc", 0);
 247         if (!priv->wq) {
 248                 ret = -ENOMEM;
 249                 goto init_failed;
 250         }
 251
 252         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 253         if (!res) {
 254                 dev_err(dev, "failed to get memory resource\n");
 255                 ret = -EINVAL;
 256                 goto init_failed;
 257         }
 258
 259         priv->mmio = ioremap_nocache(res->start, resource_size(res));
 260         if (!priv->mmio) {
 261                 dev_err(dev, "failed to ioremap\n");
 262                 ret = -ENOMEM;
 263                 goto init_failed;
 264         }
 265
 266         priv->clk = clk_get(dev, "fck");
 267         if (IS_ERR(priv->clk)) {
 268                 dev_err(dev, "failed to get functional clock\n");
 269                 ret = -ENODEV;
 270                 goto init_failed;
 271         }
 272
 273 #ifdef CONFIG_CPU_FREQ
 274         priv->freq_transition.notifier_call = cpufreq_transition;
 275         ret = cpufreq_register_notifier(&priv->freq_transition,
 276                         CPUFREQ_TRANSITION_NOTIFIER);
 277         if (ret) {
 278                 dev_err(dev, "failed to register cpufreq notifier\n");
 279                 priv->freq_transition.notifier_call = NULL;
 280                 goto init_failed;
 281         }
 282 #endif
 283
 284         if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
 285                 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
 286
 287         DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
 288
 289         if (of_property_read_u32(node, "max-width", &priv->max_width))
 290                 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
 291
 292         DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
 293
 294         if (of_property_read_u32(node, "max-pixelclock",
 295                                         &priv->max_pixelclock))
 296                 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
 297
 298         DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
 299
 300         pm_runtime_enable(dev);
 301
 302         /* Determine LCD IP Version */
 303         pm_runtime_get_sync(dev);
 304         switch (tilcdc_read(ddev, LCDC_PID_REG)) {
 305         case 0x4c100102:
 306                 priv->rev = 1;
 307                 break;
 308         case 0x4f200800:
 309         case 0x4f201000:
 310                 priv->rev = 2;
 311                 break;
 312         default:
 313                 dev_warn(dev, "Unknown PID Reg value 0x%08x, "
 314                         "defaulting to LCD revision 1\n",
 315                         tilcdc_read(ddev, LCDC_PID_REG));
 316                 priv->rev = 1;
 317                 break;
 318         }
 319
 320         pm_runtime_put_sync(dev);
 321
 322         if (priv->rev == 1) {
 323                 DBG("Revision 1 LCDC supports only RGB565 format");
 324                 priv->pixelformats = tilcdc_rev1_formats;
 325                 priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
 326                 bpp = 16;
 327         } else {
 328                 const char *str = "\0";
 329
 330                 of_property_read_string(node, "blue-and-red-wiring", &str);
 331                 if (0 == strcmp(str, "crossed")) {
 332                         DBG("Configured for crossed blue and red wires");
 333                         priv->pixelformats = tilcdc_crossed_formats;
 334                         priv->num_pixelformats =
 335                                 ARRAY_SIZE(tilcdc_crossed_formats);
 336                         bpp = 32; /* Choose bpp with RGB support for fbdef */
 337                 } else if (0 == strcmp(str, "straight")) {
 338                         DBG("Configured for straight blue and red wires");
 339                         priv->pixelformats = tilcdc_straight_formats;
 340                         priv->num_pixelformats =
 341                                 ARRAY_SIZE(tilcdc_straight_formats);
 342                         bpp = 16; /* Choose bpp with RGB support for fbdef */
 343                 } else {
 344                         DBG("Blue and red wiring '%s' unknown, use legacy mode",
 345                             str);
 346                         priv->pixelformats = tilcdc_legacy_formats;
 347                         priv->num_pixelformats =
 348                                 ARRAY_SIZE(tilcdc_legacy_formats);
 349                         bpp = 16; /* This is just a guess */
 350                 }
 351         }
 352
 353         ret = tilcdc_crtc_create(ddev);
 354         if (ret < 0) {
 355                 dev_err(dev, "failed to create crtc\n");
 356                 goto init_failed;
 357         }
 358         modeset_init(ddev);
 359
 360         if (priv->is_componentized) {
 361                 ret = component_bind_all(dev, ddev);
 362                 if (ret < 0)
 363                         goto init_failed;
 364
 365                 ret = tilcdc_add_component_encoder(ddev);
 366                 if (ret < 0)
 367                         goto init_failed;
 368         } else {
 369                 ret = tilcdc_attach_external_device(ddev);
 370                 if (ret)
 371                         goto init_failed;
 372         }
 373
 374         if (!priv->external_connector &&
 375             ((priv->num_encoders == 0) || (priv->num_connectors == 0))) {
 376                 dev_err(dev, "no encoders/connectors found\n");
 377                 ret = -EPROBE_DEFER;
 378                 goto init_failed;
 379         }
 380
 381         ret = drm_vblank_init(ddev, 1);
 382         if (ret < 0) {
 383                 dev_err(dev, "failed to initialize vblank\n");
 384                 goto init_failed;
 385         }
 386
 387         ret = drm_irq_install(ddev, platform_get_irq(pdev, 0));
 388         if (ret < 0) {
 389                 dev_err(dev, "failed to install IRQ handler\n");
 390                 goto init_failed;
 391         }
 392
 393         drm_mode_config_reset(ddev);
 394
 395         drm_kms_helper_poll_init(ddev);
 396
 397         ret = drm_dev_register(ddev, 0);
 398         if (ret)
 399                 goto init_failed;
 400
 401         drm_fbdev_generic_setup(ddev, bpp);
 402
 403         priv->is_registered = true;
 404         return 0;
 405
 406 init_failed:
 407         tilcdc_fini(ddev);
 408
 409         return ret;
 410 }
 411
 412 static irqreturn_t tilcdc_irq(int irq, void *arg)
 413 {
 414         struct drm_device *dev = arg;
 415         struct tilcdc_drm_private *priv = dev->dev_private;
 416         return tilcdc_crtc_irq(priv->crtc);
 417 }
 418
 419 #if defined(CONFIG_DEBUG_FS)
 420 static const struct {
 421         const char *name;
 422         uint8_t  rev;
 423         uint8_t  save;
 424         uint32_t reg;
 425 } registers[] =         {
 426 #define REG(rev, save, reg) { #reg, rev, save, reg }
 427                 /* exists in revision 1: */
 428                 REG(1, false, LCDC_PID_REG),
 429                 REG(1, true,  LCDC_CTRL_REG),
 430                 REG(1, false, LCDC_STAT_REG),
 431                 REG(1, true,  LCDC_RASTER_CTRL_REG),
 432                 REG(1, true,  LCDC_RASTER_TIMING_0_REG),
 433                 REG(1, true,  LCDC_RASTER_TIMING_1_REG),
 434                 REG(1, true,  LCDC_RASTER_TIMING_2_REG),
 435                 REG(1, true,  LCDC_DMA_CTRL_REG),
 436                 REG(1, true,  LCDC_DMA_FB_BASE_ADDR_0_REG),
 437                 REG(1, true,  LCDC_DMA_FB_CEILING_ADDR_0_REG),
 438                 REG(1, true,  LCDC_DMA_FB_BASE_ADDR_1_REG),
 439                 REG(1, true,  LCDC_DMA_FB_CEILING_ADDR_1_REG),
 440                 /* new in revision 2: */
 441                 REG(2, false, LCDC_RAW_STAT_REG),
 442                 REG(2, false, LCDC_MASKED_STAT_REG),
 443                 REG(2, true, LCDC_INT_ENABLE_SET_REG),
 444                 REG(2, false, LCDC_INT_ENABLE_CLR_REG),
 445                 REG(2, false, LCDC_END_OF_INT_IND_REG),
 446                 REG(2, true,  LCDC_CLK_ENABLE_REG),
 447 #undef REG
 448 };
 449
 450 #endif
 451
 452 #ifdef CONFIG_DEBUG_FS
 453 static int tilcdc_regs_show(struct seq_file *m, void *arg)
 454 {
 455         struct drm_info_node *node = (struct drm_info_node *) m->private;
 456         struct drm_device *dev = node->minor->dev;
 457         struct tilcdc_drm_private *priv = dev->dev_private;
 458         unsigned i;
 459
 460         pm_runtime_get_sync(dev->dev);
 461
 462         seq_printf(m, "revision: %d\n", priv->rev);
 463
 464         for (i = 0; i < ARRAY_SIZE(registers); i++)
 465                 if (priv->rev >= registers[i].rev)
 466                         seq_printf(m, "%s:\t %08x\n", registers[i].name,
 467                                         tilcdc_read(dev, registers[i].reg));
 468
 469         pm_runtime_put_sync(dev->dev);
 470
 471         return 0;
 472 }
 473
 474 static int tilcdc_mm_show(struct seq_file *m, void *arg)
 475 {
 476         struct drm_info_node *node = (struct drm_info_node *) m->private;
 477         struct drm_device *dev = node->minor->dev;
 478         struct drm_printer p = drm_seq_file_printer(m);
 479         drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p);
 480         return 0;
 481 }
 482
 483 static struct drm_info_list tilcdc_debugfs_list[] = {
 484                 { "regs", tilcdc_regs_show, 0 },
 485                 { "mm",   tilcdc_mm_show,   0 },
 486 };
 487
 488 static int tilcdc_debugfs_init(struct drm_minor *minor)
 489 {
 490         struct drm_device *dev = minor->dev;
 491         struct tilcdc_module *mod;
 492         int ret;
 493
 494         ret = drm_debugfs_create_files(tilcdc_debugfs_list,
 495                         ARRAY_SIZE(tilcdc_debugfs_list),
 496                         minor->debugfs_root, minor);
 497
 498         list_for_each_entry(mod, &module_list, list)
 499                 if (mod->funcs->debugfs_init)
 500                         mod->funcs->debugfs_init(mod, minor);
 501
 502         if (ret) {
 503                 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
 504                 return ret;
 505         }
 506
 507         return ret;
 508 }
 509 #endif
 510
 511 DEFINE_DRM_GEM_CMA_FOPS(fops);
 512
 513 static struct drm_driver tilcdc_driver = {
 514         .driver_features    = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET |
 515                                DRIVER_PRIME | DRIVER_ATOMIC),
 516         .irq_handler        = tilcdc_irq,
 517         .gem_free_object_unlocked = drm_gem_cma_free_object,
 518         .gem_print_info     = drm_gem_cma_print_info,
 519         .gem_vm_ops         = &drm_gem_cma_vm_ops,
 520         .dumb_create        = drm_gem_cma_dumb_create,
 521
 522         .prime_handle_to_fd     = drm_gem_prime_handle_to_fd,
 523         .prime_fd_to_handle     = drm_gem_prime_fd_to_handle,
 524         .gem_prime_import       = drm_gem_prime_import,
 525         .gem_prime_export       = drm_gem_prime_export,
 526         .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
 527         .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
 528         .gem_prime_vmap         = drm_gem_cma_prime_vmap,
 529         .gem_prime_vunmap       = drm_gem_cma_prime_vunmap,
 530         .gem_prime_mmap         = drm_gem_cma_prime_mmap,
 531 #ifdef CONFIG_DEBUG_FS
 532         .debugfs_init       = tilcdc_debugfs_init,
 533 #endif
 534         .fops               = &fops,
 535         .name               = "tilcdc",
 536         .desc               = "TI LCD Controller DRM",
 537         .date               = "20121205",
 538         .major              = 1,
 539         .minor              = 0,
 540 };
 541
 542 /*
 543  * Power management:
 544  */
 545
 546 #ifdef CONFIG_PM_SLEEP
 547 static int tilcdc_pm_suspend(struct device *dev)
 548 {
 549         struct drm_device *ddev = dev_get_drvdata(dev);
 550         int ret = 0;
 551
 552         ret = drm_mode_config_helper_suspend(ddev);
 553
 554         /* Select sleep pin state */
 555         pinctrl_pm_select_sleep_state(dev);
 556
 557         return ret;
 558 }
 559
 560 static int tilcdc_pm_resume(struct device *dev)
 561 {
 562         struct drm_device *ddev = dev_get_drvdata(dev);
 563
 564         /* Select default pin state */
 565         pinctrl_pm_select_default_state(dev);
 566         return  drm_mode_config_helper_resume(ddev);
 567 }
 568 #endif
 569
 570 static const struct dev_pm_ops tilcdc_pm_ops = {
 571         SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
 572 };
 573
 574 /*
 575  * Platform driver:
 576  */
 577 static int tilcdc_bind(struct device *dev)
 578 {
 579         return tilcdc_init(&tilcdc_driver, dev);
 580 }
 581
 582 static void tilcdc_unbind(struct device *dev)
 583 {
 584         struct drm_device *ddev = dev_get_drvdata(dev);
 585
 586         /* Check if a subcomponent has already triggered the unloading. */
 587         if (!ddev->dev_private)
 588                 return;
 589
 590         tilcdc_fini(dev_get_drvdata(dev));
 591 }
 592
 593 static const struct component_master_ops tilcdc_comp_ops = {
 594         .bind = tilcdc_bind,
 595         .unbind = tilcdc_unbind,
 596 };
 597
 598 static int tilcdc_pdev_probe(struct platform_device *pdev)
 599 {
 600         struct component_match *match = NULL;
 601         int ret;
 602
 603         /* bail out early if no DT data: */
 604         if (!pdev->dev.of_node) {
 605                 dev_err(&pdev->dev, "device-tree data is missing\n");
 606                 return -ENXIO;
 607         }
 608
 609         ret = tilcdc_get_external_components(&pdev->dev, &match);
 610         if (ret < 0)
 611                 return ret;
 612         else if (ret == 0)
 613                 return tilcdc_init(&tilcdc_driver, &pdev->dev);
 614         else
 615                 return component_master_add_with_match(&pdev->dev,
 616                                                        &tilcdc_comp_ops,
 617                                                        match);
 618 }
 619
 620 static int tilcdc_pdev_remove(struct platform_device *pdev)
 621 {
 622         int ret;
 623
 624         ret = tilcdc_get_external_components(&pdev->dev, NULL);
 625         if (ret < 0)
 626                 return ret;
 627         else if (ret == 0)
 628                 tilcdc_fini(platform_get_drvdata(pdev));
 629         else
 630                 component_master_del(&pdev->dev, &tilcdc_comp_ops);
 631
 632         return 0;
 633 }
 634
 635 static struct of_device_id tilcdc_of_match[] = {
 636                 { .compatible = "ti,am33xx-tilcdc", },
 637                 { .compatible = "ti,da850-tilcdc", },
 638                 { },
 639 };
 640 MODULE_DEVICE_TABLE(of, tilcdc_of_match);
 641
 642 static struct platform_driver tilcdc_platform_driver = {
 643         .probe      = tilcdc_pdev_probe,
 644         .remove     = tilcdc_pdev_remove,
 645         .driver     = {
 646                 .name   = "tilcdc",
 647                 .pm     = &tilcdc_pm_ops,
 648                 .of_match_table = tilcdc_of_match,
 649         },
 650 };
 651
 652 static int __init tilcdc_drm_init(void)
 653 {
 654         DBG("init");
 655         tilcdc_tfp410_init();
 656         tilcdc_panel_init();
 657         return platform_driver_register(&tilcdc_platform_driver);
 658 }
 659
 660 static void __exit tilcdc_drm_fini(void)
 661 {
 662         DBG("fini");
 663         platform_driver_unregister(&tilcdc_platform_driver);
 664         tilcdc_panel_fini();
 665         tilcdc_tfp410_fini();
 666 }
 667
 668 module_init(tilcdc_drm_init);
 669 module_exit(tilcdc_drm_fini);
 670
 671 MODULE_AUTHOR("Rob Clark <[email protected]");
 672 MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
 673 MODULE_LICENSE("GPL");