drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/string_helpers.h>
  27 #include <linux/uaccess.h>
  28
  29 #include "dc.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm.h"
  32 #include "amdgpu_dm_debugfs.h"
  33 #include "dm_helpers.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "resource.h"
  36 #include "dsc.h"
  37 #include "link_hwss.h"
  38 #include "dc/dc_dmub_srv.h"
  39 #include "link/protocols/link_dp_capability.h"
  40
  41 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
  42 #include "amdgpu_dm_psr.h"
  43 #endif
  44
  45 struct dmub_debugfs_trace_header {
  46         uint32_t entry_count;
  47         uint32_t reserved[3];
  48 };
  49
  50 struct dmub_debugfs_trace_entry {
  51         uint32_t trace_code;
  52         uint32_t tick_count;
  53         uint32_t param0;
  54         uint32_t param1;
  55 };
  56
  57 static const char *const mst_progress_status[] = {
  58         "probe",
  59         "remote_edid",
  60         "allocate_new_payload",
  61         "clear_allocated_payload",
  62 };
  63
  64 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
  65  *
  66  * Function takes in attributes passed to debugfs write entry
  67  * and writes into param array.
  68  * The user passes max_param_num to identify maximum number of
  69  * parameters that could be parsed.
  70  *
  71  */
  72 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
  73                                           long *param, const char __user *buf,
  74                                           int max_param_num,
  75                                           uint8_t *param_nums)
  76 {
  77         char *wr_buf_ptr = NULL;
  78         uint32_t wr_buf_count = 0;
  79         int r;
  80         char *sub_str = NULL;
  81         const char delimiter[3] = {' ', '\n', '\0'};
  82         uint8_t param_index = 0;
  83
  84         *param_nums = 0;
  85
  86         wr_buf_ptr = wr_buf;
  87
  88         /* r is bytes not be copied */
  89         if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) {
  90                 DRM_DEBUG_DRIVER("user data could not be read successfully\n");
  91                 return -EFAULT;
  92         }
  93
  94         /* check number of parameters. isspace could not differ space and \n */
  95         while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
  96                 /* skip space*/
  97                 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
  98                         wr_buf_ptr++;
  99                         wr_buf_count++;
 100                         }
 101
 102                 if (wr_buf_count == wr_buf_size)
 103                         break;
 104
 105                 /* skip non-space*/
 106                 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
 107                         wr_buf_ptr++;
 108                         wr_buf_count++;
 109                 }
 110
 111                 (*param_nums)++;
 112
 113                 if (wr_buf_count == wr_buf_size)
 114                         break;
 115         }
 116
 117         if (*param_nums > max_param_num)
 118                 *param_nums = max_param_num;
 119
 120         wr_buf_ptr = wr_buf; /* reset buf pointer */
 121         wr_buf_count = 0; /* number of char already checked */
 122
 123         while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
 124                 wr_buf_ptr++;
 125                 wr_buf_count++;
 126         }
 127
 128         while (param_index < *param_nums) {
 129                 /* after strsep, wr_buf_ptr will be moved to after space */
 130                 sub_str = strsep(&wr_buf_ptr, delimiter);
 131
 132                 r = kstrtol(sub_str, 16, &(param[param_index]));
 133
 134                 if (r)
 135                         DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
 136
 137                 param_index++;
 138         }
 139
 140         return 0;
 141 }
 142
 143 /* function description
 144  * get/ set DP configuration: lane_count, link_rate, spread_spectrum
 145  *
 146  * valid lane count value: 1, 2, 4
 147  * valid link rate value:
 148  * 06h = 1.62Gbps per lane
 149  * 0Ah = 2.7Gbps per lane
 150  * 0Ch = 3.24Gbps per lane
 151  * 14h = 5.4Gbps per lane
 152  * 1Eh = 8.1Gbps per lane
 153  *
 154  * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
 155  *
 156  * --- to get dp configuration
 157  *
 158  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 159  *
 160  * It will list current, verified, reported, preferred dp configuration.
 161  * current -- for current video mode
 162  * verified --- maximum configuration which pass link training
 163  * reported --- DP rx report caps (DPCD register offset 0, 1 2)
 164  * preferred --- user force settings
 165  *
 166  * --- set (or force) dp configuration
 167  *
 168  * echo <lane_count>  <link_rate> > link_settings
 169  *
 170  * for example, to force to  2 lane, 2.7GHz,
 171  * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings
 172  *
 173  * spread_spectrum could not be changed dynamically.
 174  *
 175  * in case invalid lane count, link rate are force, no hw programming will be
 176  * done. please check link settings after force operation to see if HW get
 177  * programming.
 178  *
 179  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 180  *
 181  * check current and preferred settings.
 182  *
 183  */
 184 static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
 185                                  size_t size, loff_t *pos)
 186 {
 187         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 188         struct dc_link *link = connector->dc_link;
 189         char *rd_buf = NULL;
 190         char *rd_buf_ptr = NULL;
 191         const uint32_t rd_buf_size = 100;
 192         uint32_t result = 0;
 193         uint8_t str_len = 0;
 194         int r;
 195
 196         if (*pos & 3 || size & 3)
 197                 return -EINVAL;
 198
 199         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 200         if (!rd_buf)
 201                 return 0;
 202
 203         rd_buf_ptr = rd_buf;
 204
 205         str_len = strlen("Current:  %d  0x%x  %d  ");
 206         snprintf(rd_buf_ptr, str_len, "Current:  %d  0x%x  %d  ",
 207                         link->cur_link_settings.lane_count,
 208                         link->cur_link_settings.link_rate,
 209                         link->cur_link_settings.link_spread);
 210         rd_buf_ptr += str_len;
 211
 212         str_len = strlen("Verified:  %d  0x%x  %d  ");
 213         snprintf(rd_buf_ptr, str_len, "Verified:  %d  0x%x  %d  ",
 214                         link->verified_link_cap.lane_count,
 215                         link->verified_link_cap.link_rate,
 216                         link->verified_link_cap.link_spread);
 217         rd_buf_ptr += str_len;
 218
 219         str_len = strlen("Reported:  %d  0x%x  %d  ");
 220         snprintf(rd_buf_ptr, str_len, "Reported:  %d  0x%x  %d  ",
 221                         link->reported_link_cap.lane_count,
 222                         link->reported_link_cap.link_rate,
 223                         link->reported_link_cap.link_spread);
 224         rd_buf_ptr += str_len;
 225
 226         str_len = strlen("Preferred:  %d  0x%x  %d  ");
 227         snprintf(rd_buf_ptr, str_len, "Preferred:  %d  0x%x  %d\n",
 228                         link->preferred_link_setting.lane_count,
 229                         link->preferred_link_setting.link_rate,
 230                         link->preferred_link_setting.link_spread);
 231
 232         while (size) {
 233                 if (*pos >= rd_buf_size)
 234                         break;
 235
 236                 r = put_user(*(rd_buf + result), buf);
 237                 if (r) {
 238                         kfree(rd_buf);
 239                         return r; /* r = -EFAULT */
 240                 }
 241
 242                 buf += 1;
 243                 size -= 1;
 244                 *pos += 1;
 245                 result += 1;
 246         }
 247
 248         kfree(rd_buf);
 249         return result;
 250 }
 251
 252 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
 253                                  size_t size, loff_t *pos)
 254 {
 255         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 256         struct dc_link *link = connector->dc_link;
 257         struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
 258         struct dc *dc = (struct dc *)link->dc;
 259         struct dc_link_settings prefer_link_settings;
 260         char *wr_buf = NULL;
 261         const uint32_t wr_buf_size = 40;
 262         /* 0: lane_count; 1: link_rate */
 263         int max_param_num = 2;
 264         uint8_t param_nums = 0;
 265         long param[2];
 266         bool valid_input = true;
 267
 268         if (size == 0)
 269                 return -EINVAL;
 270
 271         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 272         if (!wr_buf)
 273                 return -ENOSPC;
 274
 275         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 276                                            (long *)param, buf,
 277                                            max_param_num,
 278                                            &param_nums)) {
 279                 kfree(wr_buf);
 280                 return -EINVAL;
 281         }
 282
 283         if (param_nums <= 0) {
 284                 kfree(wr_buf);
 285                 DRM_DEBUG_DRIVER("user data not be read\n");
 286                 return -EINVAL;
 287         }
 288
 289         switch (param[0]) {
 290         case LANE_COUNT_ONE:
 291         case LANE_COUNT_TWO:
 292         case LANE_COUNT_FOUR:
 293                 break;
 294         default:
 295                 valid_input = false;
 296                 break;
 297         }
 298
 299         switch (param[1]) {
 300         case LINK_RATE_LOW:
 301         case LINK_RATE_HIGH:
 302         case LINK_RATE_RBR2:
 303         case LINK_RATE_HIGH2:
 304         case LINK_RATE_HIGH3:
 305         case LINK_RATE_UHBR10:
 306         case LINK_RATE_UHBR13_5:
 307         case LINK_RATE_UHBR20:
 308                 break;
 309         default:
 310                 valid_input = false;
 311                 break;
 312         }
 313
 314         if (!valid_input) {
 315                 kfree(wr_buf);
 316                 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
 317                 mutex_lock(&adev->dm.dc_lock);
 318                 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
 319                 mutex_unlock(&adev->dm.dc_lock);
 320                 return size;
 321         }
 322
 323         /* save user force lane_count, link_rate to preferred settings
 324          * spread spectrum will not be changed
 325          */
 326         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
 327         prefer_link_settings.use_link_rate_set = false;
 328         prefer_link_settings.lane_count = param[0];
 329         prefer_link_settings.link_rate = param[1];
 330
 331         mutex_lock(&adev->dm.dc_lock);
 332         dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false);
 333         mutex_unlock(&adev->dm.dc_lock);
 334
 335         kfree(wr_buf);
 336         return size;
 337 }
 338
 339 /* function: get current DP PHY settings: voltage swing, pre-emphasis,
 340  * post-cursor2 (defined by VESA DP specification)
 341  *
 342  * valid values
 343  * voltage swing: 0,1,2,3
 344  * pre-emphasis : 0,1,2,3
 345  * post cursor2 : 0,1,2,3
 346  *
 347  *
 348  * how to use this debugfs
 349  *
 350  * debugfs is located at /sys/kernel/debug/dri/0/DP-x
 351  *
 352  * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display
 353  *
 354  * To figure out which DP-x is the display for DP to be check,
 355  * cd DP-x
 356  * ls -ll
 357  * There should be debugfs file, like link_settings, phy_settings.
 358  * cat link_settings
 359  * from lane_count, link_rate to figure which DP-x is for display to be worked
 360  * on
 361  *
 362  * To get current DP PHY settings,
 363  * cat phy_settings
 364  *
 365  * To change DP PHY settings,
 366  * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings
 367  * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to
 368  * 0,
 369  * echo 2 3 0 > phy_settings
 370  *
 371  * To check if change be applied, get current phy settings by
 372  * cat phy_settings
 373  *
 374  * In case invalid values are set by user, like
 375  * echo 1 4 0 > phy_settings
 376  *
 377  * HW will NOT be programmed by these settings.
 378  * cat phy_settings will show the previous valid settings.
 379  */
 380 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
 381                                  size_t size, loff_t *pos)
 382 {
 383         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 384         struct dc_link *link = connector->dc_link;
 385         char *rd_buf = NULL;
 386         const uint32_t rd_buf_size = 20;
 387         uint32_t result = 0;
 388         int r;
 389
 390         if (*pos & 3 || size & 3)
 391                 return -EINVAL;
 392
 393         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 394         if (!rd_buf)
 395                 return -EINVAL;
 396
 397         snprintf(rd_buf, rd_buf_size, "  %d  %d  %d\n",
 398                         link->cur_lane_setting[0].VOLTAGE_SWING,
 399                         link->cur_lane_setting[0].PRE_EMPHASIS,
 400                         link->cur_lane_setting[0].POST_CURSOR2);
 401
 402         while (size) {
 403                 if (*pos >= rd_buf_size)
 404                         break;
 405
 406                 r = put_user((*(rd_buf + result)), buf);
 407                 if (r) {
 408                         kfree(rd_buf);
 409                         return r; /* r = -EFAULT */
 410                 }
 411
 412                 buf += 1;
 413                 size -= 1;
 414                 *pos += 1;
 415                 result += 1;
 416         }
 417
 418         kfree(rd_buf);
 419         return result;
 420 }
 421
 422 static int dp_lttpr_status_show(struct seq_file *m, void *unused)
 423 {
 424         struct drm_connector *connector = m->private;
 425         struct amdgpu_dm_connector *aconnector =
 426                 to_amdgpu_dm_connector(connector);
 427         struct dc_lttpr_caps caps = aconnector->dc_link->dpcd_caps.lttpr_caps;
 428
 429         if (connector->status != connector_status_connected)
 430                 return -ENODEV;
 431
 432         seq_printf(m, "phy repeater count: %u (raw: 0x%x)\n",
 433                    dp_parse_lttpr_repeater_count(caps.phy_repeater_cnt),
 434                    caps.phy_repeater_cnt);
 435
 436         seq_puts(m, "phy repeater mode: ");
 437
 438         switch (caps.mode) {
 439         case DP_PHY_REPEATER_MODE_TRANSPARENT:
 440                 seq_puts(m, "transparent");
 441                 break;
 442         case DP_PHY_REPEATER_MODE_NON_TRANSPARENT:
 443                 seq_puts(m, "non-transparent");
 444                 break;
 445         case 0x00:
 446                 seq_puts(m, "non lttpr");
 447                 break;
 448         default:
 449                 seq_printf(m, "read error (raw: 0x%x)", caps.mode);
 450                 break;
 451         }
 452
 453         seq_puts(m, "\n");
 454         return 0;
 455 }
 456
 457 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
 458                                  size_t size, loff_t *pos)
 459 {
 460         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 461         struct dc_link *link = connector->dc_link;
 462         struct dc *dc = (struct dc *)link->dc;
 463         char *wr_buf = NULL;
 464         uint32_t wr_buf_size = 40;
 465         long param[3];
 466         bool use_prefer_link_setting;
 467         struct link_training_settings link_lane_settings;
 468         int max_param_num = 3;
 469         uint8_t param_nums = 0;
 470         int r = 0;
 471
 472
 473         if (size == 0)
 474                 return -EINVAL;
 475
 476         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 477         if (!wr_buf)
 478                 return -ENOSPC;
 479
 480         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 481                                            (long *)param, buf,
 482                                            max_param_num,
 483                                            &param_nums)) {
 484                 kfree(wr_buf);
 485                 return -EINVAL;
 486         }
 487
 488         if (param_nums <= 0) {
 489                 kfree(wr_buf);
 490                 DRM_DEBUG_DRIVER("user data not be read\n");
 491                 return -EINVAL;
 492         }
 493
 494         if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
 495                         (param[1] > PRE_EMPHASIS_MAX_LEVEL) ||
 496                         (param[2] > POST_CURSOR2_MAX_LEVEL)) {
 497                 kfree(wr_buf);
 498                 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
 499                 return size;
 500         }
 501
 502         /* get link settings: lane count, link rate */
 503         use_prefer_link_setting =
 504                 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) &&
 505                 (link->test_pattern_enabled));
 506
 507         memset(&link_lane_settings, 0, sizeof(link_lane_settings));
 508
 509         if (use_prefer_link_setting) {
 510                 link_lane_settings.link_settings.lane_count =
 511                                 link->preferred_link_setting.lane_count;
 512                 link_lane_settings.link_settings.link_rate =
 513                                 link->preferred_link_setting.link_rate;
 514                 link_lane_settings.link_settings.link_spread =
 515                                 link->preferred_link_setting.link_spread;
 516         } else {
 517                 link_lane_settings.link_settings.lane_count =
 518                                 link->cur_link_settings.lane_count;
 519                 link_lane_settings.link_settings.link_rate =
 520                                 link->cur_link_settings.link_rate;
 521                 link_lane_settings.link_settings.link_spread =
 522                                 link->cur_link_settings.link_spread;
 523         }
 524
 525         /* apply phy settings from user */
 526         for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
 527                 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING =
 528                                 (enum dc_voltage_swing) (param[0]);
 529                 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS =
 530                                 (enum dc_pre_emphasis) (param[1]);
 531                 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 =
 532                                 (enum dc_post_cursor2) (param[2]);
 533         }
 534
 535         /* program ASIC registers and DPCD registers */
 536         dc_link_set_drive_settings(dc, &link_lane_settings, link);
 537
 538         kfree(wr_buf);
 539         return size;
 540 }
 541
 542 /* function description
 543  *
 544  * set PHY layer or Link layer test pattern
 545  * PHY test pattern is used for PHY SI check.
 546  * Link layer test will not affect PHY SI.
 547  *
 548  * Reset Test Pattern:
 549  * 0 = DP_TEST_PATTERN_VIDEO_MODE
 550  *
 551  * PHY test pattern supported:
 552  * 1 = DP_TEST_PATTERN_D102
 553  * 2 = DP_TEST_PATTERN_SYMBOL_ERROR
 554  * 3 = DP_TEST_PATTERN_PRBS7
 555  * 4 = DP_TEST_PATTERN_80BIT_CUSTOM
 556  * 5 = DP_TEST_PATTERN_CP2520_1
 557  * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
 558  * 7 = DP_TEST_PATTERN_CP2520_3
 559  *
 560  * DP PHY Link Training Patterns
 561  * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1
 562  * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2
 563  * a = DP_TEST_PATTERN_TRAINING_PATTERN3
 564  * b = DP_TEST_PATTERN_TRAINING_PATTERN4
 565  *
 566  * DP Link Layer Test pattern
 567  * c = DP_TEST_PATTERN_COLOR_SQUARES
 568  * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA
 569  * e = DP_TEST_PATTERN_VERTICAL_BARS
 570  * f = DP_TEST_PATTERN_HORIZONTAL_BARS
 571  * 10= DP_TEST_PATTERN_COLOR_RAMP
 572  *
 573  * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x
 574  *
 575  * --- set test pattern
 576  * echo <test pattern #> > test_pattern
 577  *
 578  * If test pattern # is not supported, NO HW programming will be done.
 579  * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
 580  * for the user pattern. input 10 bytes data are separated by space
 581  *
 582  * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern
 583  *
 584  * --- reset test pattern
 585  * echo 0 > test_pattern
 586  *
 587  * --- HPD detection is disabled when set PHY test pattern
 588  *
 589  * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC
 590  * is disable. User could unplug DP display from DP connected and plug scope to
 591  * check test pattern PHY SI.
 592  * If there is need unplug scope and plug DP display back, do steps below:
 593  * echo 0 > phy_test_pattern
 594  * unplug scope
 595  * plug DP display.
 596  *
 597  * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw
 598  * driver could detect "unplug scope" and "plug DP display"
 599  */
 600 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
 601                                  size_t size, loff_t *pos)
 602 {
 603         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 604         struct dc_link *link = connector->dc_link;
 605         char *wr_buf = NULL;
 606         uint32_t wr_buf_size = 100;
 607         long param[11] = {0x0};
 608         int max_param_num = 11;
 609         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 610         bool disable_hpd = false;
 611         bool valid_test_pattern = false;
 612         uint8_t param_nums = 0;
 613         /* init with default 80bit custom pattern */
 614         uint8_t custom_pattern[10] = {
 615                         0x1f, 0x7c, 0xf0, 0xc1, 0x07,
 616                         0x1f, 0x7c, 0xf0, 0xc1, 0x07
 617                         };
 618         struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN,
 619                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 620         struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,
 621                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 622         struct link_training_settings link_training_settings;
 623         int i;
 624
 625         if (size == 0)
 626                 return -EINVAL;
 627
 628         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 629         if (!wr_buf)
 630                 return -ENOSPC;
 631
 632         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 633                                            (long *)param, buf,
 634                                            max_param_num,
 635                                            &param_nums)) {
 636                 kfree(wr_buf);
 637                 return -EINVAL;
 638         }
 639
 640         if (param_nums <= 0) {
 641                 kfree(wr_buf);
 642                 DRM_DEBUG_DRIVER("user data not be read\n");
 643                 return -EINVAL;
 644         }
 645
 646
 647         test_pattern = param[0];
 648
 649         switch (test_pattern) {
 650         case DP_TEST_PATTERN_VIDEO_MODE:
 651         case DP_TEST_PATTERN_COLOR_SQUARES:
 652         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
 653         case DP_TEST_PATTERN_VERTICAL_BARS:
 654         case DP_TEST_PATTERN_HORIZONTAL_BARS:
 655         case DP_TEST_PATTERN_COLOR_RAMP:
 656                 valid_test_pattern = true;
 657                 break;
 658
 659         case DP_TEST_PATTERN_D102:
 660         case DP_TEST_PATTERN_SYMBOL_ERROR:
 661         case DP_TEST_PATTERN_PRBS7:
 662         case DP_TEST_PATTERN_80BIT_CUSTOM:
 663         case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
 664         case DP_TEST_PATTERN_TRAINING_PATTERN4:
 665                 disable_hpd = true;
 666                 valid_test_pattern = true;
 667                 break;
 668
 669         default:
 670                 valid_test_pattern = false;
 671                 test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 672                 break;
 673         }
 674
 675         if (!valid_test_pattern) {
 676                 kfree(wr_buf);
 677                 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
 678                 return size;
 679         }
 680
 681         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
 682                 for (i = 0; i < 10; i++) {
 683                         if ((uint8_t) param[i + 1] != 0x0)
 684                                 break;
 685                 }
 686
 687                 if (i < 10) {
 688                         /* not use default value */
 689                         for (i = 0; i < 10; i++)
 690                                 custom_pattern[i] = (uint8_t) param[i + 1];
 691                 }
 692         }
 693
 694         /* Usage: set DP physical test pattern using debugfs with normal DP
 695          * panel. Then plug out DP panel and connect a scope to measure
 696          * For normal video mode and test pattern generated from CRCT,
 697          * they are visibile to user. So do not disable HPD.
 698          * Video Mode is also set to clear the test pattern, so enable HPD
 699          * because it might have been disabled after a test pattern was set.
 700          * AUX depends on HPD * sequence dependent, do not move!
 701          */
 702         if (!disable_hpd)
 703                 dc_link_enable_hpd(link);
 704
 705         prefer_link_settings.lane_count = link->verified_link_cap.lane_count;
 706         prefer_link_settings.link_rate = link->verified_link_cap.link_rate;
 707         prefer_link_settings.link_spread = link->verified_link_cap.link_spread;
 708
 709         cur_link_settings.lane_count = link->cur_link_settings.lane_count;
 710         cur_link_settings.link_rate = link->cur_link_settings.link_rate;
 711         cur_link_settings.link_spread = link->cur_link_settings.link_spread;
 712
 713         link_training_settings.link_settings = cur_link_settings;
 714
 715
 716         if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
 717                 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN &&
 718                         prefer_link_settings.link_rate !=  LINK_RATE_UNKNOWN &&
 719                         (prefer_link_settings.lane_count != cur_link_settings.lane_count ||
 720                         prefer_link_settings.link_rate != cur_link_settings.link_rate))
 721                         link_training_settings.link_settings = prefer_link_settings;
 722         }
 723
 724         for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
 725                 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i];
 726
 727         dc_link_dp_set_test_pattern(
 728                 link,
 729                 test_pattern,
 730                 DP_TEST_PATTERN_COLOR_SPACE_RGB,
 731                 &link_training_settings,
 732                 custom_pattern,
 733                 10);
 734
 735         /* Usage: Set DP physical test pattern using AMDDP with normal DP panel
 736          * Then plug out DP panel and connect a scope to measure DP PHY signal.
 737          * Need disable interrupt to avoid SW driver disable DP output. This is
 738          * done after the test pattern is set.
 739          */
 740         if (valid_test_pattern && disable_hpd)
 741                 dc_link_disable_hpd(link);
 742
 743         kfree(wr_buf);
 744
 745         return size;
 746 }
 747
 748 /*
 749  * Returns the DMCUB tracebuffer contents.
 750  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
 751  */
 752 static int dmub_tracebuffer_show(struct seq_file *m, void *data)
 753 {
 754         struct amdgpu_device *adev = m->private;
 755         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 756         struct dmub_debugfs_trace_entry *entries;
 757         uint8_t *tbuf_base;
 758         uint32_t tbuf_size, max_entries, num_entries, i;
 759
 760         if (!fb_info)
 761                 return 0;
 762
 763         tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
 764         if (!tbuf_base)
 765                 return 0;
 766
 767         tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size;
 768         max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
 769                       sizeof(struct dmub_debugfs_trace_entry);
 770
 771         num_entries =
 772                 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
 773
 774         num_entries = min(num_entries, max_entries);
 775
 776         entries = (struct dmub_debugfs_trace_entry
 777                            *)(tbuf_base +
 778                               sizeof(struct dmub_debugfs_trace_header));
 779
 780         for (i = 0; i < num_entries; ++i) {
 781                 struct dmub_debugfs_trace_entry *entry = &entries[i];
 782
 783                 seq_printf(m,
 784                            "trace_code=%u tick_count=%u param0=%u param1=%u\n",
 785                            entry->trace_code, entry->tick_count, entry->param0,
 786                            entry->param1);
 787         }
 788
 789         return 0;
 790 }
 791
 792 /*
 793  * Returns the DMCUB firmware state contents.
 794  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
 795  */
 796 static int dmub_fw_state_show(struct seq_file *m, void *data)
 797 {
 798         struct amdgpu_device *adev = m->private;
 799         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 800         uint8_t *state_base;
 801         uint32_t state_size;
 802
 803         if (!fb_info)
 804                 return 0;
 805
 806         state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;
 807         if (!state_base)
 808                 return 0;
 809
 810         state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size;
 811
 812         return seq_write(m, state_base, state_size);
 813 }
 814
 815 /* psr_capability_show() - show eDP panel PSR capability
 816  *
 817  * The read function: sink_psr_capability_show
 818  * Shows if sink has PSR capability or not.
 819  * If yes - the PSR version is appended
 820  *
 821  *      cat /sys/kernel/debug/dri/0/eDP-X/psr_capability
 822  *
 823  * Expected output:
 824  * "Sink support: no\n" - if panel doesn't support PSR
 825  * "Sink support: yes [0x01]\n" - if panel supports PSR1
 826  * "Driver support: no\n" - if driver doesn't support PSR
 827  * "Driver support: yes [0x01]\n" - if driver supports PSR1
 828  */
 829 static int psr_capability_show(struct seq_file *m, void *data)
 830 {
 831         struct drm_connector *connector = m->private;
 832         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 833         struct dc_link *link = aconnector->dc_link;
 834
 835         if (!link)
 836                 return -ENODEV;
 837
 838         if (link->type == dc_connection_none)
 839                 return -ENODEV;
 840
 841         if (!(link->connector_signal & SIGNAL_TYPE_EDP))
 842                 return -ENODEV;
 843
 844         seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0));
 845         if (link->dpcd_caps.psr_info.psr_version)
 846                 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version);
 847         seq_puts(m, "\n");
 848
 849         seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled));
 850         if (link->psr_settings.psr_version)
 851                 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version);
 852         seq_puts(m, "\n");
 853
 854         return 0;
 855 }
 856
 857 /*
 858  * Returns the current bpc for the crtc.
 859  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc
 860  */
 861 static int amdgpu_current_bpc_show(struct seq_file *m, void *data)
 862 {
 863         struct drm_crtc *crtc = m->private;
 864         struct drm_device *dev = crtc->dev;
 865         struct dm_crtc_state *dm_crtc_state = NULL;
 866         int res = -ENODEV;
 867         unsigned int bpc;
 868
 869         mutex_lock(&dev->mode_config.mutex);
 870         drm_modeset_lock(&crtc->mutex, NULL);
 871         if (crtc->state == NULL)
 872                 goto unlock;
 873
 874         dm_crtc_state = to_dm_crtc_state(crtc->state);
 875         if (dm_crtc_state->stream == NULL)
 876                 goto unlock;
 877
 878         switch (dm_crtc_state->stream->timing.display_color_depth) {
 879         case COLOR_DEPTH_666:
 880                 bpc = 6;
 881                 break;
 882         case COLOR_DEPTH_888:
 883                 bpc = 8;
 884                 break;
 885         case COLOR_DEPTH_101010:
 886                 bpc = 10;
 887                 break;
 888         case COLOR_DEPTH_121212:
 889                 bpc = 12;
 890                 break;
 891         case COLOR_DEPTH_161616:
 892                 bpc = 16;
 893                 break;
 894         default:
 895                 goto unlock;
 896         }
 897
 898         seq_printf(m, "Current: %u\n", bpc);
 899         res = 0;
 900
 901 unlock:
 902         drm_modeset_unlock(&crtc->mutex);
 903         mutex_unlock(&dev->mode_config.mutex);
 904
 905         return res;
 906 }
 907 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc);
 908
 909 /*
 910  * Example usage:
 911  * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
 912  *   echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
 913  * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
 914  *   echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
 915  */
 916 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
 917                                  size_t size, loff_t *pos)
 918 {
 919         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
 920         char *wr_buf = NULL;
 921         uint32_t wr_buf_size = 42;
 922         int max_param_num = 1;
 923         long param;
 924         uint8_t param_nums = 0;
 925
 926         if (size == 0)
 927                 return -EINVAL;
 928
 929         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 930
 931         if (!wr_buf) {
 932                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
 933                 return -ENOSPC;
 934         }
 935
 936         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 937                                            &param, buf,
 938                                            max_param_num,
 939                                            &param_nums)) {
 940                 kfree(wr_buf);
 941                 return -EINVAL;
 942         }
 943
 944         aconnector->dsc_settings.dsc_force_disable_passthrough = param;
 945
 946         kfree(wr_buf);
 947         return 0;
 948 }
 949
 950 /*
 951  * Returns the HDCP capability of the Display (1.4 for now).
 952  *
 953  * NOTE* Not all HDMI displays report their HDCP caps even when they are capable.
 954  * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable.
 955  *
 956  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability
 957  *              or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability
 958  */
 959 static int hdcp_sink_capability_show(struct seq_file *m, void *data)
 960 {
 961         struct drm_connector *connector = m->private;
 962         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 963         bool hdcp_cap, hdcp2_cap;
 964
 965         if (connector->status != connector_status_connected)
 966                 return -ENODEV;
 967
 968         seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id);
 969
 970         hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 971         hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 972
 973
 974         if (hdcp_cap)
 975                 seq_printf(m, "%s ", "HDCP1.4");
 976         if (hdcp2_cap)
 977                 seq_printf(m, "%s ", "HDCP2.2");
 978
 979         if (!hdcp_cap && !hdcp2_cap)
 980                 seq_printf(m, "%s ", "None");
 981
 982         seq_puts(m, "\n");
 983
 984         return 0;
 985 }
 986
 987 /*
 988  * Returns whether the connected display is internal and not hotpluggable.
 989  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display
 990  */
 991 static int internal_display_show(struct seq_file *m, void *data)
 992 {
 993         struct drm_connector *connector = m->private;
 994         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 995         struct dc_link *link = aconnector->dc_link;
 996
 997         seq_printf(m, "Internal: %u\n", link->is_internal_display);
 998
 999         return 0;
1000 }
1001
1002 /* function description
1003  *
1004  * generic SDP message access for testing
1005  *
1006  * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x
1007  *
1008  * SDP header
1009  * Hb0 : Secondary-Data Packet ID
1010  * Hb1 : Secondary-Data Packet type
1011  * Hb2 : Secondary-Data-packet-specific header, Byte 0
1012  * Hb3 : Secondary-Data-packet-specific header, Byte 1
1013  *
1014  * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data
1015  */
1016 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf,
1017                                  size_t size, loff_t *pos)
1018 {
1019         int r;
1020         uint8_t data[36];
1021         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1022         struct dm_crtc_state *acrtc_state;
1023         uint32_t write_size = 36;
1024
1025         if (connector->base.status != connector_status_connected)
1026                 return -ENODEV;
1027
1028         if (size == 0)
1029                 return 0;
1030
1031         acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
1032
1033         r = copy_from_user(data, buf, write_size);
1034
1035         write_size -= r;
1036
1037         dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size);
1038
1039         return write_size;
1040 }
1041
1042 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf,
1043                                  size_t size, loff_t *pos)
1044 {
1045         int r;
1046         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1047
1048         if (size < sizeof(connector->debugfs_dpcd_address))
1049                 return -EINVAL;
1050
1051         r = copy_from_user(&connector->debugfs_dpcd_address,
1052                         buf, sizeof(connector->debugfs_dpcd_address));
1053
1054         return size - r;
1055 }
1056
1057 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf,
1058                                  size_t size, loff_t *pos)
1059 {
1060         int r;
1061         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1062
1063         if (size < sizeof(connector->debugfs_dpcd_size))
1064                 return -EINVAL;
1065
1066         r = copy_from_user(&connector->debugfs_dpcd_size,
1067                         buf, sizeof(connector->debugfs_dpcd_size));
1068
1069         if (connector->debugfs_dpcd_size > 256)
1070                 connector->debugfs_dpcd_size = 0;
1071
1072         return size - r;
1073 }
1074
1075 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf,
1076                                  size_t size, loff_t *pos)
1077 {
1078         int r;
1079         char *data;
1080         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1081         struct dc_link *link = connector->dc_link;
1082         uint32_t write_size = connector->debugfs_dpcd_size;
1083
1084         if (!write_size || size < write_size)
1085                 return -EINVAL;
1086
1087         data = kzalloc(write_size, GFP_KERNEL);
1088         if (!data)
1089                 return 0;
1090
1091         r = copy_from_user(data, buf, write_size);
1092
1093         dm_helpers_dp_write_dpcd(link->ctx, link,
1094                         connector->debugfs_dpcd_address, data, write_size - r);
1095         kfree(data);
1096         return write_size - r;
1097 }
1098
1099 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf,
1100                                  size_t size, loff_t *pos)
1101 {
1102         int r;
1103         char *data;
1104         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1105         struct dc_link *link = connector->dc_link;
1106         uint32_t read_size = connector->debugfs_dpcd_size;
1107
1108         if (!read_size || size < read_size)
1109                 return 0;
1110
1111         data = kzalloc(read_size, GFP_KERNEL);
1112         if (!data)
1113                 return 0;
1114
1115         dm_helpers_dp_read_dpcd(link->ctx, link,
1116                         connector->debugfs_dpcd_address, data, read_size);
1117
1118         r = copy_to_user(buf, data, read_size);
1119
1120         kfree(data);
1121         return read_size - r;
1122 }
1123
1124 /* function: Read link's DSC & FEC capabilities
1125  *
1126  *
1127  * Access it with the following command (you need to specify
1128  * connector like DP-1):
1129  *
1130  *      cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support
1131  *
1132  */
1133 static int dp_dsc_fec_support_show(struct seq_file *m, void *data)
1134 {
1135         struct drm_connector *connector = m->private;
1136         struct drm_modeset_acquire_ctx ctx;
1137         struct drm_device *dev = connector->dev;
1138         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1139         int ret = 0;
1140         bool try_again = false;
1141         bool is_fec_supported = false;
1142         bool is_dsc_supported = false;
1143         struct dpcd_caps dpcd_caps;
1144
1145         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1146         do {
1147                 try_again = false;
1148                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
1149                 if (ret) {
1150                         if (ret == -EDEADLK) {
1151                                 ret = drm_modeset_backoff(&ctx);
1152                                 if (!ret) {
1153                                         try_again = true;
1154                                         continue;
1155                                 }
1156                         }
1157                         break;
1158                 }
1159                 if (connector->status != connector_status_connected) {
1160                         ret = -ENODEV;
1161                         break;
1162                 }
1163                 dpcd_caps = aconnector->dc_link->dpcd_caps;
1164                 if (aconnector->mst_output_port) {
1165                         /* aconnector sets dsc_aux during get_modes call
1166                          * if MST connector has it means it can either
1167                          * enable DSC on the sink device or on MST branch
1168                          * its connected to.
1169                          */
1170                         if (aconnector->dsc_aux) {
1171                                 is_fec_supported = true;
1172                                 is_dsc_supported = true;
1173                         }
1174                 } else {
1175                         is_fec_supported = dpcd_caps.fec_cap.raw & 0x1;
1176                         is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1;
1177                 }
1178         } while (try_again);
1179
1180         drm_modeset_drop_locks(&ctx);
1181         drm_modeset_acquire_fini(&ctx);
1182
1183         seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported));
1184         seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported));
1185
1186         return ret;
1187 }
1188
1189 /* function: Trigger virtual HPD redetection on connector
1190  *
1191  * This function will perform link rediscovery, link disable
1192  * and enable, and dm connector state update.
1193  *
1194  * Retrigger HPD on an existing connector by echoing 1 into
1195  * its respectful "trigger_hotplug" debugfs entry:
1196  *
1197  *      echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1198  *
1199  * This function can perform HPD unplug:
1200  *
1201  *      echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1202  *
1203  */
1204 static ssize_t trigger_hotplug(struct file *f, const char __user *buf,
1205                                                         size_t size, loff_t *pos)
1206 {
1207         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1208         struct drm_connector *connector = &aconnector->base;
1209         struct dc_link *link = NULL;
1210         struct drm_device *dev = connector->dev;
1211         struct amdgpu_device *adev = drm_to_adev(dev);
1212         enum dc_connection_type new_connection_type = dc_connection_none;
1213         char *wr_buf = NULL;
1214         uint32_t wr_buf_size = 42;
1215         int max_param_num = 1;
1216         long param[1] = {0};
1217         uint8_t param_nums = 0;
1218         bool ret = false;
1219
1220         if (!aconnector || !aconnector->dc_link)
1221                 return -EINVAL;
1222
1223         if (size == 0)
1224                 return -EINVAL;
1225
1226         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1227
1228         if (!wr_buf) {
1229                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1230                 return -ENOSPC;
1231         }
1232
1233         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1234                                                 (long *)param, buf,
1235                                                 max_param_num,
1236                                                 &param_nums)) {
1237                 kfree(wr_buf);
1238                 return -EINVAL;
1239         }
1240
1241         kfree(wr_buf);
1242
1243         if (param_nums <= 0) {
1244                 DRM_DEBUG_DRIVER("user data not be read\n");
1245                 return -EINVAL;
1246         }
1247
1248         mutex_lock(&aconnector->hpd_lock);
1249
1250         /* Don't support for mst end device*/
1251         if (aconnector->mst_root) {
1252                 mutex_unlock(&aconnector->hpd_lock);
1253                 return -EINVAL;
1254         }
1255
1256         if (param[0] == 1) {
1257
1258                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type) &&
1259                         new_connection_type != dc_connection_none)
1260                         goto unlock;
1261
1262                 mutex_lock(&adev->dm.dc_lock);
1263                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1264                 mutex_unlock(&adev->dm.dc_lock);
1265
1266                 if (!ret)
1267                         goto unlock;
1268
1269                 amdgpu_dm_update_connector_after_detect(aconnector);
1270
1271                 drm_modeset_lock_all(dev);
1272                 dm_restore_drm_connector_state(dev, connector);
1273                 drm_modeset_unlock_all(dev);
1274
1275                 drm_kms_helper_connector_hotplug_event(connector);
1276         } else if (param[0] == 0) {
1277                 if (!aconnector->dc_link)
1278                         goto unlock;
1279
1280                 link = aconnector->dc_link;
1281
1282                 if (link->local_sink) {
1283                         dc_sink_release(link->local_sink);
1284                         link->local_sink = NULL;
1285                 }
1286
1287                 link->dpcd_sink_count = 0;
1288                 link->type = dc_connection_none;
1289                 link->dongle_max_pix_clk = 0;
1290
1291                 amdgpu_dm_update_connector_after_detect(aconnector);
1292
1293                 /* If the aconnector is the root node in mst topology */
1294                 if (aconnector->mst_mgr.mst_state == true)
1295                         dc_link_reset_cur_dp_mst_topology(link);
1296
1297                 drm_modeset_lock_all(dev);
1298                 dm_restore_drm_connector_state(dev, connector);
1299                 drm_modeset_unlock_all(dev);
1300
1301                 drm_kms_helper_connector_hotplug_event(connector);
1302         }
1303
1304 unlock:
1305         mutex_unlock(&aconnector->hpd_lock);
1306
1307         return size;
1308 }
1309
1310 /* function: read DSC status on the connector
1311  *
1312  * The read function: dp_dsc_clock_en_read
1313  * returns current status of DSC clock on the connector.
1314  * The return is a boolean flag: 1 or 0.
1315  *
1316  * Access it with the following command (you need to specify
1317  * connector like DP-1):
1318  *
1319  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1320  *
1321  * Expected output:
1322  * 1 - means that DSC is currently enabled
1323  * 0 - means that DSC is disabled
1324  */
1325 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
1326                                     size_t size, loff_t *pos)
1327 {
1328         char *rd_buf = NULL;
1329         char *rd_buf_ptr = NULL;
1330         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1331         struct display_stream_compressor *dsc;
1332         struct dcn_dsc_state dsc_state = {0};
1333         const uint32_t rd_buf_size = 10;
1334         struct pipe_ctx *pipe_ctx;
1335         ssize_t result = 0;
1336         int i, r, str_len = 30;
1337
1338         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1339
1340         if (!rd_buf)
1341                 return -ENOMEM;
1342
1343         rd_buf_ptr = rd_buf;
1344
1345         for (i = 0; i < MAX_PIPES; i++) {
1346                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1347                 if (pipe_ctx->stream &&
1348                     pipe_ctx->stream->link == aconnector->dc_link)
1349                         break;
1350         }
1351
1352         dsc = pipe_ctx->stream_res.dsc;
1353         if (dsc)
1354                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1355
1356         snprintf(rd_buf_ptr, str_len,
1357                 "%d\n",
1358                 dsc_state.dsc_clock_en);
1359         rd_buf_ptr += str_len;
1360
1361         while (size) {
1362                 if (*pos >= rd_buf_size)
1363                         break;
1364
1365                 r = put_user(*(rd_buf + result), buf);
1366                 if (r) {
1367                         kfree(rd_buf);
1368                         return r; /* r = -EFAULT */
1369                 }
1370
1371                 buf += 1;
1372                 size -= 1;
1373                 *pos += 1;
1374                 result += 1;
1375         }
1376
1377         kfree(rd_buf);
1378         return result;
1379 }
1380
1381 /* function: write force DSC on the connector
1382  *
1383  * The write function: dp_dsc_clock_en_write
1384  * enables to force DSC on the connector.
1385  * User can write to either force enable or force disable DSC
1386  * on the next modeset or set it to driver default
1387  *
1388  * Accepted inputs:
1389  * 0 - default DSC enablement policy
1390  * 1 - force enable DSC on the connector
1391  * 2 - force disable DSC on the connector (might cause fail in atomic_check)
1392  *
1393  * Writing DSC settings is done with the following command:
1394  * - To force enable DSC (you need to specify
1395  * connector like DP-1):
1396  *
1397  *      echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1398  *
1399  * - To return to default state set the flag to zero and
1400  * let driver deal with DSC automatically
1401  * (you need to specify connector like DP-1):
1402  *
1403  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1404  *
1405  */
1406 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
1407                                      size_t size, loff_t *pos)
1408 {
1409         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1410         struct drm_connector *connector = &aconnector->base;
1411         struct drm_device *dev = connector->dev;
1412         struct drm_crtc *crtc = NULL;
1413         struct dm_crtc_state *dm_crtc_state = NULL;
1414         struct pipe_ctx *pipe_ctx;
1415         int i;
1416         char *wr_buf = NULL;
1417         uint32_t wr_buf_size = 42;
1418         int max_param_num = 1;
1419         long param[1] = {0};
1420         uint8_t param_nums = 0;
1421
1422         if (size == 0)
1423                 return -EINVAL;
1424
1425         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1426
1427         if (!wr_buf) {
1428                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1429                 return -ENOSPC;
1430         }
1431
1432         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1433                                             (long *)param, buf,
1434                                             max_param_num,
1435                                             &param_nums)) {
1436                 kfree(wr_buf);
1437                 return -EINVAL;
1438         }
1439
1440         if (param_nums <= 0) {
1441                 DRM_DEBUG_DRIVER("user data not be read\n");
1442                 kfree(wr_buf);
1443                 return -EINVAL;
1444         }
1445
1446         for (i = 0; i < MAX_PIPES; i++) {
1447                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1448                 if (pipe_ctx->stream &&
1449                     pipe_ctx->stream->link == aconnector->dc_link)
1450                         break;
1451         }
1452
1453         if (!pipe_ctx->stream)
1454                 goto done;
1455
1456         // Get CRTC state
1457         mutex_lock(&dev->mode_config.mutex);
1458         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1459
1460         if (connector->state == NULL)
1461                 goto unlock;
1462
1463         crtc = connector->state->crtc;
1464         if (crtc == NULL)
1465                 goto unlock;
1466
1467         drm_modeset_lock(&crtc->mutex, NULL);
1468         if (crtc->state == NULL)
1469                 goto unlock;
1470
1471         dm_crtc_state = to_dm_crtc_state(crtc->state);
1472         if (dm_crtc_state->stream == NULL)
1473                 goto unlock;
1474
1475         if (param[0] == 1)
1476                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE;
1477         else if (param[0] == 2)
1478                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE;
1479         else
1480                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT;
1481
1482         dm_crtc_state->dsc_force_changed = true;
1483
1484 unlock:
1485         if (crtc)
1486                 drm_modeset_unlock(&crtc->mutex);
1487         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1488         mutex_unlock(&dev->mode_config.mutex);
1489
1490 done:
1491         kfree(wr_buf);
1492         return size;
1493 }
1494
1495 /* function: read DSC slice width parameter on the connector
1496  *
1497  * The read function: dp_dsc_slice_width_read
1498  * returns dsc slice width used in the current configuration
1499  * The return is an integer: 0 or other positive number
1500  *
1501  * Access the status with the following command:
1502  *
1503  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1504  *
1505  * 0 - means that DSC is disabled
1506  *
1507  * Any other number more than zero represents the
1508  * slice width currently used by DSC in pixels
1509  *
1510  */
1511 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
1512                                     size_t size, loff_t *pos)
1513 {
1514         char *rd_buf = NULL;
1515         char *rd_buf_ptr = NULL;
1516         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1517         struct display_stream_compressor *dsc;
1518         struct dcn_dsc_state dsc_state = {0};
1519         const uint32_t rd_buf_size = 100;
1520         struct pipe_ctx *pipe_ctx;
1521         ssize_t result = 0;
1522         int i, r, str_len = 30;
1523
1524         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1525
1526         if (!rd_buf)
1527                 return -ENOMEM;
1528
1529         rd_buf_ptr = rd_buf;
1530
1531         for (i = 0; i < MAX_PIPES; i++) {
1532                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1533                 if (pipe_ctx->stream &&
1534                     pipe_ctx->stream->link == aconnector->dc_link)
1535                         break;
1536         }
1537
1538         dsc = pipe_ctx->stream_res.dsc;
1539         if (dsc)
1540                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1541
1542         snprintf(rd_buf_ptr, str_len,
1543                 "%d\n",
1544                 dsc_state.dsc_slice_width);
1545         rd_buf_ptr += str_len;
1546
1547         while (size) {
1548                 if (*pos >= rd_buf_size)
1549                         break;
1550
1551                 r = put_user(*(rd_buf + result), buf);
1552                 if (r) {
1553                         kfree(rd_buf);
1554                         return r; /* r = -EFAULT */
1555                 }
1556
1557                 buf += 1;
1558                 size -= 1;
1559                 *pos += 1;
1560                 result += 1;
1561         }
1562
1563         kfree(rd_buf);
1564         return result;
1565 }
1566
1567 /* function: write DSC slice width parameter
1568  *
1569  * The write function: dp_dsc_slice_width_write
1570  * overwrites automatically generated DSC configuration
1571  * of slice width.
1572  *
1573  * The user has to write the slice width divisible by the
1574  * picture width.
1575  *
1576  * Also the user has to write width in hexidecimal
1577  * rather than in decimal.
1578  *
1579  * Writing DSC settings is done with the following command:
1580  * - To force overwrite slice width: (example sets to 1920 pixels)
1581  *
1582  *      echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1583  *
1584  *  - To stop overwriting and let driver find the optimal size,
1585  * set the width to zero:
1586  *
1587  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1588  *
1589  */
1590 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
1591                                      size_t size, loff_t *pos)
1592 {
1593         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1594         struct pipe_ctx *pipe_ctx;
1595         struct drm_connector *connector = &aconnector->base;
1596         struct drm_device *dev = connector->dev;
1597         struct drm_crtc *crtc = NULL;
1598         struct dm_crtc_state *dm_crtc_state = NULL;
1599         int i;
1600         char *wr_buf = NULL;
1601         uint32_t wr_buf_size = 42;
1602         int max_param_num = 1;
1603         long param[1] = {0};
1604         uint8_t param_nums = 0;
1605
1606         if (size == 0)
1607                 return -EINVAL;
1608
1609         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1610
1611         if (!wr_buf) {
1612                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1613                 return -ENOSPC;
1614         }
1615
1616         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1617                                             (long *)param, buf,
1618                                             max_param_num,
1619                                             &param_nums)) {
1620                 kfree(wr_buf);
1621                 return -EINVAL;
1622         }
1623
1624         if (param_nums <= 0) {
1625                 DRM_DEBUG_DRIVER("user data not be read\n");
1626                 kfree(wr_buf);
1627                 return -EINVAL;
1628         }
1629
1630         for (i = 0; i < MAX_PIPES; i++) {
1631                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1632                 if (pipe_ctx->stream &&
1633                     pipe_ctx->stream->link == aconnector->dc_link)
1634                         break;
1635         }
1636
1637         if (!pipe_ctx->stream)
1638                 goto done;
1639
1640         // Safely get CRTC state
1641         mutex_lock(&dev->mode_config.mutex);
1642         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1643
1644         if (connector->state == NULL)
1645                 goto unlock;
1646
1647         crtc = connector->state->crtc;
1648         if (crtc == NULL)
1649                 goto unlock;
1650
1651         drm_modeset_lock(&crtc->mutex, NULL);
1652         if (crtc->state == NULL)
1653                 goto unlock;
1654
1655         dm_crtc_state = to_dm_crtc_state(crtc->state);
1656         if (dm_crtc_state->stream == NULL)
1657                 goto unlock;
1658
1659         if (param[0] > 0)
1660                 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
1661                                         pipe_ctx->stream->timing.h_addressable,
1662                                         param[0]);
1663         else
1664                 aconnector->dsc_settings.dsc_num_slices_h = 0;
1665
1666         dm_crtc_state->dsc_force_changed = true;
1667
1668 unlock:
1669         if (crtc)
1670                 drm_modeset_unlock(&crtc->mutex);
1671         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1672         mutex_unlock(&dev->mode_config.mutex);
1673
1674 done:
1675         kfree(wr_buf);
1676         return size;
1677 }
1678
1679 /* function: read DSC slice height parameter on the connector
1680  *
1681  * The read function: dp_dsc_slice_height_read
1682  * returns dsc slice height used in the current configuration
1683  * The return is an integer: 0 or other positive number
1684  *
1685  * Access the status with the following command:
1686  *
1687  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1688  *
1689  * 0 - means that DSC is disabled
1690  *
1691  * Any other number more than zero represents the
1692  * slice height currently used by DSC in pixels
1693  *
1694  */
1695 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
1696                                     size_t size, loff_t *pos)
1697 {
1698         char *rd_buf = NULL;
1699         char *rd_buf_ptr = NULL;
1700         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1701         struct display_stream_compressor *dsc;
1702         struct dcn_dsc_state dsc_state = {0};
1703         const uint32_t rd_buf_size = 100;
1704         struct pipe_ctx *pipe_ctx;
1705         ssize_t result = 0;
1706         int i, r, str_len = 30;
1707
1708         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1709
1710         if (!rd_buf)
1711                 return -ENOMEM;
1712
1713         rd_buf_ptr = rd_buf;
1714
1715         for (i = 0; i < MAX_PIPES; i++) {
1716                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1717                 if (pipe_ctx->stream &&
1718                     pipe_ctx->stream->link == aconnector->dc_link)
1719                         break;
1720         }
1721
1722         dsc = pipe_ctx->stream_res.dsc;
1723         if (dsc)
1724                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1725
1726         snprintf(rd_buf_ptr, str_len,
1727                 "%d\n",
1728                 dsc_state.dsc_slice_height);
1729         rd_buf_ptr += str_len;
1730
1731         while (size) {
1732                 if (*pos >= rd_buf_size)
1733                         break;
1734
1735                 r = put_user(*(rd_buf + result), buf);
1736                 if (r) {
1737                         kfree(rd_buf);
1738                         return r; /* r = -EFAULT */
1739                 }
1740
1741                 buf += 1;
1742                 size -= 1;
1743                 *pos += 1;
1744                 result += 1;
1745         }
1746
1747         kfree(rd_buf);
1748         return result;
1749 }
1750
1751 /* function: write DSC slice height parameter
1752  *
1753  * The write function: dp_dsc_slice_height_write
1754  * overwrites automatically generated DSC configuration
1755  * of slice height.
1756  *
1757  * The user has to write the slice height divisible by the
1758  * picture height.
1759  *
1760  * Also the user has to write height in hexidecimal
1761  * rather than in decimal.
1762  *
1763  * Writing DSC settings is done with the following command:
1764  * - To force overwrite slice height (example sets to 128 pixels):
1765  *
1766  *      echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1767  *
1768  *  - To stop overwriting and let driver find the optimal size,
1769  * set the height to zero:
1770  *
1771  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1772  *
1773  */
1774 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
1775                                      size_t size, loff_t *pos)
1776 {
1777         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1778         struct drm_connector *connector = &aconnector->base;
1779         struct drm_device *dev = connector->dev;
1780         struct drm_crtc *crtc = NULL;
1781         struct dm_crtc_state *dm_crtc_state = NULL;
1782         struct pipe_ctx *pipe_ctx;
1783         int i;
1784         char *wr_buf = NULL;
1785         uint32_t wr_buf_size = 42;
1786         int max_param_num = 1;
1787         uint8_t param_nums = 0;
1788         long param[1] = {0};
1789
1790         if (size == 0)
1791                 return -EINVAL;
1792
1793         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1794
1795         if (!wr_buf) {
1796                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1797                 return -ENOSPC;
1798         }
1799
1800         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1801                                             (long *)param, buf,
1802                                             max_param_num,
1803                                             &param_nums)) {
1804                 kfree(wr_buf);
1805                 return -EINVAL;
1806         }
1807
1808         if (param_nums <= 0) {
1809                 DRM_DEBUG_DRIVER("user data not be read\n");
1810                 kfree(wr_buf);
1811                 return -EINVAL;
1812         }
1813
1814         for (i = 0; i < MAX_PIPES; i++) {
1815                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1816                 if (pipe_ctx->stream &&
1817                     pipe_ctx->stream->link == aconnector->dc_link)
1818                         break;
1819         }
1820
1821         if (!pipe_ctx->stream)
1822                 goto done;
1823
1824         // Get CRTC state
1825         mutex_lock(&dev->mode_config.mutex);
1826         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1827
1828         if (connector->state == NULL)
1829                 goto unlock;
1830
1831         crtc = connector->state->crtc;
1832         if (crtc == NULL)
1833                 goto unlock;
1834
1835         drm_modeset_lock(&crtc->mutex, NULL);
1836         if (crtc->state == NULL)
1837                 goto unlock;
1838
1839         dm_crtc_state = to_dm_crtc_state(crtc->state);
1840         if (dm_crtc_state->stream == NULL)
1841                 goto unlock;
1842
1843         if (param[0] > 0)
1844                 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
1845                                         pipe_ctx->stream->timing.v_addressable,
1846                                         param[0]);
1847         else
1848                 aconnector->dsc_settings.dsc_num_slices_v = 0;
1849
1850         dm_crtc_state->dsc_force_changed = true;
1851
1852 unlock:
1853         if (crtc)
1854                 drm_modeset_unlock(&crtc->mutex);
1855         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1856         mutex_unlock(&dev->mode_config.mutex);
1857
1858 done:
1859         kfree(wr_buf);
1860         return size;
1861 }
1862
1863 /* function: read DSC target rate on the connector in bits per pixel
1864  *
1865  * The read function: dp_dsc_bits_per_pixel_read
1866  * returns target rate of compression in bits per pixel
1867  * The return is an integer: 0 or other positive integer
1868  *
1869  * Access it with the following command:
1870  *
1871  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1872  *
1873  *  0 - means that DSC is disabled
1874  */
1875 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
1876                                     size_t size, loff_t *pos)
1877 {
1878         char *rd_buf = NULL;
1879         char *rd_buf_ptr = NULL;
1880         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1881         struct display_stream_compressor *dsc;
1882         struct dcn_dsc_state dsc_state = {0};
1883         const uint32_t rd_buf_size = 100;
1884         struct pipe_ctx *pipe_ctx;
1885         ssize_t result = 0;
1886         int i, r, str_len = 30;
1887
1888         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1889
1890         if (!rd_buf)
1891                 return -ENOMEM;
1892
1893         rd_buf_ptr = rd_buf;
1894
1895         for (i = 0; i < MAX_PIPES; i++) {
1896                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1897                 if (pipe_ctx->stream &&
1898                     pipe_ctx->stream->link == aconnector->dc_link)
1899                         break;
1900         }
1901
1902         dsc = pipe_ctx->stream_res.dsc;
1903         if (dsc)
1904                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1905
1906         snprintf(rd_buf_ptr, str_len,
1907                 "%d\n",
1908                 dsc_state.dsc_bits_per_pixel);
1909         rd_buf_ptr += str_len;
1910
1911         while (size) {
1912                 if (*pos >= rd_buf_size)
1913                         break;
1914
1915                 r = put_user(*(rd_buf + result), buf);
1916                 if (r) {
1917                         kfree(rd_buf);
1918                         return r; /* r = -EFAULT */
1919                 }
1920
1921                 buf += 1;
1922                 size -= 1;
1923                 *pos += 1;
1924                 result += 1;
1925         }
1926
1927         kfree(rd_buf);
1928         return result;
1929 }
1930
1931 /* function: write DSC target rate in bits per pixel
1932  *
1933  * The write function: dp_dsc_bits_per_pixel_write
1934  * overwrites automatically generated DSC configuration
1935  * of DSC target bit rate.
1936  *
1937  * Also the user has to write bpp in hexidecimal
1938  * rather than in decimal.
1939  *
1940  * Writing DSC settings is done with the following command:
1941  * - To force overwrite rate (example sets to 256 bpp x 1/16):
1942  *
1943  *      echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1944  *
1945  *  - To stop overwriting and let driver find the optimal rate,
1946  * set the rate to zero:
1947  *
1948  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1949  *
1950  */
1951 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
1952                                      size_t size, loff_t *pos)
1953 {
1954         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1955         struct drm_connector *connector = &aconnector->base;
1956         struct drm_device *dev = connector->dev;
1957         struct drm_crtc *crtc = NULL;
1958         struct dm_crtc_state *dm_crtc_state = NULL;
1959         struct pipe_ctx *pipe_ctx;
1960         int i;
1961         char *wr_buf = NULL;
1962         uint32_t wr_buf_size = 42;
1963         int max_param_num = 1;
1964         uint8_t param_nums = 0;
1965         long param[1] = {0};
1966
1967         if (size == 0)
1968                 return -EINVAL;
1969
1970         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1971
1972         if (!wr_buf) {
1973                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1974                 return -ENOSPC;
1975         }
1976
1977         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1978                                             (long *)param, buf,
1979                                             max_param_num,
1980                                             &param_nums)) {
1981                 kfree(wr_buf);
1982                 return -EINVAL;
1983         }
1984
1985         if (param_nums <= 0) {
1986                 DRM_DEBUG_DRIVER("user data not be read\n");
1987                 kfree(wr_buf);
1988                 return -EINVAL;
1989         }
1990
1991         for (i = 0; i < MAX_PIPES; i++) {
1992                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1993                 if (pipe_ctx->stream &&
1994                     pipe_ctx->stream->link == aconnector->dc_link)
1995                         break;
1996         }
1997
1998         if (!pipe_ctx->stream)
1999                 goto done;
2000
2001         // Get CRTC state
2002         mutex_lock(&dev->mode_config.mutex);
2003         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2004
2005         if (connector->state == NULL)
2006                 goto unlock;
2007
2008         crtc = connector->state->crtc;
2009         if (crtc == NULL)
2010                 goto unlock;
2011
2012         drm_modeset_lock(&crtc->mutex, NULL);
2013         if (crtc->state == NULL)
2014                 goto unlock;
2015
2016         dm_crtc_state = to_dm_crtc_state(crtc->state);
2017         if (dm_crtc_state->stream == NULL)
2018                 goto unlock;
2019
2020         aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
2021
2022         dm_crtc_state->dsc_force_changed = true;
2023
2024 unlock:
2025         if (crtc)
2026                 drm_modeset_unlock(&crtc->mutex);
2027         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2028         mutex_unlock(&dev->mode_config.mutex);
2029
2030 done:
2031         kfree(wr_buf);
2032         return size;
2033 }
2034
2035 /* function: read DSC picture width parameter on the connector
2036  *
2037  * The read function: dp_dsc_pic_width_read
2038  * returns dsc picture width used in the current configuration
2039  * It is the same as h_addressable of the current
2040  * display's timing
2041  * The return is an integer: 0 or other positive integer
2042  * If 0 then DSC is disabled.
2043  *
2044  * Access it with the following command:
2045  *
2046  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width
2047  *
2048  * 0 - means that DSC is disabled
2049  */
2050 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
2051                                     size_t size, loff_t *pos)
2052 {
2053         char *rd_buf = NULL;
2054         char *rd_buf_ptr = NULL;
2055         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2056         struct display_stream_compressor *dsc;
2057         struct dcn_dsc_state dsc_state = {0};
2058         const uint32_t rd_buf_size = 100;
2059         struct pipe_ctx *pipe_ctx;
2060         ssize_t result = 0;
2061         int i, r, str_len = 30;
2062
2063         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2064
2065         if (!rd_buf)
2066                 return -ENOMEM;
2067
2068         rd_buf_ptr = rd_buf;
2069
2070         for (i = 0; i < MAX_PIPES; i++) {
2071                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2072                 if (pipe_ctx->stream &&
2073                     pipe_ctx->stream->link == aconnector->dc_link)
2074                         break;
2075         }
2076
2077         dsc = pipe_ctx->stream_res.dsc;
2078         if (dsc)
2079                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2080
2081         snprintf(rd_buf_ptr, str_len,
2082                 "%d\n",
2083                 dsc_state.dsc_pic_width);
2084         rd_buf_ptr += str_len;
2085
2086         while (size) {
2087                 if (*pos >= rd_buf_size)
2088                         break;
2089
2090                 r = put_user(*(rd_buf + result), buf);
2091                 if (r) {
2092                         kfree(rd_buf);
2093                         return r; /* r = -EFAULT */
2094                 }
2095
2096                 buf += 1;
2097                 size -= 1;
2098                 *pos += 1;
2099                 result += 1;
2100         }
2101
2102         kfree(rd_buf);
2103         return result;
2104 }
2105
2106 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
2107                                     size_t size, loff_t *pos)
2108 {
2109         char *rd_buf = NULL;
2110         char *rd_buf_ptr = NULL;
2111         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2112         struct display_stream_compressor *dsc;
2113         struct dcn_dsc_state dsc_state = {0};
2114         const uint32_t rd_buf_size = 100;
2115         struct pipe_ctx *pipe_ctx;
2116         ssize_t result = 0;
2117         int i, r, str_len = 30;
2118
2119         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2120
2121         if (!rd_buf)
2122                 return -ENOMEM;
2123
2124         rd_buf_ptr = rd_buf;
2125
2126         for (i = 0; i < MAX_PIPES; i++) {
2127                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2128                 if (pipe_ctx->stream &&
2129                     pipe_ctx->stream->link == aconnector->dc_link)
2130                         break;
2131         }
2132
2133         dsc = pipe_ctx->stream_res.dsc;
2134         if (dsc)
2135                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2136
2137         snprintf(rd_buf_ptr, str_len,
2138                 "%d\n",
2139                 dsc_state.dsc_pic_height);
2140         rd_buf_ptr += str_len;
2141
2142         while (size) {
2143                 if (*pos >= rd_buf_size)
2144                         break;
2145
2146                 r = put_user(*(rd_buf + result), buf);
2147                 if (r) {
2148                         kfree(rd_buf);
2149                         return r; /* r = -EFAULT */
2150                 }
2151
2152                 buf += 1;
2153                 size -= 1;
2154                 *pos += 1;
2155                 result += 1;
2156         }
2157
2158         kfree(rd_buf);
2159         return result;
2160 }
2161
2162 /* function: read DSC chunk size parameter on the connector
2163  *
2164  * The read function: dp_dsc_chunk_size_read
2165  * returns dsc chunk size set in the current configuration
2166  * The value is calculated automatically by DSC code
2167  * and depends on slice parameters and bpp target rate
2168  * The return is an integer: 0 or other positive integer
2169  * If 0 then DSC is disabled.
2170  *
2171  * Access it with the following command:
2172  *
2173  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size
2174  *
2175  * 0 - means that DSC is disabled
2176  */
2177 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
2178                                     size_t size, loff_t *pos)
2179 {
2180         char *rd_buf = NULL;
2181         char *rd_buf_ptr = NULL;
2182         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2183         struct display_stream_compressor *dsc;
2184         struct dcn_dsc_state dsc_state = {0};
2185         const uint32_t rd_buf_size = 100;
2186         struct pipe_ctx *pipe_ctx;
2187         ssize_t result = 0;
2188         int i, r, str_len = 30;
2189
2190         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2191
2192         if (!rd_buf)
2193                 return -ENOMEM;
2194
2195         rd_buf_ptr = rd_buf;
2196
2197         for (i = 0; i < MAX_PIPES; i++) {
2198                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2199                 if (pipe_ctx->stream &&
2200                     pipe_ctx->stream->link == aconnector->dc_link)
2201                         break;
2202         }
2203
2204         dsc = pipe_ctx->stream_res.dsc;
2205         if (dsc)
2206                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2207
2208         snprintf(rd_buf_ptr, str_len,
2209                 "%d\n",
2210                 dsc_state.dsc_chunk_size);
2211         rd_buf_ptr += str_len;
2212
2213         while (size) {
2214                 if (*pos >= rd_buf_size)
2215                         break;
2216
2217                 r = put_user(*(rd_buf + result), buf);
2218                 if (r) {
2219                         kfree(rd_buf);
2220                         return r; /* r = -EFAULT */
2221                 }
2222
2223                 buf += 1;
2224                 size -= 1;
2225                 *pos += 1;
2226                 result += 1;
2227         }
2228
2229         kfree(rd_buf);
2230         return result;
2231 }
2232
2233 /* function: read DSC slice bpg offset on the connector
2234  *
2235  * The read function: dp_dsc_slice_bpg_offset_read
2236  * returns dsc bpg slice offset set in the current configuration
2237  * The value is calculated automatically by DSC code
2238  * and depends on slice parameters and bpp target rate
2239  * The return is an integer: 0 or other positive integer
2240  * If 0 then DSC is disabled.
2241  *
2242  * Access it with the following command:
2243  *
2244  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset
2245  *
2246  * 0 - means that DSC is disabled
2247  */
2248 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
2249                                     size_t size, loff_t *pos)
2250 {
2251         char *rd_buf = NULL;
2252         char *rd_buf_ptr = NULL;
2253         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2254         struct display_stream_compressor *dsc;
2255         struct dcn_dsc_state dsc_state = {0};
2256         const uint32_t rd_buf_size = 100;
2257         struct pipe_ctx *pipe_ctx;
2258         ssize_t result = 0;
2259         int i, r, str_len = 30;
2260
2261         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2262
2263         if (!rd_buf)
2264                 return -ENOMEM;
2265
2266         rd_buf_ptr = rd_buf;
2267
2268         for (i = 0; i < MAX_PIPES; i++) {
2269                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2270                 if (pipe_ctx->stream &&
2271                     pipe_ctx->stream->link == aconnector->dc_link)
2272                         break;
2273         }
2274
2275         dsc = pipe_ctx->stream_res.dsc;
2276         if (dsc)
2277                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2278
2279         snprintf(rd_buf_ptr, str_len,
2280                 "%d\n",
2281                 dsc_state.dsc_slice_bpg_offset);
2282         rd_buf_ptr += str_len;
2283
2284         while (size) {
2285                 if (*pos >= rd_buf_size)
2286                         break;
2287
2288                 r = put_user(*(rd_buf + result), buf);
2289                 if (r) {
2290                         kfree(rd_buf);
2291                         return r; /* r = -EFAULT */
2292                 }
2293
2294                 buf += 1;
2295                 size -= 1;
2296                 *pos += 1;
2297                 result += 1;
2298         }
2299
2300         kfree(rd_buf);
2301         return result;
2302 }
2303
2304
2305 /*
2306  * function description: Read max_requested_bpc property from the connector
2307  *
2308  * Access it with the following command:
2309  *
2310  *      cat /sys/kernel/debug/dri/0/DP-X/max_bpc
2311  *
2312  */
2313 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf,
2314                 size_t size, loff_t *pos)
2315 {
2316         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2317         struct drm_connector *connector = &aconnector->base;
2318         struct drm_device *dev = connector->dev;
2319         struct dm_connector_state *state;
2320         ssize_t result = 0;
2321         char *rd_buf = NULL;
2322         char *rd_buf_ptr = NULL;
2323         const uint32_t rd_buf_size = 10;
2324         int r;
2325
2326         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2327
2328         if (!rd_buf)
2329                 return -ENOMEM;
2330
2331         mutex_lock(&dev->mode_config.mutex);
2332         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2333
2334         if (connector->state == NULL)
2335                 goto unlock;
2336
2337         state = to_dm_connector_state(connector->state);
2338
2339         rd_buf_ptr = rd_buf;
2340         snprintf(rd_buf_ptr, rd_buf_size,
2341                 "%u\n",
2342                 state->base.max_requested_bpc);
2343
2344         while (size) {
2345                 if (*pos >= rd_buf_size)
2346                         break;
2347
2348                 r = put_user(*(rd_buf + result), buf);
2349                 if (r) {
2350                         result = r; /* r = -EFAULT */
2351                         goto unlock;
2352                 }
2353                 buf += 1;
2354                 size -= 1;
2355                 *pos += 1;
2356                 result += 1;
2357         }
2358 unlock:
2359         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2360         mutex_unlock(&dev->mode_config.mutex);
2361         kfree(rd_buf);
2362         return result;
2363 }
2364
2365
2366 /*
2367  * function description: Set max_requested_bpc property on the connector
2368  *
2369  * This function will not force the input BPC on connector, it will only
2370  * change the max value. This is equivalent to setting max_bpc through
2371  * xrandr.
2372  *
2373  * The BPC value written must be >= 6 and <= 16. Values outside of this
2374  * range will result in errors.
2375  *
2376  * BPC values:
2377  *      0x6 - 6 BPC
2378  *      0x8 - 8 BPC
2379  *      0xa - 10 BPC
2380  *      0xc - 12 BPC
2381  *      0x10 - 16 BPC
2382  *
2383  * Write the max_bpc in the following way:
2384  *
2385  * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc
2386  *
2387  */
2388 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf,
2389                                      size_t size, loff_t *pos)
2390 {
2391         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2392         struct drm_connector *connector = &aconnector->base;
2393         struct dm_connector_state *state;
2394         struct drm_device *dev = connector->dev;
2395         char *wr_buf = NULL;
2396         uint32_t wr_buf_size = 42;
2397         int max_param_num = 1;
2398         long param[1] = {0};
2399         uint8_t param_nums = 0;
2400
2401         if (size == 0)
2402                 return -EINVAL;
2403
2404         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2405
2406         if (!wr_buf) {
2407                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2408                 return -ENOSPC;
2409         }
2410
2411         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2412                                            (long *)param, buf,
2413                                            max_param_num,
2414                                            &param_nums)) {
2415                 kfree(wr_buf);
2416                 return -EINVAL;
2417         }
2418
2419         if (param_nums <= 0) {
2420                 DRM_DEBUG_DRIVER("user data not be read\n");
2421                 kfree(wr_buf);
2422                 return -EINVAL;
2423         }
2424
2425         if (param[0] < 6 || param[0] > 16) {
2426                 DRM_DEBUG_DRIVER("bad max_bpc value\n");
2427                 kfree(wr_buf);
2428                 return -EINVAL;
2429         }
2430
2431         mutex_lock(&dev->mode_config.mutex);
2432         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2433
2434         if (connector->state == NULL)
2435                 goto unlock;
2436
2437         state = to_dm_connector_state(connector->state);
2438         state->base.max_requested_bpc = param[0];
2439 unlock:
2440         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2441         mutex_unlock(&dev->mode_config.mutex);
2442
2443         kfree(wr_buf);
2444         return size;
2445 }
2446
2447 /*
2448  * Backlight at this moment.  Read only.
2449  * As written to display, taking ABM and backlight lut into account.
2450  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2451  *
2452  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight
2453  */
2454 static int current_backlight_show(struct seq_file *m, void *unused)
2455 {
2456         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2457         struct dc_link *link = aconnector->dc_link;
2458         unsigned int backlight;
2459
2460         backlight = dc_link_get_backlight_level(link);
2461         seq_printf(m, "0x%x\n", backlight);
2462
2463         return 0;
2464 }
2465
2466 /*
2467  * Backlight value that is being approached.  Read only.
2468  * As written to display, taking ABM and backlight lut into account.
2469  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2470  *
2471  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight
2472  */
2473 static int target_backlight_show(struct seq_file *m, void *unused)
2474 {
2475         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2476         struct dc_link *link = aconnector->dc_link;
2477         unsigned int backlight;
2478
2479         backlight = dc_link_get_target_backlight_pwm(link);
2480         seq_printf(m, "0x%x\n", backlight);
2481
2482         return 0;
2483 }
2484
2485 /*
2486  * function description: Determine if the connector is mst connector
2487  *
2488  * This function helps to determine whether a connector is a mst connector.
2489  * - "root" stands for the root connector of the topology
2490  * - "branch" stands for branch device of the topology
2491  * - "end" stands for leaf node connector of the topology
2492  * - "no" stands for the connector is not a device of a mst topology
2493  * Access it with the following command:
2494  *
2495  *      cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector
2496  *
2497  */
2498 static int dp_is_mst_connector_show(struct seq_file *m, void *unused)
2499 {
2500         struct drm_connector *connector = m->private;
2501         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2502         struct drm_dp_mst_topology_mgr *mgr = NULL;
2503         struct drm_dp_mst_port *port = NULL;
2504         char *role = NULL;
2505
2506         mutex_lock(&aconnector->hpd_lock);
2507
2508         if (aconnector->mst_mgr.mst_state) {
2509                 role = "root";
2510         } else if (aconnector->mst_root &&
2511                 aconnector->mst_root->mst_mgr.mst_state) {
2512
2513                 role = "end";
2514
2515                 mgr = &aconnector->mst_root->mst_mgr;
2516                 port = aconnector->mst_output_port;
2517
2518                 drm_modeset_lock(&mgr->base.lock, NULL);
2519                 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING &&
2520                         port->mcs)
2521                         role = "branch";
2522                 drm_modeset_unlock(&mgr->base.lock);
2523
2524         } else {
2525                 role = "no";
2526         }
2527
2528         seq_printf(m, "%s\n", role);
2529
2530         mutex_unlock(&aconnector->hpd_lock);
2531
2532         return 0;
2533 }
2534
2535 /*
2536  * function description: Read out the mst progress status
2537  *
2538  * This function helps to determine the mst progress status of
2539  * a mst connector.
2540  *
2541  * Access it with the following command:
2542  *
2543  *      cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status
2544  *
2545  */
2546 static int dp_mst_progress_status_show(struct seq_file *m, void *unused)
2547 {
2548         struct drm_connector *connector = m->private;
2549         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2550         struct amdgpu_device *adev = drm_to_adev(connector->dev);
2551         int i;
2552
2553         mutex_lock(&aconnector->hpd_lock);
2554         mutex_lock(&adev->dm.dc_lock);
2555
2556         if (aconnector->mst_status == MST_STATUS_DEFAULT) {
2557                 seq_puts(m, "disabled\n");
2558         } else {
2559                 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++)
2560                         seq_printf(m, "%s:%s\n",
2561                                 mst_progress_status[i],
2562                                 aconnector->mst_status & BIT(i) ? "done" : "not_done");
2563         }
2564
2565         mutex_unlock(&adev->dm.dc_lock);
2566         mutex_unlock(&aconnector->hpd_lock);
2567
2568         return 0;
2569 }
2570
2571 /*
2572  * Reports whether the connected display is a USB4 DPIA tunneled display
2573  * Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link
2574  */
2575 static int is_dpia_link_show(struct seq_file *m, void *data)
2576 {
2577         struct drm_connector *connector = m->private;
2578         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2579         struct dc_link *link = aconnector->dc_link;
2580
2581         if (connector->status != connector_status_connected)
2582                 return -ENODEV;
2583
2584         seq_printf(m, "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" :
2585                                 (link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown");
2586
2587         return 0;
2588 }
2589
2590 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
2591 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
2592 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
2593 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
2594 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
2595 DEFINE_SHOW_ATTRIBUTE(internal_display);
2596 DEFINE_SHOW_ATTRIBUTE(psr_capability);
2597 DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector);
2598 DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status);
2599 DEFINE_SHOW_ATTRIBUTE(is_dpia_link);
2600
2601 static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
2602         .owner = THIS_MODULE,
2603         .read = dp_dsc_clock_en_read,
2604         .write = dp_dsc_clock_en_write,
2605         .llseek = default_llseek
2606 };
2607
2608 static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
2609         .owner = THIS_MODULE,
2610         .read = dp_dsc_slice_width_read,
2611         .write = dp_dsc_slice_width_write,
2612         .llseek = default_llseek
2613 };
2614
2615 static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
2616         .owner = THIS_MODULE,
2617         .read = dp_dsc_slice_height_read,
2618         .write = dp_dsc_slice_height_write,
2619         .llseek = default_llseek
2620 };
2621
2622 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
2623         .owner = THIS_MODULE,
2624         .read = dp_dsc_bits_per_pixel_read,
2625         .write = dp_dsc_bits_per_pixel_write,
2626         .llseek = default_llseek
2627 };
2628
2629 static const struct file_operations dp_dsc_pic_width_debugfs_fops = {
2630         .owner = THIS_MODULE,
2631         .read = dp_dsc_pic_width_read,
2632         .llseek = default_llseek
2633 };
2634
2635 static const struct file_operations dp_dsc_pic_height_debugfs_fops = {
2636         .owner = THIS_MODULE,
2637         .read = dp_dsc_pic_height_read,
2638         .llseek = default_llseek
2639 };
2640
2641 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = {
2642         .owner = THIS_MODULE,
2643         .read = dp_dsc_chunk_size_read,
2644         .llseek = default_llseek
2645 };
2646
2647 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = {
2648         .owner = THIS_MODULE,
2649         .read = dp_dsc_slice_bpg_offset_read,
2650         .llseek = default_llseek
2651 };
2652
2653 static const struct file_operations trigger_hotplug_debugfs_fops = {
2654         .owner = THIS_MODULE,
2655         .write = trigger_hotplug,
2656         .llseek = default_llseek
2657 };
2658
2659 static const struct file_operations dp_link_settings_debugfs_fops = {
2660         .owner = THIS_MODULE,
2661         .read = dp_link_settings_read,
2662         .write = dp_link_settings_write,
2663         .llseek = default_llseek
2664 };
2665
2666 static const struct file_operations dp_phy_settings_debugfs_fop = {
2667         .owner = THIS_MODULE,
2668         .read = dp_phy_settings_read,
2669         .write = dp_phy_settings_write,
2670         .llseek = default_llseek
2671 };
2672
2673 static const struct file_operations dp_phy_test_pattern_fops = {
2674         .owner = THIS_MODULE,
2675         .write = dp_phy_test_pattern_debugfs_write,
2676         .llseek = default_llseek
2677 };
2678
2679 static const struct file_operations sdp_message_fops = {
2680         .owner = THIS_MODULE,
2681         .write = dp_sdp_message_debugfs_write,
2682         .llseek = default_llseek
2683 };
2684
2685 static const struct file_operations dp_dpcd_address_debugfs_fops = {
2686         .owner = THIS_MODULE,
2687         .write = dp_dpcd_address_write,
2688         .llseek = default_llseek
2689 };
2690
2691 static const struct file_operations dp_dpcd_size_debugfs_fops = {
2692         .owner = THIS_MODULE,
2693         .write = dp_dpcd_size_write,
2694         .llseek = default_llseek
2695 };
2696
2697 static const struct file_operations dp_dpcd_data_debugfs_fops = {
2698         .owner = THIS_MODULE,
2699         .read = dp_dpcd_data_read,
2700         .write = dp_dpcd_data_write,
2701         .llseek = default_llseek
2702 };
2703
2704 static const struct file_operations dp_max_bpc_debugfs_fops = {
2705         .owner = THIS_MODULE,
2706         .read = dp_max_bpc_read,
2707         .write = dp_max_bpc_write,
2708         .llseek = default_llseek
2709 };
2710
2711 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
2712         .owner = THIS_MODULE,
2713         .write = dp_dsc_passthrough_set,
2714         .llseek = default_llseek
2715 };
2716
2717 static const struct {
2718         char *name;
2719         const struct file_operations *fops;
2720 } dp_debugfs_entries[] = {
2721                 {"link_settings", &dp_link_settings_debugfs_fops},
2722                 {"phy_settings", &dp_phy_settings_debugfs_fop},
2723                 {"lttpr_status", &dp_lttpr_status_fops},
2724                 {"test_pattern", &dp_phy_test_pattern_fops},
2725                 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
2726                 {"sdp_message", &sdp_message_fops},
2727                 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops},
2728                 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops},
2729                 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops},
2730                 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops},
2731                 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops},
2732                 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops},
2733                 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops},
2734                 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops},
2735                 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops},
2736                 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
2737                 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
2738                 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
2739                 {"max_bpc", &dp_max_bpc_debugfs_fops},
2740                 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops},
2741                 {"is_mst_connector", &dp_is_mst_connector_fops},
2742                 {"mst_progress_status", &dp_mst_progress_status_fops},
2743                 {"is_dpia_link", &is_dpia_link_fops}
2744 };
2745
2746 static const struct {
2747         char *name;
2748         const struct file_operations *fops;
2749 } hdmi_debugfs_entries[] = {
2750                 {"hdcp_sink_capability", &hdcp_sink_capability_fops}
2751 };
2752
2753 /*
2754  * Force YUV420 output if available from the given mode
2755  */
2756 static int force_yuv420_output_set(void *data, u64 val)
2757 {
2758         struct amdgpu_dm_connector *connector = data;
2759
2760         connector->force_yuv420_output = (bool)val;
2761
2762         return 0;
2763 }
2764
2765 /*
2766  * Check if YUV420 is forced when available from the given mode
2767  */
2768 static int force_yuv420_output_get(void *data, u64 *val)
2769 {
2770         struct amdgpu_dm_connector *connector = data;
2771
2772         *val = connector->force_yuv420_output;
2773
2774         return 0;
2775 }
2776
2777 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
2778                          force_yuv420_output_set, "%llu\n");
2779
2780 /*
2781  *  Read PSR state
2782  */
2783 static int psr_get(void *data, u64 *val)
2784 {
2785         struct amdgpu_dm_connector *connector = data;
2786         struct dc_link *link = connector->dc_link;
2787         enum dc_psr_state state = PSR_STATE0;
2788
2789         dc_link_get_psr_state(link, &state);
2790
2791         *val = state;
2792
2793         return 0;
2794 }
2795
2796 /*
2797  *  Read PSR state residency
2798  */
2799 static int psr_read_residency(void *data, u64 *val)
2800 {
2801         struct amdgpu_dm_connector *connector = data;
2802         struct dc_link *link = connector->dc_link;
2803         u32 residency;
2804
2805         link->dc->link_srv->edp_get_psr_residency(link, &residency);
2806
2807         *val = (u64)residency;
2808
2809         return 0;
2810 }
2811
2812 /*
2813  * Set dmcub trace event IRQ enable or disable.
2814  * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2815  * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2816  */
2817 static int dmcub_trace_event_state_set(void *data, u64 val)
2818 {
2819         struct amdgpu_device *adev = data;
2820
2821         if (val == 1 || val == 0) {
2822                 dc_dmub_trace_event_control(adev->dm.dc, val);
2823                 adev->dm.dmcub_trace_event_en = (bool)val;
2824         } else
2825                 return 0;
2826
2827         return 0;
2828 }
2829
2830 /*
2831  * The interface doesn't need get function, so it will return the
2832  * value of zero
2833  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2834  */
2835 static int dmcub_trace_event_state_get(void *data, u64 *val)
2836 {
2837         struct amdgpu_device *adev = data;
2838
2839         *val = adev->dm.dmcub_trace_event_en;
2840         return 0;
2841 }
2842
2843 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get,
2844                          dmcub_trace_event_state_set, "%llu\n");
2845
2846 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
2847 DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL,
2848                          "%llu\n");
2849
2850 DEFINE_SHOW_ATTRIBUTE(current_backlight);
2851 DEFINE_SHOW_ATTRIBUTE(target_backlight);
2852
2853 static const struct {
2854         char *name;
2855         const struct file_operations *fops;
2856 } connector_debugfs_entries[] = {
2857                 {"force_yuv420_output", &force_yuv420_output_fops},
2858                 {"trigger_hotplug", &trigger_hotplug_debugfs_fops},
2859                 {"internal_display", &internal_display_fops}
2860 };
2861
2862 /*
2863  * Returns supported customized link rates by this eDP panel.
2864  * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting
2865  */
2866 static int edp_ilr_show(struct seq_file *m, void *unused)
2867 {
2868         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2869         struct dc_link *link = aconnector->dc_link;
2870         uint8_t supported_link_rates[16];
2871         uint32_t link_rate_in_khz;
2872         uint32_t entry = 0;
2873         uint8_t dpcd_rev;
2874
2875         memset(supported_link_rates, 0, sizeof(supported_link_rates));
2876         dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES,
2877                 supported_link_rates, sizeof(supported_link_rates));
2878
2879         dpcd_rev = link->dpcd_caps.dpcd_rev.raw;
2880
2881         if (dpcd_rev >= DP_DPCD_REV_13 &&
2882                 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) {
2883
2884                 for (entry = 0; entry < 16; entry += 2) {
2885                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
2886                                                                                 supported_link_rates[entry]) * 200;
2887                         seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz);
2888                 }
2889         } else {
2890                 seq_printf(m, "ILR is not supported by this eDP panel.\n");
2891         }
2892
2893         return 0;
2894 }
2895
2896 /*
2897  * Set supported customized link rate to eDP panel.
2898  *
2899  * echo <lane_count>  <link_rate option> > ilr_setting
2900  *
2901  * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ...
2902  * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting
2903  * to set 4 lanes and 2.16 GHz
2904  */
2905 static ssize_t edp_ilr_write(struct file *f, const char __user *buf,
2906                                  size_t size, loff_t *pos)
2907 {
2908         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
2909         struct dc_link *link = connector->dc_link;
2910         struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
2911         struct dc *dc = (struct dc *)link->dc;
2912         struct dc_link_settings prefer_link_settings;
2913         char *wr_buf = NULL;
2914         const uint32_t wr_buf_size = 40;
2915         /* 0: lane_count; 1: link_rate */
2916         int max_param_num = 2;
2917         uint8_t param_nums = 0;
2918         long param[2];
2919         bool valid_input = true;
2920
2921         if (size == 0)
2922                 return -EINVAL;
2923
2924         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2925         if (!wr_buf)
2926                 return -ENOMEM;
2927
2928         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2929                                            (long *)param, buf,
2930                                            max_param_num,
2931                                            &param_nums)) {
2932                 kfree(wr_buf);
2933                 return -EINVAL;
2934         }
2935
2936         if (param_nums <= 0) {
2937                 kfree(wr_buf);
2938                 return -EINVAL;
2939         }
2940
2941         switch (param[0]) {
2942         case LANE_COUNT_ONE:
2943         case LANE_COUNT_TWO:
2944         case LANE_COUNT_FOUR:
2945                 break;
2946         default:
2947                 valid_input = false;
2948                 break;
2949         }
2950
2951         if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count)
2952                 valid_input = false;
2953
2954         if (!valid_input) {
2955                 kfree(wr_buf);
2956                 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n");
2957                 prefer_link_settings.use_link_rate_set = false;
2958                 mutex_lock(&adev->dm.dc_lock);
2959                 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
2960                 mutex_unlock(&adev->dm.dc_lock);
2961                 return size;
2962         }
2963
2964         /* save user force lane_count, link_rate to preferred settings
2965          * spread spectrum will not be changed
2966          */
2967         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
2968         prefer_link_settings.lane_count = param[0];
2969         prefer_link_settings.use_link_rate_set = true;
2970         prefer_link_settings.link_rate_set = param[1];
2971         prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]];
2972
2973         mutex_lock(&adev->dm.dc_lock);
2974         dc_link_set_preferred_training_settings(dc, &prefer_link_settings,
2975                                                 NULL, link, false);
2976         mutex_unlock(&adev->dm.dc_lock);
2977
2978         kfree(wr_buf);
2979         return size;
2980 }
2981
2982 static int edp_ilr_open(struct inode *inode, struct file *file)
2983 {
2984         return single_open(file, edp_ilr_show, inode->i_private);
2985 }
2986
2987 static const struct file_operations edp_ilr_debugfs_fops = {
2988         .owner = THIS_MODULE,
2989         .open = edp_ilr_open,
2990         .read = seq_read,
2991         .llseek = seq_lseek,
2992         .release = single_release,
2993         .write = edp_ilr_write
2994 };
2995
2996 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
2997 {
2998         int i;
2999         struct dentry *dir = connector->base.debugfs_entry;
3000
3001         if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3002             connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3003                 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
3004                         debugfs_create_file(dp_debugfs_entries[i].name,
3005                                             0644, dir, connector,
3006                                             dp_debugfs_entries[i].fops);
3007                 }
3008         }
3009         if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3010                 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops);
3011                 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
3012                 debugfs_create_file_unsafe("psr_residency", 0444, dir,
3013                                            connector, &psr_residency_fops);
3014                 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector,
3015                                     &current_backlight_fops);
3016                 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector,
3017                                     &target_backlight_fops);
3018                 debugfs_create_file("ilr_setting", 0644, dir, connector,
3019                                         &edp_ilr_debugfs_fops);
3020         }
3021
3022         for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
3023                 debugfs_create_file(connector_debugfs_entries[i].name,
3024                                     0644, dir, connector,
3025                                     connector_debugfs_entries[i].fops);
3026         }
3027
3028         connector->debugfs_dpcd_address = 0;
3029         connector->debugfs_dpcd_size = 0;
3030
3031         if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
3032                 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {
3033                         debugfs_create_file(hdmi_debugfs_entries[i].name,
3034                                             0644, dir, connector,
3035                                             hdmi_debugfs_entries[i].fops);
3036                 }
3037         }
3038 }
3039
3040 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3041 /*
3042  * Set crc window coordinate x start
3043  */
3044 static int crc_win_x_start_set(void *data, u64 val)
3045 {
3046         struct drm_crtc *crtc = data;
3047         struct drm_device *drm_dev = crtc->dev;
3048         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3049
3050         spin_lock_irq(&drm_dev->event_lock);
3051         acrtc->dm_irq_params.window_param.x_start = (uint16_t) val;
3052         acrtc->dm_irq_params.window_param.update_win = false;
3053         spin_unlock_irq(&drm_dev->event_lock);
3054
3055         return 0;
3056 }
3057
3058 /*
3059  * Get crc window coordinate x start
3060  */
3061 static int crc_win_x_start_get(void *data, u64 *val)
3062 {
3063         struct drm_crtc *crtc = data;
3064         struct drm_device *drm_dev = crtc->dev;
3065         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3066
3067         spin_lock_irq(&drm_dev->event_lock);
3068         *val = acrtc->dm_irq_params.window_param.x_start;
3069         spin_unlock_irq(&drm_dev->event_lock);
3070
3071         return 0;
3072 }
3073
3074 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get,
3075                          crc_win_x_start_set, "%llu\n");
3076
3077
3078 /*
3079  * Set crc window coordinate y start
3080  */
3081 static int crc_win_y_start_set(void *data, u64 val)
3082 {
3083         struct drm_crtc *crtc = data;
3084         struct drm_device *drm_dev = crtc->dev;
3085         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3086
3087         spin_lock_irq(&drm_dev->event_lock);
3088         acrtc->dm_irq_params.window_param.y_start = (uint16_t) val;
3089         acrtc->dm_irq_params.window_param.update_win = false;
3090         spin_unlock_irq(&drm_dev->event_lock);
3091
3092         return 0;
3093 }
3094
3095 /*
3096  * Get crc window coordinate y start
3097  */
3098 static int crc_win_y_start_get(void *data, u64 *val)
3099 {
3100         struct drm_crtc *crtc = data;
3101         struct drm_device *drm_dev = crtc->dev;
3102         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3103
3104         spin_lock_irq(&drm_dev->event_lock);
3105         *val = acrtc->dm_irq_params.window_param.y_start;
3106         spin_unlock_irq(&drm_dev->event_lock);
3107
3108         return 0;
3109 }
3110
3111 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get,
3112                          crc_win_y_start_set, "%llu\n");
3113
3114 /*
3115  * Set crc window coordinate x end
3116  */
3117 static int crc_win_x_end_set(void *data, u64 val)
3118 {
3119         struct drm_crtc *crtc = data;
3120         struct drm_device *drm_dev = crtc->dev;
3121         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3122
3123         spin_lock_irq(&drm_dev->event_lock);
3124         acrtc->dm_irq_params.window_param.x_end = (uint16_t) val;
3125         acrtc->dm_irq_params.window_param.update_win = false;
3126         spin_unlock_irq(&drm_dev->event_lock);
3127
3128         return 0;
3129 }
3130
3131 /*
3132  * Get crc window coordinate x end
3133  */
3134 static int crc_win_x_end_get(void *data, u64 *val)
3135 {
3136         struct drm_crtc *crtc = data;
3137         struct drm_device *drm_dev = crtc->dev;
3138         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3139
3140         spin_lock_irq(&drm_dev->event_lock);
3141         *val = acrtc->dm_irq_params.window_param.x_end;
3142         spin_unlock_irq(&drm_dev->event_lock);
3143
3144         return 0;
3145 }
3146
3147 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get,
3148                          crc_win_x_end_set, "%llu\n");
3149
3150 /*
3151  * Set crc window coordinate y end
3152  */
3153 static int crc_win_y_end_set(void *data, u64 val)
3154 {
3155         struct drm_crtc *crtc = data;
3156         struct drm_device *drm_dev = crtc->dev;
3157         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3158
3159         spin_lock_irq(&drm_dev->event_lock);
3160         acrtc->dm_irq_params.window_param.y_end = (uint16_t) val;
3161         acrtc->dm_irq_params.window_param.update_win = false;
3162         spin_unlock_irq(&drm_dev->event_lock);
3163
3164         return 0;
3165 }
3166
3167 /*
3168  * Get crc window coordinate y end
3169  */
3170 static int crc_win_y_end_get(void *data, u64 *val)
3171 {
3172         struct drm_crtc *crtc = data;
3173         struct drm_device *drm_dev = crtc->dev;
3174         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3175
3176         spin_lock_irq(&drm_dev->event_lock);
3177         *val = acrtc->dm_irq_params.window_param.y_end;
3178         spin_unlock_irq(&drm_dev->event_lock);
3179
3180         return 0;
3181 }
3182
3183 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get,
3184                          crc_win_y_end_set, "%llu\n");
3185 /*
3186  * Trigger to commit crc window
3187  */
3188 static int crc_win_update_set(void *data, u64 val)
3189 {
3190         struct drm_crtc *crtc = data;
3191         struct amdgpu_crtc *acrtc;
3192         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
3193
3194         if (val) {
3195                 acrtc = to_amdgpu_crtc(crtc);
3196                 mutex_lock(&adev->dm.dc_lock);
3197                 /* PSR may write to OTG CRC window control register,
3198                  * so close it before starting secure_display.
3199                  */
3200                 amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream);
3201
3202                 spin_lock_irq(&adev_to_drm(adev)->event_lock);
3203
3204                 acrtc->dm_irq_params.window_param.activated = true;
3205                 acrtc->dm_irq_params.window_param.update_win = true;
3206                 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
3207
3208                 spin_unlock_irq(&adev_to_drm(adev)->event_lock);
3209                 mutex_unlock(&adev->dm.dc_lock);
3210         }
3211
3212         return 0;
3213 }
3214
3215 /*
3216  * Get crc window update flag
3217  */
3218 static int crc_win_update_get(void *data, u64 *val)
3219 {
3220         *val = 0;
3221         return 0;
3222 }
3223
3224 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get,
3225                          crc_win_update_set, "%llu\n");
3226 #endif
3227 void crtc_debugfs_init(struct drm_crtc *crtc)
3228 {
3229 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3230         struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry);
3231
3232         if (!dir)
3233                 return;
3234
3235         debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc,
3236                                    &crc_win_x_start_fops);
3237         debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc,
3238                                    &crc_win_y_start_fops);
3239         debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc,
3240                                    &crc_win_x_end_fops);
3241         debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc,
3242                                    &crc_win_y_end_fops);
3243         debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc,
3244                                    &crc_win_update_fops);
3245         dput(dir);
3246 #endif
3247         debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry,
3248                             crtc, &amdgpu_current_bpc_fops);
3249 }
3250
3251 /*
3252  * Writes DTN log state to the user supplied buffer.
3253  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3254  */
3255 static ssize_t dtn_log_read(
3256         struct file *f,
3257         char __user *buf,
3258         size_t size,
3259         loff_t *pos)
3260 {
3261         struct amdgpu_device *adev = file_inode(f)->i_private;
3262         struct dc *dc = adev->dm.dc;
3263         struct dc_log_buffer_ctx log_ctx = { 0 };
3264         ssize_t result = 0;
3265
3266         if (!buf || !size)
3267                 return -EINVAL;
3268
3269         if (!dc->hwss.log_hw_state)
3270                 return 0;
3271
3272         dc->hwss.log_hw_state(dc, &log_ctx);
3273
3274         if (*pos < log_ctx.pos) {
3275                 size_t to_copy = log_ctx.pos - *pos;
3276
3277                 to_copy = min(to_copy, size);
3278
3279                 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) {
3280                         *pos += to_copy;
3281                         result = to_copy;
3282                 }
3283         }
3284
3285         kfree(log_ctx.buf);
3286
3287         return result;
3288 }
3289
3290 /*
3291  * Writes DTN log state to dmesg when triggered via a write.
3292  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3293  */
3294 static ssize_t dtn_log_write(
3295         struct file *f,
3296         const char __user *buf,
3297         size_t size,
3298         loff_t *pos)
3299 {
3300         struct amdgpu_device *adev = file_inode(f)->i_private;
3301         struct dc *dc = adev->dm.dc;
3302
3303         /* Write triggers log output via dmesg. */
3304         if (size == 0)
3305                 return 0;
3306
3307         if (dc->hwss.log_hw_state)
3308                 dc->hwss.log_hw_state(dc, NULL);
3309
3310         return size;
3311 }
3312
3313 static int mst_topo_show(struct seq_file *m, void *unused)
3314 {
3315         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3316         struct drm_device *dev = adev_to_drm(adev);
3317         struct drm_connector *connector;
3318         struct drm_connector_list_iter conn_iter;
3319         struct amdgpu_dm_connector *aconnector;
3320
3321         drm_connector_list_iter_begin(dev, &conn_iter);
3322         drm_for_each_connector_iter(connector, &conn_iter) {
3323                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3324                         continue;
3325
3326                 aconnector = to_amdgpu_dm_connector(connector);
3327
3328                 /* Ensure we're only dumping the topology of a root mst node */
3329                 if (!aconnector->mst_mgr.mst_state)
3330                         continue;
3331
3332                 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
3333                 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
3334         }
3335         drm_connector_list_iter_end(&conn_iter);
3336
3337         return 0;
3338 }
3339
3340 /*
3341  * Sets trigger hpd for MST topologies.
3342  * All connected connectors will be rediscovered and re started as needed if val of 1 is sent.
3343  * All topologies will be disconnected if val of 0 is set .
3344  * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3345  * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3346  */
3347 static int trigger_hpd_mst_set(void *data, u64 val)
3348 {
3349         struct amdgpu_device *adev = data;
3350         struct drm_device *dev = adev_to_drm(adev);
3351         struct drm_connector_list_iter iter;
3352         struct amdgpu_dm_connector *aconnector;
3353         struct drm_connector *connector;
3354         struct dc_link *link = NULL;
3355
3356         if (val == 1) {
3357                 drm_connector_list_iter_begin(dev, &iter);
3358                 drm_for_each_connector_iter(connector, &iter) {
3359                         aconnector = to_amdgpu_dm_connector(connector);
3360                         if (aconnector->dc_link->type == dc_connection_mst_branch &&
3361                             aconnector->mst_mgr.aux) {
3362                                 mutex_lock(&adev->dm.dc_lock);
3363                                 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3364                                 mutex_unlock(&adev->dm.dc_lock);
3365
3366                                 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
3367                         }
3368                 }
3369         } else if (val == 0) {
3370                 drm_connector_list_iter_begin(dev, &iter);
3371                 drm_for_each_connector_iter(connector, &iter) {
3372                         aconnector = to_amdgpu_dm_connector(connector);
3373                         if (!aconnector->dc_link)
3374                                 continue;
3375
3376                         if (!aconnector->mst_root)
3377                                 continue;
3378
3379                         link = aconnector->dc_link;
3380                         dc_link_dp_receiver_power_ctrl(link, false);
3381                         drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_root->mst_mgr, false);
3382                         link->mst_stream_alloc_table.stream_count = 0;
3383                         memset(link->mst_stream_alloc_table.stream_allocations, 0,
3384                                         sizeof(link->mst_stream_alloc_table.stream_allocations));
3385                 }
3386         } else {
3387                 return 0;
3388         }
3389         drm_kms_helper_hotplug_event(dev);
3390
3391         return 0;
3392 }
3393
3394 /*
3395  * The interface doesn't need get function, so it will return the
3396  * value of zero
3397  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3398  */
3399 static int trigger_hpd_mst_get(void *data, u64 *val)
3400 {
3401         *val = 0;
3402         return 0;
3403 }
3404
3405 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get,
3406                          trigger_hpd_mst_set, "%llu\n");
3407
3408
3409 /*
3410  * Sets the force_timing_sync debug option from the given string.
3411  * All connected displays will be force synchronized immediately.
3412  * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3413  */
3414 static int force_timing_sync_set(void *data, u64 val)
3415 {
3416         struct amdgpu_device *adev = data;
3417
3418         adev->dm.force_timing_sync = (bool)val;
3419
3420         amdgpu_dm_trigger_timing_sync(adev_to_drm(adev));
3421
3422         return 0;
3423 }
3424
3425 /*
3426  * Gets the force_timing_sync debug option value into the given buffer.
3427  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3428  */
3429 static int force_timing_sync_get(void *data, u64 *val)
3430 {
3431         struct amdgpu_device *adev = data;
3432
3433         *val = adev->dm.force_timing_sync;
3434
3435         return 0;
3436 }
3437
3438 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get,
3439                          force_timing_sync_set, "%llu\n");
3440
3441
3442 /*
3443  * Disables all HPD and HPD RX interrupt handling in the
3444  * driver when set to 1. Default is 0.
3445  */
3446 static int disable_hpd_set(void *data, u64 val)
3447 {
3448         struct amdgpu_device *adev = data;
3449
3450         adev->dm.disable_hpd_irq = (bool)val;
3451
3452         return 0;
3453 }
3454
3455
3456 /*
3457  * Returns 1 if HPD and HPRX interrupt handling is disabled,
3458  * 0 otherwise.
3459  */
3460 static int disable_hpd_get(void *data, u64 *val)
3461 {
3462         struct amdgpu_device *adev = data;
3463
3464         *val = adev->dm.disable_hpd_irq;
3465
3466         return 0;
3467 }
3468
3469 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
3470                          disable_hpd_set, "%llu\n");
3471
3472 /*
3473  * Temporary w/a to force sst sequence in M42D DP2 mst receiver
3474  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst
3475  */
3476 static int dp_force_sst_set(void *data, u64 val)
3477 {
3478         struct amdgpu_device *adev = data;
3479
3480         adev->dm.dc->debug.set_mst_en_for_sst = val;
3481
3482         return 0;
3483 }
3484
3485 static int dp_force_sst_get(void *data, u64 *val)
3486 {
3487         struct amdgpu_device *adev = data;
3488
3489         *val = adev->dm.dc->debug.set_mst_en_for_sst;
3490
3491         return 0;
3492 }
3493 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get,
3494                          dp_force_sst_set, "%llu\n");
3495
3496 /*
3497  * Force DP2 sequence without VESA certified cable.
3498  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id
3499  */
3500 static int dp_ignore_cable_id_set(void *data, u64 val)
3501 {
3502         struct amdgpu_device *adev = data;
3503
3504         adev->dm.dc->debug.ignore_cable_id = val;
3505
3506         return 0;
3507 }
3508
3509 static int dp_ignore_cable_id_get(void *data, u64 *val)
3510 {
3511         struct amdgpu_device *adev = data;
3512
3513         *val = adev->dm.dc->debug.ignore_cable_id;
3514
3515         return 0;
3516 }
3517 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get,
3518                          dp_ignore_cable_id_set, "%llu\n");
3519
3520 /*
3521  * Sets the DC visual confirm debug option from the given string.
3522  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
3523  */
3524 static int visual_confirm_set(void *data, u64 val)
3525 {
3526         struct amdgpu_device *adev = data;
3527
3528         adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
3529
3530         return 0;
3531 }
3532
3533 /*
3534  * Reads the DC visual confirm debug option value into the given buffer.
3535  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
3536  */
3537 static int visual_confirm_get(void *data, u64 *val)
3538 {
3539         struct amdgpu_device *adev = data;
3540
3541         *val = adev->dm.dc->debug.visual_confirm;
3542
3543         return 0;
3544 }
3545
3546 DEFINE_SHOW_ATTRIBUTE(mst_topo);
3547 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
3548                          visual_confirm_set, "%llu\n");
3549
3550
3551 /*
3552  * Sets the DC skip_detection_link_training debug option from the given string.
3553  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training
3554  */
3555 static int skip_detection_link_training_set(void *data, u64 val)
3556 {
3557         struct amdgpu_device *adev = data;
3558
3559         if (val == 0)
3560                 adev->dm.dc->debug.skip_detection_link_training = false;
3561         else
3562                 adev->dm.dc->debug.skip_detection_link_training = true;
3563
3564         return 0;
3565 }
3566
3567 /*
3568  * Reads the DC skip_detection_link_training debug option value into the given buffer.
3569  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training
3570  */
3571 static int skip_detection_link_training_get(void *data, u64 *val)
3572 {
3573         struct amdgpu_device *adev = data;
3574
3575         *val = adev->dm.dc->debug.skip_detection_link_training;
3576
3577         return 0;
3578 }
3579
3580 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops,
3581                          skip_detection_link_training_get,
3582                          skip_detection_link_training_set, "%llu\n");
3583
3584 /*
3585  * Dumps the DCC_EN bit for each pipe.
3586  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
3587  */
3588 static ssize_t dcc_en_bits_read(
3589         struct file *f,
3590         char __user *buf,
3591         size_t size,
3592         loff_t *pos)
3593 {
3594         struct amdgpu_device *adev = file_inode(f)->i_private;
3595         struct dc *dc = adev->dm.dc;
3596         char *rd_buf = NULL;
3597         const uint32_t rd_buf_size = 32;
3598         uint32_t result = 0;
3599         int offset = 0;
3600         int num_pipes = dc->res_pool->pipe_count;
3601         int *dcc_en_bits;
3602         int i, r;
3603
3604         dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL);
3605         if (!dcc_en_bits)
3606                 return -ENOMEM;
3607
3608         if (!dc->hwss.get_dcc_en_bits) {
3609                 kfree(dcc_en_bits);
3610                 return 0;
3611         }
3612
3613         dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
3614
3615         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
3616         if (!rd_buf) {
3617                 kfree(dcc_en_bits);
3618                 return -ENOMEM;
3619         }
3620
3621         for (i = 0; i < num_pipes; i++)
3622                 offset += snprintf(rd_buf + offset, rd_buf_size - offset,
3623                                    "%d  ", dcc_en_bits[i]);
3624         rd_buf[strlen(rd_buf)] = '\n';
3625
3626         kfree(dcc_en_bits);
3627
3628         while (size) {
3629                 if (*pos >= rd_buf_size)
3630                         break;
3631                 r = put_user(*(rd_buf + result), buf);
3632                 if (r) {
3633                         kfree(rd_buf);
3634                         return r; /* r = -EFAULT */
3635                 }
3636                 buf += 1;
3637                 size -= 1;
3638                 *pos += 1;
3639                 result += 1;
3640         }
3641
3642         kfree(rd_buf);
3643         return result;
3644 }
3645
3646 void dtn_debugfs_init(struct amdgpu_device *adev)
3647 {
3648         static const struct file_operations dtn_log_fops = {
3649                 .owner = THIS_MODULE,
3650                 .read = dtn_log_read,
3651                 .write = dtn_log_write,
3652                 .llseek = default_llseek
3653         };
3654         static const struct file_operations dcc_en_bits_fops = {
3655                 .owner = THIS_MODULE,
3656                 .read = dcc_en_bits_read,
3657                 .llseek = default_llseek
3658         };
3659
3660         struct drm_minor *minor = adev_to_drm(adev)->primary;
3661         struct dentry *root = minor->debugfs_root;
3662
3663         debugfs_create_file("amdgpu_mst_topology", 0444, root,
3664                             adev, &mst_topo_fops);
3665         debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
3666                             &dtn_log_fops);
3667         debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev,
3668                                 &dp_set_mst_en_for_sst_ops);
3669         debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev,
3670                                 &dp_ignore_cable_id_ops);
3671
3672         debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
3673                                    &visual_confirm_fops);
3674
3675         debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev,
3676                                    &skip_detection_link_training_fops);
3677
3678         debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
3679                                    adev, &dmub_tracebuffer_fops);
3680
3681         debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root,
3682                                    adev, &dmub_fw_state_fops);
3683
3684         debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
3685                                    adev, &force_timing_sync_ops);
3686
3687         debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
3688                                    adev, &dmcub_trace_event_state_fops);
3689
3690         debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root,
3691                                    adev, &trigger_hpd_mst_ops);
3692
3693         debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev,
3694                                    &dcc_en_bits_fops);
3695
3696         debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
3697                                    &disable_hpd_ops);
3698
3699 }