drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27 #include <linux/pagemap.h>
  28 #include <linux/sync_file.h>
  29 #include <drm/drmP.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_syncobj.h>
  32 #include "amdgpu.h"
  33 #include "amdgpu_trace.h"
  34 #include "amdgpu_gmc.h"
  35 #include "amdgpu_gem.h"
  36
  37 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  38                                       struct drm_amdgpu_cs_chunk_fence *data,
  39                                       uint32_t *offset)
  40 {
  41         struct drm_gem_object *gobj;
  42         struct amdgpu_bo *bo;
  43         unsigned long size;
  44         int r;
  45
  46         gobj = drm_gem_object_lookup(p->filp, data->handle);
  47         if (gobj == NULL)
  48                 return -EINVAL;
  49
  50         bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  51         p->uf_entry.priority = 0;
  52         p->uf_entry.tv.bo = &bo->tbo;
  53         /* One for TTM and one for the CS job */
  54         p->uf_entry.tv.num_shared = 2;
  55
  56         drm_gem_object_put_unlocked(gobj);
  57
  58         size = amdgpu_bo_size(bo);
  59         if (size != PAGE_SIZE || (data->offset + 8) > size) {
  60                 r = -EINVAL;
  61                 goto error_unref;
  62         }
  63
  64         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
  65                 r = -EINVAL;
  66                 goto error_unref;
  67         }
  68
  69         *offset = data->offset;
  70
  71         return 0;
  72
  73 error_unref:
  74         amdgpu_bo_unref(&bo);
  75         return r;
  76 }
  77
  78 static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p,
  79                                       struct drm_amdgpu_bo_list_in *data)
  80 {
  81         int r;
  82         struct drm_amdgpu_bo_list_entry *info = NULL;
  83
  84         r = amdgpu_bo_create_list_entry_array(data, &info);
  85         if (r)
  86                 return r;
  87
  88         r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
  89                                   &p->bo_list);
  90         if (r)
  91                 goto error_free;
  92
  93         kvfree(info);
  94         return 0;
  95
  96 error_free:
  97         if (info)
  98                 kvfree(info);
  99
 100         return r;
 101 }
 102
 103 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs)
 104 {
 105         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 106         struct amdgpu_vm *vm = &fpriv->vm;
 107         uint64_t *chunk_array_user;
 108         uint64_t *chunk_array;
 109         unsigned size, num_ibs = 0;
 110         uint32_t uf_offset = 0;
 111         int i;
 112         int ret;
 113
 114         if (cs->in.num_chunks == 0)
 115                 return 0;
 116
 117         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 118         if (!chunk_array)
 119                 return -ENOMEM;
 120
 121         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 122         if (!p->ctx) {
 123                 ret = -EINVAL;
 124                 goto free_chunk;
 125         }
 126
 127         mutex_lock(&p->ctx->lock);
 128
 129         /* skip guilty context job */
 130         if (atomic_read(&p->ctx->guilty) == 1) {
 131                 ret = -ECANCELED;
 132                 goto free_chunk;
 133         }
 134
 135         /* get chunks */
 136         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
 137         if (copy_from_user(chunk_array, chunk_array_user,
 138                            sizeof(uint64_t)*cs->in.num_chunks)) {
 139                 ret = -EFAULT;
 140                 goto free_chunk;
 141         }
 142
 143         p->nchunks = cs->in.num_chunks;
 144         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 145                             GFP_KERNEL);
 146         if (!p->chunks) {
 147                 ret = -ENOMEM;
 148                 goto free_chunk;
 149         }
 150
 151         for (i = 0; i < p->nchunks; i++) {
 152                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 153                 struct drm_amdgpu_cs_chunk user_chunk;
 154                 uint32_t __user *cdata;
 155
 156                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 157                 if (copy_from_user(&user_chunk, chunk_ptr,
 158                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 159                         ret = -EFAULT;
 160                         i--;
 161                         goto free_partial_kdata;
 162                 }
 163                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 164                 p->chunks[i].length_dw = user_chunk.length_dw;
 165
 166                 size = p->chunks[i].length_dw;
 167                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 168
 169                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 170                 if (p->chunks[i].kdata == NULL) {
 171                         ret = -ENOMEM;
 172                         i--;
 173                         goto free_partial_kdata;
 174                 }
 175                 size *= sizeof(uint32_t);
 176                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 177                         ret = -EFAULT;
 178                         goto free_partial_kdata;
 179                 }
 180
 181                 switch (p->chunks[i].chunk_id) {
 182                 case AMDGPU_CHUNK_ID_IB:
 183                         ++num_ibs;
 184                         break;
 185
 186                 case AMDGPU_CHUNK_ID_FENCE:
 187                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 188                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 189                                 ret = -EINVAL;
 190                                 goto free_partial_kdata;
 191                         }
 192
 193                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 194                                                          &uf_offset);
 195                         if (ret)
 196                                 goto free_partial_kdata;
 197
 198                         break;
 199
 200                 case AMDGPU_CHUNK_ID_BO_HANDLES:
 201                         size = sizeof(struct drm_amdgpu_bo_list_in);
 202                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 203                                 ret = -EINVAL;
 204                                 goto free_partial_kdata;
 205                         }
 206
 207                         ret = amdgpu_cs_bo_handles_chunk(p, p->chunks[i].kdata);
 208                         if (ret)
 209                                 goto free_partial_kdata;
 210
 211                         break;
 212
 213                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 214                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 215                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 216                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
 217                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
 218                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
 219                         break;
 220
 221                 default:
 222                         ret = -EINVAL;
 223                         goto free_partial_kdata;
 224                 }
 225         }
 226
 227         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 228         if (ret)
 229                 goto free_all_kdata;
 230
 231         if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
 232                 ret = -ECANCELED;
 233                 goto free_all_kdata;
 234         }
 235
 236         if (p->uf_entry.tv.bo)
 237                 p->job->uf_addr = uf_offset;
 238         kfree(chunk_array);
 239
 240         /* Use this opportunity to fill in task info for the vm */
 241         amdgpu_vm_set_task_info(vm);
 242
 243         return 0;
 244
 245 free_all_kdata:
 246         i = p->nchunks - 1;
 247 free_partial_kdata:
 248         for (; i >= 0; i--)
 249                 kvfree(p->chunks[i].kdata);
 250         kfree(p->chunks);
 251         p->chunks = NULL;
 252         p->nchunks = 0;
 253 free_chunk:
 254         kfree(chunk_array);
 255
 256         return ret;
 257 }
 258
 259 /* Convert microseconds to bytes. */
 260 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 261 {
 262         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 263                 return 0;
 264
 265         /* Since accum_us is incremented by a million per second, just
 266          * multiply it by the number of MB/s to get the number of bytes.
 267          */
 268         return us << adev->mm_stats.log2_max_MBps;
 269 }
 270
 271 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 272 {
 273         if (!adev->mm_stats.log2_max_MBps)
 274                 return 0;
 275
 276         return bytes >> adev->mm_stats.log2_max_MBps;
 277 }
 278
 279 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 280  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 281  * which means it can go over the threshold once. If that happens, the driver
 282  * will be in debt and no other buffer migrations can be done until that debt
 283  * is repaid.
 284  *
 285  * This approach allows moving a buffer of any size (it's important to allow
 286  * that).
 287  *
 288  * The currency is simply time in microseconds and it increases as the clock
 289  * ticks. The accumulated microseconds (us) are converted to bytes and
 290  * returned.
 291  */
 292 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 293                                               u64 *max_bytes,
 294                                               u64 *max_vis_bytes)
 295 {
 296         s64 time_us, increment_us;
 297         u64 free_vram, total_vram, used_vram;
 298
 299         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 300          * throttling.
 301          *
 302          * It means that in order to get full max MBps, at least 5 IBs per
 303          * second must be submitted and not more than 200ms apart from each
 304          * other.
 305          */
 306         const s64 us_upper_bound = 200000;
 307
 308         if (!adev->mm_stats.log2_max_MBps) {
 309                 *max_bytes = 0;
 310                 *max_vis_bytes = 0;
 311                 return;
 312         }
 313
 314         total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
 315         used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 316         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 317
 318         spin_lock(&adev->mm_stats.lock);
 319
 320         /* Increase the amount of accumulated us. */
 321         time_us = ktime_to_us(ktime_get());
 322         increment_us = time_us - adev->mm_stats.last_update_us;
 323         adev->mm_stats.last_update_us = time_us;
 324         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 325                                       us_upper_bound);
 326
 327         /* This prevents the short period of low performance when the VRAM
 328          * usage is low and the driver is in debt or doesn't have enough
 329          * accumulated us to fill VRAM quickly.
 330          *
 331          * The situation can occur in these cases:
 332          * - a lot of VRAM is freed by userspace
 333          * - the presence of a big buffer causes a lot of evictions
 334          *   (solution: split buffers into smaller ones)
 335          *
 336          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 337          * accum_us to a positive number.
 338          */
 339         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 340                 s64 min_us;
 341
 342                 /* Be more aggresive on dGPUs. Try to fill a portion of free
 343                  * VRAM now.
 344                  */
 345                 if (!(adev->flags & AMD_IS_APU))
 346                         min_us = bytes_to_us(adev, free_vram / 4);
 347                 else
 348                         min_us = 0; /* Reset accum_us on APUs. */
 349
 350                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 351         }
 352
 353         /* This is set to 0 if the driver is in debt to disallow (optional)
 354          * buffer moves.
 355          */
 356         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 357
 358         /* Do the same for visible VRAM if half of it is free */
 359         if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
 360                 u64 total_vis_vram = adev->gmc.visible_vram_size;
 361                 u64 used_vis_vram =
 362                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 363
 364                 if (used_vis_vram < total_vis_vram) {
 365                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 366                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 367                                                           increment_us, us_upper_bound);
 368
 369                         if (free_vis_vram >= total_vis_vram / 2)
 370                                 adev->mm_stats.accum_us_vis =
 371                                         max(bytes_to_us(adev, free_vis_vram / 2),
 372                                             adev->mm_stats.accum_us_vis);
 373                 }
 374
 375                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 376         } else {
 377                 *max_vis_bytes = 0;
 378         }
 379
 380         spin_unlock(&adev->mm_stats.lock);
 381 }
 382
 383 /* Report how many bytes have really been moved for the last command
 384  * submission. This can result in a debt that can stop buffer migrations
 385  * temporarily.
 386  */
 387 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 388                                   u64 num_vis_bytes)
 389 {
 390         spin_lock(&adev->mm_stats.lock);
 391         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 392         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 393         spin_unlock(&adev->mm_stats.lock);
 394 }
 395
 396 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 397                                  struct amdgpu_bo *bo)
 398 {
 399         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 400         struct ttm_operation_ctx ctx = {
 401                 .interruptible = true,
 402                 .no_wait_gpu = false,
 403                 .resv = bo->tbo.resv,
 404                 .flags = 0
 405         };
 406         uint32_t domain;
 407         int r;
 408
 409         if (bo->pin_count)
 410                 return 0;
 411
 412         /* Don't move this buffer if we have depleted our allowance
 413          * to move it. Don't move anything if the threshold is zero.
 414          */
 415         if (p->bytes_moved < p->bytes_moved_threshold) {
 416                 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 417                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 418                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 419                          * visible VRAM if we've depleted our allowance to do
 420                          * that.
 421                          */
 422                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 423                                 domain = bo->preferred_domains;
 424                         else
 425                                 domain = bo->allowed_domains;
 426                 } else {
 427                         domain = bo->preferred_domains;
 428                 }
 429         } else {
 430                 domain = bo->allowed_domains;
 431         }
 432
 433 retry:
 434         amdgpu_bo_placement_from_domain(bo, domain);
 435         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 436
 437         p->bytes_moved += ctx.bytes_moved;
 438         if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 439             amdgpu_bo_in_cpu_visible_vram(bo))
 440                 p->bytes_moved_vis += ctx.bytes_moved;
 441
 442         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 443                 domain = bo->allowed_domains;
 444                 goto retry;
 445         }
 446
 447         return r;
 448 }
 449
 450 /* Last resort, try to evict something from the current working set */
 451 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
 452                                 struct amdgpu_bo *validated)
 453 {
 454         uint32_t domain = validated->allowed_domains;
 455         struct ttm_operation_ctx ctx = { true, false };
 456         int r;
 457
 458         if (!p->evictable)
 459                 return false;
 460
 461         for (;&p->evictable->tv.head != &p->validated;
 462              p->evictable = list_prev_entry(p->evictable, tv.head)) {
 463
 464                 struct amdgpu_bo_list_entry *candidate = p->evictable;
 465                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(candidate->tv.bo);
 466                 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 467                 bool update_bytes_moved_vis;
 468                 uint32_t other;
 469
 470                 /* If we reached our current BO we can forget it */
 471                 if (bo == validated)
 472                         break;
 473
 474                 /* We can't move pinned BOs here */
 475                 if (bo->pin_count)
 476                         continue;
 477
 478                 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 479
 480                 /* Check if this BO is in one of the domains we need space for */
 481                 if (!(other & domain))
 482                         continue;
 483
 484                 /* Check if we can move this BO somewhere else */
 485                 other = bo->allowed_domains & ~domain;
 486                 if (!other)
 487                         continue;
 488
 489                 /* Good we can try to move this BO somewhere else */
 490                 update_bytes_moved_vis =
 491                                 !amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 492                                 amdgpu_bo_in_cpu_visible_vram(bo);
 493                 amdgpu_bo_placement_from_domain(bo, other);
 494                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 495                 p->bytes_moved += ctx.bytes_moved;
 496                 if (update_bytes_moved_vis)
 497                         p->bytes_moved_vis += ctx.bytes_moved;
 498
 499                 if (unlikely(r))
 500                         break;
 501
 502                 p->evictable = list_prev_entry(p->evictable, tv.head);
 503                 list_move(&candidate->tv.head, &p->validated);
 504
 505                 return true;
 506         }
 507
 508         return false;
 509 }
 510
 511 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
 512 {
 513         struct amdgpu_cs_parser *p = param;
 514         int r;
 515
 516         do {
 517                 r = amdgpu_cs_bo_validate(p, bo);
 518         } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
 519         if (r)
 520                 return r;
 521
 522         if (bo->shadow)
 523                 r = amdgpu_cs_bo_validate(p, bo->shadow);
 524
 525         return r;
 526 }
 527
 528 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 529                             struct list_head *validated)
 530 {
 531         struct ttm_operation_ctx ctx = { true, false };
 532         struct amdgpu_bo_list_entry *lobj;
 533         int r;
 534
 535         list_for_each_entry(lobj, validated, tv.head) {
 536                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
 537                 bool binding_userptr = false;
 538                 struct mm_struct *usermm;
 539
 540                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 541                 if (usermm && usermm != current->mm)
 542                         return -EPERM;
 543
 544                 if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) &&
 545                     lobj->user_invalidated && lobj->user_pages) {
 546                         amdgpu_bo_placement_from_domain(bo,
 547                                                         AMDGPU_GEM_DOMAIN_CPU);
 548                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 549                         if (r)
 550                                 return r;
 551
 552                         amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 553                                                      lobj->user_pages);
 554                         binding_userptr = true;
 555                 }
 556
 557                 if (p->evictable == lobj)
 558                         p->evictable = NULL;
 559
 560                 r = amdgpu_cs_validate(p, bo);
 561                 if (r)
 562                         return r;
 563
 564                 if (binding_userptr) {
 565                         kvfree(lobj->user_pages);
 566                         lobj->user_pages = NULL;
 567                 }
 568         }
 569         return 0;
 570 }
 571
 572 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 573                                 union drm_amdgpu_cs *cs)
 574 {
 575         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 576         struct amdgpu_vm *vm = &fpriv->vm;
 577         struct amdgpu_bo_list_entry *e;
 578         struct list_head duplicates;
 579         struct amdgpu_bo *gds;
 580         struct amdgpu_bo *gws;
 581         struct amdgpu_bo *oa;
 582         int r;
 583
 584         INIT_LIST_HEAD(&p->validated);
 585
 586         /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
 587         if (cs->in.bo_list_handle) {
 588                 if (p->bo_list)
 589                         return -EINVAL;
 590
 591                 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
 592                                        &p->bo_list);
 593                 if (r)
 594                         return r;
 595         } else if (!p->bo_list) {
 596                 /* Create a empty bo_list when no handle is provided */
 597                 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
 598                                           &p->bo_list);
 599                 if (r)
 600                         return r;
 601         }
 602
 603         /* One for TTM and one for the CS job */
 604         amdgpu_bo_list_for_each_entry(e, p->bo_list)
 605                 e->tv.num_shared = 2;
 606
 607         amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 608         if (p->bo_list->first_userptr != p->bo_list->num_entries)
 609                 p->mn = amdgpu_mn_get(p->adev, AMDGPU_MN_TYPE_GFX);
 610
 611         INIT_LIST_HEAD(&duplicates);
 612         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 613
 614         if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
 615                 list_add(&p->uf_entry.tv.head, &p->validated);
 616
 617         /* Get userptr backing pages. If pages are updated after registered
 618          * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
 619          * amdgpu_ttm_backend_bind() to flush and invalidate new pages
 620          */
 621         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
 622                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 623                 bool userpage_invalidated = false;
 624                 int i;
 625
 626                 e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,
 627                                         sizeof(struct page *),
 628                                         GFP_KERNEL | __GFP_ZERO);
 629                 if (!e->user_pages) {
 630                         DRM_ERROR("calloc failure\n");
 631                         return -ENOMEM;
 632                 }
 633
 634                 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, e->user_pages);
 635                 if (r) {
 636                         kvfree(e->user_pages);
 637                         e->user_pages = NULL;
 638                         return r;
 639                 }
 640
 641                 for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
 642                         if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
 643                                 userpage_invalidated = true;
 644                                 break;
 645                         }
 646                 }
 647                 e->user_invalidated = userpage_invalidated;
 648         }
 649
 650         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 651                                    &duplicates, false);
 652         if (unlikely(r != 0)) {
 653                 if (r != -ERESTARTSYS)
 654                         DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 655                 goto out;
 656         }
 657
 658         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 659                                           &p->bytes_moved_vis_threshold);
 660         p->bytes_moved = 0;
 661         p->bytes_moved_vis = 0;
 662         p->evictable = list_last_entry(&p->validated,
 663                                        struct amdgpu_bo_list_entry,
 664                                        tv.head);
 665
 666         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 667                                       amdgpu_cs_validate, p);
 668         if (r) {
 669                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 670                 goto error_validate;
 671         }
 672
 673         r = amdgpu_cs_list_validate(p, &duplicates);
 674         if (r)
 675                 goto error_validate;
 676
 677         r = amdgpu_cs_list_validate(p, &p->validated);
 678         if (r)
 679                 goto error_validate;
 680
 681         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 682                                      p->bytes_moved_vis);
 683
 684         gds = p->bo_list->gds_obj;
 685         gws = p->bo_list->gws_obj;
 686         oa = p->bo_list->oa_obj;
 687
 688         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 689                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 690
 691                 /* Make sure we use the exclusive slot for shared BOs */
 692                 if (bo->prime_shared_count)
 693                         e->tv.num_shared = 0;
 694                 e->bo_va = amdgpu_vm_bo_find(vm, bo);
 695         }
 696
 697         if (gds) {
 698                 p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
 699                 p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
 700         }
 701         if (gws) {
 702                 p->job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
 703                 p->job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
 704         }
 705         if (oa) {
 706                 p->job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
 707                 p->job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
 708         }
 709
 710         if (!r && p->uf_entry.tv.bo) {
 711                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo);
 712
 713                 r = amdgpu_ttm_alloc_gart(&uf->tbo);
 714                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 715         }
 716
 717 error_validate:
 718         if (r)
 719                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 720 out:
 721         return r;
 722 }
 723
 724 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 725 {
 726         struct amdgpu_bo_list_entry *e;
 727         int r;
 728
 729         list_for_each_entry(e, &p->validated, tv.head) {
 730                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 731                 struct reservation_object *resv = bo->tbo.resv;
 732
 733                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
 734                                      amdgpu_bo_explicit_sync(bo));
 735
 736                 if (r)
 737                         return r;
 738         }
 739         return 0;
 740 }
 741
 742 /**
 743  * cs_parser_fini() - clean parser states
 744  * @parser:     parser structure holding parsing context.
 745  * @error:      error number
 746  *
 747  * If error is set than unvalidate buffer, otherwise just free memory
 748  * used by parsing context.
 749  **/
 750 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
 751                                   bool backoff)
 752 {
 753         unsigned i;
 754
 755         if (error && backoff)
 756                 ttm_eu_backoff_reservation(&parser->ticket,
 757                                            &parser->validated);
 758
 759         for (i = 0; i < parser->num_post_deps; i++) {
 760                 drm_syncobj_put(parser->post_deps[i].syncobj);
 761                 kfree(parser->post_deps[i].chain);
 762         }
 763         kfree(parser->post_deps);
 764
 765         dma_fence_put(parser->fence);
 766
 767         if (parser->ctx) {
 768                 mutex_unlock(&parser->ctx->lock);
 769                 amdgpu_ctx_put(parser->ctx);
 770         }
 771         if (parser->bo_list)
 772                 amdgpu_bo_list_put(parser->bo_list);
 773
 774         for (i = 0; i < parser->nchunks; i++)
 775                 kvfree(parser->chunks[i].kdata);
 776         kfree(parser->chunks);
 777         if (parser->job)
 778                 amdgpu_job_free(parser->job);
 779         if (parser->uf_entry.tv.bo) {
 780                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo);
 781
 782                 amdgpu_bo_unref(&uf);
 783         }
 784 }
 785
 786 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 787 {
 788         struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
 789         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 790         struct amdgpu_device *adev = p->adev;
 791         struct amdgpu_vm *vm = &fpriv->vm;
 792         struct amdgpu_bo_list_entry *e;
 793         struct amdgpu_bo_va *bo_va;
 794         struct amdgpu_bo *bo;
 795         int r;
 796
 797         /* Only for UVD/VCE VM emulation */
 798         if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
 799                 unsigned i, j;
 800
 801                 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
 802                         struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 803                         struct amdgpu_bo_va_mapping *m;
 804                         struct amdgpu_bo *aobj = NULL;
 805                         struct amdgpu_cs_chunk *chunk;
 806                         uint64_t offset, va_start;
 807                         struct amdgpu_ib *ib;
 808                         uint8_t *kptr;
 809
 810                         chunk = &p->chunks[i];
 811                         ib = &p->job->ibs[j];
 812                         chunk_ib = chunk->kdata;
 813
 814                         if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 815                                 continue;
 816
 817                         va_start = chunk_ib->va_start & AMDGPU_GMC_HOLE_MASK;
 818                         r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
 819                         if (r) {
 820                                 DRM_ERROR("IB va_start is invalid\n");
 821                                 return r;
 822                         }
 823
 824                         if ((va_start + chunk_ib->ib_bytes) >
 825                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 826                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 827                                 return -EINVAL;
 828                         }
 829
 830                         /* the IB should be reserved at this point */
 831                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 832                         if (r) {
 833                                 return r;
 834                         }
 835
 836                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 837                         kptr += va_start - offset;
 838
 839                         if (ring->funcs->parse_cs) {
 840                                 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 841                                 amdgpu_bo_kunmap(aobj);
 842
 843                                 r = amdgpu_ring_parse_cs(ring, p, j);
 844                                 if (r)
 845                                         return r;
 846                         } else {
 847                                 ib->ptr = (uint32_t *)kptr;
 848                                 r = amdgpu_ring_patch_cs_in_place(ring, p, j);
 849                                 amdgpu_bo_kunmap(aobj);
 850                                 if (r)
 851                                         return r;
 852                         }
 853
 854                         j++;
 855                 }
 856         }
 857
 858         if (!p->job->vm)
 859                 return amdgpu_cs_sync_rings(p);
 860
 861
 862         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 863         if (r)
 864                 return r;
 865
 866         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
 867         if (r)
 868                 return r;
 869
 870         r = amdgpu_sync_fence(adev, &p->job->sync,
 871                               fpriv->prt_va->last_pt_update, false);
 872         if (r)
 873                 return r;
 874
 875         if (amdgpu_sriov_vf(adev)) {
 876                 struct dma_fence *f;
 877
 878                 bo_va = fpriv->csa_va;
 879                 BUG_ON(!bo_va);
 880                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 881                 if (r)
 882                         return r;
 883
 884                 f = bo_va->last_pt_update;
 885                 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
 886                 if (r)
 887                         return r;
 888         }
 889
 890         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 891                 struct dma_fence *f;
 892
 893                 /* ignore duplicates */
 894                 bo = ttm_to_amdgpu_bo(e->tv.bo);
 895                 if (!bo)
 896                         continue;
 897
 898                 bo_va = e->bo_va;
 899                 if (bo_va == NULL)
 900                         continue;
 901
 902                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 903                 if (r)
 904                         return r;
 905
 906                 f = bo_va->last_pt_update;
 907                 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
 908                 if (r)
 909                         return r;
 910         }
 911
 912         r = amdgpu_vm_handle_moved(adev, vm);
 913         if (r)
 914                 return r;
 915
 916         r = amdgpu_vm_update_directories(adev, vm);
 917         if (r)
 918                 return r;
 919
 920         r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false);
 921         if (r)
 922                 return r;
 923
 924         p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
 925
 926         if (amdgpu_vm_debug) {
 927                 /* Invalidate all BOs to test for userspace bugs */
 928                 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 929                         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 930
 931                         /* ignore duplicates */
 932                         if (!bo)
 933                                 continue;
 934
 935                         amdgpu_vm_bo_invalidate(adev, bo, false);
 936                 }
 937         }
 938
 939         return amdgpu_cs_sync_rings(p);
 940 }
 941
 942 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 943                              struct amdgpu_cs_parser *parser)
 944 {
 945         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 946         struct amdgpu_vm *vm = &fpriv->vm;
 947         int r, ce_preempt = 0, de_preempt = 0;
 948         struct amdgpu_ring *ring;
 949         int i, j;
 950
 951         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 952                 struct amdgpu_cs_chunk *chunk;
 953                 struct amdgpu_ib *ib;
 954                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 955                 struct drm_sched_entity *entity;
 956
 957                 chunk = &parser->chunks[i];
 958                 ib = &parser->job->ibs[j];
 959                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 960
 961                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 962                         continue;
 963
 964                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) {
 965                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 966                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 967                                         ce_preempt++;
 968                                 else
 969                                         de_preempt++;
 970                         }
 971
 972                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
 973                         if (ce_preempt > 1 || de_preempt > 1)
 974                                 return -EINVAL;
 975                 }
 976
 977                 r = amdgpu_ctx_get_entity(parser->ctx, chunk_ib->ip_type,
 978                                           chunk_ib->ip_instance, chunk_ib->ring,
 979                                           &entity);
 980                 if (r)
 981                         return r;
 982
 983                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
 984                         parser->job->preamble_status |=
 985                                 AMDGPU_PREAMBLE_IB_PRESENT;
 986
 987                 if (parser->entity && parser->entity != entity)
 988                         return -EINVAL;
 989
 990                 parser->entity = entity;
 991
 992                 ring = to_amdgpu_ring(entity->rq->sched);
 993                 r =  amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
 994                                    chunk_ib->ib_bytes : 0, ib);
 995                 if (r) {
 996                         DRM_ERROR("Failed to get ib !\n");
 997                         return r;
 998                 }
 999
1000                 ib->gpu_addr = chunk_ib->va_start;
1001                 ib->length_dw = chunk_ib->ib_bytes / 4;
1002                 ib->flags = chunk_ib->flags;
1003
1004                 j++;
1005         }
1006
1007         /* MM engine doesn't support user fences */
1008         ring = to_amdgpu_ring(parser->entity->rq->sched);
1009         if (parser->job->uf_addr && ring->funcs->no_user_fence)
1010                 return -EINVAL;
1011
1012         return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->entity);
1013 }
1014
1015 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
1016                                        struct amdgpu_cs_chunk *chunk)
1017 {
1018         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1019         unsigned num_deps;
1020         int i, r;
1021         struct drm_amdgpu_cs_chunk_dep *deps;
1022
1023         deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
1024         num_deps = chunk->length_dw * 4 /
1025                 sizeof(struct drm_amdgpu_cs_chunk_dep);
1026
1027         for (i = 0; i < num_deps; ++i) {
1028                 struct amdgpu_ctx *ctx;
1029                 struct drm_sched_entity *entity;
1030                 struct dma_fence *fence;
1031
1032                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
1033                 if (ctx == NULL)
1034                         return -EINVAL;
1035
1036                 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
1037                                           deps[i].ip_instance,
1038                                           deps[i].ring, &entity);
1039                 if (r) {
1040                         amdgpu_ctx_put(ctx);
1041                         return r;
1042                 }
1043
1044                 fence = amdgpu_ctx_get_fence(ctx, entity,
1045                                              deps[i].handle);
1046
1047                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
1048                         struct drm_sched_fence *s_fence = to_drm_sched_fence(fence);
1049                         struct dma_fence *old = fence;
1050
1051                         fence = dma_fence_get(&s_fence->scheduled);
1052                         dma_fence_put(old);
1053                 }
1054
1055                 if (IS_ERR(fence)) {
1056                         r = PTR_ERR(fence);
1057                         amdgpu_ctx_put(ctx);
1058                         return r;
1059                 } else if (fence) {
1060                         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence,
1061                                         true);
1062                         dma_fence_put(fence);
1063                         amdgpu_ctx_put(ctx);
1064                         if (r)
1065                                 return r;
1066                 }
1067         }
1068         return 0;
1069 }
1070
1071 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1072                                                  uint32_t handle, u64 point,
1073                                                  u64 flags)
1074 {
1075         struct dma_fence *fence;
1076         int r;
1077
1078         r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
1079         if (r) {
1080                 DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
1081                           handle, point, r);
1082                 return r;
1083         }
1084
1085         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
1086         dma_fence_put(fence);
1087
1088         return r;
1089 }
1090
1091 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1092                                             struct amdgpu_cs_chunk *chunk)
1093 {
1094         struct drm_amdgpu_cs_chunk_sem *deps;
1095         unsigned num_deps;
1096         int i, r;
1097
1098         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1099         num_deps = chunk->length_dw * 4 /
1100                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1101         for (i = 0; i < num_deps; ++i) {
1102                 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle,
1103                                                           0, 0);
1104                 if (r)
1105                         return r;
1106         }
1107
1108         return 0;
1109 }
1110
1111
1112 static int amdgpu_cs_process_syncobj_timeline_in_dep(struct amdgpu_cs_parser *p,
1113                                                      struct amdgpu_cs_chunk *chunk)
1114 {
1115         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1116         unsigned num_deps;
1117         int i, r;
1118
1119         syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1120         num_deps = chunk->length_dw * 4 /
1121                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1122         for (i = 0; i < num_deps; ++i) {
1123                 r = amdgpu_syncobj_lookup_and_add_to_sync(p,
1124                                                           syncobj_deps[i].handle,
1125                                                           syncobj_deps[i].point,
1126                                                           syncobj_deps[i].flags);
1127                 if (r)
1128                         return r;
1129         }
1130
1131         return 0;
1132 }
1133
1134 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1135                                              struct amdgpu_cs_chunk *chunk)
1136 {
1137         struct drm_amdgpu_cs_chunk_sem *deps;
1138         unsigned num_deps;
1139         int i;
1140
1141         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1142         num_deps = chunk->length_dw * 4 /
1143                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1144
1145         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1146                                      GFP_KERNEL);
1147         p->num_post_deps = 0;
1148
1149         if (!p->post_deps)
1150                 return -ENOMEM;
1151
1152
1153         for (i = 0; i < num_deps; ++i) {
1154                 p->post_deps[i].syncobj =
1155                         drm_syncobj_find(p->filp, deps[i].handle);
1156                 if (!p->post_deps[i].syncobj)
1157                         return -EINVAL;
1158                 p->post_deps[i].chain = NULL;
1159                 p->post_deps[i].point = 0;
1160                 p->num_post_deps++;
1161         }
1162
1163         return 0;
1164 }
1165
1166
1167 static int amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p,
1168                                                       struct amdgpu_cs_chunk
1169                                                       *chunk)
1170 {
1171         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1172         unsigned num_deps;
1173         int i;
1174
1175         syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1176         num_deps = chunk->length_dw * 4 /
1177                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1178
1179         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1180                                      GFP_KERNEL);
1181         p->num_post_deps = 0;
1182
1183         if (!p->post_deps)
1184                 return -ENOMEM;
1185
1186         for (i = 0; i < num_deps; ++i) {
1187                 struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
1188
1189                 dep->chain = NULL;
1190                 if (syncobj_deps[i].point) {
1191                         dep->chain = kmalloc(sizeof(*dep->chain), GFP_KERNEL);
1192                         if (!dep->chain)
1193                                 return -ENOMEM;
1194                 }
1195
1196                 dep->syncobj = drm_syncobj_find(p->filp,
1197                                                 syncobj_deps[i].handle);
1198                 if (!dep->syncobj) {
1199                         kfree(dep->chain);
1200                         return -EINVAL;
1201                 }
1202                 dep->point = syncobj_deps[i].point;
1203                 p->num_post_deps++;
1204         }
1205
1206         return 0;
1207 }
1208
1209 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1210                                   struct amdgpu_cs_parser *p)
1211 {
1212         int i, r;
1213
1214         for (i = 0; i < p->nchunks; ++i) {
1215                 struct amdgpu_cs_chunk *chunk;
1216
1217                 chunk = &p->chunks[i];
1218
1219                 switch (chunk->chunk_id) {
1220                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
1221                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
1222                         r = amdgpu_cs_process_fence_dep(p, chunk);
1223                         if (r)
1224                                 return r;
1225                         break;
1226                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
1227                         r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1228                         if (r)
1229                                 return r;
1230                         break;
1231                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
1232                         r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1233                         if (r)
1234                                 return r;
1235                         break;
1236                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
1237                         r = amdgpu_cs_process_syncobj_timeline_in_dep(p, chunk);
1238                         if (r)
1239                                 return r;
1240                         break;
1241                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
1242                         r = amdgpu_cs_process_syncobj_timeline_out_dep(p, chunk);
1243                         if (r)
1244                                 return r;
1245                         break;
1246                 }
1247         }
1248
1249         return 0;
1250 }
1251
1252 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1253 {
1254         int i;
1255
1256         for (i = 0; i < p->num_post_deps; ++i) {
1257                 if (p->post_deps[i].chain && p->post_deps[i].point) {
1258                         drm_syncobj_add_point(p->post_deps[i].syncobj,
1259                                               p->post_deps[i].chain,
1260                                               p->fence, p->post_deps[i].point);
1261                         p->post_deps[i].chain = NULL;
1262                 } else {
1263                         drm_syncobj_replace_fence(p->post_deps[i].syncobj,
1264                                                   p->fence);
1265                 }
1266         }
1267 }
1268
1269 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1270                             union drm_amdgpu_cs *cs)
1271 {
1272         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1273         struct drm_sched_entity *entity = p->entity;
1274         enum drm_sched_priority priority;
1275         struct amdgpu_ring *ring;
1276         struct amdgpu_bo_list_entry *e;
1277         struct amdgpu_job *job;
1278         uint64_t seq;
1279         int r;
1280
1281         job = p->job;
1282         p->job = NULL;
1283
1284         r = drm_sched_job_init(&job->base, entity, p->filp);
1285         if (r)
1286                 goto error_unlock;
1287
1288         /* No memory allocation is allowed while holding the mn lock.
1289          * p->mn is hold until amdgpu_cs_submit is finished and fence is added
1290          * to BOs.
1291          */
1292         amdgpu_mn_lock(p->mn);
1293
1294         /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1295          * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1296          */
1297         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1298                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1299
1300                 r |= !amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
1301         }
1302         if (r) {
1303                 r = -EAGAIN;
1304                 goto error_abort;
1305         }
1306
1307         job->owner = p->filp;
1308         p->fence = dma_fence_get(&job->base.s_fence->finished);
1309
1310         amdgpu_ctx_add_fence(p->ctx, entity, p->fence, &seq);
1311         amdgpu_cs_post_dependencies(p);
1312
1313         if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1314             !p->ctx->preamble_presented) {
1315                 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1316                 p->ctx->preamble_presented = true;
1317         }
1318
1319         cs->out.handle = seq;
1320         job->uf_sequence = seq;
1321
1322         amdgpu_job_free_resources(job);
1323
1324         trace_amdgpu_cs_ioctl(job);
1325         amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
1326         priority = job->base.s_priority;
1327         drm_sched_entity_push_job(&job->base, entity);
1328
1329         ring = to_amdgpu_ring(entity->rq->sched);
1330         amdgpu_ring_priority_get(ring, priority);
1331
1332         amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1333
1334         ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1335         amdgpu_mn_unlock(p->mn);
1336
1337         return 0;
1338
1339 error_abort:
1340         drm_sched_job_cleanup(&job->base);
1341         amdgpu_mn_unlock(p->mn);
1342
1343 error_unlock:
1344         amdgpu_job_free(job);
1345         return r;
1346 }
1347
1348 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1349 {
1350         struct amdgpu_device *adev = dev->dev_private;
1351         union drm_amdgpu_cs *cs = data;
1352         struct amdgpu_cs_parser parser = {};
1353         bool reserved_buffers = false;
1354         int i, r;
1355
1356         if (!adev->accel_working)
1357                 return -EBUSY;
1358
1359         parser.adev = adev;
1360         parser.filp = filp;
1361
1362         r = amdgpu_cs_parser_init(&parser, data);
1363         if (r) {
1364                 DRM_ERROR("Failed to initialize parser %d!\n", r);
1365                 goto out;
1366         }
1367
1368         r = amdgpu_cs_ib_fill(adev, &parser);
1369         if (r)
1370                 goto out;
1371
1372         r = amdgpu_cs_dependencies(adev, &parser);
1373         if (r) {
1374                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1375                 goto out;
1376         }
1377
1378         r = amdgpu_cs_parser_bos(&parser, data);
1379         if (r) {
1380                 if (r == -ENOMEM)
1381                         DRM_ERROR("Not enough memory for command submission!\n");
1382                 else if (r != -ERESTARTSYS && r != -EAGAIN)
1383                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1384                 goto out;
1385         }
1386
1387         reserved_buffers = true;
1388
1389         for (i = 0; i < parser.job->num_ibs; i++)
1390                 trace_amdgpu_cs(&parser, i);
1391
1392         r = amdgpu_cs_vm_handling(&parser);
1393         if (r)
1394                 goto out;
1395
1396         r = amdgpu_cs_submit(&parser, cs);
1397
1398 out:
1399         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1400
1401         return r;
1402 }
1403
1404 /**
1405  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1406  *
1407  * @dev: drm device
1408  * @data: data from userspace
1409  * @filp: file private
1410  *
1411  * Wait for the command submission identified by handle to finish.
1412  */
1413 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1414                          struct drm_file *filp)
1415 {
1416         union drm_amdgpu_wait_cs *wait = data;
1417         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1418         struct drm_sched_entity *entity;
1419         struct amdgpu_ctx *ctx;
1420         struct dma_fence *fence;
1421         long r;
1422
1423         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1424         if (ctx == NULL)
1425                 return -EINVAL;
1426
1427         r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1428                                   wait->in.ring, &entity);
1429         if (r) {
1430                 amdgpu_ctx_put(ctx);
1431                 return r;
1432         }
1433
1434         fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1435         if (IS_ERR(fence))
1436                 r = PTR_ERR(fence);
1437         else if (fence) {
1438                 r = dma_fence_wait_timeout(fence, true, timeout);
1439                 if (r > 0 && fence->error)
1440                         r = fence->error;
1441                 dma_fence_put(fence);
1442         } else
1443                 r = 1;
1444
1445         amdgpu_ctx_put(ctx);
1446         if (r < 0)
1447                 return r;
1448
1449         memset(wait, 0, sizeof(*wait));
1450         wait->out.status = (r == 0);
1451
1452         return 0;
1453 }
1454
1455 /**
1456  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1457  *
1458  * @adev: amdgpu device
1459  * @filp: file private
1460  * @user: drm_amdgpu_fence copied from user space
1461  */
1462 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1463                                              struct drm_file *filp,
1464                                              struct drm_amdgpu_fence *user)
1465 {
1466         struct drm_sched_entity *entity;
1467         struct amdgpu_ctx *ctx;
1468         struct dma_fence *fence;
1469         int r;
1470
1471         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1472         if (ctx == NULL)
1473                 return ERR_PTR(-EINVAL);
1474
1475         r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1476                                   user->ring, &entity);
1477         if (r) {
1478                 amdgpu_ctx_put(ctx);
1479                 return ERR_PTR(r);
1480         }
1481
1482         fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1483         amdgpu_ctx_put(ctx);
1484
1485         return fence;
1486 }
1487
1488 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1489                                     struct drm_file *filp)
1490 {
1491         struct amdgpu_device *adev = dev->dev_private;
1492         union drm_amdgpu_fence_to_handle *info = data;
1493         struct dma_fence *fence;
1494         struct drm_syncobj *syncobj;
1495         struct sync_file *sync_file;
1496         int fd, r;
1497
1498         fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1499         if (IS_ERR(fence))
1500                 return PTR_ERR(fence);
1501
1502         if (!fence)
1503                 fence = dma_fence_get_stub();
1504
1505         switch (info->in.what) {
1506         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1507                 r = drm_syncobj_create(&syncobj, 0, fence);
1508                 dma_fence_put(fence);
1509                 if (r)
1510                         return r;
1511                 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1512                 drm_syncobj_put(syncobj);
1513                 return r;
1514
1515         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1516                 r = drm_syncobj_create(&syncobj, 0, fence);
1517                 dma_fence_put(fence);
1518                 if (r)
1519                         return r;
1520                 r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
1521                 drm_syncobj_put(syncobj);
1522                 return r;
1523
1524         case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1525                 fd = get_unused_fd_flags(O_CLOEXEC);
1526                 if (fd < 0) {
1527                         dma_fence_put(fence);
1528                         return fd;
1529                 }
1530
1531                 sync_file = sync_file_create(fence);
1532                 dma_fence_put(fence);
1533                 if (!sync_file) {
1534                         put_unused_fd(fd);
1535                         return -ENOMEM;
1536                 }
1537
1538                 fd_install(fd, sync_file->file);
1539                 info->out.handle = fd;
1540                 return 0;
1541
1542         default:
1543                 return -EINVAL;
1544         }
1545 }
1546
1547 /**
1548  * amdgpu_cs_wait_all_fence - wait on all fences to signal
1549  *
1550  * @adev: amdgpu device
1551  * @filp: file private
1552  * @wait: wait parameters
1553  * @fences: array of drm_amdgpu_fence
1554  */
1555 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1556                                      struct drm_file *filp,
1557                                      union drm_amdgpu_wait_fences *wait,
1558                                      struct drm_amdgpu_fence *fences)
1559 {
1560         uint32_t fence_count = wait->in.fence_count;
1561         unsigned int i;
1562         long r = 1;
1563
1564         for (i = 0; i < fence_count; i++) {
1565                 struct dma_fence *fence;
1566                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1567
1568                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1569                 if (IS_ERR(fence))
1570                         return PTR_ERR(fence);
1571                 else if (!fence)
1572                         continue;
1573
1574                 r = dma_fence_wait_timeout(fence, true, timeout);
1575                 dma_fence_put(fence);
1576                 if (r < 0)
1577                         return r;
1578
1579                 if (r == 0)
1580                         break;
1581
1582                 if (fence->error)
1583                         return fence->error;
1584         }
1585
1586         memset(wait, 0, sizeof(*wait));
1587         wait->out.status = (r > 0);
1588
1589         return 0;
1590 }
1591
1592 /**
1593  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1594  *
1595  * @adev: amdgpu device
1596  * @filp: file private
1597  * @wait: wait parameters
1598  * @fences: array of drm_amdgpu_fence
1599  */
1600 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1601                                     struct drm_file *filp,
1602                                     union drm_amdgpu_wait_fences *wait,
1603                                     struct drm_amdgpu_fence *fences)
1604 {
1605         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1606         uint32_t fence_count = wait->in.fence_count;
1607         uint32_t first = ~0;
1608         struct dma_fence **array;
1609         unsigned int i;
1610         long r;
1611
1612         /* Prepare the fence array */
1613         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1614
1615         if (array == NULL)
1616                 return -ENOMEM;
1617
1618         for (i = 0; i < fence_count; i++) {
1619                 struct dma_fence *fence;
1620
1621                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1622                 if (IS_ERR(fence)) {
1623                         r = PTR_ERR(fence);
1624                         goto err_free_fence_array;
1625                 } else if (fence) {
1626                         array[i] = fence;
1627                 } else { /* NULL, the fence has been already signaled */
1628                         r = 1;
1629                         first = i;
1630                         goto out;
1631                 }
1632         }
1633
1634         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1635                                        &first);
1636         if (r < 0)
1637                 goto err_free_fence_array;
1638
1639 out:
1640         memset(wait, 0, sizeof(*wait));
1641         wait->out.status = (r > 0);
1642         wait->out.first_signaled = first;
1643
1644         if (first < fence_count && array[first])
1645                 r = array[first]->error;
1646         else
1647                 r = 0;
1648
1649 err_free_fence_array:
1650         for (i = 0; i < fence_count; i++)
1651                 dma_fence_put(array[i]);
1652         kfree(array);
1653
1654         return r;
1655 }
1656
1657 /**
1658  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1659  *
1660  * @dev: drm device
1661  * @data: data from userspace
1662  * @filp: file private
1663  */
1664 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1665                                 struct drm_file *filp)
1666 {
1667         struct amdgpu_device *adev = dev->dev_private;
1668         union drm_amdgpu_wait_fences *wait = data;
1669         uint32_t fence_count = wait->in.fence_count;
1670         struct drm_amdgpu_fence *fences_user;
1671         struct drm_amdgpu_fence *fences;
1672         int r;
1673
1674         /* Get the fences from userspace */
1675         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1676                         GFP_KERNEL);
1677         if (fences == NULL)
1678                 return -ENOMEM;
1679
1680         fences_user = u64_to_user_ptr(wait->in.fences);
1681         if (copy_from_user(fences, fences_user,
1682                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1683                 r = -EFAULT;
1684                 goto err_free_fences;
1685         }
1686
1687         if (wait->in.wait_all)
1688                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1689         else
1690                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1691
1692 err_free_fences:
1693         kfree(fences);
1694
1695         return r;
1696 }
1697
1698 /**
1699  * amdgpu_cs_find_bo_va - find bo_va for VM address
1700  *
1701  * @parser: command submission parser context
1702  * @addr: VM address
1703  * @bo: resulting BO of the mapping found
1704  *
1705  * Search the buffer objects in the command submission context for a certain
1706  * virtual memory address. Returns allocation structure when found, NULL
1707  * otherwise.
1708  */
1709 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1710                            uint64_t addr, struct amdgpu_bo **bo,
1711                            struct amdgpu_bo_va_mapping **map)
1712 {
1713         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1714         struct ttm_operation_ctx ctx = { false, false };
1715         struct amdgpu_vm *vm = &fpriv->vm;
1716         struct amdgpu_bo_va_mapping *mapping;
1717         int r;
1718
1719         addr /= AMDGPU_GPU_PAGE_SIZE;
1720
1721         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1722         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1723                 return -EINVAL;
1724
1725         *bo = mapping->bo_va->base.bo;
1726         *map = mapping;
1727
1728         /* Double check that the BO is reserved by this CS */
1729         if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket)
1730                 return -EINVAL;
1731
1732         if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1733                 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1734                 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1735                 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1736                 if (r)
1737                         return r;
1738         }
1739
1740         return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1741 }