drivers/gpu/drm/amd/amdgpu/cik_sdma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "cikd.h"
  30 #include "cik.h"
  31
  32 #include "bif/bif_4_1_d.h"
  33 #include "bif/bif_4_1_sh_mask.h"
  34
  35 #include "gca/gfx_7_2_d.h"
  36 #include "gca/gfx_7_2_enum.h"
  37 #include "gca/gfx_7_2_sh_mask.h"
  38
  39 #include "gmc/gmc_7_1_d.h"
  40 #include "gmc/gmc_7_1_sh_mask.h"
  41
  42 #include "oss/oss_2_0_d.h"
  43 #include "oss/oss_2_0_sh_mask.h"
  44
  45 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  46 {
  47         SDMA0_REGISTER_OFFSET,
  48         SDMA1_REGISTER_OFFSET
  49 };
  50
  51 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
  52 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
  53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
  54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
  55
  56 MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
  57 MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
  58 MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
  59 MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
  60 MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
  61 MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
  62 MODULE_FIRMWARE("radeon/kabini_sdma.bin");
  63 MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
  64 MODULE_FIRMWARE("radeon/mullins_sdma.bin");
  65 MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
  66
  67 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
  68
  69
  70 static void cik_sdma_free_microcode(struct amdgpu_device *adev)
  71 {
  72         int i;
  73         for (i = 0; i < adev->sdma.num_instances; i++) {
  74                         release_firmware(adev->sdma.instance[i].fw);
  75                         adev->sdma.instance[i].fw = NULL;
  76         }
  77 }
  78
  79 /*
  80  * sDMA - System DMA
  81  * Starting with CIK, the GPU has new asynchronous
  82  * DMA engines.  These engines are used for compute
  83  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  84  * and each one supports 1 ring buffer used for gfx
  85  * and 2 queues used for compute.
  86  *
  87  * The programming model is very similar to the CP
  88  * (ring buffer, IBs, etc.), but sDMA has it's own
  89  * packet format that is different from the PM4 format
  90  * used by the CP. sDMA supports copying data, writing
  91  * embedded data, solid fills, and a number of other
  92  * things.  It also has support for tiling/detiling of
  93  * buffers.
  94  */
  95
  96 /**
  97  * cik_sdma_init_microcode - load ucode images from disk
  98  *
  99  * @adev: amdgpu_device pointer
 100  *
 101  * Use the firmware interface to load the ucode images into
 102  * the driver (not loaded into hw).
 103  * Returns 0 on success, error on failure.
 104  */
 105 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
 106 {
 107         const char *chip_name;
 108         char fw_name[30];
 109         int err = 0, i;
 110
 111         DRM_DEBUG("\n");
 112
 113         switch (adev->asic_type) {
 114         case CHIP_BONAIRE:
 115                 chip_name = "bonaire";
 116                 break;
 117         case CHIP_HAWAII:
 118                 chip_name = "hawaii";
 119                 break;
 120         case CHIP_KAVERI:
 121                 chip_name = "kaveri";
 122                 break;
 123         case CHIP_KABINI:
 124                 chip_name = "kabini";
 125                 break;
 126         case CHIP_MULLINS:
 127                 chip_name = "mullins";
 128                 break;
 129         default: BUG();
 130         }
 131
 132         for (i = 0; i < adev->sdma.num_instances; i++) {
 133                 if (i == 0)
 134                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
 135                 else
 136                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
 137                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 138                 if (err)
 139                         goto out;
 140                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 141         }
 142 out:
 143         if (err) {
 144                 printk(KERN_ERR
 145                        "cik_sdma: Failed to load firmware \"%s\"\n",
 146                        fw_name);
 147                 for (i = 0; i < adev->sdma.num_instances; i++) {
 148                         release_firmware(adev->sdma.instance[i].fw);
 149                         adev->sdma.instance[i].fw = NULL;
 150                 }
 151         }
 152         return err;
 153 }
 154
 155 /**
 156  * cik_sdma_ring_get_rptr - get the current read pointer
 157  *
 158  * @ring: amdgpu ring pointer
 159  *
 160  * Get the current rptr from the hardware (CIK+).
 161  */
 162 static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 163 {
 164         u32 rptr;
 165
 166         rptr = ring->adev->wb.wb[ring->rptr_offs];
 167
 168         return (rptr & 0x3fffc) >> 2;
 169 }
 170
 171 /**
 172  * cik_sdma_ring_get_wptr - get the current write pointer
 173  *
 174  * @ring: amdgpu ring pointer
 175  *
 176  * Get the current wptr from the hardware (CIK+).
 177  */
 178 static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 179 {
 180         struct amdgpu_device *adev = ring->adev;
 181         u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 182
 183         return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
 184 }
 185
 186 /**
 187  * cik_sdma_ring_set_wptr - commit the write pointer
 188  *
 189  * @ring: amdgpu ring pointer
 190  *
 191  * Write the wptr back to the hardware (CIK+).
 192  */
 193 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 194 {
 195         struct amdgpu_device *adev = ring->adev;
 196         u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 197
 198         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
 199 }
 200
 201 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 202 {
 203         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 204         int i;
 205
 206         for (i = 0; i < count; i++)
 207                 if (sdma && sdma->burst_nop && (i == 0))
 208                         amdgpu_ring_write(ring, ring->nop |
 209                                           SDMA_NOP_COUNT(count - 1));
 210                 else
 211                         amdgpu_ring_write(ring, ring->nop);
 212 }
 213
 214 /**
 215  * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
 216  *
 217  * @ring: amdgpu ring pointer
 218  * @ib: IB object to schedule
 219  *
 220  * Schedule an IB in the DMA ring (CIK).
 221  */
 222 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
 223                                   struct amdgpu_ib *ib,
 224                                   unsigned vm_id, bool ctx_switch)
 225 {
 226         u32 extra_bits = vm_id & 0xf;
 227
 228         /* IB packet must end on a 8 DW boundary */
 229         cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8);
 230
 231         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
 232         amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
 233         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
 234         amdgpu_ring_write(ring, ib->length_dw);
 235
 236 }
 237
 238 /**
 239  * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 240  *
 241  * @ring: amdgpu ring pointer
 242  *
 243  * Emit an hdp flush packet on the requested DMA ring.
 244  */
 245 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 246 {
 247         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
 248                           SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
 249         u32 ref_and_mask;
 250
 251         if (ring == &ring->adev->sdma.instance[0].ring)
 252                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
 253         else
 254                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
 255
 256         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 257         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 258         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 259         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 260         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 261         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 262 }
 263
 264 static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 265 {
 266         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 267         amdgpu_ring_write(ring, mmHDP_DEBUG0);
 268         amdgpu_ring_write(ring, 1);
 269 }
 270
 271 /**
 272  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
 273  *
 274  * @ring: amdgpu ring pointer
 275  * @fence: amdgpu fence object
 276  *
 277  * Add a DMA fence packet to the ring to write
 278  * the fence seq number and DMA trap packet to generate
 279  * an interrupt if needed (CIK).
 280  */
 281 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 282                                      unsigned flags)
 283 {
 284         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 285         /* write the fence */
 286         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 287         amdgpu_ring_write(ring, lower_32_bits(addr));
 288         amdgpu_ring_write(ring, upper_32_bits(addr));
 289         amdgpu_ring_write(ring, lower_32_bits(seq));
 290
 291         /* optionally write high bits as well */
 292         if (write64bit) {
 293                 addr += 4;
 294                 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 295                 amdgpu_ring_write(ring, lower_32_bits(addr));
 296                 amdgpu_ring_write(ring, upper_32_bits(addr));
 297                 amdgpu_ring_write(ring, upper_32_bits(seq));
 298         }
 299
 300         /* generate an interrupt */
 301         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
 302 }
 303
 304 /**
 305  * cik_sdma_gfx_stop - stop the gfx async dma engines
 306  *
 307  * @adev: amdgpu_device pointer
 308  *
 309  * Stop the gfx async dma ring buffers (CIK).
 310  */
 311 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
 312 {
 313         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 314         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 315         u32 rb_cntl;
 316         int i;
 317
 318         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 319             (adev->mman.buffer_funcs_ring == sdma1))
 320                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 321
 322         for (i = 0; i < adev->sdma.num_instances; i++) {
 323                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 324                 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
 325                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 326                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
 327         }
 328         sdma0->ready = false;
 329         sdma1->ready = false;
 330 }
 331
 332 /**
 333  * cik_sdma_rlc_stop - stop the compute async dma engines
 334  *
 335  * @adev: amdgpu_device pointer
 336  *
 337  * Stop the compute async dma queues (CIK).
 338  */
 339 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
 340 {
 341         /* XXX todo */
 342 }
 343
 344 /**
 345  * cik_sdma_enable - stop the async dma engines
 346  *
 347  * @adev: amdgpu_device pointer
 348  * @enable: enable/disable the DMA MEs.
 349  *
 350  * Halt or unhalt the async dma engines (CIK).
 351  */
 352 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
 353 {
 354         u32 me_cntl;
 355         int i;
 356
 357         if (enable == false) {
 358                 cik_sdma_gfx_stop(adev);
 359                 cik_sdma_rlc_stop(adev);
 360         }
 361
 362         for (i = 0; i < adev->sdma.num_instances; i++) {
 363                 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 364                 if (enable)
 365                         me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
 366                 else
 367                         me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
 368                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
 369         }
 370 }
 371
 372 /**
 373  * cik_sdma_gfx_resume - setup and start the async dma engines
 374  *
 375  * @adev: amdgpu_device pointer
 376  *
 377  * Set up the gfx DMA ring buffers and enable them (CIK).
 378  * Returns 0 for success, error for failure.
 379  */
 380 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 381 {
 382         struct amdgpu_ring *ring;
 383         u32 rb_cntl, ib_cntl;
 384         u32 rb_bufsz;
 385         u32 wb_offset;
 386         int i, j, r;
 387
 388         for (i = 0; i < adev->sdma.num_instances; i++) {
 389                 ring = &adev->sdma.instance[i].ring;
 390                 wb_offset = (ring->rptr_offs * 4);
 391
 392                 mutex_lock(&adev->srbm_mutex);
 393                 for (j = 0; j < 16; j++) {
 394                         cik_srbm_select(adev, 0, 0, 0, j);
 395                         /* SDMA GFX */
 396                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 397                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 398                         /* XXX SDMA RLC - todo */
 399                 }
 400                 cik_srbm_select(adev, 0, 0, 0, 0);
 401                 mutex_unlock(&adev->srbm_mutex);
 402
 403                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 404                        adev->gfx.config.gb_addr_config & 0x70);
 405
 406                 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
 407                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 408
 409                 /* Set ring buffer size in dwords */
 410                 rb_bufsz = order_base_2(ring->ring_size / 4);
 411                 rb_cntl = rb_bufsz << 1;
 412 #ifdef __BIG_ENDIAN
 413                 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
 414                         SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
 415 #endif
 416                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 417
 418                 /* Initialize the ring buffer's read and write pointers */
 419                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 420                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 421                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 422                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 423
 424                 /* set the wb address whether it's enabled or not */
 425                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 426                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 427                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 428                        ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
 429
 430                 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
 431
 432                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 433                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 434
 435                 ring->wptr = 0;
 436                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 437
 438                 /* enable DMA RB */
 439                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
 440                        rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
 441
 442                 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
 443 #ifdef __BIG_ENDIAN
 444                 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
 445 #endif
 446                 /* enable DMA IBs */
 447                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 448
 449                 ring->ready = true;
 450         }
 451
 452         cik_sdma_enable(adev, true);
 453
 454         for (i = 0; i < adev->sdma.num_instances; i++) {
 455                 ring = &adev->sdma.instance[i].ring;
 456                 r = amdgpu_ring_test_ring(ring);
 457                 if (r) {
 458                         ring->ready = false;
 459                         return r;
 460                 }
 461
 462                 if (adev->mman.buffer_funcs_ring == ring)
 463                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 464         }
 465
 466         return 0;
 467 }
 468
 469 /**
 470  * cik_sdma_rlc_resume - setup and start the async dma engines
 471  *
 472  * @adev: amdgpu_device pointer
 473  *
 474  * Set up the compute DMA queues and enable them (CIK).
 475  * Returns 0 for success, error for failure.
 476  */
 477 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
 478 {
 479         /* XXX todo */
 480         return 0;
 481 }
 482
 483 /**
 484  * cik_sdma_load_microcode - load the sDMA ME ucode
 485  *
 486  * @adev: amdgpu_device pointer
 487  *
 488  * Loads the sDMA0/1 ucode.
 489  * Returns 0 for success, -EINVAL if the ucode is not available.
 490  */
 491 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
 492 {
 493         const struct sdma_firmware_header_v1_0 *hdr;
 494         const __le32 *fw_data;
 495         u32 fw_size;
 496         int i, j;
 497
 498         /* halt the MEs */
 499         cik_sdma_enable(adev, false);
 500
 501         for (i = 0; i < adev->sdma.num_instances; i++) {
 502                 if (!adev->sdma.instance[i].fw)
 503                         return -EINVAL;
 504                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 505                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 506                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 507                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 508                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 509                 if (adev->sdma.instance[i].feature_version >= 20)
 510                         adev->sdma.instance[i].burst_nop = true;
 511                 fw_data = (const __le32 *)
 512                         (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 513                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 514                 for (j = 0; j < fw_size; j++)
 515                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 516                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 517         }
 518
 519         return 0;
 520 }
 521
 522 /**
 523  * cik_sdma_start - setup and start the async dma engines
 524  *
 525  * @adev: amdgpu_device pointer
 526  *
 527  * Set up the DMA engines and enable them (CIK).
 528  * Returns 0 for success, error for failure.
 529  */
 530 static int cik_sdma_start(struct amdgpu_device *adev)
 531 {
 532         int r;
 533
 534         r = cik_sdma_load_microcode(adev);
 535         if (r)
 536                 return r;
 537
 538         /* halt the engine before programing */
 539         cik_sdma_enable(adev, false);
 540
 541         /* start the gfx rings and rlc compute queues */
 542         r = cik_sdma_gfx_resume(adev);
 543         if (r)
 544                 return r;
 545         r = cik_sdma_rlc_resume(adev);
 546         if (r)
 547                 return r;
 548
 549         return 0;
 550 }
 551
 552 /**
 553  * cik_sdma_ring_test_ring - simple async dma engine test
 554  *
 555  * @ring: amdgpu_ring structure holding ring information
 556  *
 557  * Test the DMA engine by writing using it to write an
 558  * value to memory. (CIK).
 559  * Returns 0 for success, error for failure.
 560  */
 561 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
 562 {
 563         struct amdgpu_device *adev = ring->adev;
 564         unsigned i;
 565         unsigned index;
 566         int r;
 567         u32 tmp;
 568         u64 gpu_addr;
 569
 570         r = amdgpu_wb_get(adev, &index);
 571         if (r) {
 572                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 573                 return r;
 574         }
 575
 576         gpu_addr = adev->wb.gpu_addr + (index * 4);
 577         tmp = 0xCAFEDEAD;
 578         adev->wb.wb[index] = cpu_to_le32(tmp);
 579
 580         r = amdgpu_ring_alloc(ring, 5);
 581         if (r) {
 582                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 583                 amdgpu_wb_free(adev, index);
 584                 return r;
 585         }
 586         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 587         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 588         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 589         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 590         amdgpu_ring_write(ring, 0xDEADBEEF);
 591         amdgpu_ring_commit(ring);
 592
 593         for (i = 0; i < adev->usec_timeout; i++) {
 594                 tmp = le32_to_cpu(adev->wb.wb[index]);
 595                 if (tmp == 0xDEADBEEF)
 596                         break;
 597                 DRM_UDELAY(1);
 598         }
 599
 600         if (i < adev->usec_timeout) {
 601                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 602         } else {
 603                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 604                           ring->idx, tmp);
 605                 r = -EINVAL;
 606         }
 607         amdgpu_wb_free(adev, index);
 608
 609         return r;
 610 }
 611
 612 /**
 613  * cik_sdma_ring_test_ib - test an IB on the DMA engine
 614  *
 615  * @ring: amdgpu_ring structure holding ring information
 616  *
 617  * Test a simple IB in the DMA ring (CIK).
 618  * Returns 0 on success, error on failure.
 619  */
 620 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
 621 {
 622         struct amdgpu_device *adev = ring->adev;
 623         struct amdgpu_ib ib;
 624         struct fence *f = NULL;
 625         unsigned index;
 626         int r;
 627         u32 tmp = 0;
 628         u64 gpu_addr;
 629
 630         r = amdgpu_wb_get(adev, &index);
 631         if (r) {
 632                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 633                 return r;
 634         }
 635
 636         gpu_addr = adev->wb.gpu_addr + (index * 4);
 637         tmp = 0xCAFEDEAD;
 638         adev->wb.wb[index] = cpu_to_le32(tmp);
 639         memset(&ib, 0, sizeof(ib));
 640         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 641         if (r) {
 642                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 643                 goto err0;
 644         }
 645
 646         ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 647                                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 648         ib.ptr[1] = lower_32_bits(gpu_addr);
 649         ib.ptr[2] = upper_32_bits(gpu_addr);
 650         ib.ptr[3] = 1;
 651         ib.ptr[4] = 0xDEADBEEF;
 652         ib.length_dw = 5;
 653         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
 654         if (r)
 655                 goto err1;
 656
 657         r = fence_wait(f, false);
 658         if (r) {
 659                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 660                 goto err1;
 661         }
 662         tmp = le32_to_cpu(adev->wb.wb[index]);
 663         if (tmp == 0xDEADBEEF) {
 664                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 665         } else {
 666                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 667                 r = -EINVAL;
 668         }
 669
 670 err1:
 671         amdgpu_ib_free(adev, &ib, NULL);
 672         fence_put(f);
 673 err0:
 674         amdgpu_wb_free(adev, index);
 675         return r;
 676 }
 677
 678 /**
 679  * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
 680  *
 681  * @ib: indirect buffer to fill with commands
 682  * @pe: addr of the page entry
 683  * @src: src addr to copy from
 684  * @count: number of page entries to update
 685  *
 686  * Update PTEs by copying them from the GART using sDMA (CIK).
 687  */
 688 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
 689                                  uint64_t pe, uint64_t src,
 690                                  unsigned count)
 691 {
 692         while (count) {
 693                 unsigned bytes = count * 8;
 694                 if (bytes > 0x1FFFF8)
 695                         bytes = 0x1FFFF8;
 696
 697                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
 698                         SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 699                 ib->ptr[ib->length_dw++] = bytes;
 700                 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 701                 ib->ptr[ib->length_dw++] = lower_32_bits(src);
 702                 ib->ptr[ib->length_dw++] = upper_32_bits(src);
 703                 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 704                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 705
 706                 pe += bytes;
 707                 src += bytes;
 708                 count -= bytes / 8;
 709         }
 710 }
 711
 712 /**
 713  * cik_sdma_vm_write_pages - update PTEs by writing them manually
 714  *
 715  * @ib: indirect buffer to fill with commands
 716  * @pe: addr of the page entry
 717  * @addr: dst addr to write into pe
 718  * @count: number of page entries to update
 719  * @incr: increase next addr by incr bytes
 720  * @flags: access flags
 721  *
 722  * Update PTEs by writing them manually using sDMA (CIK).
 723  */
 724 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
 725                                   const dma_addr_t *pages_addr, uint64_t pe,
 726                                   uint64_t addr, unsigned count,
 727                                   uint32_t incr, uint32_t flags)
 728 {
 729         uint64_t value;
 730         unsigned ndw;
 731
 732         while (count) {
 733                 ndw = count * 2;
 734                 if (ndw > 0xFFFFE)
 735                         ndw = 0xFFFFE;
 736
 737                 /* for non-physically contiguous pages (system) */
 738                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 739                         SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 740                 ib->ptr[ib->length_dw++] = pe;
 741                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 742                 ib->ptr[ib->length_dw++] = ndw;
 743                 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 744                         value = amdgpu_vm_map_gart(pages_addr, addr);
 745                         addr += incr;
 746                         value |= flags;
 747                         ib->ptr[ib->length_dw++] = value;
 748                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
 749                 }
 750         }
 751 }
 752
 753 /**
 754  * cik_sdma_vm_set_pages - update the page tables using sDMA
 755  *
 756  * @ib: indirect buffer to fill with commands
 757  * @pe: addr of the page entry
 758  * @addr: dst addr to write into pe
 759  * @count: number of page entries to update
 760  * @incr: increase next addr by incr bytes
 761  * @flags: access flags
 762  *
 763  * Update the page tables using sDMA (CIK).
 764  */
 765 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib,
 766                                     uint64_t pe,
 767                                     uint64_t addr, unsigned count,
 768                                     uint32_t incr, uint32_t flags)
 769 {
 770         uint64_t value;
 771         unsigned ndw;
 772
 773         while (count) {
 774                 ndw = count;
 775                 if (ndw > 0x7FFFF)
 776                         ndw = 0x7FFFF;
 777
 778                 if (flags & AMDGPU_PTE_VALID)
 779                         value = addr;
 780                 else
 781                         value = 0;
 782
 783                 /* for physically contiguous pages (vram) */
 784                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
 785                 ib->ptr[ib->length_dw++] = pe; /* dst addr */
 786                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 787                 ib->ptr[ib->length_dw++] = flags; /* mask */
 788                 ib->ptr[ib->length_dw++] = 0;
 789                 ib->ptr[ib->length_dw++] = value; /* value */
 790                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 791                 ib->ptr[ib->length_dw++] = incr; /* increment size */
 792                 ib->ptr[ib->length_dw++] = 0;
 793                 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
 794
 795                 pe += ndw * 8;
 796                 addr += ndw * incr;
 797                 count -= ndw;
 798         }
 799 }
 800
 801 /**
 802  * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
 803  *
 804  * @ib: indirect buffer to fill with padding
 805  *
 806  */
 807 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 808 {
 809         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 810         u32 pad_count;
 811         int i;
 812
 813         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 814         for (i = 0; i < pad_count; i++)
 815                 if (sdma && sdma->burst_nop && (i == 0))
 816                         ib->ptr[ib->length_dw++] =
 817                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
 818                                         SDMA_NOP_COUNT(pad_count - 1);
 819                 else
 820                         ib->ptr[ib->length_dw++] =
 821                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
 822 }
 823
 824 /**
 825  * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
 826  *
 827  * @ring: amdgpu_ring pointer
 828  *
 829  * Make sure all previous operations are completed (CIK).
 830  */
 831 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 832 {
 833         uint32_t seq = ring->fence_drv.sync_seq;
 834         uint64_t addr = ring->fence_drv.gpu_addr;
 835
 836         /* wait for idle */
 837         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
 838                                             SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 839                                             SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
 840                                             SDMA_POLL_REG_MEM_EXTRA_M));
 841         amdgpu_ring_write(ring, addr & 0xfffffffc);
 842         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 843         amdgpu_ring_write(ring, seq); /* reference */
 844         amdgpu_ring_write(ring, 0xfffffff); /* mask */
 845         amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
 846 }
 847
 848 /**
 849  * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
 850  *
 851  * @ring: amdgpu_ring pointer
 852  * @vm: amdgpu_vm pointer
 853  *
 854  * Update the page table base and flush the VM TLB
 855  * using sDMA (CIK).
 856  */
 857 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 858                                         unsigned vm_id, uint64_t pd_addr)
 859 {
 860         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 861                           SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 862
 863         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 864         if (vm_id < 8) {
 865                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 866         } else {
 867                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 868         }
 869         amdgpu_ring_write(ring, pd_addr >> 12);
 870
 871         /* flush TLB */
 872         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 873         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 874         amdgpu_ring_write(ring, 1 << vm_id);
 875
 876         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 877         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 878         amdgpu_ring_write(ring, 0);
 879         amdgpu_ring_write(ring, 0); /* reference */
 880         amdgpu_ring_write(ring, 0); /* mask */
 881         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 882 }
 883
 884 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
 885                                  bool enable)
 886 {
 887         u32 orig, data;
 888
 889         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
 890                 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
 891                 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
 892         } else {
 893                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
 894                 data |= 0xff000000;
 895                 if (data != orig)
 896                         WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
 897
 898                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
 899                 data |= 0xff000000;
 900                 if (data != orig)
 901                         WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
 902         }
 903 }
 904
 905 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
 906                                  bool enable)
 907 {
 908         u32 orig, data;
 909
 910         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
 911                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 912                 data |= 0x100;
 913                 if (orig != data)
 914                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 915
 916                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 917                 data |= 0x100;
 918                 if (orig != data)
 919                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 920         } else {
 921                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 922                 data &= ~0x100;
 923                 if (orig != data)
 924                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 925
 926                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 927                 data &= ~0x100;
 928                 if (orig != data)
 929                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 930         }
 931 }
 932
 933 static int cik_sdma_early_init(void *handle)
 934 {
 935         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 936
 937         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 938
 939         cik_sdma_set_ring_funcs(adev);
 940         cik_sdma_set_irq_funcs(adev);
 941         cik_sdma_set_buffer_funcs(adev);
 942         cik_sdma_set_vm_pte_funcs(adev);
 943
 944         return 0;
 945 }
 946
 947 static int cik_sdma_sw_init(void *handle)
 948 {
 949         struct amdgpu_ring *ring;
 950         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 951         int r, i;
 952
 953         r = cik_sdma_init_microcode(adev);
 954         if (r) {
 955                 DRM_ERROR("Failed to load sdma firmware!\n");
 956                 return r;
 957         }
 958
 959         /* SDMA trap event */
 960         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
 961         if (r)
 962                 return r;
 963
 964         /* SDMA Privileged inst */
 965         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
 966         if (r)
 967                 return r;
 968
 969         /* SDMA Privileged inst */
 970         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
 971         if (r)
 972                 return r;
 973
 974         for (i = 0; i < adev->sdma.num_instances; i++) {
 975                 ring = &adev->sdma.instance[i].ring;
 976                 ring->ring_obj = NULL;
 977                 sprintf(ring->name, "sdma%d", i);
 978                 r = amdgpu_ring_init(adev, ring, 1024,
 979                                      SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
 980                                      &adev->sdma.trap_irq,
 981                                      (i == 0) ?
 982                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
 983                                      AMDGPU_RING_TYPE_SDMA);
 984                 if (r)
 985                         return r;
 986         }
 987
 988         return r;
 989 }
 990
 991 static int cik_sdma_sw_fini(void *handle)
 992 {
 993         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 994         int i;
 995
 996         for (i = 0; i < adev->sdma.num_instances; i++)
 997                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 998
 999         cik_sdma_free_microcode(adev);
1000         return 0;
1001 }
1002
1003 static int cik_sdma_hw_init(void *handle)
1004 {
1005         int r;
1006         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1007
1008         r = cik_sdma_start(adev);
1009         if (r)
1010                 return r;
1011
1012         return r;
1013 }
1014
1015 static int cik_sdma_hw_fini(void *handle)
1016 {
1017         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1018
1019         cik_sdma_enable(adev, false);
1020
1021         return 0;
1022 }
1023
1024 static int cik_sdma_suspend(void *handle)
1025 {
1026         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1027
1028         return cik_sdma_hw_fini(adev);
1029 }
1030
1031 static int cik_sdma_resume(void *handle)
1032 {
1033         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1034
1035         return cik_sdma_hw_init(adev);
1036 }
1037
1038 static bool cik_sdma_is_idle(void *handle)
1039 {
1040         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1041         u32 tmp = RREG32(mmSRBM_STATUS2);
1042
1043         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1044                                 SRBM_STATUS2__SDMA1_BUSY_MASK))
1045             return false;
1046
1047         return true;
1048 }
1049
1050 static int cik_sdma_wait_for_idle(void *handle)
1051 {
1052         unsigned i;
1053         u32 tmp;
1054         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1055
1056         for (i = 0; i < adev->usec_timeout; i++) {
1057                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1058                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1059
1060                 if (!tmp)
1061                         return 0;
1062                 udelay(1);
1063         }
1064         return -ETIMEDOUT;
1065 }
1066
1067 static int cik_sdma_soft_reset(void *handle)
1068 {
1069         u32 srbm_soft_reset = 0;
1070         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1071         u32 tmp = RREG32(mmSRBM_STATUS2);
1072
1073         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1074                 /* sdma0 */
1075                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1076                 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1077                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1078                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1079         }
1080         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1081                 /* sdma1 */
1082                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1083                 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1084                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1085                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1086         }
1087
1088         if (srbm_soft_reset) {
1089                 tmp = RREG32(mmSRBM_SOFT_RESET);
1090                 tmp |= srbm_soft_reset;
1091                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1092                 WREG32(mmSRBM_SOFT_RESET, tmp);
1093                 tmp = RREG32(mmSRBM_SOFT_RESET);
1094
1095                 udelay(50);
1096
1097                 tmp &= ~srbm_soft_reset;
1098                 WREG32(mmSRBM_SOFT_RESET, tmp);
1099                 tmp = RREG32(mmSRBM_SOFT_RESET);
1100
1101                 /* Wait a little for things to settle down */
1102                 udelay(50);
1103         }
1104
1105         return 0;
1106 }
1107
1108 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1109                                        struct amdgpu_irq_src *src,
1110                                        unsigned type,
1111                                        enum amdgpu_interrupt_state state)
1112 {
1113         u32 sdma_cntl;
1114
1115         switch (type) {
1116         case AMDGPU_SDMA_IRQ_TRAP0:
1117                 switch (state) {
1118                 case AMDGPU_IRQ_STATE_DISABLE:
1119                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1120                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1121                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1122                         break;
1123                 case AMDGPU_IRQ_STATE_ENABLE:
1124                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1125                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1126                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1127                         break;
1128                 default:
1129                         break;
1130                 }
1131                 break;
1132         case AMDGPU_SDMA_IRQ_TRAP1:
1133                 switch (state) {
1134                 case AMDGPU_IRQ_STATE_DISABLE:
1135                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1136                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1137                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1138                         break;
1139                 case AMDGPU_IRQ_STATE_ENABLE:
1140                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1141                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1142                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1143                         break;
1144                 default:
1145                         break;
1146                 }
1147                 break;
1148         default:
1149                 break;
1150         }
1151         return 0;
1152 }
1153
1154 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1155                                      struct amdgpu_irq_src *source,
1156                                      struct amdgpu_iv_entry *entry)
1157 {
1158         u8 instance_id, queue_id;
1159
1160         instance_id = (entry->ring_id & 0x3) >> 0;
1161         queue_id = (entry->ring_id & 0xc) >> 2;
1162         DRM_DEBUG("IH: SDMA trap\n");
1163         switch (instance_id) {
1164         case 0:
1165                 switch (queue_id) {
1166                 case 0:
1167                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1168                         break;
1169                 case 1:
1170                         /* XXX compute */
1171                         break;
1172                 case 2:
1173                         /* XXX compute */
1174                         break;
1175                 }
1176                 break;
1177         case 1:
1178                 switch (queue_id) {
1179                 case 0:
1180                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1181                         break;
1182                 case 1:
1183                         /* XXX compute */
1184                         break;
1185                 case 2:
1186                         /* XXX compute */
1187                         break;
1188                 }
1189                 break;
1190         }
1191
1192         return 0;
1193 }
1194
1195 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1196                                              struct amdgpu_irq_src *source,
1197                                              struct amdgpu_iv_entry *entry)
1198 {
1199         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1200         schedule_work(&adev->reset_work);
1201         return 0;
1202 }
1203
1204 static int cik_sdma_set_clockgating_state(void *handle,
1205                                           enum amd_clockgating_state state)
1206 {
1207         bool gate = false;
1208         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1209
1210         if (state == AMD_CG_STATE_GATE)
1211                 gate = true;
1212
1213         cik_enable_sdma_mgcg(adev, gate);
1214         cik_enable_sdma_mgls(adev, gate);
1215
1216         return 0;
1217 }
1218
1219 static int cik_sdma_set_powergating_state(void *handle,
1220                                           enum amd_powergating_state state)
1221 {
1222         return 0;
1223 }
1224
1225 const struct amd_ip_funcs cik_sdma_ip_funcs = {
1226         .name = "cik_sdma",
1227         .early_init = cik_sdma_early_init,
1228         .late_init = NULL,
1229         .sw_init = cik_sdma_sw_init,
1230         .sw_fini = cik_sdma_sw_fini,
1231         .hw_init = cik_sdma_hw_init,
1232         .hw_fini = cik_sdma_hw_fini,
1233         .suspend = cik_sdma_suspend,
1234         .resume = cik_sdma_resume,
1235         .is_idle = cik_sdma_is_idle,
1236         .wait_for_idle = cik_sdma_wait_for_idle,
1237         .soft_reset = cik_sdma_soft_reset,
1238         .set_clockgating_state = cik_sdma_set_clockgating_state,
1239         .set_powergating_state = cik_sdma_set_powergating_state,
1240 };
1241
1242 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1243         .get_rptr = cik_sdma_ring_get_rptr,
1244         .get_wptr = cik_sdma_ring_get_wptr,
1245         .set_wptr = cik_sdma_ring_set_wptr,
1246         .parse_cs = NULL,
1247         .emit_ib = cik_sdma_ring_emit_ib,
1248         .emit_fence = cik_sdma_ring_emit_fence,
1249         .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1250         .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1251         .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1252         .emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate,
1253         .test_ring = cik_sdma_ring_test_ring,
1254         .test_ib = cik_sdma_ring_test_ib,
1255         .insert_nop = cik_sdma_ring_insert_nop,
1256         .pad_ib = cik_sdma_ring_pad_ib,
1257 };
1258
1259 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1260 {
1261         int i;
1262
1263         for (i = 0; i < adev->sdma.num_instances; i++)
1264                 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1265 }
1266
1267 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1268         .set = cik_sdma_set_trap_irq_state,
1269         .process = cik_sdma_process_trap_irq,
1270 };
1271
1272 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1273         .process = cik_sdma_process_illegal_inst_irq,
1274 };
1275
1276 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1277 {
1278         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1279         adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1280         adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1281 }
1282
1283 /**
1284  * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1285  *
1286  * @ring: amdgpu_ring structure holding ring information
1287  * @src_offset: src GPU address
1288  * @dst_offset: dst GPU address
1289  * @byte_count: number of bytes to xfer
1290  *
1291  * Copy GPU buffers using the DMA engine (CIK).
1292  * Used by the amdgpu ttm implementation to move pages if
1293  * registered as the asic copy callback.
1294  */
1295 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1296                                       uint64_t src_offset,
1297                                       uint64_t dst_offset,
1298                                       uint32_t byte_count)
1299 {
1300         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1301         ib->ptr[ib->length_dw++] = byte_count;
1302         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1303         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1304         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1305         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1306         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1307 }
1308
1309 /**
1310  * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1311  *
1312  * @ring: amdgpu_ring structure holding ring information
1313  * @src_data: value to write to buffer
1314  * @dst_offset: dst GPU address
1315  * @byte_count: number of bytes to xfer
1316  *
1317  * Fill GPU buffers using the DMA engine (CIK).
1318  */
1319 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1320                                       uint32_t src_data,
1321                                       uint64_t dst_offset,
1322                                       uint32_t byte_count)
1323 {
1324         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1325         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1326         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1327         ib->ptr[ib->length_dw++] = src_data;
1328         ib->ptr[ib->length_dw++] = byte_count;
1329 }
1330
1331 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1332         .copy_max_bytes = 0x1fffff,
1333         .copy_num_dw = 7,
1334         .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1335
1336         .fill_max_bytes = 0x1fffff,
1337         .fill_num_dw = 5,
1338         .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1339 };
1340
1341 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1342 {
1343         if (adev->mman.buffer_funcs == NULL) {
1344                 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1345                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1346         }
1347 }
1348
1349 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1350         .copy_pte = cik_sdma_vm_copy_pte,
1351         .write_pte = cik_sdma_vm_write_pte,
1352         .set_pte_pde = cik_sdma_vm_set_pte_pde,
1353 };
1354
1355 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1356 {
1357         unsigned i;
1358
1359         if (adev->vm_manager.vm_pte_funcs == NULL) {
1360                 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1361                 for (i = 0; i < adev->sdma.num_instances; i++)
1362                         adev->vm_manager.vm_pte_rings[i] =
1363                                 &adev->sdma.instance[i].ring;
1364
1365                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1366         }
1367 }