2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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6 * copy of this software and associated documentation files (the "Software"),
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
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21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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25 #include <drm/amdgpu_drm.h>
26 #include <drm/drm_drv.h>
27 #include <drm/drm_fbdev_generic.h>
28 #include <drm/drm_gem.h>
29 #include <drm/drm_vblank.h>
30 #include <drm/drm_managed.h>
31 #include "amdgpu_drv.h"
33 #include <drm/drm_pciids.h>
34 #include <linux/module.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_probe_helper.h>
38 #include <linux/mmu_notifier.h>
39 #include <linux/suspend.h>
40 #include <linux/cc_platform.h>
42 #include <linux/dynamic_debug.h>
45 #include "amdgpu_irq.h"
46 #include "amdgpu_dma_buf.h"
47 #include "amdgpu_sched.h"
48 #include "amdgpu_fdinfo.h"
49 #include "amdgpu_amdkfd.h"
51 #include "amdgpu_ras.h"
52 #include "amdgpu_xgmi.h"
53 #include "amdgpu_reset.h"
57 * - 3.0.0 - initial driver
58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
61 * - 3.3.0 - Add VM support for UVD on supported hardware.
62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
63 * - 3.5.0 - Add support for new UVD_NO_OP register.
64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
65 * - 3.7.0 - Add support for VCE clock list packet
66 * - 3.8.0 - Add support raster config init in the kernel
67 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
70 * - 3.12.0 - Add query for double offchip LDS buffers
71 * - 3.13.0 - Add PRT support
72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
73 * - 3.15.0 - Export more gpu info for gfx9
74 * - 3.16.0 - Add reserved vmid support
75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
76 * - 3.18.0 - Export gpu always on cu bitmap
77 * - 3.19.0 - Add support for UVD MJPEG decode
78 * - 3.20.0 - Add support for local BOs
79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
81 * - 3.23.0 - Add query for VRAM lost counter
82 * - 3.24.0 - Add high priority compute support for gfx9
83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
94 * - 3.36.0 - Allow reading more status registers on si/cik
95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
99 * - 3.41.0 - Add video codec query
100 * - 3.42.0 - Add 16bpc fixed point display support
101 * - 3.43.0 - Add device hot plug/unplug support
102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
103 * - 3.45.0 - Add context ioctl stable pstate interface
104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
106 * - 3.48.0 - Add IP discovery version info to HW INFO
107 * - 3.49.0 - Add gang submit into CS IOCTL
108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock
109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock
110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl
112 #define KMS_DRIVER_MAJOR 3
113 #define KMS_DRIVER_MINOR 51
114 #define KMS_DRIVER_PATCHLEVEL 0
116 unsigned int amdgpu_vram_limit = UINT_MAX;
117 int amdgpu_vis_vram_limit;
118 int amdgpu_gart_size = -1; /* auto */
119 int amdgpu_gtt_size = -1; /* auto */
120 int amdgpu_moverate = -1; /* auto */
121 int amdgpu_audio = -1;
122 int amdgpu_disp_priority;
124 int amdgpu_pcie_gen2 = -1;
126 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
128 int amdgpu_fw_load_type = -1;
129 int amdgpu_aspm = -1;
130 int amdgpu_runtime_pm = -1;
131 uint amdgpu_ip_block_mask = 0xffffffff;
132 int amdgpu_bapm = -1;
133 int amdgpu_deep_color;
134 int amdgpu_vm_size = -1;
135 int amdgpu_vm_fragment_size = -1;
136 int amdgpu_vm_block_size = -1;
137 int amdgpu_vm_fault_stop;
139 int amdgpu_vm_update_mode = -1;
140 int amdgpu_exp_hw_support;
142 int amdgpu_sched_jobs = 32;
143 int amdgpu_sched_hw_submission = 2;
144 uint amdgpu_pcie_gen_cap;
145 uint amdgpu_pcie_lane_cap;
146 u64 amdgpu_cg_mask = 0xffffffffffffffff;
147 uint amdgpu_pg_mask = 0xffffffff;
148 uint amdgpu_sdma_phase_quantum = 32;
149 char *amdgpu_disable_cu = NULL;
150 char *amdgpu_virtual_display = NULL;
153 * OverDrive(bit 14) disabled by default
154 * GFX DCS(bit 19) disabled by default
156 uint amdgpu_pp_feature_mask = 0xfff7bfff;
157 uint amdgpu_force_long_training;
158 int amdgpu_job_hang_limit;
159 int amdgpu_lbpw = -1;
160 int amdgpu_compute_multipipe = -1;
161 int amdgpu_gpu_recovery = -1; /* auto */
163 uint amdgpu_smu_memory_pool_size;
164 int amdgpu_smu_pptable_id = -1;
166 * FBC (bit 0) disabled by default
167 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
168 * - With this, for multiple monitors in sync(e.g. with the same model),
169 * mclk switching will be allowed. And the mclk will be not foced to the
170 * highest. That helps saving some idle power.
171 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
172 * PSR (bit 3) disabled by default
173 * EDP NO POWER SEQUENCING (bit 4) disabled by default
175 uint amdgpu_dc_feature_mask = 2;
176 uint amdgpu_dc_debug_mask;
177 uint amdgpu_dc_visual_confirm;
178 int amdgpu_async_gfx_ring = 1;
180 int amdgpu_discovery = -1;
183 int amdgpu_noretry = -1;
184 int amdgpu_force_asic_type = -1;
185 int amdgpu_tmz = -1; /* auto */
186 uint amdgpu_freesync_vid_mode;
187 int amdgpu_reset_method = -1; /* auto */
188 int amdgpu_num_kcq = -1;
189 int amdgpu_smartshift_bias;
190 int amdgpu_use_xgmi_p2p = 1;
191 int amdgpu_vcnfw_log;
193 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
195 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
207 struct amdgpu_mgpu_info mgpu_info = {
208 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
209 .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
210 mgpu_info.delayed_reset_work,
211 amdgpu_drv_delayed_reset_work_handler, 0),
213 int amdgpu_ras_enable = -1;
214 uint amdgpu_ras_mask = 0xffffffff;
215 int amdgpu_bad_page_threshold = -1;
216 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
217 .timeout_fatal_disable = false,
218 .period = 0x0, /* default to 0x0 (timeout disable) */
222 * DOC: vramlimit (int)
223 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
225 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
226 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
229 * DOC: vis_vramlimit (int)
230 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
232 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
233 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
236 * DOC: gartsize (uint)
237 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing.
238 * The default is -1 (The size depends on asic).
240 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)");
241 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
245 * Restrict the size of GTT domain (for userspace use) in MiB for testing.
246 * The default is -1 (Use 1/2 RAM, minimum value is 3GB).
248 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");
249 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
252 * DOC: moverate (int)
253 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
255 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
256 module_param_named(moverate, amdgpu_moverate, int, 0600);
260 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
262 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
263 module_param_named(audio, amdgpu_audio, int, 0444);
266 * DOC: disp_priority (int)
267 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
269 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
270 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
274 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
276 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
277 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
280 * DOC: pcie_gen2 (int)
281 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
283 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
284 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
288 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
290 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
291 module_param_named(msi, amdgpu_msi, int, 0444);
294 * DOC: lockup_timeout (string)
295 * Set GPU scheduler timeout value in ms.
297 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
298 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
299 * to the default timeout.
301 * - With one value specified, the setting will apply to all non-compute jobs.
302 * - With multiple values specified, the first one will be for GFX.
303 * The second one is for Compute. The third and fourth ones are
304 * for SDMA and Video.
306 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
307 * jobs is 10000. The timeout for compute is 60000.
309 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
310 "for passthrough or sriov, 10000 for all jobs."
311 " 0: keep default value. negative: infinity timeout), "
312 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
313 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
314 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
318 * Override for dynamic power management setting
319 * (0 = disable, 1 = enable)
320 * The default is -1 (auto).
322 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
323 module_param_named(dpm, amdgpu_dpm, int, 0444);
326 * DOC: fw_load_type (int)
327 * Set different firmware loading type for debugging, if supported.
328 * Set to 0 to force direct loading if supported by the ASIC. Set
329 * to -1 to select the default loading mode for the ASIC, as defined
330 * by the driver. The default is -1 (auto).
332 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
333 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
337 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
339 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
340 module_param_named(aspm, amdgpu_aspm, int, 0444);
344 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
345 * the dGPUs when they are idle if supported. The default is -1 (auto enable).
346 * Setting the value to 0 disables this functionality.
348 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)");
349 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
352 * DOC: ip_block_mask (uint)
353 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
354 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
355 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
356 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
358 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
359 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
363 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
364 * The default -1 (auto, enabled)
366 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
367 module_param_named(bapm, amdgpu_bapm, int, 0444);
370 * DOC: deep_color (int)
371 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
373 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
374 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
378 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
380 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
381 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
384 * DOC: vm_fragment_size (int)
385 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
387 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
388 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
391 * DOC: vm_block_size (int)
392 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
394 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
395 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
398 * DOC: vm_fault_stop (int)
399 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
401 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
402 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
405 * DOC: vm_debug (int)
406 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
408 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
409 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
412 * DOC: vm_update_mode (int)
413 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
414 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
416 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
417 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
420 * DOC: exp_hw_support (int)
421 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
423 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
424 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
428 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
430 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
431 module_param_named(dc, amdgpu_dc, int, 0444);
434 * DOC: sched_jobs (int)
435 * Override the max number of jobs supported in the sw queue. The default is 32.
437 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
438 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
441 * DOC: sched_hw_submission (int)
442 * Override the max number of HW submissions. The default is 2.
444 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
445 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
448 * DOC: ppfeaturemask (hexint)
449 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
450 * The default is the current set of stable power features.
452 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
453 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
456 * DOC: forcelongtraining (uint)
457 * Force long memory training in resume.
458 * The default is zero, indicates short training in resume.
460 MODULE_PARM_DESC(forcelongtraining, "force memory long training");
461 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
464 * DOC: pcie_gen_cap (uint)
465 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
466 * The default is 0 (automatic for each asic).
468 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
469 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
472 * DOC: pcie_lane_cap (uint)
473 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
474 * The default is 0 (automatic for each asic).
476 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
477 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
480 * DOC: cg_mask (ullong)
481 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
482 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
484 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
485 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
488 * DOC: pg_mask (uint)
489 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
490 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
492 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
493 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
496 * DOC: sdma_phase_quantum (uint)
497 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
499 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
500 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
503 * DOC: disable_cu (charp)
504 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
506 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
507 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
510 * DOC: virtual_display (charp)
511 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
512 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
513 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
514 * device at 26:00.0. The default is NULL.
516 MODULE_PARM_DESC(virtual_display,
517 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
518 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
521 * DOC: job_hang_limit (int)
522 * Set how much time allow a job hang and not drop it. The default is 0.
524 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
525 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
529 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
531 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
532 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
534 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
535 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
538 * DOC: gpu_recovery (int)
539 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
541 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
542 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
545 * DOC: emu_mode (int)
546 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
548 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
549 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
552 * DOC: ras_enable (int)
553 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
555 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
556 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
559 * DOC: ras_mask (uint)
560 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
561 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
563 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
564 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
567 * DOC: timeout_fatal_disable (bool)
568 * Disable Watchdog timeout fatal error event
570 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
571 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
574 * DOC: timeout_period (uint)
575 * Modify the watchdog timeout max_cycles as (1 << period)
577 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
578 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
581 * DOC: si_support (int)
582 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
583 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
584 * otherwise using amdgpu driver.
586 #ifdef CONFIG_DRM_AMDGPU_SI
588 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
589 int amdgpu_si_support = 0;
590 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
592 int amdgpu_si_support = 1;
593 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
596 module_param_named(si_support, amdgpu_si_support, int, 0444);
600 * DOC: cik_support (int)
601 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
602 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
603 * otherwise using amdgpu driver.
605 #ifdef CONFIG_DRM_AMDGPU_CIK
607 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
608 int amdgpu_cik_support = 0;
609 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
611 int amdgpu_cik_support = 1;
612 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
615 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
619 * DOC: smu_memory_pool_size (uint)
620 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
621 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
623 MODULE_PARM_DESC(smu_memory_pool_size,
624 "reserve gtt for smu debug usage, 0 = disable,"
625 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
626 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
629 * DOC: async_gfx_ring (int)
630 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
632 MODULE_PARM_DESC(async_gfx_ring,
633 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
634 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
638 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
640 MODULE_PARM_DESC(mcbp,
641 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
642 module_param_named(mcbp, amdgpu_mcbp, int, 0444);
645 * DOC: discovery (int)
646 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
647 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
649 MODULE_PARM_DESC(discovery,
650 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
651 module_param_named(discovery, amdgpu_discovery, int, 0444);
655 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
656 * (0 = disabled (default), 1 = enabled)
658 MODULE_PARM_DESC(mes,
659 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
660 module_param_named(mes, amdgpu_mes, int, 0444);
664 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.
665 * (0 = disabled (default), 1 = enabled)
667 MODULE_PARM_DESC(mes_kiq,
668 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)");
669 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444);
673 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
674 * do not support per-process XNACK this also disables retry page faults.
675 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
677 MODULE_PARM_DESC(noretry,
678 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
679 module_param_named(noretry, amdgpu_noretry, int, 0644);
682 * DOC: force_asic_type (int)
683 * A non negative value used to specify the asic type for all supported GPUs.
685 MODULE_PARM_DESC(force_asic_type,
686 "A non negative value used to specify the asic type for all supported GPUs");
687 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
690 * DOC: use_xgmi_p2p (int)
691 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
693 MODULE_PARM_DESC(use_xgmi_p2p,
694 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
695 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
698 #ifdef CONFIG_HSA_AMD
700 * DOC: sched_policy (int)
701 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
702 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
703 * assigns queues to HQDs.
705 int sched_policy = KFD_SCHED_POLICY_HWS;
706 module_param(sched_policy, int, 0444);
707 MODULE_PARM_DESC(sched_policy,
708 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
711 * DOC: hws_max_conc_proc (int)
712 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
713 * number of VMIDs assigned to the HWS, which is also the default.
715 int hws_max_conc_proc = -1;
716 module_param(hws_max_conc_proc, int, 0444);
717 MODULE_PARM_DESC(hws_max_conc_proc,
718 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
721 * DOC: cwsr_enable (int)
722 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
723 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
727 module_param(cwsr_enable, int, 0444);
728 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
731 * DOC: max_num_of_queues_per_device (int)
732 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
735 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
736 module_param(max_num_of_queues_per_device, int, 0444);
737 MODULE_PARM_DESC(max_num_of_queues_per_device,
738 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
741 * DOC: send_sigterm (int)
742 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
743 * but just print errors on dmesg. Setting 1 enables sending sigterm.
746 module_param(send_sigterm, int, 0444);
747 MODULE_PARM_DESC(send_sigterm,
748 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
751 * DOC: debug_largebar (int)
752 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
753 * system. This limits the VRAM size reported to ROCm applications to the visible
754 * size, usually 256MB.
755 * Default value is 0, diabled.
758 module_param(debug_largebar, int, 0444);
759 MODULE_PARM_DESC(debug_largebar,
760 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
763 * DOC: ignore_crat (int)
764 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
765 * table to get information about AMD APUs. This option can serve as a workaround on
766 * systems with a broken CRAT table.
768 * Default is auto (according to asic type, iommu_v2, and crat table, to decide
772 module_param(ignore_crat, int, 0444);
773 MODULE_PARM_DESC(ignore_crat,
774 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
777 * DOC: halt_if_hws_hang (int)
778 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
779 * Setting 1 enables halt on hang.
781 int halt_if_hws_hang;
782 module_param(halt_if_hws_hang, int, 0644);
783 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
786 * DOC: hws_gws_support(bool)
787 * Assume that HWS supports GWS barriers regardless of what firmware version
788 * check says. Default value: false (rely on MEC2 firmware version check).
790 bool hws_gws_support;
791 module_param(hws_gws_support, bool, 0444);
792 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
795 * DOC: queue_preemption_timeout_ms (int)
796 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
798 int queue_preemption_timeout_ms = 9000;
799 module_param(queue_preemption_timeout_ms, int, 0644);
800 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
803 * DOC: debug_evictions(bool)
804 * Enable extra debug messages to help determine the cause of evictions
806 bool debug_evictions;
807 module_param(debug_evictions, bool, 0644);
808 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
811 * DOC: no_system_mem_limit(bool)
812 * Disable system memory limit, to support multiple process shared memory
814 bool no_system_mem_limit;
815 module_param(no_system_mem_limit, bool, 0644);
816 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
819 * DOC: no_queue_eviction_on_vm_fault (int)
820 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
822 int amdgpu_no_queue_eviction_on_vm_fault = 0;
823 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
824 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
828 * DOC: pcie_p2p (bool)
829 * Enable PCIe P2P (requires large-BAR). Default value: true (on)
831 #ifdef CONFIG_HSA_AMD_P2P
832 bool pcie_p2p = true;
833 module_param(pcie_p2p, bool, 0444);
834 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
838 * DOC: dcfeaturemask (uint)
839 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
840 * The default is the current set of stable display features.
842 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
843 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
846 * DOC: dcdebugmask (uint)
847 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
849 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
850 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
852 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
853 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
856 * DOC: abmlevel (uint)
857 * Override the default ABM (Adaptive Backlight Management) level used for DC
858 * enabled hardware. Requires DMCU to be supported and loaded.
859 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
860 * default. Values 1-4 control the maximum allowable brightness reduction via
861 * the ABM algorithm, with 1 being the least reduction and 4 being the most
864 * Defaults to 0, or disabled. Userspace can still override this level later
867 uint amdgpu_dm_abm_level;
868 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
869 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
871 int amdgpu_backlight = -1;
872 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
873 module_param_named(backlight, amdgpu_backlight, bint, 0444);
877 * Trusted Memory Zone (TMZ) is a method to protect data being written
878 * to or read from memory.
880 * The default value: 0 (off). TODO: change to auto till it is completed.
882 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
883 module_param_named(tmz, amdgpu_tmz, int, 0444);
886 * DOC: freesync_video (uint)
887 * Enable the optimization to adjust front porch timing to achieve seamless
888 * mode change experience when setting a freesync supported mode for which full
889 * modeset is not needed.
891 * The Display Core will add a set of modes derived from the base FreeSync
892 * video mode into the corresponding connector's mode list based on commonly
893 * used refresh rates and VRR range of the connected display, when users enable
894 * this feature. From the userspace perspective, they can see a seamless mode
895 * change experience when the change between different refresh rates under the
896 * same resolution. Additionally, userspace applications such as Video playback
897 * can read this modeset list and change the refresh rate based on the video
898 * frame rate. Finally, the userspace can also derive an appropriate mode for a
899 * particular refresh rate based on the FreeSync Mode and add it to the
900 * connector's mode list.
902 * Note: This is an experimental feature.
904 * The default value: 0 (off).
908 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");
909 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
912 * DOC: reset_method (int)
913 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
915 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
916 module_param_named(reset_method, amdgpu_reset_method, int, 0444);
919 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
920 * threshold value of faulty pages detected by RAS ECC, which may
921 * result in the GPU entering bad status when the number of total
922 * faulty pages by ECC exceeds the threshold value.
924 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)");
925 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
927 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
928 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
931 * DOC: vcnfw_log (int)
932 * Enable vcnfw log output for debugging, the default is disabled.
934 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
935 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
938 * DOC: smu_pptable_id (int)
939 * Used to override pptable id. id = 0 use VBIOS pptable.
940 * id > 0 use the soft pptable with specicfied id.
942 MODULE_PARM_DESC(smu_pptable_id,
943 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
944 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
946 /* These devices are not supported by amdgpu.
947 * They are supported by the mach64, r128, radeon drivers
949 static const u16 amdgpu_unsupported_pciidlist[] = {
1574 /* radeon secondary ids */
1657 static const struct pci_device_id pciidlist[] = {
1658 #ifdef CONFIG_DRM_AMDGPU_SI
1659 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1660 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1661 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1662 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1663 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1664 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1665 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1666 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1667 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1668 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1669 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1670 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1671 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1672 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1673 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1674 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1675 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1676 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1677 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1678 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1679 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1680 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1681 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1682 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1683 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1684 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1685 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1686 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1687 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1688 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1689 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1690 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1691 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1692 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1693 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1694 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1695 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1696 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1697 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1698 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1699 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1700 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1701 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1702 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1703 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1704 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1705 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1706 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1707 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1708 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1709 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1710 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1711 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1712 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1713 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1714 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1715 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1716 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1717 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1718 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1719 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1720 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1721 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1722 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1723 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1724 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1725 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1726 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1727 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1728 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1729 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1730 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1732 #ifdef CONFIG_DRM_AMDGPU_CIK
1734 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1735 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1736 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1737 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1738 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1739 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1740 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1741 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1742 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1743 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1744 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1745 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1746 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1747 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1748 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1749 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1750 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1751 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1752 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1753 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1754 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1755 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1757 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1758 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1759 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1760 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1761 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1762 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1763 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1764 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1765 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1766 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1767 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1769 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1770 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1771 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1772 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1773 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1774 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1775 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1776 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1777 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1778 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1779 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1780 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1782 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1783 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1784 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1785 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1786 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1787 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1788 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1789 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1790 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1791 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1792 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1793 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1794 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1795 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1796 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1797 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1799 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1800 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1801 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1802 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1803 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1804 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1805 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1806 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1807 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1808 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1809 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1810 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1811 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1812 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1813 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1814 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1817 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1818 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1819 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1820 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1821 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1823 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1824 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1825 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1826 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1827 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1828 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1829 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1830 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1831 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1833 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1834 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1836 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1837 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1838 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1839 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1840 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1842 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
1844 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1845 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1846 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1847 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1848 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1849 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1850 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1851 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1852 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1854 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1855 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1856 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1857 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1858 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1859 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1860 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1861 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1862 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1863 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1864 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1865 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1866 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1868 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1869 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1870 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1871 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1872 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1873 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1874 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1875 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1877 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1878 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1879 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1881 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1882 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1883 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1884 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1885 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1886 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1887 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1888 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1889 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1890 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1891 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1892 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1893 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1894 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1895 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1897 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1898 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1899 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1900 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1901 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1903 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1904 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1905 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1906 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1907 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1908 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1909 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1911 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1912 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1914 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1915 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1916 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1917 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1919 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1920 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1921 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1922 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1923 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1924 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1925 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1926 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1928 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1929 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1930 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1931 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1934 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1935 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1936 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1937 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1940 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1941 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1943 /* Sienna_Cichlid */
1944 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1945 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1946 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1947 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1948 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1949 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1950 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1951 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1952 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1953 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1954 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1955 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1956 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1959 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1960 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1963 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1964 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1965 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1966 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1967 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1968 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1969 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1970 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1971 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1973 /* DIMGREY_CAVEFISH */
1974 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1975 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1976 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1977 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1978 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1979 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1980 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1981 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1982 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1983 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1984 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1985 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1988 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1989 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1990 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1991 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1993 /* CYAN_SKILLFISH */
1994 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1995 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1998 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1999 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2000 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2001 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2002 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2003 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2005 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2006 .class = PCI_CLASS_DISPLAY_VGA << 8,
2007 .class_mask = 0xffffff,
2008 .driver_data = CHIP_IP_DISCOVERY },
2010 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2011 .class = PCI_CLASS_DISPLAY_OTHER << 8,
2012 .class_mask = 0xffffff,
2013 .driver_data = CHIP_IP_DISCOVERY },
2018 MODULE_DEVICE_TABLE(pci, pciidlist);
2020 static const struct drm_driver amdgpu_kms_driver;
2022 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
2024 struct pci_dev *p = NULL;
2032 for (i = 1; i < 4; i++) {
2033 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
2034 adev->pdev->bus->number, i);
2036 pm_runtime_get_sync(&p->dev);
2037 pm_runtime_mark_last_busy(&p->dev);
2038 pm_runtime_put_autosuspend(&p->dev);
2044 static int amdgpu_pci_probe(struct pci_dev *pdev,
2045 const struct pci_device_id *ent)
2047 struct drm_device *ddev;
2048 struct amdgpu_device *adev;
2049 unsigned long flags = ent->driver_data;
2050 int ret, retry = 0, i;
2051 bool supports_atomic = false;
2053 /* skip devices which are owned by radeon */
2054 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2055 if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2059 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
2062 if (amdgpu_virtual_display ||
2063 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2064 supports_atomic = true;
2066 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
2067 DRM_INFO("This hardware requires experimental hardware support.\n"
2068 "See modparam exp_hw_support\n");
2071 /* differentiate between P10 and P11 asics with the same DID */
2072 if (pdev->device == 0x67FF &&
2073 (pdev->revision == 0xE3 ||
2074 pdev->revision == 0xE7 ||
2075 pdev->revision == 0xF3 ||
2076 pdev->revision == 0xF7)) {
2077 flags &= ~AMD_ASIC_MASK;
2078 flags |= CHIP_POLARIS10;
2081 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2082 * however, SME requires an indirect IOMMU mapping because the encryption
2083 * bit is beyond the DMA mask of the chip.
2085 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2086 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
2087 dev_info(&pdev->dev,
2088 "SME is not compatible with RAVEN\n");
2092 #ifdef CONFIG_DRM_AMDGPU_SI
2093 if (!amdgpu_si_support) {
2094 switch (flags & AMD_ASIC_MASK) {
2100 dev_info(&pdev->dev,
2101 "SI support provided by radeon.\n");
2102 dev_info(&pdev->dev,
2103 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2109 #ifdef CONFIG_DRM_AMDGPU_CIK
2110 if (!amdgpu_cik_support) {
2111 switch (flags & AMD_ASIC_MASK) {
2117 dev_info(&pdev->dev,
2118 "CIK support provided by radeon.\n");
2119 dev_info(&pdev->dev,
2120 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2127 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
2129 return PTR_ERR(adev);
2131 adev->dev = &pdev->dev;
2133 ddev = adev_to_drm(adev);
2135 if (!supports_atomic)
2136 ddev->driver_features &= ~DRIVER_ATOMIC;
2138 ret = pci_enable_device(pdev);
2142 pci_set_drvdata(pdev, ddev);
2144 ret = amdgpu_driver_load_kms(adev, flags);
2149 ret = drm_dev_register(ddev, flags);
2150 if (ret == -EAGAIN && ++retry <= 3) {
2151 DRM_INFO("retry init %d\n", retry);
2152 /* Don't request EX mode too frequently which is attacking */
2160 * 1. don't init fbdev on hw without DCE
2161 * 2. don't init fbdev if there are no connectors
2163 if (adev->mode_info.mode_config_initialized &&
2164 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2165 /* select 8 bpp console on low vram cards */
2166 if (adev->gmc.real_vram_size <= (32*1024*1024))
2167 drm_fbdev_generic_setup(adev_to_drm(adev), 8);
2169 drm_fbdev_generic_setup(adev_to_drm(adev), 32);
2172 ret = amdgpu_debugfs_init(adev);
2174 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2176 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2177 /* only need to skip on ATPX */
2178 if (amdgpu_device_supports_px(ddev))
2179 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2180 /* we want direct complete for BOCO */
2181 if (amdgpu_device_supports_boco(ddev))
2182 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2183 DPM_FLAG_SMART_SUSPEND |
2184 DPM_FLAG_MAY_SKIP_RESUME);
2185 pm_runtime_use_autosuspend(ddev->dev);
2186 pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2188 pm_runtime_allow(ddev->dev);
2190 pm_runtime_mark_last_busy(ddev->dev);
2191 pm_runtime_put_autosuspend(ddev->dev);
2194 * For runpm implemented via BACO, PMFW will handle the
2195 * timing for BACO in and out:
2196 * - put ASIC into BACO state only when both video and
2197 * audio functions are in D3 state.
2198 * - pull ASIC out of BACO state when either video or
2199 * audio function is in D0 state.
2200 * Also, at startup, PMFW assumes both functions are in
2203 * So if snd driver was loaded prior to amdgpu driver
2204 * and audio function was put into D3 state, there will
2205 * be no PMFW-aware D-state transition(D0->D3) on runpm
2206 * suspend. Thus the BACO will be not correctly kicked in.
2208 * Via amdgpu_get_secondary_funcs(), the audio dev is put
2209 * into D0 state. Then there will be a PMFW-aware D-state
2210 * transition(D0->D3) on runpm suspend.
2212 if (amdgpu_device_supports_baco(ddev) &&
2213 !(adev->flags & AMD_IS_APU) &&
2214 (adev->asic_type >= CHIP_NAVI10))
2215 amdgpu_get_secondary_funcs(adev);
2221 pci_disable_device(pdev);
2226 amdgpu_pci_remove(struct pci_dev *pdev)
2228 struct drm_device *dev = pci_get_drvdata(pdev);
2229 struct amdgpu_device *adev = drm_to_adev(dev);
2231 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2232 pm_runtime_get_sync(dev->dev);
2233 pm_runtime_forbid(dev->dev);
2236 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&
2237 !amdgpu_sriov_vf(adev)) {
2238 bool need_to_reset_gpu = false;
2240 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2241 struct amdgpu_hive_info *hive;
2243 hive = amdgpu_get_xgmi_hive(adev);
2244 if (hive->device_remove_count == 0)
2245 need_to_reset_gpu = true;
2246 hive->device_remove_count++;
2247 amdgpu_put_xgmi_hive(hive);
2249 need_to_reset_gpu = true;
2252 /* Workaround for ASICs need to reset SMU.
2253 * Called only when the first device is removed.
2255 if (need_to_reset_gpu) {
2256 struct amdgpu_reset_context reset_context;
2258 adev->shutdown = true;
2259 memset(&reset_context, 0, sizeof(reset_context));
2260 reset_context.method = AMD_RESET_METHOD_NONE;
2261 reset_context.reset_req_dev = adev;
2262 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2263 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags);
2264 amdgpu_device_gpu_recover(adev, NULL, &reset_context);
2268 amdgpu_driver_unload_kms(dev);
2270 drm_dev_unplug(dev);
2273 * Flush any in flight DMA operations from device.
2274 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2275 * StatusTransactions Pending bit.
2277 pci_disable_device(pdev);
2278 pci_wait_for_pending_transaction(pdev);
2282 amdgpu_pci_shutdown(struct pci_dev *pdev)
2284 struct drm_device *dev = pci_get_drvdata(pdev);
2285 struct amdgpu_device *adev = drm_to_adev(dev);
2287 if (amdgpu_ras_intr_triggered())
2290 /* if we are running in a VM, make sure the device
2291 * torn down properly on reboot/shutdown.
2292 * unfortunately we can't detect certain
2293 * hypervisors so just do this all the time.
2295 if (!amdgpu_passthrough(adev))
2296 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2297 amdgpu_device_ip_suspend(adev);
2298 adev->mp1_state = PP_MP1_STATE_NONE;
2302 * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2304 * @work: work_struct.
2306 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2308 struct list_head device_list;
2309 struct amdgpu_device *adev;
2311 struct amdgpu_reset_context reset_context;
2313 memset(&reset_context, 0, sizeof(reset_context));
2315 mutex_lock(&mgpu_info.mutex);
2316 if (mgpu_info.pending_reset == true) {
2317 mutex_unlock(&mgpu_info.mutex);
2320 mgpu_info.pending_reset = true;
2321 mutex_unlock(&mgpu_info.mutex);
2323 /* Use a common context, just need to make sure full reset is done */
2324 reset_context.method = AMD_RESET_METHOD_NONE;
2325 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2327 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2328 adev = mgpu_info.gpu_ins[i].adev;
2329 reset_context.reset_req_dev = adev;
2330 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
2332 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2333 r, adev_to_drm(adev)->unique);
2335 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2338 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2339 adev = mgpu_info.gpu_ins[i].adev;
2340 flush_work(&adev->xgmi_reset_work);
2341 adev->gmc.xgmi.pending_reset = false;
2344 /* reset function will rebuild the xgmi hive info , clear it now */
2345 for (i = 0; i < mgpu_info.num_dgpu; i++)
2346 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2348 INIT_LIST_HEAD(&device_list);
2350 for (i = 0; i < mgpu_info.num_dgpu; i++)
2351 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2353 /* unregister the GPU first, reset function will add them back */
2354 list_for_each_entry(adev, &device_list, reset_list)
2355 amdgpu_unregister_gpu_instance(adev);
2357 /* Use a common context, just need to make sure full reset is done */
2358 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2359 r = amdgpu_do_asic_reset(&device_list, &reset_context);
2362 DRM_ERROR("reinit gpus failure");
2365 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2366 adev = mgpu_info.gpu_ins[i].adev;
2367 if (!adev->kfd.init_complete)
2368 amdgpu_amdkfd_device_init(adev);
2369 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2374 static int amdgpu_pmops_prepare(struct device *dev)
2376 struct drm_device *drm_dev = dev_get_drvdata(dev);
2377 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2379 /* Return a positive number here so
2380 * DPM_FLAG_SMART_SUSPEND works properly
2382 if (amdgpu_device_supports_boco(drm_dev))
2383 return pm_runtime_suspended(dev);
2385 /* if we will not support s3 or s2i for the device
2388 if (!amdgpu_acpi_is_s0ix_active(adev) &&
2389 !amdgpu_acpi_is_s3_active(adev))
2395 static void amdgpu_pmops_complete(struct device *dev)
2400 static int amdgpu_pmops_suspend(struct device *dev)
2402 struct drm_device *drm_dev = dev_get_drvdata(dev);
2403 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2405 if (amdgpu_acpi_is_s0ix_active(adev))
2406 adev->in_s0ix = true;
2409 return amdgpu_device_suspend(drm_dev, true);
2412 static int amdgpu_pmops_suspend_noirq(struct device *dev)
2414 struct drm_device *drm_dev = dev_get_drvdata(dev);
2415 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2417 if (amdgpu_acpi_should_gpu_reset(adev))
2418 return amdgpu_asic_reset(adev);
2423 static int amdgpu_pmops_resume(struct device *dev)
2425 struct drm_device *drm_dev = dev_get_drvdata(dev);
2426 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2429 /* Avoids registers access if device is physically gone */
2430 if (!pci_device_is_present(adev->pdev))
2431 adev->no_hw_access = true;
2433 r = amdgpu_device_resume(drm_dev, true);
2434 if (amdgpu_acpi_is_s0ix_active(adev))
2435 adev->in_s0ix = false;
2437 adev->in_s3 = false;
2441 static int amdgpu_pmops_freeze(struct device *dev)
2443 struct drm_device *drm_dev = dev_get_drvdata(dev);
2444 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2448 r = amdgpu_device_suspend(drm_dev, true);
2449 adev->in_s4 = false;
2452 return amdgpu_asic_reset(adev);
2455 static int amdgpu_pmops_thaw(struct device *dev)
2457 struct drm_device *drm_dev = dev_get_drvdata(dev);
2459 return amdgpu_device_resume(drm_dev, true);
2462 static int amdgpu_pmops_poweroff(struct device *dev)
2464 struct drm_device *drm_dev = dev_get_drvdata(dev);
2466 return amdgpu_device_suspend(drm_dev, true);
2469 static int amdgpu_pmops_restore(struct device *dev)
2471 struct drm_device *drm_dev = dev_get_drvdata(dev);
2473 return amdgpu_device_resume(drm_dev, true);
2476 static int amdgpu_runtime_idle_check_display(struct device *dev)
2478 struct pci_dev *pdev = to_pci_dev(dev);
2479 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2480 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2482 if (adev->mode_info.num_crtc) {
2483 struct drm_connector *list_connector;
2484 struct drm_connector_list_iter iter;
2487 /* XXX: Return busy if any displays are connected to avoid
2488 * possible display wakeups after runtime resume due to
2489 * hotplug events in case any displays were connected while
2490 * the GPU was in suspend. Remove this once that is fixed.
2492 mutex_lock(&drm_dev->mode_config.mutex);
2493 drm_connector_list_iter_begin(drm_dev, &iter);
2494 drm_for_each_connector_iter(list_connector, &iter) {
2495 if (list_connector->status == connector_status_connected) {
2500 drm_connector_list_iter_end(&iter);
2501 mutex_unlock(&drm_dev->mode_config.mutex);
2506 if (adev->dc_enabled) {
2507 struct drm_crtc *crtc;
2509 drm_for_each_crtc(crtc, drm_dev) {
2510 drm_modeset_lock(&crtc->mutex, NULL);
2511 if (crtc->state->active)
2513 drm_modeset_unlock(&crtc->mutex);
2518 mutex_lock(&drm_dev->mode_config.mutex);
2519 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2521 drm_connector_list_iter_begin(drm_dev, &iter);
2522 drm_for_each_connector_iter(list_connector, &iter) {
2523 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2529 drm_connector_list_iter_end(&iter);
2531 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2532 mutex_unlock(&drm_dev->mode_config.mutex);
2541 static int amdgpu_pmops_runtime_suspend(struct device *dev)
2543 struct pci_dev *pdev = to_pci_dev(dev);
2544 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2545 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2548 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2549 pm_runtime_forbid(dev);
2553 ret = amdgpu_runtime_idle_check_display(dev);
2557 /* wait for all rings to drain before suspending */
2558 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2559 struct amdgpu_ring *ring = adev->rings[i];
2560 if (ring && ring->sched.ready) {
2561 ret = amdgpu_fence_wait_empty(ring);
2567 adev->in_runpm = true;
2568 if (amdgpu_device_supports_px(drm_dev))
2569 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2572 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2573 * proper cleanups and put itself into a state ready for PNP. That
2574 * can address some random resuming failure observed on BOCO capable
2576 * TODO: this may be also needed for PX capable platform.
2578 if (amdgpu_device_supports_boco(drm_dev))
2579 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2581 ret = amdgpu_device_suspend(drm_dev, false);
2583 adev->in_runpm = false;
2584 if (amdgpu_device_supports_boco(drm_dev))
2585 adev->mp1_state = PP_MP1_STATE_NONE;
2589 if (amdgpu_device_supports_boco(drm_dev))
2590 adev->mp1_state = PP_MP1_STATE_NONE;
2592 if (amdgpu_device_supports_px(drm_dev)) {
2593 /* Only need to handle PCI state in the driver for ATPX
2594 * PCI core handles it for _PR3.
2596 amdgpu_device_cache_pci_state(pdev);
2597 pci_disable_device(pdev);
2598 pci_ignore_hotplug(pdev);
2599 pci_set_power_state(pdev, PCI_D3cold);
2600 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
2601 } else if (amdgpu_device_supports_boco(drm_dev)) {
2603 } else if (amdgpu_device_supports_baco(drm_dev)) {
2604 amdgpu_device_baco_enter(drm_dev);
2607 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n");
2612 static int amdgpu_pmops_runtime_resume(struct device *dev)
2614 struct pci_dev *pdev = to_pci_dev(dev);
2615 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2616 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2619 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
2622 /* Avoids registers access if device is physically gone */
2623 if (!pci_device_is_present(adev->pdev))
2624 adev->no_hw_access = true;
2626 if (amdgpu_device_supports_px(drm_dev)) {
2627 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2629 /* Only need to handle PCI state in the driver for ATPX
2630 * PCI core handles it for _PR3.
2632 pci_set_power_state(pdev, PCI_D0);
2633 amdgpu_device_load_pci_state(pdev);
2634 ret = pci_enable_device(pdev);
2637 pci_set_master(pdev);
2638 } else if (amdgpu_device_supports_boco(drm_dev)) {
2639 /* Only need to handle PCI state in the driver for ATPX
2640 * PCI core handles it for _PR3.
2642 pci_set_master(pdev);
2643 } else if (amdgpu_device_supports_baco(drm_dev)) {
2644 amdgpu_device_baco_exit(drm_dev);
2646 ret = amdgpu_device_resume(drm_dev, false);
2648 if (amdgpu_device_supports_px(drm_dev))
2649 pci_disable_device(pdev);
2653 if (amdgpu_device_supports_px(drm_dev))
2654 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
2655 adev->in_runpm = false;
2659 static int amdgpu_pmops_runtime_idle(struct device *dev)
2661 struct drm_device *drm_dev = dev_get_drvdata(dev);
2662 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2663 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
2666 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2667 pm_runtime_forbid(dev);
2671 ret = amdgpu_runtime_idle_check_display(dev);
2673 pm_runtime_mark_last_busy(dev);
2674 pm_runtime_autosuspend(dev);
2678 long amdgpu_drm_ioctl(struct file *filp,
2679 unsigned int cmd, unsigned long arg)
2681 struct drm_file *file_priv = filp->private_data;
2682 struct drm_device *dev;
2684 dev = file_priv->minor->dev;
2685 ret = pm_runtime_get_sync(dev->dev);
2689 ret = drm_ioctl(filp, cmd, arg);
2691 pm_runtime_mark_last_busy(dev->dev);
2693 pm_runtime_put_autosuspend(dev->dev);
2697 static const struct dev_pm_ops amdgpu_pm_ops = {
2698 .prepare = amdgpu_pmops_prepare,
2699 .complete = amdgpu_pmops_complete,
2700 .suspend = amdgpu_pmops_suspend,
2701 .suspend_noirq = amdgpu_pmops_suspend_noirq,
2702 .resume = amdgpu_pmops_resume,
2703 .freeze = amdgpu_pmops_freeze,
2704 .thaw = amdgpu_pmops_thaw,
2705 .poweroff = amdgpu_pmops_poweroff,
2706 .restore = amdgpu_pmops_restore,
2707 .runtime_suspend = amdgpu_pmops_runtime_suspend,
2708 .runtime_resume = amdgpu_pmops_runtime_resume,
2709 .runtime_idle = amdgpu_pmops_runtime_idle,
2712 static int amdgpu_flush(struct file *f, fl_owner_t id)
2714 struct drm_file *file_priv = f->private_data;
2715 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
2716 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
2718 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2719 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
2721 return timeout >= 0 ? 0 : timeout;
2724 static const struct file_operations amdgpu_driver_kms_fops = {
2725 .owner = THIS_MODULE,
2727 .flush = amdgpu_flush,
2728 .release = drm_release,
2729 .unlocked_ioctl = amdgpu_drm_ioctl,
2730 .mmap = drm_gem_mmap,
2733 #ifdef CONFIG_COMPAT
2734 .compat_ioctl = amdgpu_kms_compat_ioctl,
2736 #ifdef CONFIG_PROC_FS
2737 .show_fdinfo = amdgpu_show_fdinfo
2741 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2743 struct drm_file *file;
2748 if (filp->f_op != &amdgpu_driver_kms_fops) {
2752 file = filp->private_data;
2753 *fpriv = file->driver_priv;
2757 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2758 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2759 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2760 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2761 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2762 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2763 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2765 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2766 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2767 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2768 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2769 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2770 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2771 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2772 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2773 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2774 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2777 static const struct drm_driver amdgpu_kms_driver = {
2781 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2782 DRIVER_SYNCOBJ_TIMELINE,
2783 .open = amdgpu_driver_open_kms,
2784 .postclose = amdgpu_driver_postclose_kms,
2785 .lastclose = amdgpu_driver_lastclose_kms,
2786 .ioctls = amdgpu_ioctls_kms,
2787 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
2788 .dumb_create = amdgpu_mode_dumb_create,
2789 .dumb_map_offset = amdgpu_mode_dumb_mmap,
2790 .fops = &amdgpu_driver_kms_fops,
2791 .release = &amdgpu_driver_release_kms,
2793 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2794 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2795 .gem_prime_import = amdgpu_gem_prime_import,
2796 .gem_prime_mmap = drm_gem_prime_mmap,
2798 .name = DRIVER_NAME,
2799 .desc = DRIVER_DESC,
2800 .date = DRIVER_DATE,
2801 .major = KMS_DRIVER_MAJOR,
2802 .minor = KMS_DRIVER_MINOR,
2803 .patchlevel = KMS_DRIVER_PATCHLEVEL,
2806 static struct pci_error_handlers amdgpu_pci_err_handler = {
2807 .error_detected = amdgpu_pci_error_detected,
2808 .mmio_enabled = amdgpu_pci_mmio_enabled,
2809 .slot_reset = amdgpu_pci_slot_reset,
2810 .resume = amdgpu_pci_resume,
2813 extern const struct attribute_group amdgpu_vram_mgr_attr_group;
2814 extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
2815 extern const struct attribute_group amdgpu_vbios_version_attr_group;
2817 static const struct attribute_group *amdgpu_sysfs_groups[] = {
2818 &amdgpu_vram_mgr_attr_group,
2819 &amdgpu_gtt_mgr_attr_group,
2820 &amdgpu_vbios_version_attr_group,
2825 static struct pci_driver amdgpu_kms_pci_driver = {
2826 .name = DRIVER_NAME,
2827 .id_table = pciidlist,
2828 .probe = amdgpu_pci_probe,
2829 .remove = amdgpu_pci_remove,
2830 .shutdown = amdgpu_pci_shutdown,
2831 .driver.pm = &amdgpu_pm_ops,
2832 .err_handler = &amdgpu_pci_err_handler,
2833 .dev_groups = amdgpu_sysfs_groups,
2836 static int __init amdgpu_init(void)
2840 if (drm_firmware_drivers_only())
2843 r = amdgpu_sync_init();
2847 r = amdgpu_fence_slab_init();
2851 DRM_INFO("amdgpu kernel modesetting enabled.\n");
2852 amdgpu_register_atpx_handler();
2853 amdgpu_acpi_detect();
2855 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
2856 amdgpu_amdkfd_init();
2858 /* let modprobe override vga console setting */
2859 return pci_register_driver(&amdgpu_kms_pci_driver);
2868 static void __exit amdgpu_exit(void)
2870 amdgpu_amdkfd_fini();
2871 pci_unregister_driver(&amdgpu_kms_pci_driver);
2872 amdgpu_unregister_atpx_handler();
2874 amdgpu_fence_slab_fini();
2875 mmu_notifier_synchronize();
2878 module_init(amdgpu_init);
2879 module_exit(amdgpu_exit);
2881 MODULE_AUTHOR(DRIVER_AUTHOR);
2882 MODULE_DESCRIPTION(DRIVER_DESC);
2883 MODULE_LICENSE("GPL and additional rights");
projects / linux.git / blob