drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_ras.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_xgmi.h"
  35 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  36
  37 static const char *RAS_FS_NAME = "ras";
  38
  39 const char *ras_error_string[] = {
  40         "none",
  41         "parity",
  42         "single_correctable",
  43         "multi_uncorrectable",
  44         "poison",
  45 };
  46
  47 const char *ras_block_string[] = {
  48         "umc",
  49         "sdma",
  50         "gfx",
  51         "mmhub",
  52         "athub",
  53         "pcie_bif",
  54         "hdp",
  55         "xgmi_wafl",
  56         "df",
  57         "smn",
  58         "sem",
  59         "mp0",
  60         "mp1",
  61         "fuse",
  62 };
  63
  64 #define ras_err_str(i) (ras_error_string[ffs(i)])
  65 #define ras_block_str(i) (ras_block_string[i])
  66
  67 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
  68
  69 /* inject address is 52 bits */
  70 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
  71
  72 /* typical ECC bad page rate(1 bad page per 100MB VRAM) */
  73 #define RAS_BAD_PAGE_RATE               (100 * 1024 * 1024ULL)
  74
  75 enum amdgpu_ras_retire_page_reservation {
  76         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
  77         AMDGPU_RAS_RETIRE_PAGE_PENDING,
  78         AMDGPU_RAS_RETIRE_PAGE_FAULT,
  79 };
  80
  81 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
  82
  83 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
  84                                 uint64_t addr);
  85 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
  86                                 uint64_t addr);
  87
  88 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
  89 {
  90         if (adev && amdgpu_ras_get_context(adev))
  91                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
  92 }
  93
  94 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
  95 {
  96         if (adev && amdgpu_ras_get_context(adev))
  97                 return amdgpu_ras_get_context(adev)->error_query_ready;
  98
  99         return false;
 100 }
 101
 102 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 103                                         size_t size, loff_t *pos)
 104 {
 105         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 106         struct ras_query_if info = {
 107                 .head = obj->head,
 108         };
 109         ssize_t s;
 110         char val[128];
 111
 112         if (amdgpu_ras_query_error_status(obj->adev, &info))
 113                 return -EINVAL;
 114
 115         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 116                         "ue", info.ue_count,
 117                         "ce", info.ce_count);
 118         if (*pos >= s)
 119                 return 0;
 120
 121         s -= *pos;
 122         s = min_t(u64, s, size);
 123
 124
 125         if (copy_to_user(buf, &val[*pos], s))
 126                 return -EINVAL;
 127
 128         *pos += s;
 129
 130         return s;
 131 }
 132
 133 static const struct file_operations amdgpu_ras_debugfs_ops = {
 134         .owner = THIS_MODULE,
 135         .read = amdgpu_ras_debugfs_read,
 136         .write = NULL,
 137         .llseek = default_llseek
 138 };
 139
 140 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 141 {
 142         int i;
 143
 144         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 145                 *block_id = i;
 146                 if (strcmp(name, ras_block_str(i)) == 0)
 147                         return 0;
 148         }
 149         return -EINVAL;
 150 }
 151
 152 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 153                 const char __user *buf, size_t size,
 154                 loff_t *pos, struct ras_debug_if *data)
 155 {
 156         ssize_t s = min_t(u64, 64, size);
 157         char str[65];
 158         char block_name[33];
 159         char err[9] = "ue";
 160         int op = -1;
 161         int block_id;
 162         uint32_t sub_block;
 163         u64 address, value;
 164
 165         if (*pos)
 166                 return -EINVAL;
 167         *pos = size;
 168
 169         memset(str, 0, sizeof(str));
 170         memset(data, 0, sizeof(*data));
 171
 172         if (copy_from_user(str, buf, s))
 173                 return -EINVAL;
 174
 175         if (sscanf(str, "disable %32s", block_name) == 1)
 176                 op = 0;
 177         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 178                 op = 1;
 179         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 180                 op = 2;
 181         else if (str[0] && str[1] && str[2] && str[3])
 182                 /* ascii string, but commands are not matched. */
 183                 return -EINVAL;
 184
 185         if (op != -1) {
 186                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 187                         return -EINVAL;
 188
 189                 data->head.block = block_id;
 190                 /* only ue and ce errors are supported */
 191                 if (!memcmp("ue", err, 2))
 192                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 193                 else if (!memcmp("ce", err, 2))
 194                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 195                 else
 196                         return -EINVAL;
 197
 198                 data->op = op;
 199
 200                 if (op == 2) {
 201                         if (sscanf(str, "%*s %*s %*s %u %llu %llu",
 202                                                 &sub_block, &address, &value) != 3)
 203                                 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 204                                                         &sub_block, &address, &value) != 3)
 205                                         return -EINVAL;
 206                         data->head.sub_block_index = sub_block;
 207                         data->inject.address = address;
 208                         data->inject.value = value;
 209                 }
 210         } else {
 211                 if (size < sizeof(*data))
 212                         return -EINVAL;
 213
 214                 if (copy_from_user(data, buf, sizeof(*data)))
 215                         return -EINVAL;
 216         }
 217
 218         return 0;
 219 }
 220
 221 /**
 222  * DOC: AMDGPU RAS debugfs control interface
 223  *
 224  * It accepts struct ras_debug_if who has two members.
 225  *
 226  * First member: ras_debug_if::head or ras_debug_if::inject.
 227  *
 228  * head is used to indicate which IP block will be under control.
 229  *
 230  * head has four members, they are block, type, sub_block_index, name.
 231  * block: which IP will be under control.
 232  * type: what kind of error will be enabled/disabled/injected.
 233  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 234  * name: the name of IP.
 235  *
 236  * inject has two more members than head, they are address, value.
 237  * As their names indicate, inject operation will write the
 238  * value to the address.
 239  *
 240  * The second member: struct ras_debug_if::op.
 241  * It has three kinds of operations.
 242  *
 243  * - 0: disable RAS on the block. Take ::head as its data.
 244  * - 1: enable RAS on the block. Take ::head as its data.
 245  * - 2: inject errors on the block. Take ::inject as its data.
 246  *
 247  * How to use the interface?
 248  *
 249  * Programs
 250  *
 251  * Copy the struct ras_debug_if in your codes and initialize it.
 252  * Write the struct to the control node.
 253  *
 254  * Shells
 255  *
 256  * .. code-block:: bash
 257  *
 258  *      echo op block [error [sub_block address value]] > .../ras/ras_ctrl
 259  *
 260  * Parameters:
 261  *
 262  * op: disable, enable, inject
 263  *      disable: only block is needed
 264  *      enable: block and error are needed
 265  *      inject: error, address, value are needed
 266  * block: umc, sdma, gfx, .........
 267  *      see ras_block_string[] for details
 268  * error: ue, ce
 269  *      ue: multi_uncorrectable
 270  *      ce: single_correctable
 271  * sub_block:
 272  *      sub block index, pass 0 if there is no sub block
 273  *
 274  * here are some examples for bash commands:
 275  *
 276  * .. code-block:: bash
 277  *
 278  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 279  *      echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 280  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 281  *
 282  * How to check the result?
 283  *
 284  * For disable/enable, please check ras features at
 285  * /sys/class/drm/card[0/1/2...]/device/ras/features
 286  *
 287  * For inject, please check corresponding err count at
 288  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 289  *
 290  * .. note::
 291  *      Operations are only allowed on blocks which are supported.
 292  *      Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
 293  *      to see which blocks support RAS on a particular asic.
 294  *
 295  */
 296 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
 297                 size_t size, loff_t *pos)
 298 {
 299         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 300         struct ras_debug_if data;
 301         int ret = 0;
 302
 303         if (!amdgpu_ras_get_error_query_ready(adev)) {
 304                 dev_warn(adev->dev, "RAS WARN: error injection "
 305                                 "currently inaccessible\n");
 306                 return size;
 307         }
 308
 309         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 310         if (ret)
 311                 return -EINVAL;
 312
 313         if (!amdgpu_ras_is_supported(adev, data.head.block))
 314                 return -EINVAL;
 315
 316         switch (data.op) {
 317         case 0:
 318                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 319                 break;
 320         case 1:
 321                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 322                 break;
 323         case 2:
 324                 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
 325                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 326                         dev_warn(adev->dev, "RAS WARN: input address "
 327                                         "0x%llx is invalid.",
 328                                         data.inject.address);
 329                         ret = -EINVAL;
 330                         break;
 331                 }
 332
 333                 /* umc ce/ue error injection for a bad page is not allowed */
 334                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 335                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 336                         dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked "
 337                                         "as bad before error injection!\n",
 338                                         data.inject.address);
 339                         break;
 340                 }
 341
 342                 /* data.inject.address is offset instead of absolute gpu address */
 343                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 344                 break;
 345         default:
 346                 ret = -EINVAL;
 347                 break;
 348         }
 349
 350         if (ret)
 351                 return -EINVAL;
 352
 353         return size;
 354 }
 355
 356 /**
 357  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 358  *
 359  * Some boards contain an EEPROM which is used to persistently store a list of
 360  * bad pages which experiences ECC errors in vram.  This interface provides
 361  * a way to reset the EEPROM, e.g., after testing error injection.
 362  *
 363  * Usage:
 364  *
 365  * .. code-block:: bash
 366  *
 367  *      echo 1 > ../ras/ras_eeprom_reset
 368  *
 369  * will reset EEPROM table to 0 entries.
 370  *
 371  */
 372 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf,
 373                 size_t size, loff_t *pos)
 374 {
 375         struct amdgpu_device *adev =
 376                 (struct amdgpu_device *)file_inode(f)->i_private;
 377         int ret;
 378
 379         ret = amdgpu_ras_eeprom_reset_table(
 380                         &(amdgpu_ras_get_context(adev)->eeprom_control));
 381
 382         if (ret == 1) {
 383                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 384                 return size;
 385         } else {
 386                 return -EIO;
 387         }
 388 }
 389
 390 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 391         .owner = THIS_MODULE,
 392         .read = NULL,
 393         .write = amdgpu_ras_debugfs_ctrl_write,
 394         .llseek = default_llseek
 395 };
 396
 397 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 398         .owner = THIS_MODULE,
 399         .read = NULL,
 400         .write = amdgpu_ras_debugfs_eeprom_write,
 401         .llseek = default_llseek
 402 };
 403
 404 /**
 405  * DOC: AMDGPU RAS sysfs Error Count Interface
 406  *
 407  * It allows the user to read the error count for each IP block on the gpu through
 408  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 409  *
 410  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 411  * (ce) error counts.
 412  *
 413  * The format of one line is below,
 414  *
 415  * [ce|ue]: count
 416  *
 417  * Example:
 418  *
 419  * .. code-block:: bash
 420  *
 421  *      ue: 0
 422  *      ce: 1
 423  *
 424  */
 425 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 426                 struct device_attribute *attr, char *buf)
 427 {
 428         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 429         struct ras_query_if info = {
 430                 .head = obj->head,
 431         };
 432
 433         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 434                 return snprintf(buf, PAGE_SIZE,
 435                                 "Query currently inaccessible\n");
 436
 437         if (amdgpu_ras_query_error_status(obj->adev, &info))
 438                 return -EINVAL;
 439
 440         return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n",
 441                         "ue", info.ue_count,
 442                         "ce", info.ce_count);
 443 }
 444
 445 /* obj begin */
 446
 447 #define get_obj(obj) do { (obj)->use++; } while (0)
 448 #define alive_obj(obj) ((obj)->use)
 449
 450 static inline void put_obj(struct ras_manager *obj)
 451 {
 452         if (obj && --obj->use == 0)
 453                 list_del(&obj->node);
 454         if (obj && obj->use < 0) {
 455                  DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
 456         }
 457 }
 458
 459 /* make one obj and return it. */
 460 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 461                 struct ras_common_if *head)
 462 {
 463         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 464         struct ras_manager *obj;
 465
 466         if (!con)
 467                 return NULL;
 468
 469         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 470                 return NULL;
 471
 472         obj = &con->objs[head->block];
 473         /* already exist. return obj? */
 474         if (alive_obj(obj))
 475                 return NULL;
 476
 477         obj->head = *head;
 478         obj->adev = adev;
 479         list_add(&obj->node, &con->head);
 480         get_obj(obj);
 481
 482         return obj;
 483 }
 484
 485 /* return an obj equal to head, or the first when head is NULL */
 486 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 487                 struct ras_common_if *head)
 488 {
 489         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 490         struct ras_manager *obj;
 491         int i;
 492
 493         if (!con)
 494                 return NULL;
 495
 496         if (head) {
 497                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 498                         return NULL;
 499
 500                 obj = &con->objs[head->block];
 501
 502                 if (alive_obj(obj)) {
 503                         WARN_ON(head->block != obj->head.block);
 504                         return obj;
 505                 }
 506         } else {
 507                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 508                         obj = &con->objs[i];
 509                         if (alive_obj(obj)) {
 510                                 WARN_ON(i != obj->head.block);
 511                                 return obj;
 512                         }
 513                 }
 514         }
 515
 516         return NULL;
 517 }
 518 /* obj end */
 519
 520 static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,
 521                                          const char* invoke_type,
 522                                          const char* block_name,
 523                                          enum ta_ras_status ret)
 524 {
 525         switch (ret) {
 526         case TA_RAS_STATUS__SUCCESS:
 527                 return;
 528         case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
 529                 dev_warn(adev->dev,
 530                         "RAS WARN: %s %s currently unavailable\n",
 531                         invoke_type,
 532                         block_name);
 533                 break;
 534         default:
 535                 dev_err(adev->dev,
 536                         "RAS ERROR: %s %s error failed ret 0x%X\n",
 537                         invoke_type,
 538                         block_name,
 539                         ret);
 540         }
 541 }
 542
 543 /* feature ctl begin */
 544 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 545                 struct ras_common_if *head)
 546 {
 547         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 548
 549         return con->hw_supported & BIT(head->block);
 550 }
 551
 552 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 553                 struct ras_common_if *head)
 554 {
 555         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 556
 557         return con->features & BIT(head->block);
 558 }
 559
 560 /*
 561  * if obj is not created, then create one.
 562  * set feature enable flag.
 563  */
 564 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 565                 struct ras_common_if *head, int enable)
 566 {
 567         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 568         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 569
 570         /* If hardware does not support ras, then do not create obj.
 571          * But if hardware support ras, we can create the obj.
 572          * Ras framework checks con->hw_supported to see if it need do
 573          * corresponding initialization.
 574          * IP checks con->support to see if it need disable ras.
 575          */
 576         if (!amdgpu_ras_is_feature_allowed(adev, head))
 577                 return 0;
 578         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
 579                 return 0;
 580
 581         if (enable) {
 582                 if (!obj) {
 583                         obj = amdgpu_ras_create_obj(adev, head);
 584                         if (!obj)
 585                                 return -EINVAL;
 586                 } else {
 587                         /* In case we create obj somewhere else */
 588                         get_obj(obj);
 589                 }
 590                 con->features |= BIT(head->block);
 591         } else {
 592                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 593                         con->features &= ~BIT(head->block);
 594                         put_obj(obj);
 595                 }
 596         }
 597
 598         return 0;
 599 }
 600
 601 /* wrapper of psp_ras_enable_features */
 602 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 603                 struct ras_common_if *head, bool enable)
 604 {
 605         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 606         union ta_ras_cmd_input *info;
 607         int ret;
 608
 609         if (!con)
 610                 return -EINVAL;
 611
 612         info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 613         if (!info)
 614                 return -ENOMEM;
 615
 616         if (!enable) {
 617                 info->disable_features = (struct ta_ras_disable_features_input) {
 618                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 619                         .error_type = amdgpu_ras_error_to_ta(head->type),
 620                 };
 621         } else {
 622                 info->enable_features = (struct ta_ras_enable_features_input) {
 623                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 624                         .error_type = amdgpu_ras_error_to_ta(head->type),
 625                 };
 626         }
 627
 628         /* Do not enable if it is not allowed. */
 629         WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
 630         /* Are we alerady in that state we are going to set? */
 631         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) {
 632                 ret = 0;
 633                 goto out;
 634         }
 635
 636         if (!amdgpu_ras_intr_triggered()) {
 637                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 638                 if (ret) {
 639                         amdgpu_ras_parse_status_code(adev,
 640                                                      enable ? "enable":"disable",
 641                                                      ras_block_str(head->block),
 642                                                     (enum ta_ras_status)ret);
 643                         if (ret == TA_RAS_STATUS__RESET_NEEDED)
 644                                 ret = -EAGAIN;
 645                         else
 646                                 ret = -EINVAL;
 647
 648                         goto out;
 649                 }
 650         }
 651
 652         /* setup the obj */
 653         __amdgpu_ras_feature_enable(adev, head, enable);
 654         ret = 0;
 655 out:
 656         kfree(info);
 657         return ret;
 658 }
 659
 660 /* Only used in device probe stage and called only once. */
 661 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 662                 struct ras_common_if *head, bool enable)
 663 {
 664         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 665         int ret;
 666
 667         if (!con)
 668                 return -EINVAL;
 669
 670         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 671                 if (enable) {
 672                         /* There is no harm to issue a ras TA cmd regardless of
 673                          * the currecnt ras state.
 674                          * If current state == target state, it will do nothing
 675                          * But sometimes it requests driver to reset and repost
 676                          * with error code -EAGAIN.
 677                          */
 678                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 679                         /* With old ras TA, we might fail to enable ras.
 680                          * Log it and just setup the object.
 681                          * TODO need remove this WA in the future.
 682                          */
 683                         if (ret == -EINVAL) {
 684                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 685                                 if (!ret)
 686                                         dev_info(adev->dev,
 687                                                 "RAS INFO: %s setup object\n",
 688                                                 ras_block_str(head->block));
 689                         }
 690                 } else {
 691                         /* setup the object then issue a ras TA disable cmd.*/
 692                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 693                         if (ret)
 694                                 return ret;
 695
 696                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 697                 }
 698         } else
 699                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 700
 701         return ret;
 702 }
 703
 704 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 705                 bool bypass)
 706 {
 707         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 708         struct ras_manager *obj, *tmp;
 709
 710         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 711                 /* bypass psp.
 712                  * aka just release the obj and corresponding flags
 713                  */
 714                 if (bypass) {
 715                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 716                                 break;
 717                 } else {
 718                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 719                                 break;
 720                 }
 721         }
 722
 723         return con->features;
 724 }
 725
 726 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 727                 bool bypass)
 728 {
 729         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 730         int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
 731         int i;
 732         const enum amdgpu_ras_error_type default_ras_type =
 733                 AMDGPU_RAS_ERROR__NONE;
 734
 735         for (i = 0; i < ras_block_count; i++) {
 736                 struct ras_common_if head = {
 737                         .block = i,
 738                         .type = default_ras_type,
 739                         .sub_block_index = 0,
 740                 };
 741                 strcpy(head.name, ras_block_str(i));
 742                 if (bypass) {
 743                         /*
 744                          * bypass psp. vbios enable ras for us.
 745                          * so just create the obj
 746                          */
 747                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 748                                 break;
 749                 } else {
 750                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 751                                 break;
 752                 }
 753         }
 754
 755         return con->features;
 756 }
 757 /* feature ctl end */
 758
 759 /* query/inject/cure begin */
 760 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 761         struct ras_query_if *info)
 762 {
 763         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 764         struct ras_err_data err_data = {0, 0, 0, NULL};
 765         int i;
 766
 767         if (!obj)
 768                 return -EINVAL;
 769
 770         switch (info->head.block) {
 771         case AMDGPU_RAS_BLOCK__UMC:
 772                 if (adev->umc.funcs->query_ras_error_count)
 773                         adev->umc.funcs->query_ras_error_count(adev, &err_data);
 774                 /* umc query_ras_error_address is also responsible for clearing
 775                  * error status
 776                  */
 777                 if (adev->umc.funcs->query_ras_error_address)
 778                         adev->umc.funcs->query_ras_error_address(adev, &err_data);
 779                 break;
 780         case AMDGPU_RAS_BLOCK__SDMA:
 781                 if (adev->sdma.funcs->query_ras_error_count) {
 782                         for (i = 0; i < adev->sdma.num_instances; i++)
 783                                 adev->sdma.funcs->query_ras_error_count(adev, i,
 784                                                                         &err_data);
 785                 }
 786                 break;
 787         case AMDGPU_RAS_BLOCK__GFX:
 788                 if (adev->gfx.funcs->query_ras_error_count)
 789                         adev->gfx.funcs->query_ras_error_count(adev, &err_data);
 790
 791                 if (adev->gfx.funcs->query_ras_error_status)
 792                         adev->gfx.funcs->query_ras_error_status(adev);
 793                 break;
 794         case AMDGPU_RAS_BLOCK__MMHUB:
 795                 if (adev->mmhub.funcs->query_ras_error_count)
 796                         adev->mmhub.funcs->query_ras_error_count(adev, &err_data);
 797
 798                 if (adev->mmhub.funcs->query_ras_error_status)
 799                         adev->mmhub.funcs->query_ras_error_status(adev);
 800                 break;
 801         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 802                 if (adev->nbio.funcs->query_ras_error_count)
 803                         adev->nbio.funcs->query_ras_error_count(adev, &err_data);
 804                 break;
 805         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 806                 amdgpu_xgmi_query_ras_error_count(adev, &err_data);
 807                 break;
 808         default:
 809                 break;
 810         }
 811
 812         obj->err_data.ue_count += err_data.ue_count;
 813         obj->err_data.ce_count += err_data.ce_count;
 814
 815         info->ue_count = obj->err_data.ue_count;
 816         info->ce_count = obj->err_data.ce_count;
 817
 818         if (err_data.ce_count) {
 819                 dev_info(adev->dev, "%ld correctable hardware errors "
 820                                         "detected in %s block, no user "
 821                                         "action is needed.\n",
 822                                         obj->err_data.ce_count,
 823                                         ras_block_str(info->head.block));
 824         }
 825         if (err_data.ue_count) {
 826                 dev_info(adev->dev, "%ld uncorrectable hardware errors "
 827                                         "detected in %s block\n",
 828                                         obj->err_data.ue_count,
 829                                         ras_block_str(info->head.block));
 830         }
 831
 832         return 0;
 833 }
 834
 835 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 836                 enum amdgpu_ras_block block)
 837 {
 838         if (!amdgpu_ras_is_supported(adev, block))
 839                 return -EINVAL;
 840
 841         switch (block) {
 842         case AMDGPU_RAS_BLOCK__GFX:
 843                 if (adev->gfx.funcs->reset_ras_error_count)
 844                         adev->gfx.funcs->reset_ras_error_count(adev);
 845
 846                 if (adev->gfx.funcs->reset_ras_error_status)
 847                         adev->gfx.funcs->reset_ras_error_status(adev);
 848                 break;
 849         case AMDGPU_RAS_BLOCK__MMHUB:
 850                 if (adev->mmhub.funcs->reset_ras_error_count)
 851                         adev->mmhub.funcs->reset_ras_error_count(adev);
 852                 break;
 853         case AMDGPU_RAS_BLOCK__SDMA:
 854                 if (adev->sdma.funcs->reset_ras_error_count)
 855                         adev->sdma.funcs->reset_ras_error_count(adev);
 856                 break;
 857         default:
 858                 break;
 859         }
 860
 861         return 0;
 862 }
 863
 864 /* Trigger XGMI/WAFL error */
 865 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
 866                                  struct ta_ras_trigger_error_input *block_info)
 867 {
 868         int ret;
 869
 870         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
 871                 dev_warn(adev->dev, "Failed to disallow df cstate");
 872
 873         if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
 874                 dev_warn(adev->dev, "Failed to disallow XGMI power down");
 875
 876         ret = psp_ras_trigger_error(&adev->psp, block_info);
 877
 878         if (amdgpu_ras_intr_triggered())
 879                 return ret;
 880
 881         if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
 882                 dev_warn(adev->dev, "Failed to allow XGMI power down");
 883
 884         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
 885                 dev_warn(adev->dev, "Failed to allow df cstate");
 886
 887         return ret;
 888 }
 889
 890 /* wrapper of psp_ras_trigger_error */
 891 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 892                 struct ras_inject_if *info)
 893 {
 894         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 895         struct ta_ras_trigger_error_input block_info = {
 896                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
 897                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
 898                 .sub_block_index = info->head.sub_block_index,
 899                 .address = info->address,
 900                 .value = info->value,
 901         };
 902         int ret = 0;
 903
 904         if (!obj)
 905                 return -EINVAL;
 906
 907         /* Calculate XGMI relative offset */
 908         if (adev->gmc.xgmi.num_physical_nodes > 1) {
 909                 block_info.address =
 910                         amdgpu_xgmi_get_relative_phy_addr(adev,
 911                                                           block_info.address);
 912         }
 913
 914         switch (info->head.block) {
 915         case AMDGPU_RAS_BLOCK__GFX:
 916                 if (adev->gfx.funcs->ras_error_inject)
 917                         ret = adev->gfx.funcs->ras_error_inject(adev, info);
 918                 else
 919                         ret = -EINVAL;
 920                 break;
 921         case AMDGPU_RAS_BLOCK__UMC:
 922         case AMDGPU_RAS_BLOCK__MMHUB:
 923         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 924                 ret = psp_ras_trigger_error(&adev->psp, &block_info);
 925                 break;
 926         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 927                 ret = amdgpu_ras_error_inject_xgmi(adev, &block_info);
 928                 break;
 929         default:
 930                 dev_info(adev->dev, "%s error injection is not supported yet\n",
 931                          ras_block_str(info->head.block));
 932                 ret = -EINVAL;
 933         }
 934
 935         amdgpu_ras_parse_status_code(adev,
 936                                      "inject",
 937                                      ras_block_str(info->head.block),
 938                                      (enum ta_ras_status)ret);
 939
 940         return ret;
 941 }
 942
 943 /* get the total error counts on all IPs */
 944 unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
 945                 bool is_ce)
 946 {
 947         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 948         struct ras_manager *obj;
 949         struct ras_err_data data = {0, 0};
 950
 951         if (!con)
 952                 return 0;
 953
 954         list_for_each_entry(obj, &con->head, node) {
 955                 struct ras_query_if info = {
 956                         .head = obj->head,
 957                 };
 958
 959                 if (amdgpu_ras_query_error_status(adev, &info))
 960                         return 0;
 961
 962                 data.ce_count += info.ce_count;
 963                 data.ue_count += info.ue_count;
 964         }
 965
 966         return is_ce ? data.ce_count : data.ue_count;
 967 }
 968 /* query/inject/cure end */
 969
 970
 971 /* sysfs begin */
 972
 973 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
 974                 struct ras_badpage **bps, unsigned int *count);
 975
 976 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
 977 {
 978         switch (flags) {
 979         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
 980                 return "R";
 981         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
 982                 return "P";
 983         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
 984         default:
 985                 return "F";
 986         }
 987 }
 988
 989 /**
 990  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
 991  *
 992  * It allows user to read the bad pages of vram on the gpu through
 993  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
 994  *
 995  * It outputs multiple lines, and each line stands for one gpu page.
 996  *
 997  * The format of one line is below,
 998  * gpu pfn : gpu page size : flags
 999  *
1000  * gpu pfn and gpu page size are printed in hex format.
1001  * flags can be one of below character,
1002  *
1003  * R: reserved, this gpu page is reserved and not able to use.
1004  *
1005  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1006  * in next window of page_reserve.
1007  *
1008  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1009  *
1010  * Examples:
1011  *
1012  * .. code-block:: bash
1013  *
1014  *      0x00000001 : 0x00001000 : R
1015  *      0x00000002 : 0x00001000 : P
1016  *
1017  */
1018
1019 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1020                 struct kobject *kobj, struct bin_attribute *attr,
1021                 char *buf, loff_t ppos, size_t count)
1022 {
1023         struct amdgpu_ras *con =
1024                 container_of(attr, struct amdgpu_ras, badpages_attr);
1025         struct amdgpu_device *adev = con->adev;
1026         const unsigned int element_size =
1027                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1028         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1029         unsigned int end = div64_ul(ppos + count - 1, element_size);
1030         ssize_t s = 0;
1031         struct ras_badpage *bps = NULL;
1032         unsigned int bps_count = 0;
1033
1034         memset(buf, 0, count);
1035
1036         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1037                 return 0;
1038
1039         for (; start < end && start < bps_count; start++)
1040                 s += scnprintf(&buf[s], element_size + 1,
1041                                 "0x%08x : 0x%08x : %1s\n",
1042                                 bps[start].bp,
1043                                 bps[start].size,
1044                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1045
1046         kfree(bps);
1047
1048         return s;
1049 }
1050
1051 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1052                 struct device_attribute *attr, char *buf)
1053 {
1054         struct amdgpu_ras *con =
1055                 container_of(attr, struct amdgpu_ras, features_attr);
1056
1057         return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1058 }
1059
1060 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1061 {
1062         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1063
1064         sysfs_remove_file_from_group(&adev->dev->kobj,
1065                                 &con->badpages_attr.attr,
1066                                 RAS_FS_NAME);
1067 }
1068
1069 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1070 {
1071         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1072         struct attribute *attrs[] = {
1073                 &con->features_attr.attr,
1074                 NULL
1075         };
1076         struct attribute_group group = {
1077                 .name = RAS_FS_NAME,
1078                 .attrs = attrs,
1079         };
1080
1081         sysfs_remove_group(&adev->dev->kobj, &group);
1082
1083         return 0;
1084 }
1085
1086 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1087                 struct ras_fs_if *head)
1088 {
1089         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1090
1091         if (!obj || obj->attr_inuse)
1092                 return -EINVAL;
1093
1094         get_obj(obj);
1095
1096         memcpy(obj->fs_data.sysfs_name,
1097                         head->sysfs_name,
1098                         sizeof(obj->fs_data.sysfs_name));
1099
1100         obj->sysfs_attr = (struct device_attribute){
1101                 .attr = {
1102                         .name = obj->fs_data.sysfs_name,
1103                         .mode = S_IRUGO,
1104                 },
1105                         .show = amdgpu_ras_sysfs_read,
1106         };
1107         sysfs_attr_init(&obj->sysfs_attr.attr);
1108
1109         if (sysfs_add_file_to_group(&adev->dev->kobj,
1110                                 &obj->sysfs_attr.attr,
1111                                 RAS_FS_NAME)) {
1112                 put_obj(obj);
1113                 return -EINVAL;
1114         }
1115
1116         obj->attr_inuse = 1;
1117
1118         return 0;
1119 }
1120
1121 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1122                 struct ras_common_if *head)
1123 {
1124         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1125
1126         if (!obj || !obj->attr_inuse)
1127                 return -EINVAL;
1128
1129         sysfs_remove_file_from_group(&adev->dev->kobj,
1130                                 &obj->sysfs_attr.attr,
1131                                 RAS_FS_NAME);
1132         obj->attr_inuse = 0;
1133         put_obj(obj);
1134
1135         return 0;
1136 }
1137
1138 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1139 {
1140         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1141         struct ras_manager *obj, *tmp;
1142
1143         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1144                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1145         }
1146
1147         if (amdgpu_bad_page_threshold != 0)
1148                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1149
1150         amdgpu_ras_sysfs_remove_feature_node(adev);
1151
1152         return 0;
1153 }
1154 /* sysfs end */
1155
1156 /**
1157  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1158  *
1159  * Normally when there is an uncorrectable error, the driver will reset
1160  * the GPU to recover.  However, in the event of an unrecoverable error,
1161  * the driver provides an interface to reboot the system automatically
1162  * in that event.
1163  *
1164  * The following file in debugfs provides that interface:
1165  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1166  *
1167  * Usage:
1168  *
1169  * .. code-block:: bash
1170  *
1171  *      echo true > .../ras/auto_reboot
1172  *
1173  */
1174 /* debugfs begin */
1175 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1176 {
1177         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1178         struct dentry *dir;
1179         struct drm_minor *minor = adev_to_drm(adev)->primary;
1180
1181         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1182         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1183                             &amdgpu_ras_debugfs_ctrl_ops);
1184         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1185                             &amdgpu_ras_debugfs_eeprom_ops);
1186
1187         /*
1188          * After one uncorrectable error happens, usually GPU recovery will
1189          * be scheduled. But due to the known problem in GPU recovery failing
1190          * to bring GPU back, below interface provides one direct way to
1191          * user to reboot system automatically in such case within
1192          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1193          * will never be called.
1194          */
1195         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1196
1197         /*
1198          * User could set this not to clean up hardware's error count register
1199          * of RAS IPs during ras recovery.
1200          */
1201         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1202                             &con->disable_ras_err_cnt_harvest);
1203         return dir;
1204 }
1205
1206 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1207                                       struct ras_fs_if *head,
1208                                       struct dentry *dir)
1209 {
1210         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1211
1212         if (!obj || !dir)
1213                 return;
1214
1215         get_obj(obj);
1216
1217         memcpy(obj->fs_data.debugfs_name,
1218                         head->debugfs_name,
1219                         sizeof(obj->fs_data.debugfs_name));
1220
1221         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1222                             obj, &amdgpu_ras_debugfs_ops);
1223 }
1224
1225 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1226 {
1227         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1228         struct dentry *dir;
1229         struct ras_manager *obj;
1230         struct ras_fs_if fs_info;
1231
1232         /*
1233          * it won't be called in resume path, no need to check
1234          * suspend and gpu reset status
1235          */
1236         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1237                 return;
1238
1239         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1240
1241         list_for_each_entry(obj, &con->head, node) {
1242                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1243                         (obj->attr_inuse == 1)) {
1244                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1245                                         ras_block_str(obj->head.block));
1246                         fs_info.head = obj->head;
1247                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1248                 }
1249         }
1250 }
1251
1252 /* debugfs end */
1253
1254 /* ras fs */
1255 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1256                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1257 static DEVICE_ATTR(features, S_IRUGO,
1258                 amdgpu_ras_sysfs_features_read, NULL);
1259 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1260 {
1261         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1262         struct attribute_group group = {
1263                 .name = RAS_FS_NAME,
1264         };
1265         struct attribute *attrs[] = {
1266                 &con->features_attr.attr,
1267                 NULL
1268         };
1269         struct bin_attribute *bin_attrs[] = {
1270                 NULL,
1271                 NULL,
1272         };
1273         int r;
1274
1275         /* add features entry */
1276         con->features_attr = dev_attr_features;
1277         group.attrs = attrs;
1278         sysfs_attr_init(attrs[0]);
1279
1280         if (amdgpu_bad_page_threshold != 0) {
1281                 /* add bad_page_features entry */
1282                 bin_attr_gpu_vram_bad_pages.private = NULL;
1283                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1284                 bin_attrs[0] = &con->badpages_attr;
1285                 group.bin_attrs = bin_attrs;
1286                 sysfs_bin_attr_init(bin_attrs[0]);
1287         }
1288
1289         r = sysfs_create_group(&adev->dev->kobj, &group);
1290         if (r)
1291                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1292
1293         return 0;
1294 }
1295
1296 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1297 {
1298         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1299         struct ras_manager *con_obj, *ip_obj, *tmp;
1300
1301         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1302                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1303                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1304                         if (ip_obj)
1305                                 put_obj(ip_obj);
1306                 }
1307         }
1308
1309         amdgpu_ras_sysfs_remove_all(adev);
1310         return 0;
1311 }
1312 /* ras fs end */
1313
1314 /* ih begin */
1315 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1316 {
1317         struct ras_ih_data *data = &obj->ih_data;
1318         struct amdgpu_iv_entry entry;
1319         int ret;
1320         struct ras_err_data err_data = {0, 0, 0, NULL};
1321
1322         while (data->rptr != data->wptr) {
1323                 rmb();
1324                 memcpy(&entry, &data->ring[data->rptr],
1325                                 data->element_size);
1326
1327                 wmb();
1328                 data->rptr = (data->aligned_element_size +
1329                                 data->rptr) % data->ring_size;
1330
1331                 /* Let IP handle its data, maybe we need get the output
1332                  * from the callback to udpate the error type/count, etc
1333                  */
1334                 if (data->cb) {
1335                         ret = data->cb(obj->adev, &err_data, &entry);
1336                         /* ue will trigger an interrupt, and in that case
1337                          * we need do a reset to recovery the whole system.
1338                          * But leave IP do that recovery, here we just dispatch
1339                          * the error.
1340                          */
1341                         if (ret == AMDGPU_RAS_SUCCESS) {
1342                                 /* these counts could be left as 0 if
1343                                  * some blocks do not count error number
1344                                  */
1345                                 obj->err_data.ue_count += err_data.ue_count;
1346                                 obj->err_data.ce_count += err_data.ce_count;
1347                         }
1348                 }
1349         }
1350 }
1351
1352 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1353 {
1354         struct ras_ih_data *data =
1355                 container_of(work, struct ras_ih_data, ih_work);
1356         struct ras_manager *obj =
1357                 container_of(data, struct ras_manager, ih_data);
1358
1359         amdgpu_ras_interrupt_handler(obj);
1360 }
1361
1362 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1363                 struct ras_dispatch_if *info)
1364 {
1365         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1366         struct ras_ih_data *data = &obj->ih_data;
1367
1368         if (!obj)
1369                 return -EINVAL;
1370
1371         if (data->inuse == 0)
1372                 return 0;
1373
1374         /* Might be overflow... */
1375         memcpy(&data->ring[data->wptr], info->entry,
1376                         data->element_size);
1377
1378         wmb();
1379         data->wptr = (data->aligned_element_size +
1380                         data->wptr) % data->ring_size;
1381
1382         schedule_work(&data->ih_work);
1383
1384         return 0;
1385 }
1386
1387 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1388                 struct ras_ih_if *info)
1389 {
1390         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1391         struct ras_ih_data *data;
1392
1393         if (!obj)
1394                 return -EINVAL;
1395
1396         data = &obj->ih_data;
1397         if (data->inuse == 0)
1398                 return 0;
1399
1400         cancel_work_sync(&data->ih_work);
1401
1402         kfree(data->ring);
1403         memset(data, 0, sizeof(*data));
1404         put_obj(obj);
1405
1406         return 0;
1407 }
1408
1409 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1410                 struct ras_ih_if *info)
1411 {
1412         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1413         struct ras_ih_data *data;
1414
1415         if (!obj) {
1416                 /* in case we registe the IH before enable ras feature */
1417                 obj = amdgpu_ras_create_obj(adev, &info->head);
1418                 if (!obj)
1419                         return -EINVAL;
1420         } else
1421                 get_obj(obj);
1422
1423         data = &obj->ih_data;
1424         /* add the callback.etc */
1425         *data = (struct ras_ih_data) {
1426                 .inuse = 0,
1427                 .cb = info->cb,
1428                 .element_size = sizeof(struct amdgpu_iv_entry),
1429                 .rptr = 0,
1430                 .wptr = 0,
1431         };
1432
1433         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1434
1435         data->aligned_element_size = ALIGN(data->element_size, 8);
1436         /* the ring can store 64 iv entries. */
1437         data->ring_size = 64 * data->aligned_element_size;
1438         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1439         if (!data->ring) {
1440                 put_obj(obj);
1441                 return -ENOMEM;
1442         }
1443
1444         /* IH is ready */
1445         data->inuse = 1;
1446
1447         return 0;
1448 }
1449
1450 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1451 {
1452         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1453         struct ras_manager *obj, *tmp;
1454
1455         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1456                 struct ras_ih_if info = {
1457                         .head = obj->head,
1458                 };
1459                 amdgpu_ras_interrupt_remove_handler(adev, &info);
1460         }
1461
1462         return 0;
1463 }
1464 /* ih end */
1465
1466 /* traversal all IPs except NBIO to query error counter */
1467 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1468 {
1469         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1470         struct ras_manager *obj;
1471
1472         if (!con)
1473                 return;
1474
1475         list_for_each_entry(obj, &con->head, node) {
1476                 struct ras_query_if info = {
1477                         .head = obj->head,
1478                 };
1479
1480                 /*
1481                  * PCIE_BIF IP has one different isr by ras controller
1482                  * interrupt, the specific ras counter query will be
1483                  * done in that isr. So skip such block from common
1484                  * sync flood interrupt isr calling.
1485                  */
1486                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1487                         continue;
1488
1489                 amdgpu_ras_query_error_status(adev, &info);
1490         }
1491 }
1492
1493 /* Parse RdRspStatus and WrRspStatus */
1494 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1495                                           struct ras_query_if *info)
1496 {
1497         /*
1498          * Only two block need to query read/write
1499          * RspStatus at current state
1500          */
1501         switch (info->head.block) {
1502         case AMDGPU_RAS_BLOCK__GFX:
1503                 if (adev->gfx.funcs->query_ras_error_status)
1504                         adev->gfx.funcs->query_ras_error_status(adev);
1505                 break;
1506         case AMDGPU_RAS_BLOCK__MMHUB:
1507                 if (adev->mmhub.funcs->query_ras_error_status)
1508                         adev->mmhub.funcs->query_ras_error_status(adev);
1509                 break;
1510         default:
1511                 break;
1512         }
1513 }
1514
1515 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1516 {
1517         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1518         struct ras_manager *obj;
1519
1520         if (!con)
1521                 return;
1522
1523         list_for_each_entry(obj, &con->head, node) {
1524                 struct ras_query_if info = {
1525                         .head = obj->head,
1526                 };
1527
1528                 amdgpu_ras_error_status_query(adev, &info);
1529         }
1530 }
1531
1532 /* recovery begin */
1533
1534 /* return 0 on success.
1535  * caller need free bps.
1536  */
1537 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1538                 struct ras_badpage **bps, unsigned int *count)
1539 {
1540         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1541         struct ras_err_handler_data *data;
1542         int i = 0;
1543         int ret = 0, status;
1544
1545         if (!con || !con->eh_data || !bps || !count)
1546                 return -EINVAL;
1547
1548         mutex_lock(&con->recovery_lock);
1549         data = con->eh_data;
1550         if (!data || data->count == 0) {
1551                 *bps = NULL;
1552                 ret = -EINVAL;
1553                 goto out;
1554         }
1555
1556         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1557         if (!*bps) {
1558                 ret = -ENOMEM;
1559                 goto out;
1560         }
1561
1562         for (; i < data->count; i++) {
1563                 (*bps)[i] = (struct ras_badpage){
1564                         .bp = data->bps[i].retired_page,
1565                         .size = AMDGPU_GPU_PAGE_SIZE,
1566                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1567                 };
1568                 status = amdgpu_vram_mgr_query_page_status(
1569                                 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1570                                 data->bps[i].retired_page);
1571                 if (status == -EBUSY)
1572                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1573                 else if (status == -ENOENT)
1574                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1575         }
1576
1577         *count = data->count;
1578 out:
1579         mutex_unlock(&con->recovery_lock);
1580         return ret;
1581 }
1582
1583 static void amdgpu_ras_do_recovery(struct work_struct *work)
1584 {
1585         struct amdgpu_ras *ras =
1586                 container_of(work, struct amdgpu_ras, recovery_work);
1587         struct amdgpu_device *remote_adev = NULL;
1588         struct amdgpu_device *adev = ras->adev;
1589         struct list_head device_list, *device_list_handle =  NULL;
1590
1591         if (!ras->disable_ras_err_cnt_harvest) {
1592                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1593
1594                 /* Build list of devices to query RAS related errors */
1595                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1596                         device_list_handle = &hive->device_list;
1597                 } else {
1598                         INIT_LIST_HEAD(&device_list);
1599                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
1600                         device_list_handle = &device_list;
1601                 }
1602
1603                 list_for_each_entry(remote_adev,
1604                                 device_list_handle, gmc.xgmi.head) {
1605                         amdgpu_ras_query_err_status(remote_adev);
1606                         amdgpu_ras_log_on_err_counter(remote_adev);
1607                 }
1608
1609                 amdgpu_put_xgmi_hive(hive);
1610         }
1611
1612         if (amdgpu_device_should_recover_gpu(ras->adev))
1613                 amdgpu_device_gpu_recover(ras->adev, NULL);
1614         atomic_set(&ras->in_recovery, 0);
1615 }
1616
1617 /* alloc/realloc bps array */
1618 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1619                 struct ras_err_handler_data *data, int pages)
1620 {
1621         unsigned int old_space = data->count + data->space_left;
1622         unsigned int new_space = old_space + pages;
1623         unsigned int align_space = ALIGN(new_space, 512);
1624         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1625
1626         if (!bps) {
1627                 kfree(bps);
1628                 return -ENOMEM;
1629         }
1630
1631         if (data->bps) {
1632                 memcpy(bps, data->bps,
1633                                 data->count * sizeof(*data->bps));
1634                 kfree(data->bps);
1635         }
1636
1637         data->bps = bps;
1638         data->space_left += align_space - old_space;
1639         return 0;
1640 }
1641
1642 /* it deal with vram only. */
1643 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1644                 struct eeprom_table_record *bps, int pages)
1645 {
1646         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1647         struct ras_err_handler_data *data;
1648         int ret = 0;
1649         uint32_t i;
1650
1651         if (!con || !con->eh_data || !bps || pages <= 0)
1652                 return 0;
1653
1654         mutex_lock(&con->recovery_lock);
1655         data = con->eh_data;
1656         if (!data)
1657                 goto out;
1658
1659         for (i = 0; i < pages; i++) {
1660                 if (amdgpu_ras_check_bad_page_unlock(con,
1661                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1662                         continue;
1663
1664                 if (!data->space_left &&
1665                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1666                         ret = -ENOMEM;
1667                         goto out;
1668                 }
1669
1670                 amdgpu_vram_mgr_reserve_range(
1671                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1672                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1673                         AMDGPU_GPU_PAGE_SIZE);
1674
1675                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1676                 data->count++;
1677                 data->space_left--;
1678         }
1679 out:
1680         mutex_unlock(&con->recovery_lock);
1681
1682         return ret;
1683 }
1684
1685 /*
1686  * write error record array to eeprom, the function should be
1687  * protected by recovery_lock
1688  */
1689 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1690 {
1691         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1692         struct ras_err_handler_data *data;
1693         struct amdgpu_ras_eeprom_control *control;
1694         int save_count;
1695
1696         if (!con || !con->eh_data)
1697                 return 0;
1698
1699         control = &con->eeprom_control;
1700         data = con->eh_data;
1701         save_count = data->count - control->num_recs;
1702         /* only new entries are saved */
1703         if (save_count > 0) {
1704                 if (amdgpu_ras_eeprom_process_recods(control,
1705                                                         &data->bps[control->num_recs],
1706                                                         true,
1707                                                         save_count)) {
1708                         dev_err(adev->dev, "Failed to save EEPROM table data!");
1709                         return -EIO;
1710                 }
1711
1712                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
1713         }
1714
1715         return 0;
1716 }
1717
1718 /*
1719  * read error record array in eeprom and reserve enough space for
1720  * storing new bad pages
1721  */
1722 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1723 {
1724         struct amdgpu_ras_eeprom_control *control =
1725                                         &adev->psp.ras.ras->eeprom_control;
1726         struct eeprom_table_record *bps = NULL;
1727         int ret = 0;
1728
1729         /* no bad page record, skip eeprom access */
1730         if (!control->num_recs || (amdgpu_bad_page_threshold == 0))
1731                 return ret;
1732
1733         bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
1734         if (!bps)
1735                 return -ENOMEM;
1736
1737         if (amdgpu_ras_eeprom_process_recods(control, bps, false,
1738                 control->num_recs)) {
1739                 dev_err(adev->dev, "Failed to load EEPROM table records!");
1740                 ret = -EIO;
1741                 goto out;
1742         }
1743
1744         ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
1745
1746 out:
1747         kfree(bps);
1748         return ret;
1749 }
1750
1751 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
1752                                 uint64_t addr)
1753 {
1754         struct ras_err_handler_data *data = con->eh_data;
1755         int i;
1756
1757         addr >>= AMDGPU_GPU_PAGE_SHIFT;
1758         for (i = 0; i < data->count; i++)
1759                 if (addr == data->bps[i].retired_page)
1760                         return true;
1761
1762         return false;
1763 }
1764
1765 /*
1766  * check if an address belongs to bad page
1767  *
1768  * Note: this check is only for umc block
1769  */
1770 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1771                                 uint64_t addr)
1772 {
1773         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1774         bool ret = false;
1775
1776         if (!con || !con->eh_data)
1777                 return ret;
1778
1779         mutex_lock(&con->recovery_lock);
1780         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
1781         mutex_unlock(&con->recovery_lock);
1782         return ret;
1783 }
1784
1785 static uint32_t
1786 amdgpu_ras_calculate_badpags_threshold(struct amdgpu_device *adev)
1787 {
1788         int tmp_threshold = amdgpu_bad_page_threshold;
1789         u64 val;
1790         uint32_t max_length = 0;
1791
1792         max_length = amdgpu_ras_eeprom_get_record_max_length();
1793         /*
1794          * Justification of value bad_page_cnt_threshold in ras structure
1795          *
1796          * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
1797          * in eeprom, and introduce two scenarios accordingly.
1798          *
1799          * Bad page retirement enablement:
1800          *    - If amdgpu_bad_page_threshold = -1,
1801          *      bad_page_cnt_threshold = typical value by formula.
1802          *
1803          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
1804          *      max record length in eeprom, use it directly.
1805          *
1806          * Bad page retirement disablement:
1807          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
1808          *      functionality is disabled, and bad_page_cnt_threshold will
1809          *      take no effect.
1810          */
1811
1812         if (tmp_threshold < -1)
1813                 tmp_threshold = -1;
1814         else if (tmp_threshold > max_length)
1815                 tmp_threshold = max_length;
1816
1817         if (tmp_threshold == -1) {
1818                 val = adev->gmc.real_vram_size;
1819                 do_div(val, RAS_BAD_PAGE_RATE);
1820                 tmp_threshold = min(lower_32_bits(val), max_length);
1821         }
1822
1823         return tmp_threshold;
1824 }
1825
1826 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1827 {
1828         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1829         struct ras_err_handler_data **data;
1830         bool exc_err_limit = false;
1831         int ret;
1832
1833         if (con)
1834                 data = &con->eh_data;
1835         else
1836                 return 0;
1837
1838         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
1839         if (!*data) {
1840                 ret = -ENOMEM;
1841                 goto out;
1842         }
1843
1844         mutex_init(&con->recovery_lock);
1845         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1846         atomic_set(&con->in_recovery, 0);
1847         con->adev = adev;
1848
1849         if (!con->bad_page_cnt_threshold) {
1850                 con->bad_page_cnt_threshold =
1851                         amdgpu_ras_calculate_badpags_threshold(adev);
1852
1853                 ret = amdgpu_vram_mgr_reserve_backup_pages(
1854                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1855                         con->bad_page_cnt_threshold);
1856                 if (ret)
1857                         goto out;
1858         }
1859
1860         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
1861         /*
1862          * This calling fails when exc_err_limit is true or
1863          * ret != 0.
1864          */
1865         if (exc_err_limit || ret)
1866                 goto free;
1867
1868         if (con->eeprom_control.num_recs) {
1869                 ret = amdgpu_ras_load_bad_pages(adev);
1870                 if (ret)
1871                         goto free;
1872         }
1873
1874         return 0;
1875
1876 free:
1877         kfree((*data)->bps);
1878         kfree(*data);
1879         con->eh_data = NULL;
1880 out:
1881         dev_warn(adev->dev, "Failed to initialize ras recovery!\n");
1882
1883         /*
1884          * Except error threshold exceeding case, other failure cases in this
1885          * function would not fail amdgpu driver init.
1886          */
1887         if (!exc_err_limit)
1888                 ret = 0;
1889         else
1890                 ret = -EINVAL;
1891
1892         return ret;
1893 }
1894
1895 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
1896 {
1897         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1898         struct ras_err_handler_data *data = con->eh_data;
1899
1900         /* recovery_init failed to init it, fini is useless */
1901         if (!data)
1902                 return 0;
1903
1904         cancel_work_sync(&con->recovery_work);
1905
1906         mutex_lock(&con->recovery_lock);
1907         con->eh_data = NULL;
1908         kfree(data->bps);
1909         kfree(data);
1910         mutex_unlock(&con->recovery_lock);
1911
1912         return 0;
1913 }
1914 /* recovery end */
1915
1916 /* return 0 if ras will reset gpu and repost.*/
1917 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
1918                 unsigned int block)
1919 {
1920         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1921
1922         if (!ras)
1923                 return -EINVAL;
1924
1925         ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
1926         return 0;
1927 }
1928
1929 static int amdgpu_ras_check_asic_type(struct amdgpu_device *adev)
1930 {
1931         if (adev->asic_type != CHIP_VEGA10 &&
1932                 adev->asic_type != CHIP_VEGA20 &&
1933                 adev->asic_type != CHIP_ARCTURUS &&
1934                 adev->asic_type != CHIP_SIENNA_CICHLID)
1935                 return 1;
1936         else
1937                 return 0;
1938 }
1939
1940 /*
1941  * check hardware's ras ability which will be saved in hw_supported.
1942  * if hardware does not support ras, we can skip some ras initializtion and
1943  * forbid some ras operations from IP.
1944  * if software itself, say boot parameter, limit the ras ability. We still
1945  * need allow IP do some limited operations, like disable. In such case,
1946  * we have to initialize ras as normal. but need check if operation is
1947  * allowed or not in each function.
1948  */
1949 static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
1950                 uint32_t *hw_supported, uint32_t *supported)
1951 {
1952         *hw_supported = 0;
1953         *supported = 0;
1954
1955         if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
1956                 amdgpu_ras_check_asic_type(adev))
1957                 return;
1958
1959         if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
1960                 dev_info(adev->dev, "HBM ECC is active.\n");
1961                 *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC |
1962                                 1 << AMDGPU_RAS_BLOCK__DF);
1963         } else
1964                 dev_info(adev->dev, "HBM ECC is not presented.\n");
1965
1966         if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
1967                 dev_info(adev->dev, "SRAM ECC is active.\n");
1968                 *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
1969                                 1 << AMDGPU_RAS_BLOCK__DF);
1970         } else
1971                 dev_info(adev->dev, "SRAM ECC is not presented.\n");
1972
1973         /* hw_supported needs to be aligned with RAS block mask. */
1974         *hw_supported &= AMDGPU_RAS_BLOCK_MASK;
1975
1976         *supported = amdgpu_ras_enable == 0 ?
1977                         0 : *hw_supported & amdgpu_ras_mask;
1978         adev->ras_features = *supported;
1979 }
1980
1981 int amdgpu_ras_init(struct amdgpu_device *adev)
1982 {
1983         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1984         int r;
1985
1986         if (con)
1987                 return 0;
1988
1989         con = kmalloc(sizeof(struct amdgpu_ras) +
1990                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
1991                         GFP_KERNEL|__GFP_ZERO);
1992         if (!con)
1993                 return -ENOMEM;
1994
1995         con->objs = (struct ras_manager *)(con + 1);
1996
1997         amdgpu_ras_set_context(adev, con);
1998
1999         amdgpu_ras_check_supported(adev, &con->hw_supported,
2000                         &con->supported);
2001         if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) {
2002                 r = 0;
2003                 goto release_con;
2004         }
2005
2006         con->features = 0;
2007         INIT_LIST_HEAD(&con->head);
2008         /* Might need get this flag from vbios. */
2009         con->flags = RAS_DEFAULT_FLAGS;
2010
2011         if (adev->nbio.funcs->init_ras_controller_interrupt) {
2012                 r = adev->nbio.funcs->init_ras_controller_interrupt(adev);
2013                 if (r)
2014                         goto release_con;
2015         }
2016
2017         if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) {
2018                 r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev);
2019                 if (r)
2020                         goto release_con;
2021         }
2022
2023         if (amdgpu_ras_fs_init(adev)) {
2024                 r = -EINVAL;
2025                 goto release_con;
2026         }
2027
2028         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2029                         "hardware ability[%x] ras_mask[%x]\n",
2030                         con->hw_supported, con->supported);
2031         return 0;
2032 release_con:
2033         amdgpu_ras_set_context(adev, NULL);
2034         kfree(con);
2035
2036         return r;
2037 }
2038
2039 /* helper function to handle common stuff in ip late init phase */
2040 int amdgpu_ras_late_init(struct amdgpu_device *adev,
2041                          struct ras_common_if *ras_block,
2042                          struct ras_fs_if *fs_info,
2043                          struct ras_ih_if *ih_info)
2044 {
2045         int r;
2046
2047         /* disable RAS feature per IP block if it is not supported */
2048         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2049                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2050                 return 0;
2051         }
2052
2053         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2054         if (r) {
2055                 if (r == -EAGAIN) {
2056                         /* request gpu reset. will run again */
2057                         amdgpu_ras_request_reset_on_boot(adev,
2058                                         ras_block->block);
2059                         return 0;
2060                 } else if (adev->in_suspend || amdgpu_in_reset(adev)) {
2061                         /* in resume phase, if fail to enable ras,
2062                          * clean up all ras fs nodes, and disable ras */
2063                         goto cleanup;
2064                 } else
2065                         return r;
2066         }
2067
2068         /* in resume phase, no need to create ras fs node */
2069         if (adev->in_suspend || amdgpu_in_reset(adev))
2070                 return 0;
2071
2072         if (ih_info->cb) {
2073                 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2074                 if (r)
2075                         goto interrupt;
2076         }
2077
2078         r = amdgpu_ras_sysfs_create(adev, fs_info);
2079         if (r)
2080                 goto sysfs;
2081
2082         return 0;
2083 cleanup:
2084         amdgpu_ras_sysfs_remove(adev, ras_block);
2085 sysfs:
2086         if (ih_info->cb)
2087                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2088 interrupt:
2089         amdgpu_ras_feature_enable(adev, ras_block, 0);
2090         return r;
2091 }
2092
2093 /* helper function to remove ras fs node and interrupt handler */
2094 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2095                           struct ras_common_if *ras_block,
2096                           struct ras_ih_if *ih_info)
2097 {
2098         if (!ras_block || !ih_info)
2099                 return;
2100
2101         amdgpu_ras_sysfs_remove(adev, ras_block);
2102         if (ih_info->cb)
2103                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2104         amdgpu_ras_feature_enable(adev, ras_block, 0);
2105 }
2106
2107 /* do some init work after IP late init as dependence.
2108  * and it runs in resume/gpu reset/booting up cases.
2109  */
2110 void amdgpu_ras_resume(struct amdgpu_device *adev)
2111 {
2112         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2113         struct ras_manager *obj, *tmp;
2114
2115         if (!con)
2116                 return;
2117
2118         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2119                 /* Set up all other IPs which are not implemented. There is a
2120                  * tricky thing that IP's actual ras error type should be
2121                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2122                  * ERROR_NONE make sense anyway.
2123                  */
2124                 amdgpu_ras_enable_all_features(adev, 1);
2125
2126                 /* We enable ras on all hw_supported block, but as boot
2127                  * parameter might disable some of them and one or more IP has
2128                  * not implemented yet. So we disable them on behalf.
2129                  */
2130                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2131                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2132                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2133                                 /* there should be no any reference. */
2134                                 WARN_ON(alive_obj(obj));
2135                         }
2136                 }
2137         }
2138
2139         if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
2140                 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2141                 /* setup ras obj state as disabled.
2142                  * for init_by_vbios case.
2143                  * if we want to enable ras, just enable it in a normal way.
2144                  * If we want do disable it, need setup ras obj as enabled,
2145                  * then issue another TA disable cmd.
2146                  * See feature_enable_on_boot
2147                  */
2148                 amdgpu_ras_disable_all_features(adev, 1);
2149                 amdgpu_ras_reset_gpu(adev);
2150         }
2151 }
2152
2153 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2154 {
2155         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2156
2157         if (!con)
2158                 return;
2159
2160         amdgpu_ras_disable_all_features(adev, 0);
2161         /* Make sure all ras objects are disabled. */
2162         if (con->features)
2163                 amdgpu_ras_disable_all_features(adev, 1);
2164 }
2165
2166 /* do some fini work before IP fini as dependence */
2167 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2168 {
2169         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2170
2171         if (!con)
2172                 return 0;
2173
2174         /* Need disable ras on all IPs here before ip [hw/sw]fini */
2175         amdgpu_ras_disable_all_features(adev, 0);
2176         amdgpu_ras_recovery_fini(adev);
2177         return 0;
2178 }
2179
2180 int amdgpu_ras_fini(struct amdgpu_device *adev)
2181 {
2182         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2183
2184         if (!con)
2185                 return 0;
2186
2187         amdgpu_ras_fs_fini(adev);
2188         amdgpu_ras_interrupt_remove_all(adev);
2189
2190         WARN(con->features, "Feature mask is not cleared");
2191
2192         if (con->features)
2193                 amdgpu_ras_disable_all_features(adev, 1);
2194
2195         amdgpu_ras_set_context(adev, NULL);
2196         kfree(con);
2197
2198         return 0;
2199 }
2200
2201 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2202 {
2203         uint32_t hw_supported, supported;
2204
2205         amdgpu_ras_check_supported(adev, &hw_supported, &supported);
2206         if (!hw_supported)
2207                 return;
2208
2209         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2210                 dev_info(adev->dev, "uncorrectable hardware error"
2211                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2212
2213                 amdgpu_ras_reset_gpu(adev);
2214         }
2215 }
2216
2217 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2218 {
2219         if (adev->asic_type == CHIP_VEGA20 &&
2220             adev->pm.fw_version <= 0x283400) {
2221                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2222                                 amdgpu_ras_intr_triggered();
2223         }
2224
2225         return false;
2226 }