drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/amdgpu_drm.h>
  25 #include "amdgpu.h"
  26 #include "atomfirmware.h"
  27 #include "amdgpu_atomfirmware.h"
  28 #include "atom.h"
  29 #include "atombios.h"
  30 #include "soc15_hw_ip.h"
  31
  32 bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
  33 {
  34         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  35                                                 firmwareinfo);
  36         uint16_t data_offset;
  37
  38         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  39                                           NULL, NULL, &data_offset)) {
  40                 struct atom_firmware_info_v3_1 *firmware_info =
  41                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  42                                                            data_offset);
  43
  44                 if (le32_to_cpu(firmware_info->firmware_capability) &
  45                     ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION)
  46                         return true;
  47         }
  48         return false;
  49 }
  50
  51 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
  52 {
  53         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  54                                                 firmwareinfo);
  55         uint16_t data_offset;
  56
  57         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  58                                           NULL, NULL, &data_offset)) {
  59                 struct atom_firmware_info_v3_1 *firmware_info =
  60                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  61                                                            data_offset);
  62
  63                 adev->bios_scratch_reg_offset =
  64                         le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
  65         }
  66 }
  67
  68 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
  69 {
  70         struct atom_context *ctx = adev->mode_info.atom_context;
  71         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  72                                                 vram_usagebyfirmware);
  73         struct vram_usagebyfirmware_v2_1 *firmware_usage;
  74         uint32_t start_addr, size;
  75         uint16_t data_offset;
  76         int usage_bytes = 0;
  77
  78         if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
  79                 firmware_usage = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
  80                 DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",
  81                           le32_to_cpu(firmware_usage->start_address_in_kb),
  82                           le16_to_cpu(firmware_usage->used_by_firmware_in_kb),
  83                           le16_to_cpu(firmware_usage->used_by_driver_in_kb));
  84
  85                 start_addr = le32_to_cpu(firmware_usage->start_address_in_kb);
  86                 size = le16_to_cpu(firmware_usage->used_by_firmware_in_kb);
  87
  88                 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
  89                         (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
  90                         ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
  91                         /* Firmware request VRAM reservation for SR-IOV */
  92                         adev->mman.fw_vram_usage_start_offset = (start_addr &
  93                                 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
  94                         adev->mman.fw_vram_usage_size = size << 10;
  95                         /* Use the default scratch size */
  96                         usage_bytes = 0;
  97                 } else {
  98                         usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) << 10;
  99                 }
 100         }
 101         ctx->scratch_size_bytes = 0;
 102         if (usage_bytes == 0)
 103                 usage_bytes = 20 * 1024;
 104         /* allocate some scratch memory */
 105         ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
 106         if (!ctx->scratch)
 107                 return -ENOMEM;
 108         ctx->scratch_size_bytes = usage_bytes;
 109         return 0;
 110 }
 111
 112 union igp_info {
 113         struct atom_integrated_system_info_v1_11 v11;
 114         struct atom_integrated_system_info_v1_12 v12;
 115         struct atom_integrated_system_info_v2_1 v21;
 116 };
 117
 118 union umc_info {
 119         struct atom_umc_info_v3_1 v31;
 120 };
 121
 122 union vram_info {
 123         struct atom_vram_info_header_v2_3 v23;
 124         struct atom_vram_info_header_v2_4 v24;
 125         struct atom_vram_info_header_v2_5 v25;
 126         struct atom_vram_info_header_v2_6 v26;
 127 };
 128
 129 union vram_module {
 130         struct atom_vram_module_v9 v9;
 131         struct atom_vram_module_v10 v10;
 132         struct atom_vram_module_v11 v11;
 133 };
 134
 135 static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
 136                                               int atom_mem_type)
 137 {
 138         int vram_type;
 139
 140         if (adev->flags & AMD_IS_APU) {
 141                 switch (atom_mem_type) {
 142                 case Ddr2MemType:
 143                 case LpDdr2MemType:
 144                         vram_type = AMDGPU_VRAM_TYPE_DDR2;
 145                         break;
 146                 case Ddr3MemType:
 147                 case LpDdr3MemType:
 148                         vram_type = AMDGPU_VRAM_TYPE_DDR3;
 149                         break;
 150                 case Ddr4MemType:
 151                 case LpDdr4MemType:
 152                         vram_type = AMDGPU_VRAM_TYPE_DDR4;
 153                         break;
 154                 case Ddr5MemType:
 155                 case LpDdr5MemType:
 156                         vram_type = AMDGPU_VRAM_TYPE_DDR5;
 157                         break;
 158                 default:
 159                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 160                         break;
 161                 }
 162         } else {
 163                 switch (atom_mem_type) {
 164                 case ATOM_DGPU_VRAM_TYPE_GDDR5:
 165                         vram_type = AMDGPU_VRAM_TYPE_GDDR5;
 166                         break;
 167                 case ATOM_DGPU_VRAM_TYPE_HBM2:
 168                 case ATOM_DGPU_VRAM_TYPE_HBM2E:
 169                         vram_type = AMDGPU_VRAM_TYPE_HBM;
 170                         break;
 171                 case ATOM_DGPU_VRAM_TYPE_GDDR6:
 172                         vram_type = AMDGPU_VRAM_TYPE_GDDR6;
 173                         break;
 174                 default:
 175                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 176                         break;
 177                 }
 178         }
 179
 180         return vram_type;
 181 }
 182
 183
 184 int
 185 amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
 186                                   int *vram_width, int *vram_type,
 187                                   int *vram_vendor)
 188 {
 189         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 190         int index, i = 0;
 191         u16 data_offset, size;
 192         union igp_info *igp_info;
 193         union vram_info *vram_info;
 194         union vram_module *vram_module;
 195         u8 frev, crev;
 196         u8 mem_type;
 197         u8 mem_vendor;
 198         u32 mem_channel_number;
 199         u32 mem_channel_width;
 200         u32 module_id;
 201
 202         if (adev->flags & AMD_IS_APU)
 203                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 204                                                     integratedsysteminfo);
 205         else
 206                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 207                                                     vram_info);
 208
 209         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 210                                           index, &size,
 211                                           &frev, &crev, &data_offset)) {
 212                 if (adev->flags & AMD_IS_APU) {
 213                         igp_info = (union igp_info *)
 214                                 (mode_info->atom_context->bios + data_offset);
 215                         switch (frev) {
 216                         case 1:
 217                                 switch (crev) {
 218                                 case 11:
 219                                 case 12:
 220                                         mem_channel_number = igp_info->v11.umachannelnumber;
 221                                         if (!mem_channel_number)
 222                                                 mem_channel_number = 1;
 223                                         /* channel width is 64 */
 224                                         if (vram_width)
 225                                                 *vram_width = mem_channel_number * 64;
 226                                         mem_type = igp_info->v11.memorytype;
 227                                         if (vram_type)
 228                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 229                                         break;
 230                                 default:
 231                                         return -EINVAL;
 232                                 }
 233                                 break;
 234                         case 2:
 235                                 switch (crev) {
 236                                 case 1:
 237                                 case 2:
 238                                         mem_channel_number = igp_info->v21.umachannelnumber;
 239                                         if (!mem_channel_number)
 240                                                 mem_channel_number = 1;
 241                                         /* channel width is 64 */
 242                                         if (vram_width)
 243                                                 *vram_width = mem_channel_number * 64;
 244                                         mem_type = igp_info->v21.memorytype;
 245                                         if (vram_type)
 246                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 247                                         break;
 248                                 default:
 249                                         return -EINVAL;
 250                                 }
 251                                 break;
 252                         default:
 253                                 return -EINVAL;
 254                         }
 255                 } else {
 256                         vram_info = (union vram_info *)
 257                                 (mode_info->atom_context->bios + data_offset);
 258                         module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
 259                         switch (crev) {
 260                         case 3:
 261                                 if (module_id > vram_info->v23.vram_module_num)
 262                                         module_id = 0;
 263                                 vram_module = (union vram_module *)vram_info->v23.vram_module;
 264                                 while (i < module_id) {
 265                                         vram_module = (union vram_module *)
 266                                                 ((u8 *)vram_module + vram_module->v9.vram_module_size);
 267                                         i++;
 268                                 }
 269                                 mem_type = vram_module->v9.memory_type;
 270                                 if (vram_type)
 271                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 272                                 mem_channel_number = vram_module->v9.channel_num;
 273                                 mem_channel_width = vram_module->v9.channel_width;
 274                                 if (vram_width)
 275                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 276                                 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 277                                 if (vram_vendor)
 278                                         *vram_vendor = mem_vendor;
 279                                 break;
 280                         case 4:
 281                                 if (module_id > vram_info->v24.vram_module_num)
 282                                         module_id = 0;
 283                                 vram_module = (union vram_module *)vram_info->v24.vram_module;
 284                                 while (i < module_id) {
 285                                         vram_module = (union vram_module *)
 286                                                 ((u8 *)vram_module + vram_module->v10.vram_module_size);
 287                                         i++;
 288                                 }
 289                                 mem_type = vram_module->v10.memory_type;
 290                                 if (vram_type)
 291                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 292                                 mem_channel_number = vram_module->v10.channel_num;
 293                                 mem_channel_width = vram_module->v10.channel_width;
 294                                 if (vram_width)
 295                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 296                                 mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
 297                                 if (vram_vendor)
 298                                         *vram_vendor = mem_vendor;
 299                                 break;
 300                         case 5:
 301                                 if (module_id > vram_info->v25.vram_module_num)
 302                                         module_id = 0;
 303                                 vram_module = (union vram_module *)vram_info->v25.vram_module;
 304                                 while (i < module_id) {
 305                                         vram_module = (union vram_module *)
 306                                                 ((u8 *)vram_module + vram_module->v11.vram_module_size);
 307                                         i++;
 308                                 }
 309                                 mem_type = vram_module->v11.memory_type;
 310                                 if (vram_type)
 311                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 312                                 mem_channel_number = vram_module->v11.channel_num;
 313                                 mem_channel_width = vram_module->v11.channel_width;
 314                                 if (vram_width)
 315                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 316                                 mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
 317                                 if (vram_vendor)
 318                                         *vram_vendor = mem_vendor;
 319                                 break;
 320                         case 6:
 321                                 if (module_id > vram_info->v26.vram_module_num)
 322                                         module_id = 0;
 323                                 vram_module = (union vram_module *)vram_info->v26.vram_module;
 324                                 while (i < module_id) {
 325                                         vram_module = (union vram_module *)
 326                                                 ((u8 *)vram_module + vram_module->v9.vram_module_size);
 327                                         i++;
 328                                 }
 329                                 mem_type = vram_module->v9.memory_type;
 330                                 if (vram_type)
 331                                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 332                                 mem_channel_number = vram_module->v9.channel_num;
 333                                 mem_channel_width = vram_module->v9.channel_width;
 334                                 if (vram_width)
 335                                         *vram_width = mem_channel_number * (1 << mem_channel_width);
 336                                 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 337                                 if (vram_vendor)
 338                                         *vram_vendor = mem_vendor;
 339                                 break;
 340                         default:
 341                                 return -EINVAL;
 342                         }
 343                 }
 344
 345         }
 346
 347         return 0;
 348 }
 349
 350 /*
 351  * Return true if vbios enabled ecc by default, if umc info table is available
 352  * or false if ecc is not enabled or umc info table is not available
 353  */
 354 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
 355 {
 356         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 357         int index;
 358         u16 data_offset, size;
 359         union umc_info *umc_info;
 360         u8 frev, crev;
 361         bool ecc_default_enabled = false;
 362
 363         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 364                         umc_info);
 365
 366         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 367                                 index, &size, &frev, &crev, &data_offset)) {
 368                 /* support umc_info 3.1+ */
 369                 if ((frev == 3 && crev >= 1) || (frev > 3)) {
 370                         umc_info = (union umc_info *)
 371                                 (mode_info->atom_context->bios + data_offset);
 372                         ecc_default_enabled =
 373                                 (le32_to_cpu(umc_info->v31.umc_config) &
 374                                  UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 375                 }
 376         }
 377
 378         return ecc_default_enabled;
 379 }
 380
 381 union firmware_info {
 382         struct atom_firmware_info_v3_1 v31;
 383         struct atom_firmware_info_v3_2 v32;
 384         struct atom_firmware_info_v3_3 v33;
 385         struct atom_firmware_info_v3_4 v34;
 386 };
 387
 388 /*
 389  * Return true if vbios supports sram ecc or false if not
 390  */
 391 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
 392 {
 393         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 394         int index;
 395         u16 data_offset, size;
 396         union firmware_info *firmware_info;
 397         u8 frev, crev;
 398         bool sram_ecc_supported = false;
 399
 400         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 401                         firmwareinfo);
 402
 403         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
 404                                 index, &size, &frev, &crev, &data_offset)) {
 405                 /* support firmware_info 3.1 + */
 406                 if ((frev == 3 && crev >=1) || (frev > 3)) {
 407                         firmware_info = (union firmware_info *)
 408                                 (mode_info->atom_context->bios + data_offset);
 409                         sram_ecc_supported =
 410                                 (le32_to_cpu(firmware_info->v31.firmware_capability) &
 411                                  ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
 412                 }
 413         }
 414
 415         return sram_ecc_supported;
 416 }
 417
 418 union smu_info {
 419         struct atom_smu_info_v3_1 v31;
 420 };
 421
 422 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
 423 {
 424         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 425         struct amdgpu_pll *spll = &adev->clock.spll;
 426         struct amdgpu_pll *mpll = &adev->clock.mpll;
 427         uint8_t frev, crev;
 428         uint16_t data_offset;
 429         int ret = -EINVAL, index;
 430
 431         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 432                                             firmwareinfo);
 433         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 434                                    &frev, &crev, &data_offset)) {
 435                 union firmware_info *firmware_info =
 436                         (union firmware_info *)(mode_info->atom_context->bios +
 437                                                 data_offset);
 438
 439                 adev->clock.default_sclk =
 440                         le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
 441                 adev->clock.default_mclk =
 442                         le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
 443
 444                 adev->pm.current_sclk = adev->clock.default_sclk;
 445                 adev->pm.current_mclk = adev->clock.default_mclk;
 446
 447                 /* not technically a clock, but... */
 448                 adev->mode_info.firmware_flags =
 449                         le32_to_cpu(firmware_info->v31.firmware_capability);
 450
 451                 ret = 0;
 452         }
 453
 454         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 455                                             smu_info);
 456         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 457                                    &frev, &crev, &data_offset)) {
 458                 union smu_info *smu_info =
 459                         (union smu_info *)(mode_info->atom_context->bios +
 460                                            data_offset);
 461
 462                 /* system clock */
 463                 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
 464
 465                 spll->reference_div = 0;
 466                 spll->min_post_div = 1;
 467                 spll->max_post_div = 1;
 468                 spll->min_ref_div = 2;
 469                 spll->max_ref_div = 0xff;
 470                 spll->min_feedback_div = 4;
 471                 spll->max_feedback_div = 0xff;
 472                 spll->best_vco = 0;
 473
 474                 ret = 0;
 475         }
 476
 477         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 478                                             umc_info);
 479         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 480                                    &frev, &crev, &data_offset)) {
 481                 union umc_info *umc_info =
 482                         (union umc_info *)(mode_info->atom_context->bios +
 483                                            data_offset);
 484
 485                 /* memory clock */
 486                 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
 487
 488                 mpll->reference_div = 0;
 489                 mpll->min_post_div = 1;
 490                 mpll->max_post_div = 1;
 491                 mpll->min_ref_div = 2;
 492                 mpll->max_ref_div = 0xff;
 493                 mpll->min_feedback_div = 4;
 494                 mpll->max_feedback_div = 0xff;
 495                 mpll->best_vco = 0;
 496
 497                 ret = 0;
 498         }
 499
 500         return ret;
 501 }
 502
 503 union gfx_info {
 504         struct atom_gfx_info_v2_4 v24;
 505         struct atom_gfx_info_v2_7 v27;
 506 };
 507
 508 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
 509 {
 510         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 511         int index;
 512         uint8_t frev, crev;
 513         uint16_t data_offset;
 514
 515         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 516                                             gfx_info);
 517         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 518                                    &frev, &crev, &data_offset)) {
 519                 union gfx_info *gfx_info = (union gfx_info *)
 520                         (mode_info->atom_context->bios + data_offset);
 521                 switch (crev) {
 522                 case 4:
 523                         adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
 524                         adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
 525                         adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
 526                         adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
 527                         adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
 528                         adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
 529                         adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
 530                         adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
 531                         adev->gfx.config.gs_prim_buffer_depth =
 532                                 le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
 533                         adev->gfx.config.double_offchip_lds_buf =
 534                                 gfx_info->v24.gc_double_offchip_lds_buffer;
 535                         adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
 536                         adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
 537                         adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
 538                         adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
 539                         return 0;
 540                 case 7:
 541                         adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines;
 542                         adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh;
 543                         adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se;
 544                         adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se;
 545                         adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches;
 546                         adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs);
 547                         adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds;
 548                         adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth;
 549                         adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth);
 550                         adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer;
 551                         adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size);
 552                         adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd);
 553                         adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu;
 554                         adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size);
 555                         return 0;
 556                 default:
 557                         return -EINVAL;
 558                 }
 559
 560         }
 561         return -EINVAL;
 562 }
 563
 564 /*
 565  * Check if VBIOS supports GDDR6 training data save/restore
 566  */
 567 static bool gddr6_mem_train_vbios_support(struct amdgpu_device *adev)
 568 {
 569         uint16_t data_offset;
 570         int index;
 571
 572         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 573                                             firmwareinfo);
 574         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
 575                                           NULL, NULL, &data_offset)) {
 576                 struct atom_firmware_info_v3_1 *firmware_info =
 577                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
 578                                                            data_offset);
 579
 580                 DRM_DEBUG("atom firmware capability:0x%08x.\n",
 581                           le32_to_cpu(firmware_info->firmware_capability));
 582
 583                 if (le32_to_cpu(firmware_info->firmware_capability) &
 584                     ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING)
 585                         return true;
 586         }
 587
 588         return false;
 589 }
 590
 591 int amdgpu_mem_train_support(struct amdgpu_device *adev)
 592 {
 593         int ret;
 594         uint32_t major, minor, revision, hw_v;
 595
 596         if (gddr6_mem_train_vbios_support(adev)) {
 597                 amdgpu_discovery_get_ip_version(adev, MP0_HWID, &major, &minor, &revision);
 598                 hw_v = HW_REV(major, minor, revision);
 599                 /*
 600                  * treat 0 revision as a special case since register for MP0 and MMHUB is missing
 601                  * for some Navi10 A0, preventing driver from discovering the hwip information since
 602                  * none of the functions will be initialized, it should not cause any problems
 603                  */
 604                 switch (hw_v) {
 605                 case HW_REV(11, 0, 0):
 606                 case HW_REV(11, 0, 5):
 607                 case HW_REV(11, 0, 7):
 608                 case HW_REV(11, 0, 11):
 609                 case HW_REV(11, 0, 12):
 610                         ret = 1;
 611                         break;
 612                 default:
 613                         DRM_ERROR("memory training vbios supports but psp hw(%08x)"
 614                                   " doesn't support!\n", hw_v);
 615                         ret = -1;
 616                         break;
 617                 }
 618         } else {
 619                 ret = 0;
 620                 hw_v = -1;
 621         }
 622
 623
 624         DRM_DEBUG("mp0 hw_v %08x, ret:%d.\n", hw_v, ret);
 625         return ret;
 626 }
 627
 628 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
 629 {
 630         struct atom_context *ctx = adev->mode_info.atom_context;
 631         union firmware_info *firmware_info;
 632         int index;
 633         u16 data_offset, size;
 634         u8 frev, crev;
 635         int fw_reserved_fb_size;
 636
 637         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 638                         firmwareinfo);
 639
 640         if (!amdgpu_atom_parse_data_header(ctx, index, &size,
 641                                 &frev, &crev, &data_offset))
 642                 /* fail to parse data_header */
 643                 return 0;
 644
 645         firmware_info = (union firmware_info *)(ctx->bios + data_offset);
 646
 647         if (frev !=3)
 648                 return -EINVAL;
 649
 650         switch (crev) {
 651         case 4:
 652                 fw_reserved_fb_size =
 653                         (firmware_info->v34.fw_reserved_size_in_kb << 10);
 654                 break;
 655         default:
 656                 fw_reserved_fb_size = 0;
 657                 break;
 658         }
 659
 660         return fw_reserved_fb_size;
 661 }