drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "atom.h"
  36 #include "amd_pcie.h"
  37
  38 #include "uvd/uvd_7_0_offset.h"
  39 #include "gc/gc_9_0_offset.h"
  40 #include "gc/gc_9_0_sh_mask.h"
  41 #include "sdma0/sdma0_4_0_offset.h"
  42 #include "sdma1/sdma1_4_0_offset.h"
  43 #include "hdp/hdp_4_0_offset.h"
  44 #include "hdp/hdp_4_0_sh_mask.h"
  45 #include "smuio/smuio_9_0_offset.h"
  46 #include "smuio/smuio_9_0_sh_mask.h"
  47 #include "nbio/nbio_7_0_default.h"
  48 #include "nbio/nbio_7_0_offset.h"
  49 #include "nbio/nbio_7_0_sh_mask.h"
  50 #include "nbio/nbio_7_0_smn.h"
  51 #include "mp/mp_9_0_offset.h"
  52
  53 #include "soc15.h"
  54 #include "soc15_common.h"
  55 #include "gfx_v9_0.h"
  56 #include "gmc_v9_0.h"
  57 #include "gfxhub_v1_0.h"
  58 #include "mmhub_v1_0.h"
  59 #include "df_v1_7.h"
  60 #include "df_v3_6.h"
  61 #include "nbio_v6_1.h"
  62 #include "nbio_v7_0.h"
  63 #include "nbio_v7_4.h"
  64 #include "vega10_ih.h"
  65 #include "sdma_v4_0.h"
  66 #include "uvd_v7_0.h"
  67 #include "vce_v4_0.h"
  68 #include "vcn_v1_0.h"
  69 #include "vcn_v2_0.h"
  70 #include "jpeg_v2_0.h"
  71 #include "vcn_v2_5.h"
  72 #include "jpeg_v2_5.h"
  73 #include "dce_virtual.h"
  74 #include "mxgpu_ai.h"
  75 #include "amdgpu_smu.h"
  76 #include "amdgpu_ras.h"
  77 #include "amdgpu_xgmi.h"
  78 #include <uapi/linux/kfd_ioctl.h>
  79
  80 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  81 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  82 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  83 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  84
  85 /* for Vega20 register name change */
  86 #define mmHDP_MEM_POWER_CTRL    0x00d4
  87 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK  0x00000001L
  88 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK    0x00000002L
  89 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK   0x00010000L
  90 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK             0x00020000L
  91 #define mmHDP_MEM_POWER_CTRL_BASE_IDX   0
  92
  93 /* for Vega20/arcturus regiter offset change */
  94 #define mmROM_INDEX_VG20                                0x00e4
  95 #define mmROM_INDEX_VG20_BASE_IDX                       0
  96 #define mmROM_DATA_VG20                                 0x00e5
  97 #define mmROM_DATA_VG20_BASE_IDX                        0
  98
  99 /*
 100  * Indirect registers accessor
 101  */
 102 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 103 {
 104         unsigned long flags, address, data;
 105         u32 r;
 106         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 107         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 108
 109         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 110         WREG32(address, reg);
 111         (void)RREG32(address);
 112         r = RREG32(data);
 113         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 114         return r;
 115 }
 116
 117 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 118 {
 119         unsigned long flags, address, data;
 120
 121         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 122         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 123
 124         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 125         WREG32(address, reg);
 126         (void)RREG32(address);
 127         WREG32(data, v);
 128         (void)RREG32(data);
 129         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 130 }
 131
 132 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 133 {
 134         unsigned long flags, address, data;
 135         u64 r;
 136         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 137         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 138
 139         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 140         /* read low 32 bit */
 141         WREG32(address, reg);
 142         (void)RREG32(address);
 143         r = RREG32(data);
 144
 145         /* read high 32 bit*/
 146         WREG32(address, reg + 4);
 147         (void)RREG32(address);
 148         r |= ((u64)RREG32(data) << 32);
 149         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 150         return r;
 151 }
 152
 153 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 154 {
 155         unsigned long flags, address, data;
 156
 157         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 158         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 159
 160         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 161         /* write low 32 bit */
 162         WREG32(address, reg);
 163         (void)RREG32(address);
 164         WREG32(data, (u32)(v & 0xffffffffULL));
 165         (void)RREG32(data);
 166
 167         /* write high 32 bit */
 168         WREG32(address, reg + 4);
 169         (void)RREG32(address);
 170         WREG32(data, (u32)(v >> 32));
 171         (void)RREG32(data);
 172         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 173 }
 174
 175 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 176 {
 177         unsigned long flags, address, data;
 178         u32 r;
 179
 180         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 181         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 182
 183         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 184         WREG32(address, ((reg) & 0x1ff));
 185         r = RREG32(data);
 186         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 187         return r;
 188 }
 189
 190 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 191 {
 192         unsigned long flags, address, data;
 193
 194         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 195         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 196
 197         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 198         WREG32(address, ((reg) & 0x1ff));
 199         WREG32(data, (v));
 200         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 201 }
 202
 203 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 204 {
 205         unsigned long flags, address, data;
 206         u32 r;
 207
 208         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 209         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 210
 211         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 212         WREG32(address, (reg));
 213         r = RREG32(data);
 214         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 215         return r;
 216 }
 217
 218 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 219 {
 220         unsigned long flags, address, data;
 221
 222         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 223         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 224
 225         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 226         WREG32(address, (reg));
 227         WREG32(data, (v));
 228         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 229 }
 230
 231 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 232 {
 233         unsigned long flags;
 234         u32 r;
 235
 236         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 237         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 238         r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
 239         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 240         return r;
 241 }
 242
 243 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 244 {
 245         unsigned long flags;
 246
 247         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 248         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 249         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
 250         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 251 }
 252
 253 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
 254 {
 255         unsigned long flags;
 256         u32 r;
 257
 258         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 259         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 260         r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
 261         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 262         return r;
 263 }
 264
 265 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 266 {
 267         unsigned long flags;
 268
 269         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 270         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 271         WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
 272         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 273 }
 274
 275 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 276 {
 277         return adev->nbio.funcs->get_memsize(adev);
 278 }
 279
 280 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 281 {
 282         u32 reference_clock = adev->clock.spll.reference_freq;
 283
 284         if (adev->asic_type == CHIP_RAVEN)
 285                 return reference_clock / 4;
 286
 287         return reference_clock;
 288 }
 289
 290
 291 void soc15_grbm_select(struct amdgpu_device *adev,
 292                      u32 me, u32 pipe, u32 queue, u32 vmid)
 293 {
 294         u32 grbm_gfx_cntl = 0;
 295         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 296         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 297         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 298         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 299
 300         WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 301 }
 302
 303 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 304 {
 305         /* todo */
 306 }
 307
 308 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 309 {
 310         /* todo */
 311         return false;
 312 }
 313
 314 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 315                                      u8 *bios, u32 length_bytes)
 316 {
 317         u32 *dw_ptr;
 318         u32 i, length_dw;
 319         uint32_t rom_index_offset;
 320         uint32_t rom_data_offset;
 321
 322         if (bios == NULL)
 323                 return false;
 324         if (length_bytes == 0)
 325                 return false;
 326         /* APU vbios image is part of sbios image */
 327         if (adev->flags & AMD_IS_APU)
 328                 return false;
 329
 330         dw_ptr = (u32 *)bios;
 331         length_dw = ALIGN(length_bytes, 4) / 4;
 332
 333         switch (adev->asic_type) {
 334         case CHIP_VEGA20:
 335         case CHIP_ARCTURUS:
 336                 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX_VG20);
 337                 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA_VG20);
 338                 break;
 339         default:
 340                 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
 341                 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
 342                 break;
 343         }
 344
 345         /* set rom index to 0 */
 346         WREG32(rom_index_offset, 0);
 347         /* read out the rom data */
 348         for (i = 0; i < length_dw; i++)
 349                 dw_ptr[i] = RREG32(rom_data_offset);
 350
 351         return true;
 352 }
 353
 354 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 355         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 356         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 357         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 358         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 359         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 360         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 361         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 362         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 363         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 364         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 365         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 366         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 367         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 368         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 369         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 370         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 371         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 372         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 373         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 374         { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
 375 };
 376
 377 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 378                                          u32 sh_num, u32 reg_offset)
 379 {
 380         uint32_t val;
 381
 382         mutex_lock(&adev->grbm_idx_mutex);
 383         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 384                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 385
 386         val = RREG32(reg_offset);
 387
 388         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 389                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 390         mutex_unlock(&adev->grbm_idx_mutex);
 391         return val;
 392 }
 393
 394 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 395                                          bool indexed, u32 se_num,
 396                                          u32 sh_num, u32 reg_offset)
 397 {
 398         if (indexed) {
 399                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 400         } else {
 401                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 402                         return adev->gfx.config.gb_addr_config;
 403                 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
 404                         return adev->gfx.config.db_debug2;
 405                 return RREG32(reg_offset);
 406         }
 407 }
 408
 409 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 410                             u32 sh_num, u32 reg_offset, u32 *value)
 411 {
 412         uint32_t i;
 413         struct soc15_allowed_register_entry  *en;
 414
 415         *value = 0;
 416         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 417                 en = &soc15_allowed_read_registers[i];
 418                 if (adev->reg_offset[en->hwip][en->inst] &&
 419                         reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 420                                         + en->reg_offset))
 421                         continue;
 422
 423                 *value = soc15_get_register_value(adev,
 424                                                   soc15_allowed_read_registers[i].grbm_indexed,
 425                                                   se_num, sh_num, reg_offset);
 426                 return 0;
 427         }
 428         return -EINVAL;
 429 }
 430
 431
 432 /**
 433  * soc15_program_register_sequence - program an array of registers.
 434  *
 435  * @adev: amdgpu_device pointer
 436  * @regs: pointer to the register array
 437  * @array_size: size of the register array
 438  *
 439  * Programs an array or registers with and and or masks.
 440  * This is a helper for setting golden registers.
 441  */
 442
 443 void soc15_program_register_sequence(struct amdgpu_device *adev,
 444                                              const struct soc15_reg_golden *regs,
 445                                              const u32 array_size)
 446 {
 447         const struct soc15_reg_golden *entry;
 448         u32 tmp, reg;
 449         int i;
 450
 451         for (i = 0; i < array_size; ++i) {
 452                 entry = &regs[i];
 453                 reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 454
 455                 if (entry->and_mask == 0xffffffff) {
 456                         tmp = entry->or_mask;
 457                 } else {
 458                         tmp = RREG32(reg);
 459                         tmp &= ~(entry->and_mask);
 460                         tmp |= (entry->or_mask & entry->and_mask);
 461                 }
 462
 463                 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
 464                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
 465                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
 466                         reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
 467                         WREG32_RLC(reg, tmp);
 468                 else
 469                         WREG32(reg, tmp);
 470
 471         }
 472
 473 }
 474
 475 static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
 476 {
 477         u32 i;
 478         int ret = 0;
 479
 480         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 481
 482         dev_info(adev->dev, "GPU mode1 reset\n");
 483
 484         /* disable BM */
 485         pci_clear_master(adev->pdev);
 486
 487         pci_save_state(adev->pdev);
 488
 489         ret = psp_gpu_reset(adev);
 490         if (ret)
 491                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 492
 493         pci_restore_state(adev->pdev);
 494
 495         /* wait for asic to come out of reset */
 496         for (i = 0; i < adev->usec_timeout; i++) {
 497                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 498
 499                 if (memsize != 0xffffffff)
 500                         break;
 501                 udelay(1);
 502         }
 503
 504         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 505
 506         return ret;
 507 }
 508
 509 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
 510 {
 511         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 512         int ret = 0;
 513
 514         /* avoid NBIF got stuck when do RAS recovery in BACO reset */
 515         if (ras && ras->supported)
 516                 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
 517
 518         ret = amdgpu_dpm_baco_reset(adev);
 519         if (ret)
 520                 return ret;
 521
 522         /* re-enable doorbell interrupt after BACO exit */
 523         if (ras && ras->supported)
 524                 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
 525
 526         return 0;
 527 }
 528
 529 static enum amd_reset_method
 530 soc15_asic_reset_method(struct amdgpu_device *adev)
 531 {
 532         bool baco_reset = false;
 533         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 534
 535         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 536             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 537                 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
 538                 return amdgpu_reset_method;
 539
 540         if (amdgpu_reset_method != -1)
 541                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 542                                   amdgpu_reset_method);
 543
 544         switch (adev->asic_type) {
 545         case CHIP_RAVEN:
 546         case CHIP_RENOIR:
 547                 return AMD_RESET_METHOD_MODE2;
 548         case CHIP_VEGA10:
 549         case CHIP_VEGA12:
 550         case CHIP_ARCTURUS:
 551                 baco_reset = amdgpu_dpm_is_baco_supported(adev);
 552                 break;
 553         case CHIP_VEGA20:
 554                 if (adev->psp.sos_fw_version >= 0x80067)
 555                         baco_reset = amdgpu_dpm_is_baco_supported(adev);
 556
 557                 /*
 558                  * 1. PMFW version > 0x284300: all cases use baco
 559                  * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
 560                  */
 561                 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
 562                         baco_reset = false;
 563                 break;
 564         default:
 565                 break;
 566         }
 567
 568         if (baco_reset)
 569                 return AMD_RESET_METHOD_BACO;
 570         else
 571                 return AMD_RESET_METHOD_MODE1;
 572 }
 573
 574 static int soc15_asic_reset(struct amdgpu_device *adev)
 575 {
 576         /* original raven doesn't have full asic reset */
 577         if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
 578             !(adev->apu_flags & AMD_APU_IS_RAVEN2))
 579                 return 0;
 580
 581         switch (soc15_asic_reset_method(adev)) {
 582                 case AMD_RESET_METHOD_BACO:
 583                         dev_info(adev->dev, "BACO reset\n");
 584                         return soc15_asic_baco_reset(adev);
 585                 case AMD_RESET_METHOD_MODE2:
 586                         dev_info(adev->dev, "MODE2 reset\n");
 587                         return amdgpu_dpm_mode2_reset(adev);
 588                 default:
 589                         dev_info(adev->dev, "MODE1 reset\n");
 590                         return soc15_asic_mode1_reset(adev);
 591         }
 592 }
 593
 594 static bool soc15_supports_baco(struct amdgpu_device *adev)
 595 {
 596         switch (adev->asic_type) {
 597         case CHIP_VEGA10:
 598         case CHIP_VEGA12:
 599         case CHIP_ARCTURUS:
 600                 return amdgpu_dpm_is_baco_supported(adev);
 601         case CHIP_VEGA20:
 602                 if (adev->psp.sos_fw_version >= 0x80067)
 603                         return amdgpu_dpm_is_baco_supported(adev);
 604                 return false;
 605         default:
 606                 return false;
 607         }
 608 }
 609
 610 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 611                         u32 cntl_reg, u32 status_reg)
 612 {
 613         return 0;
 614 }*/
 615
 616 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 617 {
 618         /*int r;
 619
 620         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 621         if (r)
 622                 return r;
 623
 624         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 625         */
 626         return 0;
 627 }
 628
 629 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 630 {
 631         /* todo */
 632
 633         return 0;
 634 }
 635
 636 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 637 {
 638         if (pci_is_root_bus(adev->pdev->bus))
 639                 return;
 640
 641         if (amdgpu_pcie_gen2 == 0)
 642                 return;
 643
 644         if (adev->flags & AMD_IS_APU)
 645                 return;
 646
 647         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 648                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 649                 return;
 650
 651         /* todo */
 652 }
 653
 654 static void soc15_program_aspm(struct amdgpu_device *adev)
 655 {
 656
 657         if (amdgpu_aspm == 0)
 658                 return;
 659
 660         /* todo */
 661 }
 662
 663 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 664                                            bool enable)
 665 {
 666         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 667         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 668 }
 669
 670 static const struct amdgpu_ip_block_version vega10_common_ip_block =
 671 {
 672         .type = AMD_IP_BLOCK_TYPE_COMMON,
 673         .major = 2,
 674         .minor = 0,
 675         .rev = 0,
 676         .funcs = &soc15_common_ip_funcs,
 677 };
 678
 679 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 680 {
 681         return adev->nbio.funcs->get_rev_id(adev);
 682 }
 683
 684 static void soc15_reg_base_init(struct amdgpu_device *adev)
 685 {
 686         int r;
 687
 688         /* Set IP register base before any HW register access */
 689         switch (adev->asic_type) {
 690         case CHIP_VEGA10:
 691         case CHIP_VEGA12:
 692         case CHIP_RAVEN:
 693                 vega10_reg_base_init(adev);
 694                 break;
 695         case CHIP_RENOIR:
 696                 /* It's safe to do ip discovery here for Renior,
 697                  * it doesn't support SRIOV. */
 698                 if (amdgpu_discovery) {
 699                         r = amdgpu_discovery_reg_base_init(adev);
 700                         if (r) {
 701                                 DRM_WARN("failed to init reg base from ip discovery table, "
 702                                          "fallback to legacy init method\n");
 703                                 vega10_reg_base_init(adev);
 704                         }
 705                 }
 706                 break;
 707         case CHIP_VEGA20:
 708                 vega20_reg_base_init(adev);
 709                 break;
 710         case CHIP_ARCTURUS:
 711                 arct_reg_base_init(adev);
 712                 break;
 713         default:
 714                 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
 715                 break;
 716         }
 717 }
 718
 719 void soc15_set_virt_ops(struct amdgpu_device *adev)
 720 {
 721         adev->virt.ops = &xgpu_ai_virt_ops;
 722
 723         /* init soc15 reg base early enough so we can
 724          * request request full access for sriov before
 725          * set_ip_blocks. */
 726         soc15_reg_base_init(adev);
 727 }
 728
 729 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 730 {
 731         /* for bare metal case */
 732         if (!amdgpu_sriov_vf(adev))
 733                 soc15_reg_base_init(adev);
 734
 735         if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
 736                 adev->gmc.xgmi.supported = true;
 737
 738         if (adev->flags & AMD_IS_APU) {
 739                 adev->nbio.funcs = &nbio_v7_0_funcs;
 740                 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
 741         } else if (adev->asic_type == CHIP_VEGA20 ||
 742                    adev->asic_type == CHIP_ARCTURUS) {
 743                 adev->nbio.funcs = &nbio_v7_4_funcs;
 744                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
 745         } else {
 746                 adev->nbio.funcs = &nbio_v6_1_funcs;
 747                 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
 748         }
 749
 750         if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
 751                 adev->df.funcs = &df_v3_6_funcs;
 752         else
 753                 adev->df.funcs = &df_v1_7_funcs;
 754
 755         adev->rev_id = soc15_get_rev_id(adev);
 756
 757         switch (adev->asic_type) {
 758         case CHIP_VEGA10:
 759         case CHIP_VEGA12:
 760         case CHIP_VEGA20:
 761                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 762                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 763
 764                 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
 765                 if (amdgpu_sriov_vf(adev)) {
 766                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 767                                 if (adev->asic_type == CHIP_VEGA20)
 768                                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 769                                 else
 770                                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 771                         }
 772                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 773                 } else {
 774                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 775                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 776                                 if (adev->asic_type == CHIP_VEGA20)
 777                                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 778                                 else
 779                                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 780                         }
 781                 }
 782                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 783                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 784                 if (is_support_sw_smu(adev)) {
 785                         if (!amdgpu_sriov_vf(adev))
 786                                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 787                 } else {
 788                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 789                 }
 790                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 791                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 792 #if defined(CONFIG_DRM_AMD_DC)
 793                 else if (amdgpu_device_has_dc_support(adev))
 794                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 795 #endif
 796                 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
 797                         amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
 798                         amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
 799                 }
 800                 break;
 801         case CHIP_RAVEN:
 802                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 803                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 804                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 805                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 806                         amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
 807                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 808                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 809                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 810                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 811                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 812 #if defined(CONFIG_DRM_AMD_DC)
 813                 else if (amdgpu_device_has_dc_support(adev))
 814                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 815 #endif
 816                 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
 817                 break;
 818         case CHIP_ARCTURUS:
 819                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 820                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 821
 822                 if (amdgpu_sriov_vf(adev)) {
 823                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 824                                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 825                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 826                 } else {
 827                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 828                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 829                                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 830                 }
 831
 832                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 833                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 834                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 835                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 836                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 837
 838                 if (amdgpu_sriov_vf(adev)) {
 839                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 840                                 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
 841                 } else {
 842                         amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
 843                 }
 844                 if (!amdgpu_sriov_vf(adev))
 845                         amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
 846                 break;
 847         case CHIP_RENOIR:
 848                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 849                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 850                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 851                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 852                         amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
 853                 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
 854                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 855                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 856                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 857                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 858 #if defined(CONFIG_DRM_AMD_DC)
 859                 else if (amdgpu_device_has_dc_support(adev))
 860                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 861 #endif
 862                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 863                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 864                 break;
 865         default:
 866                 return -EINVAL;
 867         }
 868
 869         return 0;
 870 }
 871
 872 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 873 {
 874         adev->nbio.funcs->hdp_flush(adev, ring);
 875 }
 876
 877 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
 878                                  struct amdgpu_ring *ring)
 879 {
 880         if (!ring || !ring->funcs->emit_wreg)
 881                 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 882         else
 883                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 884                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 885 }
 886
 887 static bool soc15_need_full_reset(struct amdgpu_device *adev)
 888 {
 889         /* change this when we implement soft reset */
 890         return true;
 891 }
 892
 893 static void vega20_reset_hdp_ras_error_count(struct amdgpu_device *adev)
 894 {
 895         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
 896                 return;
 897         /*read back hdp ras counter to reset it to 0 */
 898         RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
 899 }
 900
 901 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 902                                  uint64_t *count1)
 903 {
 904         uint32_t perfctr = 0;
 905         uint64_t cnt0_of, cnt1_of;
 906         int tmp;
 907
 908         /* This reports 0 on APUs, so return to avoid writing/reading registers
 909          * that may or may not be different from their GPU counterparts
 910          */
 911         if (adev->flags & AMD_IS_APU)
 912                 return;
 913
 914         /* Set the 2 events that we wish to watch, defined above */
 915         /* Reg 40 is # received msgs */
 916         /* Reg 104 is # of posted requests sent */
 917         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
 918         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
 919
 920         /* Write to enable desired perf counters */
 921         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
 922         /* Zero out and enable the perf counters
 923          * Write 0x5:
 924          * Bit 0 = Start all counters(1)
 925          * Bit 2 = Global counter reset enable(1)
 926          */
 927         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 928
 929         msleep(1000);
 930
 931         /* Load the shadow and disable the perf counters
 932          * Write 0x2:
 933          * Bit 0 = Stop counters(0)
 934          * Bit 1 = Load the shadow counters(1)
 935          */
 936         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 937
 938         /* Read register values to get any >32bit overflow */
 939         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
 940         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
 941         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
 942
 943         /* Get the values and add the overflow */
 944         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
 945         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
 946 }
 947
 948 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 949                                  uint64_t *count1)
 950 {
 951         uint32_t perfctr = 0;
 952         uint64_t cnt0_of, cnt1_of;
 953         int tmp;
 954
 955         /* This reports 0 on APUs, so return to avoid writing/reading registers
 956          * that may or may not be different from their GPU counterparts
 957          */
 958         if (adev->flags & AMD_IS_APU)
 959                 return;
 960
 961         /* Set the 2 events that we wish to watch, defined above */
 962         /* Reg 40 is # received msgs */
 963         /* Reg 108 is # of posted requests sent on VG20 */
 964         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 965                                 EVENT0_SEL, 40);
 966         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 967                                 EVENT1_SEL, 108);
 968
 969         /* Write to enable desired perf counters */
 970         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
 971         /* Zero out and enable the perf counters
 972          * Write 0x5:
 973          * Bit 0 = Start all counters(1)
 974          * Bit 2 = Global counter reset enable(1)
 975          */
 976         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 977
 978         msleep(1000);
 979
 980         /* Load the shadow and disable the perf counters
 981          * Write 0x2:
 982          * Bit 0 = Stop counters(0)
 983          * Bit 1 = Load the shadow counters(1)
 984          */
 985         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 986
 987         /* Read register values to get any >32bit overflow */
 988         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
 989         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
 990         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
 991
 992         /* Get the values and add the overflow */
 993         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
 994         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
 995 }
 996
 997 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
 998 {
 999         u32 sol_reg;
1000
1001         /* Just return false for soc15 GPUs.  Reset does not seem to
1002          * be necessary.
1003          */
1004         if (!amdgpu_passthrough(adev))
1005                 return false;
1006
1007         if (adev->flags & AMD_IS_APU)
1008                 return false;
1009
1010         /* Check sOS sign of life register to confirm sys driver and sOS
1011          * are already been loaded.
1012          */
1013         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1014         if (sol_reg)
1015                 return true;
1016
1017         return false;
1018 }
1019
1020 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
1021 {
1022         uint64_t nak_r, nak_g;
1023
1024         /* Get the number of NAKs received and generated */
1025         nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
1026         nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
1027
1028         /* Add the total number of NAKs, i.e the number of replays */
1029         return (nak_r + nak_g);
1030 }
1031
1032 static const struct amdgpu_asic_funcs soc15_asic_funcs =
1033 {
1034         .read_disabled_bios = &soc15_read_disabled_bios,
1035         .read_bios_from_rom = &soc15_read_bios_from_rom,
1036         .read_register = &soc15_read_register,
1037         .reset = &soc15_asic_reset,
1038         .reset_method = &soc15_asic_reset_method,
1039         .set_vga_state = &soc15_vga_set_state,
1040         .get_xclk = &soc15_get_xclk,
1041         .set_uvd_clocks = &soc15_set_uvd_clocks,
1042         .set_vce_clocks = &soc15_set_vce_clocks,
1043         .get_config_memsize = &soc15_get_config_memsize,
1044         .flush_hdp = &soc15_flush_hdp,
1045         .invalidate_hdp = &soc15_invalidate_hdp,
1046         .need_full_reset = &soc15_need_full_reset,
1047         .init_doorbell_index = &vega10_doorbell_index_init,
1048         .get_pcie_usage = &soc15_get_pcie_usage,
1049         .need_reset_on_init = &soc15_need_reset_on_init,
1050         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1051         .supports_baco = &soc15_supports_baco,
1052 };
1053
1054 static const struct amdgpu_asic_funcs vega20_asic_funcs =
1055 {
1056         .read_disabled_bios = &soc15_read_disabled_bios,
1057         .read_bios_from_rom = &soc15_read_bios_from_rom,
1058         .read_register = &soc15_read_register,
1059         .reset = &soc15_asic_reset,
1060         .reset_method = &soc15_asic_reset_method,
1061         .set_vga_state = &soc15_vga_set_state,
1062         .get_xclk = &soc15_get_xclk,
1063         .set_uvd_clocks = &soc15_set_uvd_clocks,
1064         .set_vce_clocks = &soc15_set_vce_clocks,
1065         .get_config_memsize = &soc15_get_config_memsize,
1066         .flush_hdp = &soc15_flush_hdp,
1067         .invalidate_hdp = &soc15_invalidate_hdp,
1068         .reset_hdp_ras_error_count = &vega20_reset_hdp_ras_error_count,
1069         .need_full_reset = &soc15_need_full_reset,
1070         .init_doorbell_index = &vega20_doorbell_index_init,
1071         .get_pcie_usage = &vega20_get_pcie_usage,
1072         .need_reset_on_init = &soc15_need_reset_on_init,
1073         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1074         .supports_baco = &soc15_supports_baco,
1075 };
1076
1077 static int soc15_common_early_init(void *handle)
1078 {
1079 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1080         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1081
1082         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1083         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1084         adev->smc_rreg = NULL;
1085         adev->smc_wreg = NULL;
1086         adev->pcie_rreg = &soc15_pcie_rreg;
1087         adev->pcie_wreg = &soc15_pcie_wreg;
1088         adev->pcie_rreg64 = &soc15_pcie_rreg64;
1089         adev->pcie_wreg64 = &soc15_pcie_wreg64;
1090         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1091         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1092         adev->didt_rreg = &soc15_didt_rreg;
1093         adev->didt_wreg = &soc15_didt_wreg;
1094         adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1095         adev->gc_cac_wreg = &soc15_gc_cac_wreg;
1096         adev->se_cac_rreg = &soc15_se_cac_rreg;
1097         adev->se_cac_wreg = &soc15_se_cac_wreg;
1098
1099
1100         adev->external_rev_id = 0xFF;
1101         switch (adev->asic_type) {
1102         case CHIP_VEGA10:
1103                 adev->asic_funcs = &soc15_asic_funcs;
1104                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1105                         AMD_CG_SUPPORT_GFX_MGLS |
1106                         AMD_CG_SUPPORT_GFX_RLC_LS |
1107                         AMD_CG_SUPPORT_GFX_CP_LS |
1108                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1109                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1110                         AMD_CG_SUPPORT_GFX_CGCG |
1111                         AMD_CG_SUPPORT_GFX_CGLS |
1112                         AMD_CG_SUPPORT_BIF_MGCG |
1113                         AMD_CG_SUPPORT_BIF_LS |
1114                         AMD_CG_SUPPORT_HDP_LS |
1115                         AMD_CG_SUPPORT_DRM_MGCG |
1116                         AMD_CG_SUPPORT_DRM_LS |
1117                         AMD_CG_SUPPORT_ROM_MGCG |
1118                         AMD_CG_SUPPORT_DF_MGCG |
1119                         AMD_CG_SUPPORT_SDMA_MGCG |
1120                         AMD_CG_SUPPORT_SDMA_LS |
1121                         AMD_CG_SUPPORT_MC_MGCG |
1122                         AMD_CG_SUPPORT_MC_LS;
1123                 adev->pg_flags = 0;
1124                 adev->external_rev_id = 0x1;
1125                 break;
1126         case CHIP_VEGA12:
1127                 adev->asic_funcs = &soc15_asic_funcs;
1128                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1129                         AMD_CG_SUPPORT_GFX_MGLS |
1130                         AMD_CG_SUPPORT_GFX_CGCG |
1131                         AMD_CG_SUPPORT_GFX_CGLS |
1132                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1133                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1134                         AMD_CG_SUPPORT_GFX_CP_LS |
1135                         AMD_CG_SUPPORT_MC_LS |
1136                         AMD_CG_SUPPORT_MC_MGCG |
1137                         AMD_CG_SUPPORT_SDMA_MGCG |
1138                         AMD_CG_SUPPORT_SDMA_LS |
1139                         AMD_CG_SUPPORT_BIF_MGCG |
1140                         AMD_CG_SUPPORT_BIF_LS |
1141                         AMD_CG_SUPPORT_HDP_MGCG |
1142                         AMD_CG_SUPPORT_HDP_LS |
1143                         AMD_CG_SUPPORT_ROM_MGCG |
1144                         AMD_CG_SUPPORT_VCE_MGCG |
1145                         AMD_CG_SUPPORT_UVD_MGCG;
1146                 adev->pg_flags = 0;
1147                 adev->external_rev_id = adev->rev_id + 0x14;
1148                 break;
1149         case CHIP_VEGA20:
1150                 adev->asic_funcs = &vega20_asic_funcs;
1151                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1152                         AMD_CG_SUPPORT_GFX_MGLS |
1153                         AMD_CG_SUPPORT_GFX_CGCG |
1154                         AMD_CG_SUPPORT_GFX_CGLS |
1155                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1156                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1157                         AMD_CG_SUPPORT_GFX_CP_LS |
1158                         AMD_CG_SUPPORT_MC_LS |
1159                         AMD_CG_SUPPORT_MC_MGCG |
1160                         AMD_CG_SUPPORT_SDMA_MGCG |
1161                         AMD_CG_SUPPORT_SDMA_LS |
1162                         AMD_CG_SUPPORT_BIF_MGCG |
1163                         AMD_CG_SUPPORT_BIF_LS |
1164                         AMD_CG_SUPPORT_HDP_MGCG |
1165                         AMD_CG_SUPPORT_HDP_LS |
1166                         AMD_CG_SUPPORT_ROM_MGCG |
1167                         AMD_CG_SUPPORT_VCE_MGCG |
1168                         AMD_CG_SUPPORT_UVD_MGCG;
1169                 adev->pg_flags = 0;
1170                 adev->external_rev_id = adev->rev_id + 0x28;
1171                 break;
1172         case CHIP_RAVEN:
1173                 adev->asic_funcs = &soc15_asic_funcs;
1174                 if (adev->pdev->device == 0x15dd)
1175                         adev->apu_flags |= AMD_APU_IS_RAVEN;
1176                 if (adev->pdev->device == 0x15d8)
1177                         adev->apu_flags |= AMD_APU_IS_PICASSO;
1178                 if (adev->rev_id >= 0x8)
1179                         adev->apu_flags |= AMD_APU_IS_RAVEN2;
1180
1181                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1182                         adev->external_rev_id = adev->rev_id + 0x79;
1183                 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1184                         adev->external_rev_id = adev->rev_id + 0x41;
1185                 else if (adev->rev_id == 1)
1186                         adev->external_rev_id = adev->rev_id + 0x20;
1187                 else
1188                         adev->external_rev_id = adev->rev_id + 0x01;
1189
1190                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1191                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1192                                 AMD_CG_SUPPORT_GFX_MGLS |
1193                                 AMD_CG_SUPPORT_GFX_CP_LS |
1194                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1195                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1196                                 AMD_CG_SUPPORT_GFX_CGCG |
1197                                 AMD_CG_SUPPORT_GFX_CGLS |
1198                                 AMD_CG_SUPPORT_BIF_LS |
1199                                 AMD_CG_SUPPORT_HDP_LS |
1200                                 AMD_CG_SUPPORT_ROM_MGCG |
1201                                 AMD_CG_SUPPORT_MC_MGCG |
1202                                 AMD_CG_SUPPORT_MC_LS |
1203                                 AMD_CG_SUPPORT_SDMA_MGCG |
1204                                 AMD_CG_SUPPORT_SDMA_LS |
1205                                 AMD_CG_SUPPORT_VCN_MGCG;
1206
1207                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1208                 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1209                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1210                                 AMD_CG_SUPPORT_GFX_MGLS |
1211                                 AMD_CG_SUPPORT_GFX_CP_LS |
1212                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1213                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1214                                 AMD_CG_SUPPORT_GFX_CGCG |
1215                                 AMD_CG_SUPPORT_GFX_CGLS |
1216                                 AMD_CG_SUPPORT_BIF_LS |
1217                                 AMD_CG_SUPPORT_HDP_LS |
1218                                 AMD_CG_SUPPORT_ROM_MGCG |
1219                                 AMD_CG_SUPPORT_MC_MGCG |
1220                                 AMD_CG_SUPPORT_MC_LS |
1221                                 AMD_CG_SUPPORT_SDMA_MGCG |
1222                                 AMD_CG_SUPPORT_SDMA_LS;
1223
1224                         adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1225                                 AMD_PG_SUPPORT_MMHUB |
1226                                 AMD_PG_SUPPORT_VCN |
1227                                 AMD_PG_SUPPORT_VCN_DPG;
1228                 } else {
1229                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1230                                 AMD_CG_SUPPORT_GFX_MGLS |
1231                                 AMD_CG_SUPPORT_GFX_RLC_LS |
1232                                 AMD_CG_SUPPORT_GFX_CP_LS |
1233                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1234                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1235                                 AMD_CG_SUPPORT_GFX_CGCG |
1236                                 AMD_CG_SUPPORT_GFX_CGLS |
1237                                 AMD_CG_SUPPORT_BIF_MGCG |
1238                                 AMD_CG_SUPPORT_BIF_LS |
1239                                 AMD_CG_SUPPORT_HDP_MGCG |
1240                                 AMD_CG_SUPPORT_HDP_LS |
1241                                 AMD_CG_SUPPORT_DRM_MGCG |
1242                                 AMD_CG_SUPPORT_DRM_LS |
1243                                 AMD_CG_SUPPORT_ROM_MGCG |
1244                                 AMD_CG_SUPPORT_MC_MGCG |
1245                                 AMD_CG_SUPPORT_MC_LS |
1246                                 AMD_CG_SUPPORT_SDMA_MGCG |
1247                                 AMD_CG_SUPPORT_SDMA_LS |
1248                                 AMD_CG_SUPPORT_VCN_MGCG;
1249
1250                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1251                 }
1252                 break;
1253         case CHIP_ARCTURUS:
1254                 adev->asic_funcs = &vega20_asic_funcs;
1255                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1256                         AMD_CG_SUPPORT_GFX_MGLS |
1257                         AMD_CG_SUPPORT_GFX_CGCG |
1258                         AMD_CG_SUPPORT_GFX_CGLS |
1259                         AMD_CG_SUPPORT_GFX_CP_LS |
1260                         AMD_CG_SUPPORT_HDP_MGCG |
1261                         AMD_CG_SUPPORT_HDP_LS |
1262                         AMD_CG_SUPPORT_SDMA_MGCG |
1263                         AMD_CG_SUPPORT_SDMA_LS |
1264                         AMD_CG_SUPPORT_MC_MGCG |
1265                         AMD_CG_SUPPORT_MC_LS |
1266                         AMD_CG_SUPPORT_IH_CG |
1267                         AMD_CG_SUPPORT_VCN_MGCG |
1268                         AMD_CG_SUPPORT_JPEG_MGCG;
1269                 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1270                 adev->external_rev_id = adev->rev_id + 0x32;
1271                 break;
1272         case CHIP_RENOIR:
1273                 adev->asic_funcs = &soc15_asic_funcs;
1274                 adev->apu_flags |= AMD_APU_IS_RENOIR;
1275                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1276                                  AMD_CG_SUPPORT_GFX_MGLS |
1277                                  AMD_CG_SUPPORT_GFX_3D_CGCG |
1278                                  AMD_CG_SUPPORT_GFX_3D_CGLS |
1279                                  AMD_CG_SUPPORT_GFX_CGCG |
1280                                  AMD_CG_SUPPORT_GFX_CGLS |
1281                                  AMD_CG_SUPPORT_GFX_CP_LS |
1282                                  AMD_CG_SUPPORT_MC_MGCG |
1283                                  AMD_CG_SUPPORT_MC_LS |
1284                                  AMD_CG_SUPPORT_SDMA_MGCG |
1285                                  AMD_CG_SUPPORT_SDMA_LS |
1286                                  AMD_CG_SUPPORT_BIF_LS |
1287                                  AMD_CG_SUPPORT_HDP_LS |
1288                                  AMD_CG_SUPPORT_ROM_MGCG |
1289                                  AMD_CG_SUPPORT_VCN_MGCG |
1290                                  AMD_CG_SUPPORT_JPEG_MGCG |
1291                                  AMD_CG_SUPPORT_IH_CG |
1292                                  AMD_CG_SUPPORT_ATHUB_LS |
1293                                  AMD_CG_SUPPORT_ATHUB_MGCG |
1294                                  AMD_CG_SUPPORT_DF_MGCG;
1295                 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1296                                  AMD_PG_SUPPORT_VCN |
1297                                  AMD_PG_SUPPORT_JPEG |
1298                                  AMD_PG_SUPPORT_VCN_DPG;
1299                 adev->external_rev_id = adev->rev_id + 0x91;
1300                 break;
1301         default:
1302                 /* FIXME: not supported yet */
1303                 return -EINVAL;
1304         }
1305
1306         if (amdgpu_sriov_vf(adev)) {
1307                 amdgpu_virt_init_setting(adev);
1308                 xgpu_ai_mailbox_set_irq_funcs(adev);
1309         }
1310
1311         return 0;
1312 }
1313
1314 static int soc15_common_late_init(void *handle)
1315 {
1316         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1317         int r = 0;
1318
1319         if (amdgpu_sriov_vf(adev))
1320                 xgpu_ai_mailbox_get_irq(adev);
1321
1322         if (adev->asic_funcs &&
1323             adev->asic_funcs->reset_hdp_ras_error_count)
1324                 adev->asic_funcs->reset_hdp_ras_error_count(adev);
1325
1326         if (adev->nbio.funcs->ras_late_init)
1327                 r = adev->nbio.funcs->ras_late_init(adev);
1328
1329         return r;
1330 }
1331
1332 static int soc15_common_sw_init(void *handle)
1333 {
1334         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1335
1336         if (amdgpu_sriov_vf(adev))
1337                 xgpu_ai_mailbox_add_irq_id(adev);
1338
1339         adev->df.funcs->sw_init(adev);
1340
1341         return 0;
1342 }
1343
1344 static int soc15_common_sw_fini(void *handle)
1345 {
1346         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1347
1348         amdgpu_nbio_ras_fini(adev);
1349         adev->df.funcs->sw_fini(adev);
1350         return 0;
1351 }
1352
1353 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1354 {
1355         int i;
1356         struct amdgpu_ring *ring;
1357
1358         /* sdma/ih doorbell range are programed by hypervisor */
1359         if (!amdgpu_sriov_vf(adev)) {
1360                 for (i = 0; i < adev->sdma.num_instances; i++) {
1361                         ring = &adev->sdma.instance[i].ring;
1362                         adev->nbio.funcs->sdma_doorbell_range(adev, i,
1363                                 ring->use_doorbell, ring->doorbell_index,
1364                                 adev->doorbell_index.sdma_doorbell_range);
1365                 }
1366
1367                 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1368                                                 adev->irq.ih.doorbell_index);
1369         }
1370 }
1371
1372 static int soc15_common_hw_init(void *handle)
1373 {
1374         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1375
1376         /* enable pcie gen2/3 link */
1377         soc15_pcie_gen3_enable(adev);
1378         /* enable aspm */
1379         soc15_program_aspm(adev);
1380         /* setup nbio registers */
1381         adev->nbio.funcs->init_registers(adev);
1382         /* remap HDP registers to a hole in mmio space,
1383          * for the purpose of expose those registers
1384          * to process space
1385          */
1386         if (adev->nbio.funcs->remap_hdp_registers)
1387                 adev->nbio.funcs->remap_hdp_registers(adev);
1388
1389         /* enable the doorbell aperture */
1390         soc15_enable_doorbell_aperture(adev, true);
1391         /* HW doorbell routing policy: doorbell writing not
1392          * in SDMA/IH/MM/ACV range will be routed to CP. So
1393          * we need to init SDMA/IH/MM/ACV doorbell range prior
1394          * to CP ip block init and ring test.
1395          */
1396         soc15_doorbell_range_init(adev);
1397
1398         return 0;
1399 }
1400
1401 static int soc15_common_hw_fini(void *handle)
1402 {
1403         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1404
1405         /* disable the doorbell aperture */
1406         soc15_enable_doorbell_aperture(adev, false);
1407         if (amdgpu_sriov_vf(adev))
1408                 xgpu_ai_mailbox_put_irq(adev);
1409
1410         if (adev->nbio.ras_if &&
1411             amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1412                 if (adev->nbio.funcs->init_ras_controller_interrupt)
1413                         amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1414                 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
1415                         amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1416         }
1417
1418         return 0;
1419 }
1420
1421 static int soc15_common_suspend(void *handle)
1422 {
1423         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1424
1425         return soc15_common_hw_fini(adev);
1426 }
1427
1428 static int soc15_common_resume(void *handle)
1429 {
1430         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1431
1432         return soc15_common_hw_init(adev);
1433 }
1434
1435 static bool soc15_common_is_idle(void *handle)
1436 {
1437         return true;
1438 }
1439
1440 static int soc15_common_wait_for_idle(void *handle)
1441 {
1442         return 0;
1443 }
1444
1445 static int soc15_common_soft_reset(void *handle)
1446 {
1447         return 0;
1448 }
1449
1450 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1451 {
1452         uint32_t def, data;
1453
1454         if (adev->asic_type == CHIP_VEGA20 ||
1455                 adev->asic_type == CHIP_ARCTURUS) {
1456                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1457
1458                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1459                         data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1460                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1461                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1462                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1463                 else
1464                         data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1465                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1466                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1467                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1468
1469                 if (def != data)
1470                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1471         } else {
1472                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1473
1474                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1475                         data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1476                 else
1477                         data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1478
1479                 if (def != data)
1480                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1481         }
1482 }
1483
1484 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1485 {
1486         uint32_t def, data;
1487
1488         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1489
1490         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1491                 data &= ~(0x01000000 |
1492                           0x02000000 |
1493                           0x04000000 |
1494                           0x08000000 |
1495                           0x10000000 |
1496                           0x20000000 |
1497                           0x40000000 |
1498                           0x80000000);
1499         else
1500                 data |= (0x01000000 |
1501                          0x02000000 |
1502                          0x04000000 |
1503                          0x08000000 |
1504                          0x10000000 |
1505                          0x20000000 |
1506                          0x40000000 |
1507                          0x80000000);
1508
1509         if (def != data)
1510                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1511 }
1512
1513 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1514 {
1515         uint32_t def, data;
1516
1517         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1518
1519         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1520                 data |= 1;
1521         else
1522                 data &= ~1;
1523
1524         if (def != data)
1525                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1526 }
1527
1528 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1529                                                        bool enable)
1530 {
1531         uint32_t def, data;
1532
1533         def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1534
1535         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1536                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1537                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1538         else
1539                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1540                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1541
1542         if (def != data)
1543                 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1544 }
1545
1546 static int soc15_common_set_clockgating_state(void *handle,
1547                                             enum amd_clockgating_state state)
1548 {
1549         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1550
1551         if (amdgpu_sriov_vf(adev))
1552                 return 0;
1553
1554         switch (adev->asic_type) {
1555         case CHIP_VEGA10:
1556         case CHIP_VEGA12:
1557         case CHIP_VEGA20:
1558                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1559                                 state == AMD_CG_STATE_GATE);
1560                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1561                                 state == AMD_CG_STATE_GATE);
1562                 soc15_update_hdp_light_sleep(adev,
1563                                 state == AMD_CG_STATE_GATE);
1564                 soc15_update_drm_clock_gating(adev,
1565                                 state == AMD_CG_STATE_GATE);
1566                 soc15_update_drm_light_sleep(adev,
1567                                 state == AMD_CG_STATE_GATE);
1568                 soc15_update_rom_medium_grain_clock_gating(adev,
1569                                 state == AMD_CG_STATE_GATE);
1570                 adev->df.funcs->update_medium_grain_clock_gating(adev,
1571                                 state == AMD_CG_STATE_GATE);
1572                 break;
1573         case CHIP_RAVEN:
1574         case CHIP_RENOIR:
1575                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1576                                 state == AMD_CG_STATE_GATE);
1577                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1578                                 state == AMD_CG_STATE_GATE);
1579                 soc15_update_hdp_light_sleep(adev,
1580                                 state == AMD_CG_STATE_GATE);
1581                 soc15_update_drm_clock_gating(adev,
1582                                 state == AMD_CG_STATE_GATE);
1583                 soc15_update_drm_light_sleep(adev,
1584                                 state == AMD_CG_STATE_GATE);
1585                 soc15_update_rom_medium_grain_clock_gating(adev,
1586                                 state == AMD_CG_STATE_GATE);
1587                 break;
1588         case CHIP_ARCTURUS:
1589                 soc15_update_hdp_light_sleep(adev,
1590                                 state == AMD_CG_STATE_GATE);
1591                 break;
1592         default:
1593                 break;
1594         }
1595         return 0;
1596 }
1597
1598 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1599 {
1600         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1601         int data;
1602
1603         if (amdgpu_sriov_vf(adev))
1604                 *flags = 0;
1605
1606         adev->nbio.funcs->get_clockgating_state(adev, flags);
1607
1608         /* AMD_CG_SUPPORT_HDP_LS */
1609         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1610         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1611                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1612
1613         /* AMD_CG_SUPPORT_DRM_MGCG */
1614         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1615         if (!(data & 0x01000000))
1616                 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1617
1618         /* AMD_CG_SUPPORT_DRM_LS */
1619         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1620         if (data & 0x1)
1621                 *flags |= AMD_CG_SUPPORT_DRM_LS;
1622
1623         /* AMD_CG_SUPPORT_ROM_MGCG */
1624         data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1625         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1626                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1627
1628         adev->df.funcs->get_clockgating_state(adev, flags);
1629 }
1630
1631 static int soc15_common_set_powergating_state(void *handle,
1632                                             enum amd_powergating_state state)
1633 {
1634         /* todo */
1635         return 0;
1636 }
1637
1638 const struct amd_ip_funcs soc15_common_ip_funcs = {
1639         .name = "soc15_common",
1640         .early_init = soc15_common_early_init,
1641         .late_init = soc15_common_late_init,
1642         .sw_init = soc15_common_sw_init,
1643         .sw_fini = soc15_common_sw_fini,
1644         .hw_init = soc15_common_hw_init,
1645         .hw_fini = soc15_common_hw_fini,
1646         .suspend = soc15_common_suspend,
1647         .resume = soc15_common_resume,
1648         .is_idle = soc15_common_is_idle,
1649         .wait_for_idle = soc15_common_wait_for_idle,
1650         .soft_reset = soc15_common_soft_reset,
1651         .set_clockgating_state = soc15_common_set_clockgating_state,
1652         .set_powergating_state = soc15_common_set_powergating_state,
1653         .get_clockgating_state= soc15_common_get_clockgating_state,
1654 };