drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "amdgpu_smu.h"
  36 #include "atom.h"
  37 #include "amd_pcie.h"
  38
  39 #include "gc/gc_10_1_0_offset.h"
  40 #include "gc/gc_10_1_0_sh_mask.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "hdp/hdp_5_0_0_sh_mask.h"
  43 #include "smuio/smuio_11_0_0_offset.h"
  44 #include "mp/mp_11_0_offset.h"
  45
  46 #include "soc15.h"
  47 #include "soc15_common.h"
  48 #include "gmc_v10_0.h"
  49 #include "gfxhub_v2_0.h"
  50 #include "mmhub_v2_0.h"
  51 #include "nbio_v2_3.h"
  52 #include "nv.h"
  53 #include "navi10_ih.h"
  54 #include "gfx_v10_0.h"
  55 #include "sdma_v5_0.h"
  56 #include "sdma_v5_2.h"
  57 #include "vcn_v2_0.h"
  58 #include "jpeg_v2_0.h"
  59 #include "vcn_v3_0.h"
  60 #include "jpeg_v3_0.h"
  61 #include "dce_virtual.h"
  62 #include "mes_v10_1.h"
  63 #include "mxgpu_nv.h"
  64
  65 static const struct amd_ip_funcs nv_common_ip_funcs;
  66
  67 /*
  68  * Indirect registers accessor
  69  */
  70 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  71 {
  72         unsigned long flags, address, data;
  73         u32 r;
  74         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  75         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  76
  77         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  78         WREG32(address, reg);
  79         (void)RREG32(address);
  80         r = RREG32(data);
  81         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  82         return r;
  83 }
  84
  85 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  86 {
  87         unsigned long flags, address, data;
  88
  89         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  90         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  91
  92         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  93         WREG32(address, reg);
  94         (void)RREG32(address);
  95         WREG32(data, v);
  96         (void)RREG32(data);
  97         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  98 }
  99
 100 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 101 {
 102         unsigned long flags, address, data;
 103         u64 r;
 104         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 105         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 106
 107         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 108         /* read low 32 bit */
 109         WREG32(address, reg);
 110         (void)RREG32(address);
 111         r = RREG32(data);
 112
 113         /* read high 32 bit*/
 114         WREG32(address, reg + 4);
 115         (void)RREG32(address);
 116         r |= ((u64)RREG32(data) << 32);
 117         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 118         return r;
 119 }
 120
 121 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 122 {
 123         unsigned long flags, address, data;
 124
 125         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 126         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 127
 128         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 129         /* write low 32 bit */
 130         WREG32(address, reg);
 131         (void)RREG32(address);
 132         WREG32(data, (u32)(v & 0xffffffffULL));
 133         (void)RREG32(data);
 134
 135         /* write high 32 bit */
 136         WREG32(address, reg + 4);
 137         (void)RREG32(address);
 138         WREG32(data, (u32)(v >> 32));
 139         (void)RREG32(data);
 140         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 141 }
 142
 143 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 144 {
 145         unsigned long flags, address, data;
 146         u32 r;
 147
 148         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 149         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 150
 151         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 152         WREG32(address, (reg));
 153         r = RREG32(data);
 154         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 155         return r;
 156 }
 157
 158 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 159 {
 160         unsigned long flags, address, data;
 161
 162         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 163         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 164
 165         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 166         WREG32(address, (reg));
 167         WREG32(data, (v));
 168         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 169 }
 170
 171 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 172 {
 173         return adev->nbio.funcs->get_memsize(adev);
 174 }
 175
 176 static u32 nv_get_xclk(struct amdgpu_device *adev)
 177 {
 178         return adev->clock.spll.reference_freq;
 179 }
 180
 181
 182 void nv_grbm_select(struct amdgpu_device *adev,
 183                      u32 me, u32 pipe, u32 queue, u32 vmid)
 184 {
 185         u32 grbm_gfx_cntl = 0;
 186         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 187         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 188         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 189         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 190
 191         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 192 }
 193
 194 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 195 {
 196         /* todo */
 197 }
 198
 199 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 200 {
 201         /* todo */
 202         return false;
 203 }
 204
 205 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
 206                                   u8 *bios, u32 length_bytes)
 207 {
 208         u32 *dw_ptr;
 209         u32 i, length_dw;
 210
 211         if (bios == NULL)
 212                 return false;
 213         if (length_bytes == 0)
 214                 return false;
 215         /* APU vbios image is part of sbios image */
 216         if (adev->flags & AMD_IS_APU)
 217                 return false;
 218
 219         dw_ptr = (u32 *)bios;
 220         length_dw = ALIGN(length_bytes, 4) / 4;
 221
 222         /* set rom index to 0 */
 223         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 224         /* read out the rom data */
 225         for (i = 0; i < length_dw; i++)
 226                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 227
 228         return true;
 229 }
 230
 231 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 232         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 233         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 234         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 235         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 236         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 237         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 238         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 239         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 240         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 241         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 242         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 243         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 244         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 245         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 246         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 247         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 248         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 249         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 250         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 251 };
 252
 253 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 254                                          u32 sh_num, u32 reg_offset)
 255 {
 256         uint32_t val;
 257
 258         mutex_lock(&adev->grbm_idx_mutex);
 259         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 260                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 261
 262         val = RREG32(reg_offset);
 263
 264         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 265                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 266         mutex_unlock(&adev->grbm_idx_mutex);
 267         return val;
 268 }
 269
 270 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 271                                       bool indexed, u32 se_num,
 272                                       u32 sh_num, u32 reg_offset)
 273 {
 274         if (indexed) {
 275                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 276         } else {
 277                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 278                         return adev->gfx.config.gb_addr_config;
 279                 return RREG32(reg_offset);
 280         }
 281 }
 282
 283 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 284                             u32 sh_num, u32 reg_offset, u32 *value)
 285 {
 286         uint32_t i;
 287         struct soc15_allowed_register_entry  *en;
 288
 289         *value = 0;
 290         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 291                 en = &nv_allowed_read_registers[i];
 292                 if (reg_offset !=
 293                     (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 294                         continue;
 295
 296                 *value = nv_get_register_value(adev,
 297                                                nv_allowed_read_registers[i].grbm_indexed,
 298                                                se_num, sh_num, reg_offset);
 299                 return 0;
 300         }
 301         return -EINVAL;
 302 }
 303
 304 static int nv_asic_mode1_reset(struct amdgpu_device *adev)
 305 {
 306         u32 i;
 307         int ret = 0;
 308
 309         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 310
 311         /* disable BM */
 312         pci_clear_master(adev->pdev);
 313
 314         pci_save_state(adev->pdev);
 315
 316         if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
 317                 dev_info(adev->dev, "GPU smu mode1 reset\n");
 318                 ret = amdgpu_dpm_mode1_reset(adev);
 319         } else {
 320                 dev_info(adev->dev, "GPU psp mode1 reset\n");
 321                 ret = psp_gpu_reset(adev);
 322         }
 323
 324         if (ret)
 325                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 326         pci_restore_state(adev->pdev);
 327
 328         /* wait for asic to come out of reset */
 329         for (i = 0; i < adev->usec_timeout; i++) {
 330                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 331
 332                 if (memsize != 0xffffffff)
 333                         break;
 334                 udelay(1);
 335         }
 336
 337         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 338
 339         return ret;
 340 }
 341
 342 static bool nv_asic_supports_baco(struct amdgpu_device *adev)
 343 {
 344         struct smu_context *smu = &adev->smu;
 345
 346         if (smu_baco_is_support(smu))
 347                 return true;
 348         else
 349                 return false;
 350 }
 351
 352 static enum amd_reset_method
 353 nv_asic_reset_method(struct amdgpu_device *adev)
 354 {
 355         struct smu_context *smu = &adev->smu;
 356
 357         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 358             amdgpu_reset_method == AMD_RESET_METHOD_BACO)
 359                 return amdgpu_reset_method;
 360
 361         if (amdgpu_reset_method != -1)
 362                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 363                                   amdgpu_reset_method);
 364
 365         switch (adev->asic_type) {
 366         case CHIP_SIENNA_CICHLID:
 367                 return AMD_RESET_METHOD_MODE1;
 368         default:
 369                 if (smu_baco_is_support(smu))
 370                         return AMD_RESET_METHOD_BACO;
 371                 else
 372                         return AMD_RESET_METHOD_MODE1;
 373         }
 374 }
 375
 376 static int nv_asic_reset(struct amdgpu_device *adev)
 377 {
 378         int ret = 0;
 379         struct smu_context *smu = &adev->smu;
 380
 381         if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
 382                 dev_info(adev->dev, "BACO reset\n");
 383
 384                 ret = smu_baco_enter(smu);
 385                 if (ret)
 386                         return ret;
 387                 ret = smu_baco_exit(smu);
 388                 if (ret)
 389                         return ret;
 390         } else {
 391                 dev_info(adev->dev, "MODE1 reset\n");
 392                 ret = nv_asic_mode1_reset(adev);
 393         }
 394
 395         return ret;
 396 }
 397
 398 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 399 {
 400         /* todo */
 401         return 0;
 402 }
 403
 404 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 405 {
 406         /* todo */
 407         return 0;
 408 }
 409
 410 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 411 {
 412         if (pci_is_root_bus(adev->pdev->bus))
 413                 return;
 414
 415         if (amdgpu_pcie_gen2 == 0)
 416                 return;
 417
 418         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 419                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 420                 return;
 421
 422         /* todo */
 423 }
 424
 425 static void nv_program_aspm(struct amdgpu_device *adev)
 426 {
 427
 428         if (amdgpu_aspm == 0)
 429                 return;
 430
 431         /* todo */
 432 }
 433
 434 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 435                                         bool enable)
 436 {
 437         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 438         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 439 }
 440
 441 static const struct amdgpu_ip_block_version nv_common_ip_block =
 442 {
 443         .type = AMD_IP_BLOCK_TYPE_COMMON,
 444         .major = 1,
 445         .minor = 0,
 446         .rev = 0,
 447         .funcs = &nv_common_ip_funcs,
 448 };
 449
 450 static int nv_reg_base_init(struct amdgpu_device *adev)
 451 {
 452         int r;
 453
 454         if (amdgpu_discovery) {
 455                 r = amdgpu_discovery_reg_base_init(adev);
 456                 if (r) {
 457                         DRM_WARN("failed to init reg base from ip discovery table, "
 458                                         "fallback to legacy init method\n");
 459                         goto legacy_init;
 460                 }
 461
 462                 return 0;
 463         }
 464
 465 legacy_init:
 466         switch (adev->asic_type) {
 467         case CHIP_NAVI10:
 468                 navi10_reg_base_init(adev);
 469                 break;
 470         case CHIP_NAVI14:
 471                 navi14_reg_base_init(adev);
 472                 break;
 473         case CHIP_NAVI12:
 474                 navi12_reg_base_init(adev);
 475                 break;
 476         case CHIP_SIENNA_CICHLID:
 477         case CHIP_NAVY_FLOUNDER:
 478                 sienna_cichlid_reg_base_init(adev);
 479                 break;
 480         default:
 481                 return -EINVAL;
 482         }
 483
 484         return 0;
 485 }
 486
 487 void nv_set_virt_ops(struct amdgpu_device *adev)
 488 {
 489         adev->virt.ops = &xgpu_nv_virt_ops;
 490 }
 491
 492 int nv_set_ip_blocks(struct amdgpu_device *adev)
 493 {
 494         int r;
 495
 496         adev->nbio.funcs = &nbio_v2_3_funcs;
 497         adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
 498
 499         if (adev->asic_type == CHIP_SIENNA_CICHLID)
 500                 adev->gmc.xgmi.supported = true;
 501
 502         /* Set IP register base before any HW register access */
 503         r = nv_reg_base_init(adev);
 504         if (r)
 505                 return r;
 506
 507         switch (adev->asic_type) {
 508         case CHIP_NAVI10:
 509         case CHIP_NAVI14:
 510                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 511                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 512                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 513                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 514                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 515                     !amdgpu_sriov_vf(adev))
 516                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 517                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 518                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 519 #if defined(CONFIG_DRM_AMD_DC)
 520                 else if (amdgpu_device_has_dc_support(adev))
 521                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 522 #endif
 523                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 524                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 525                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 526                     !amdgpu_sriov_vf(adev))
 527                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 528                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 529                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 530                 if (adev->enable_mes)
 531                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 532                 break;
 533         case CHIP_NAVI12:
 534                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 535                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 536                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 537                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 538                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 539                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 540                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 541                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 542 #if defined(CONFIG_DRM_AMD_DC)
 543                 else if (amdgpu_device_has_dc_support(adev))
 544                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 545 #endif
 546                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 547                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 548                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 549                     !amdgpu_sriov_vf(adev))
 550                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 551                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 552                 if (!amdgpu_sriov_vf(adev))
 553                         amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 554                 break;
 555         case CHIP_SIENNA_CICHLID:
 556                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 557                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 558                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 559                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 560                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 561                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 562                     is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
 563                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 564                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 565                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 566 #if defined(CONFIG_DRM_AMD_DC)
 567                 else if (amdgpu_device_has_dc_support(adev))
 568                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 569 #endif
 570                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 571                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 572                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 573                 if (!amdgpu_sriov_vf(adev))
 574                         amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 575
 576                 if (adev->enable_mes)
 577                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 578                 break;
 579         case CHIP_NAVY_FLOUNDER:
 580                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 581                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 582                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 583                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 584                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 585                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 586                     is_support_sw_smu(adev))
 587                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 588                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 589                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 590 #if defined(CONFIG_DRM_AMD_DC)
 591                 else if (amdgpu_device_has_dc_support(adev))
 592                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 593 #endif
 594                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 595                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 596                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 597                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 598                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 599                     is_support_sw_smu(adev))
 600                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 601                 break;
 602         default:
 603                 return -EINVAL;
 604         }
 605
 606         return 0;
 607 }
 608
 609 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
 610 {
 611         return adev->nbio.funcs->get_rev_id(adev);
 612 }
 613
 614 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 615 {
 616         adev->nbio.funcs->hdp_flush(adev, ring);
 617 }
 618
 619 static void nv_invalidate_hdp(struct amdgpu_device *adev,
 620                                 struct amdgpu_ring *ring)
 621 {
 622         if (!ring || !ring->funcs->emit_wreg) {
 623                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 624         } else {
 625                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 626                                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 627         }
 628 }
 629
 630 static bool nv_need_full_reset(struct amdgpu_device *adev)
 631 {
 632         return true;
 633 }
 634
 635 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 636 {
 637         u32 sol_reg;
 638
 639         if (adev->flags & AMD_IS_APU)
 640                 return false;
 641
 642         /* Check sOS sign of life register to confirm sys driver and sOS
 643          * are already been loaded.
 644          */
 645         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 646         if (sol_reg)
 647                 return true;
 648
 649         return false;
 650 }
 651
 652 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
 653 {
 654
 655         /* TODO
 656          * dummy implement for pcie_replay_count sysfs interface
 657          * */
 658
 659         return 0;
 660 }
 661
 662 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 663 {
 664         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 665         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 666         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 667         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 668         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 669         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 670         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 671         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 672         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 673         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 674         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 675         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 676         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 677         adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
 678         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 679         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 680         adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
 681         adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
 682         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 683         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 684         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 685         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 686         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 687         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 688         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 689
 690         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 691         adev->doorbell_index.sdma_doorbell_range = 20;
 692 }
 693
 694 static const struct amdgpu_asic_funcs nv_asic_funcs =
 695 {
 696         .read_disabled_bios = &nv_read_disabled_bios,
 697         .read_bios_from_rom = &nv_read_bios_from_rom,
 698         .read_register = &nv_read_register,
 699         .reset = &nv_asic_reset,
 700         .reset_method = &nv_asic_reset_method,
 701         .set_vga_state = &nv_vga_set_state,
 702         .get_xclk = &nv_get_xclk,
 703         .set_uvd_clocks = &nv_set_uvd_clocks,
 704         .set_vce_clocks = &nv_set_vce_clocks,
 705         .get_config_memsize = &nv_get_config_memsize,
 706         .flush_hdp = &nv_flush_hdp,
 707         .invalidate_hdp = &nv_invalidate_hdp,
 708         .init_doorbell_index = &nv_init_doorbell_index,
 709         .need_full_reset = &nv_need_full_reset,
 710         .need_reset_on_init = &nv_need_reset_on_init,
 711         .get_pcie_replay_count = &nv_get_pcie_replay_count,
 712         .supports_baco = &nv_asic_supports_baco,
 713 };
 714
 715 static int nv_common_early_init(void *handle)
 716 {
 717 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 718         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 719
 720         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 721         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 722         adev->smc_rreg = NULL;
 723         adev->smc_wreg = NULL;
 724         adev->pcie_rreg = &nv_pcie_rreg;
 725         adev->pcie_wreg = &nv_pcie_wreg;
 726         adev->pcie_rreg64 = &nv_pcie_rreg64;
 727         adev->pcie_wreg64 = &nv_pcie_wreg64;
 728
 729         /* TODO: will add them during VCN v2 implementation */
 730         adev->uvd_ctx_rreg = NULL;
 731         adev->uvd_ctx_wreg = NULL;
 732
 733         adev->didt_rreg = &nv_didt_rreg;
 734         adev->didt_wreg = &nv_didt_wreg;
 735
 736         adev->asic_funcs = &nv_asic_funcs;
 737
 738         adev->rev_id = nv_get_rev_id(adev);
 739         adev->external_rev_id = 0xff;
 740         switch (adev->asic_type) {
 741         case CHIP_NAVI10:
 742                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 743                         AMD_CG_SUPPORT_GFX_CGCG |
 744                         AMD_CG_SUPPORT_IH_CG |
 745                         AMD_CG_SUPPORT_HDP_MGCG |
 746                         AMD_CG_SUPPORT_HDP_LS |
 747                         AMD_CG_SUPPORT_SDMA_MGCG |
 748                         AMD_CG_SUPPORT_SDMA_LS |
 749                         AMD_CG_SUPPORT_MC_MGCG |
 750                         AMD_CG_SUPPORT_MC_LS |
 751                         AMD_CG_SUPPORT_ATHUB_MGCG |
 752                         AMD_CG_SUPPORT_ATHUB_LS |
 753                         AMD_CG_SUPPORT_VCN_MGCG |
 754                         AMD_CG_SUPPORT_JPEG_MGCG |
 755                         AMD_CG_SUPPORT_BIF_MGCG |
 756                         AMD_CG_SUPPORT_BIF_LS;
 757                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 758                         AMD_PG_SUPPORT_VCN_DPG |
 759                         AMD_PG_SUPPORT_JPEG |
 760                         AMD_PG_SUPPORT_ATHUB;
 761                 adev->external_rev_id = adev->rev_id + 0x1;
 762                 break;
 763         case CHIP_NAVI14:
 764                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 765                         AMD_CG_SUPPORT_GFX_CGCG |
 766                         AMD_CG_SUPPORT_IH_CG |
 767                         AMD_CG_SUPPORT_HDP_MGCG |
 768                         AMD_CG_SUPPORT_HDP_LS |
 769                         AMD_CG_SUPPORT_SDMA_MGCG |
 770                         AMD_CG_SUPPORT_SDMA_LS |
 771                         AMD_CG_SUPPORT_MC_MGCG |
 772                         AMD_CG_SUPPORT_MC_LS |
 773                         AMD_CG_SUPPORT_ATHUB_MGCG |
 774                         AMD_CG_SUPPORT_ATHUB_LS |
 775                         AMD_CG_SUPPORT_VCN_MGCG |
 776                         AMD_CG_SUPPORT_JPEG_MGCG |
 777                         AMD_CG_SUPPORT_BIF_MGCG |
 778                         AMD_CG_SUPPORT_BIF_LS;
 779                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 780                         AMD_PG_SUPPORT_JPEG |
 781                         AMD_PG_SUPPORT_VCN_DPG;
 782                 adev->external_rev_id = adev->rev_id + 20;
 783                 break;
 784         case CHIP_NAVI12:
 785                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 786                         AMD_CG_SUPPORT_GFX_MGLS |
 787                         AMD_CG_SUPPORT_GFX_CGCG |
 788                         AMD_CG_SUPPORT_GFX_CP_LS |
 789                         AMD_CG_SUPPORT_GFX_RLC_LS |
 790                         AMD_CG_SUPPORT_IH_CG |
 791                         AMD_CG_SUPPORT_HDP_MGCG |
 792                         AMD_CG_SUPPORT_HDP_LS |
 793                         AMD_CG_SUPPORT_SDMA_MGCG |
 794                         AMD_CG_SUPPORT_SDMA_LS |
 795                         AMD_CG_SUPPORT_MC_MGCG |
 796                         AMD_CG_SUPPORT_MC_LS |
 797                         AMD_CG_SUPPORT_ATHUB_MGCG |
 798                         AMD_CG_SUPPORT_ATHUB_LS |
 799                         AMD_CG_SUPPORT_VCN_MGCG |
 800                         AMD_CG_SUPPORT_JPEG_MGCG;
 801                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 802                         AMD_PG_SUPPORT_VCN_DPG |
 803                         AMD_PG_SUPPORT_JPEG |
 804                         AMD_PG_SUPPORT_ATHUB;
 805                 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
 806                  * as a consequence, the rev_id and external_rev_id are wrong.
 807                  * workaround it by hardcoding rev_id to 0 (default value).
 808                  */
 809                 if (amdgpu_sriov_vf(adev))
 810                         adev->rev_id = 0;
 811                 adev->external_rev_id = adev->rev_id + 0xa;
 812                 break;
 813         case CHIP_SIENNA_CICHLID:
 814                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 815                         AMD_CG_SUPPORT_GFX_CGCG |
 816                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 817                         AMD_CG_SUPPORT_MC_MGCG |
 818                         AMD_CG_SUPPORT_VCN_MGCG |
 819                         AMD_CG_SUPPORT_JPEG_MGCG |
 820                         AMD_CG_SUPPORT_HDP_MGCG |
 821                         AMD_CG_SUPPORT_HDP_LS |
 822                         AMD_CG_SUPPORT_IH_CG |
 823                         AMD_CG_SUPPORT_MC_LS;
 824                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 825                         AMD_PG_SUPPORT_VCN_DPG |
 826                         AMD_PG_SUPPORT_JPEG |
 827                         AMD_PG_SUPPORT_ATHUB |
 828                         AMD_PG_SUPPORT_MMHUB;
 829                 if (amdgpu_sriov_vf(adev)) {
 830                         /* hypervisor control CG and PG enablement */
 831                         adev->cg_flags = 0;
 832                         adev->pg_flags = 0;
 833                 }
 834                 adev->external_rev_id = adev->rev_id + 0x28;
 835                 break;
 836         case CHIP_NAVY_FLOUNDER:
 837                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 838                         AMD_CG_SUPPORT_GFX_CGCG |
 839                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 840                         AMD_CG_SUPPORT_VCN_MGCG |
 841                         AMD_CG_SUPPORT_JPEG_MGCG |
 842                         AMD_CG_SUPPORT_MC_MGCG |
 843                         AMD_CG_SUPPORT_MC_LS |
 844                         AMD_CG_SUPPORT_HDP_MGCG |
 845                         AMD_CG_SUPPORT_HDP_LS |
 846                         AMD_CG_SUPPORT_IH_CG;
 847                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 848                         AMD_PG_SUPPORT_VCN_DPG |
 849                         AMD_PG_SUPPORT_JPEG |
 850                         AMD_PG_SUPPORT_ATHUB |
 851                         AMD_PG_SUPPORT_MMHUB;
 852                 adev->external_rev_id = adev->rev_id + 0x32;
 853                 break;
 854
 855         default:
 856                 /* FIXME: not supported yet */
 857                 return -EINVAL;
 858         }
 859
 860         if (amdgpu_sriov_vf(adev)) {
 861                 amdgpu_virt_init_setting(adev);
 862                 xgpu_nv_mailbox_set_irq_funcs(adev);
 863         }
 864
 865         return 0;
 866 }
 867
 868 static int nv_common_late_init(void *handle)
 869 {
 870         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 871
 872         if (amdgpu_sriov_vf(adev))
 873                 xgpu_nv_mailbox_get_irq(adev);
 874
 875         return 0;
 876 }
 877
 878 static int nv_common_sw_init(void *handle)
 879 {
 880         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 881
 882         if (amdgpu_sriov_vf(adev))
 883                 xgpu_nv_mailbox_add_irq_id(adev);
 884
 885         return 0;
 886 }
 887
 888 static int nv_common_sw_fini(void *handle)
 889 {
 890         return 0;
 891 }
 892
 893 static int nv_common_hw_init(void *handle)
 894 {
 895         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 896
 897         /* enable pcie gen2/3 link */
 898         nv_pcie_gen3_enable(adev);
 899         /* enable aspm */
 900         nv_program_aspm(adev);
 901         /* setup nbio registers */
 902         adev->nbio.funcs->init_registers(adev);
 903         /* remap HDP registers to a hole in mmio space,
 904          * for the purpose of expose those registers
 905          * to process space
 906          */
 907         if (adev->nbio.funcs->remap_hdp_registers)
 908                 adev->nbio.funcs->remap_hdp_registers(adev);
 909         /* enable the doorbell aperture */
 910         nv_enable_doorbell_aperture(adev, true);
 911
 912         return 0;
 913 }
 914
 915 static int nv_common_hw_fini(void *handle)
 916 {
 917         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 918
 919         /* disable the doorbell aperture */
 920         nv_enable_doorbell_aperture(adev, false);
 921
 922         return 0;
 923 }
 924
 925 static int nv_common_suspend(void *handle)
 926 {
 927         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 928
 929         return nv_common_hw_fini(adev);
 930 }
 931
 932 static int nv_common_resume(void *handle)
 933 {
 934         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 935
 936         return nv_common_hw_init(adev);
 937 }
 938
 939 static bool nv_common_is_idle(void *handle)
 940 {
 941         return true;
 942 }
 943
 944 static int nv_common_wait_for_idle(void *handle)
 945 {
 946         return 0;
 947 }
 948
 949 static int nv_common_soft_reset(void *handle)
 950 {
 951         return 0;
 952 }
 953
 954 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev,
 955                                            bool enable)
 956 {
 957         uint32_t hdp_clk_cntl, hdp_clk_cntl1;
 958         uint32_t hdp_mem_pwr_cntl;
 959
 960         if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
 961                                 AMD_CG_SUPPORT_HDP_DS |
 962                                 AMD_CG_SUPPORT_HDP_SD)))
 963                 return;
 964
 965         hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
 966         hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
 967
 968         /* Before doing clock/power mode switch,
 969          * forced on IPH & RC clock */
 970         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 971                                      IPH_MEM_CLK_SOFT_OVERRIDE, 1);
 972         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 973                                      RC_MEM_CLK_SOFT_OVERRIDE, 1);
 974         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
 975
 976         /* HDP 5.0 doesn't support dynamic power mode switch,
 977          * disable clock and power gating before any changing */
 978         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 979                                          IPH_MEM_POWER_CTRL_EN, 0);
 980         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 981                                          IPH_MEM_POWER_LS_EN, 0);
 982         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 983                                          IPH_MEM_POWER_DS_EN, 0);
 984         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 985                                          IPH_MEM_POWER_SD_EN, 0);
 986         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 987                                          RC_MEM_POWER_CTRL_EN, 0);
 988         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 989                                          RC_MEM_POWER_LS_EN, 0);
 990         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 991                                          RC_MEM_POWER_DS_EN, 0);
 992         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 993                                          RC_MEM_POWER_SD_EN, 0);
 994         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
 995
 996         /* only one clock gating mode (LS/DS/SD) can be enabled */
 997         if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
 998                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 999                                                  HDP_MEM_POWER_CTRL,
1000                                                  IPH_MEM_POWER_LS_EN, enable);
1001                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
1002                                                  HDP_MEM_POWER_CTRL,
1003                                                  RC_MEM_POWER_LS_EN, enable);
1004         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
1005                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
1006                                                  HDP_MEM_POWER_CTRL,
1007                                                  IPH_MEM_POWER_DS_EN, enable);
1008                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
1009                                                  HDP_MEM_POWER_CTRL,
1010                                                  RC_MEM_POWER_DS_EN, enable);
1011         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
1012                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
1013                                                  HDP_MEM_POWER_CTRL,
1014                                                  IPH_MEM_POWER_SD_EN, enable);
1015                 /* RC should not use shut down mode, fallback to ds */
1016                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
1017                                                  HDP_MEM_POWER_CTRL,
1018                                                  RC_MEM_POWER_DS_EN, enable);
1019         }
1020
1021         /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
1022          * be set for SRAM LS/DS/SD */
1023         if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
1024                                                         AMD_CG_SUPPORT_HDP_SD)) {
1025                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
1026                                                 IPH_MEM_POWER_CTRL_EN, 1);
1027                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
1028                                                 RC_MEM_POWER_CTRL_EN, 1);
1029         }
1030
1031         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
1032
1033         /* restore IPH & RC clock override after clock/power mode changing */
1034         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1);
1035 }
1036
1037 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev,
1038                                        bool enable)
1039 {
1040         uint32_t hdp_clk_cntl;
1041
1042         if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1043                 return;
1044
1045         hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
1046
1047         if (enable) {
1048                 hdp_clk_cntl &=
1049                         ~(uint32_t)
1050                           (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
1051                            HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
1052                            HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
1053                            HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
1054                            HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
1055                            HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
1056         } else {
1057                 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
1058                         HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
1059                         HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
1060                         HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
1061                         HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
1062                         HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
1063         }
1064
1065         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
1066 }
1067
1068 static int nv_common_set_clockgating_state(void *handle,
1069                                            enum amd_clockgating_state state)
1070 {
1071         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1072
1073         if (amdgpu_sriov_vf(adev))
1074                 return 0;
1075
1076         switch (adev->asic_type) {
1077         case CHIP_NAVI10:
1078         case CHIP_NAVI14:
1079         case CHIP_NAVI12:
1080         case CHIP_SIENNA_CICHLID:
1081         case CHIP_NAVY_FLOUNDER:
1082                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1083                                 state == AMD_CG_STATE_GATE);
1084                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1085                                 state == AMD_CG_STATE_GATE);
1086                 nv_update_hdp_mem_power_gating(adev,
1087                                    state == AMD_CG_STATE_GATE);
1088                 nv_update_hdp_clock_gating(adev,
1089                                 state == AMD_CG_STATE_GATE);
1090                 break;
1091         default:
1092                 break;
1093         }
1094         return 0;
1095 }
1096
1097 static int nv_common_set_powergating_state(void *handle,
1098                                            enum amd_powergating_state state)
1099 {
1100         /* TODO */
1101         return 0;
1102 }
1103
1104 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
1105 {
1106         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1107         uint32_t tmp;
1108
1109         if (amdgpu_sriov_vf(adev))
1110                 *flags = 0;
1111
1112         adev->nbio.funcs->get_clockgating_state(adev, flags);
1113
1114         /* AMD_CG_SUPPORT_HDP_MGCG */
1115         tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
1116         if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
1117                      HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
1118                      HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
1119                      HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
1120                      HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
1121                      HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
1122                 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
1123
1124         /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
1125         tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
1126         if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK)
1127                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1128         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK)
1129                 *flags |= AMD_CG_SUPPORT_HDP_DS;
1130         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK)
1131                 *flags |= AMD_CG_SUPPORT_HDP_SD;
1132
1133         return;
1134 }
1135
1136 static const struct amd_ip_funcs nv_common_ip_funcs = {
1137         .name = "nv_common",
1138         .early_init = nv_common_early_init,
1139         .late_init = nv_common_late_init,
1140         .sw_init = nv_common_sw_init,
1141         .sw_fini = nv_common_sw_fini,
1142         .hw_init = nv_common_hw_init,
1143         .hw_fini = nv_common_hw_fini,
1144         .suspend = nv_common_suspend,
1145         .resume = nv_common_resume,
1146         .is_idle = nv_common_is_idle,
1147         .wait_for_idle = nv_common_wait_for_idle,
1148         .soft_reset = nv_common_soft_reset,
1149         .set_clockgating_state = nv_common_set_clockgating_state,
1150         .set_powergating_state = nv_common_set_powergating_state,
1151         .get_clockgating_state = nv_common_get_clockgating_state,
1152 };