drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "gfxhub_v2_0.h"
  26
  27 #include "gc/gc_10_1_0_offset.h"
  28 #include "gc/gc_10_1_0_sh_mask.h"
  29 #include "gc/gc_10_1_0_default.h"
  30 #include "navi10_enum.h"
  31
  32 #include "soc15_common.h"
  33
  34 static uint32_t gfxhub_v2_0_get_invalidate_req(unsigned int vmid,
  35                                                uint32_t flush_type)
  36 {
  37         u32 req = 0;
  38
  39         /* invalidate using legacy mode on vmid*/
  40         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
  41                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
  42         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
  43         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
  44         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
  45         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
  46         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
  47         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
  48         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
  49                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
  50
  51         return req;
  52 }
  53
  54 static void
  55 gfxhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
  56                                              uint32_t status)
  57 {
  58         dev_err(adev->dev,
  59                 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
  60                 status);
  61         dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
  62                 REG_GET_FIELD(status,
  63                 GCVM_L2_PROTECTION_FAULT_STATUS, CID));
  64         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
  65                 REG_GET_FIELD(status,
  66                 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
  67         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
  68                 REG_GET_FIELD(status,
  69                 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
  70         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
  71                 REG_GET_FIELD(status,
  72                 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
  73         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
  74                 REG_GET_FIELD(status,
  75                 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
  76         dev_err(adev->dev, "\t RW: 0x%lx\n",
  77                 REG_GET_FIELD(status,
  78                 GCVM_L2_PROTECTION_FAULT_STATUS, RW));
  79 }
  80
  81 u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev)
  82 {
  83         u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
  84
  85         base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
  86         base <<= 24;
  87
  88         return base;
  89 }
  90
  91 u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev)
  92 {
  93         return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
  94 }
  95
  96 void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
  97                                 uint64_t page_table_base)
  98 {
  99         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 100
 101         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 102                             hub->ctx_addr_distance * vmid,
 103                             lower_32_bits(page_table_base));
 104
 105         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
 106                             hub->ctx_addr_distance * vmid,
 107                             upper_32_bits(page_table_base));
 108 }
 109
 110 static void gfxhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
 111 {
 112         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
 113
 114         gfxhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
 115
 116         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
 117                      (u32)(adev->gmc.gart_start >> 12));
 118         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
 119                      (u32)(adev->gmc.gart_start >> 44));
 120
 121         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
 122                      (u32)(adev->gmc.gart_end >> 12));
 123         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 124                      (u32)(adev->gmc.gart_end >> 44));
 125 }
 126
 127 static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
 128 {
 129         uint64_t value;
 130
 131         if (!amdgpu_sriov_vf(adev)) {
 132                 /*
 133                  * the new L1 policy will block SRIOV guest from writing
 134                  * these regs, and they will be programed at host.
 135                  * so skip programing these regs.
 136                  */
 137                 /* Disable AGP. */
 138                 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
 139                 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0);
 140                 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF);
 141
 142                 /* Program the system aperture low logical page number. */
 143                 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 144                              adev->gmc.vram_start >> 18);
 145                 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 146                              adev->gmc.vram_end >> 18);
 147
 148                 /* Set default page address. */
 149                 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
 150                         + adev->vm_manager.vram_base_offset;
 151                 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 152                              (u32)(value >> 12));
 153                 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 154                              (u32)(value >> 44));
 155         }
 156
 157         /* Program "protection fault". */
 158         WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 159                      (u32)(adev->dummy_page_addr >> 12));
 160         WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 161                      (u32)((u64)adev->dummy_page_addr >> 44));
 162
 163         WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
 164                        ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 165 }
 166
 167
 168 static void gfxhub_v2_0_init_tlb_regs(struct amdgpu_device *adev)
 169 {
 170         uint32_t tmp;
 171
 172         /* Setup TLB control */
 173         tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
 174
 175         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 176         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 177         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 178                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 179         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 180                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 181         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 182         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 183                             MTYPE, MTYPE_UC); /* UC, uncached */
 184
 185         WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
 186 }
 187
 188 static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
 189 {
 190         uint32_t tmp;
 191
 192         /* These regs are not accessible for VF, PF will program these in SRIOV */
 193         if (amdgpu_sriov_vf(adev))
 194                 return;
 195
 196         /* Setup L2 cache */
 197         tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
 198         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
 199         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
 200         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
 201                             ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 202         /* XXX for emulation, Refer to closed source code.*/
 203         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
 204                             L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
 205         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 206         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 207         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 208         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
 209
 210         tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
 211         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 212         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 213         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
 214
 215         tmp = mmGCVM_L2_CNTL3_DEFAULT;
 216         if (adev->gmc.translate_further) {
 217                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
 218                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
 219                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 220         } else {
 221                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
 222                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
 223                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 224         }
 225         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
 226
 227         tmp = mmGCVM_L2_CNTL4_DEFAULT;
 228         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 229         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 230         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);
 231
 232         tmp = mmGCVM_L2_CNTL5_DEFAULT;
 233         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
 234         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);
 235 }
 236
 237 static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
 238 {
 239         uint32_t tmp;
 240
 241         tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
 242         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 243         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 244         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
 245                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 246         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);
 247 }
 248
 249 static void gfxhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
 250 {
 251         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 252                      0xFFFFFFFF);
 253         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 254                      0x0000000F);
 255
 256         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
 257                      0);
 258         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
 259                      0);
 260
 261         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
 262         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
 263
 264 }
 265
 266 static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
 267 {
 268         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 269         int i;
 270         uint32_t tmp;
 271
 272         for (i = 0; i <= 14; i++) {
 273                 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
 274                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 275                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 276                                     adev->vm_manager.num_level);
 277                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 278                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 279                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 280                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 281                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 282                                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 283                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 284                                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 285                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 286                                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 287                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 288                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 289                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 290                                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 291                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 292                                 PAGE_TABLE_BLOCK_SIZE,
 293                                 adev->vm_manager.block_size - 9);
 294                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 295                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 296                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 297                                     !amdgpu_noretry);
 298                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL,
 299                                     i * hub->ctx_distance, tmp);
 300                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 301                                     i * hub->ctx_addr_distance, 0);
 302                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 303                                     i * hub->ctx_addr_distance, 0);
 304                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 305                                     i * hub->ctx_addr_distance,
 306                                     lower_32_bits(adev->vm_manager.max_pfn - 1));
 307                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 308                                     i * hub->ctx_addr_distance,
 309                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
 310         }
 311 }
 312
 313 static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev)
 314 {
 315         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 316         unsigned i;
 317
 318         for (i = 0 ; i < 18; ++i) {
 319                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 320                                     i * hub->eng_addr_distance, 0xffffffff);
 321                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 322                                     i * hub->eng_addr_distance, 0x1f);
 323         }
 324 }
 325
 326 int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev)
 327 {
 328         /* GART Enable. */
 329         gfxhub_v2_0_init_gart_aperture_regs(adev);
 330         gfxhub_v2_0_init_system_aperture_regs(adev);
 331         gfxhub_v2_0_init_tlb_regs(adev);
 332         gfxhub_v2_0_init_cache_regs(adev);
 333
 334         gfxhub_v2_0_enable_system_domain(adev);
 335         gfxhub_v2_0_disable_identity_aperture(adev);
 336         gfxhub_v2_0_setup_vmid_config(adev);
 337         gfxhub_v2_0_program_invalidation(adev);
 338
 339         return 0;
 340 }
 341
 342 void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev)
 343 {
 344         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 345         u32 tmp;
 346         u32 i;
 347
 348         /* Disable all tables */
 349         for (i = 0; i < 16; i++)
 350                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL,
 351                                     i * hub->ctx_distance, 0);
 352
 353         /* Setup TLB control */
 354         tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
 355         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 356         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 357                             ENABLE_ADVANCED_DRIVER_MODEL, 0);
 358         WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
 359
 360         if (!amdgpu_sriov_vf(adev)) {
 361                 /* Setup L2 cache */
 362                 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
 363                 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
 364         }
 365 }
 366
 367 /**
 368  * gfxhub_v2_0_set_fault_enable_default - update GART/VM fault handling
 369  *
 370  * @adev: amdgpu_device pointer
 371  * @value: true redirects VM faults to the default page
 372  */
 373 void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,
 374                                           bool value)
 375 {
 376         u32 tmp;
 377         tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
 378         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 379                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 380         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 381                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 382         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 383                             PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 384         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 385                             PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 386         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 387                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 388                             value);
 389         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 390                             NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 391         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 392                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 393         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 394                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 395         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 396                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 397         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 398                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 399         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 400                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 401         if (!value) {
 402                 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 403                                 CRASH_ON_NO_RETRY_FAULT, 1);
 404                 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 405                                 CRASH_ON_RETRY_FAULT, 1);
 406         }
 407         WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
 408 }
 409
 410 static const struct amdgpu_vmhub_funcs gfxhub_v2_0_vmhub_funcs = {
 411         .print_l2_protection_fault_status = gfxhub_v2_0_print_l2_protection_fault_status,
 412         .get_invalidate_req = gfxhub_v2_0_get_invalidate_req,
 413 };
 414
 415 void gfxhub_v2_0_init(struct amdgpu_device *adev)
 416 {
 417         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 418
 419         hub->ctx0_ptb_addr_lo32 =
 420                 SOC15_REG_OFFSET(GC, 0,
 421                                  mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 422         hub->ctx0_ptb_addr_hi32 =
 423                 SOC15_REG_OFFSET(GC, 0,
 424                                  mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 425         hub->vm_inv_eng0_sem =
 426                 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
 427         hub->vm_inv_eng0_req =
 428                 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
 429         hub->vm_inv_eng0_ack =
 430                 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK);
 431         hub->vm_context0_cntl =
 432                 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL);
 433         hub->vm_l2_pro_fault_status =
 434                 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS);
 435         hub->vm_l2_pro_fault_cntl =
 436                 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
 437
 438         hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL;
 439         hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 440                 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 441         hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ -
 442                 mmGCVM_INVALIDATE_ENG0_REQ;
 443         hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 444                 mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 445
 446         hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 447                 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 448                 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 449                 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 450                 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 451                 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 452                 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 453
 454         hub->vmhub_funcs = &gfxhub_v2_0_vmhub_funcs;
 455 }