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1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/fence-array.h>
29 #include <drm/drmP.h>
30 #include <drm/amdgpu_drm.h>
31 #include "amdgpu.h"
32 #include "amdgpu_trace.h"
33
34 /*
35  * GPUVM
36  * GPUVM is similar to the legacy gart on older asics, however
37  * rather than there being a single global gart table
38  * for the entire GPU, there are multiple VM page tables active
39  * at any given time.  The VM page tables can contain a mix
40  * vram pages and system memory pages and system memory pages
41  * can be mapped as snooped (cached system pages) or unsnooped
42  * (uncached system pages).
43  * Each VM has an ID associated with it and there is a page table
44  * associated with each VMID.  When execting a command buffer,
45  * the kernel tells the the ring what VMID to use for that command
46  * buffer.  VMIDs are allocated dynamically as commands are submitted.
47  * The userspace drivers maintain their own address space and the kernel
48  * sets up their pages tables accordingly when they submit their
49  * command buffers and a VMID is assigned.
50  * Cayman/Trinity support up to 8 active VMs at any given time;
51  * SI supports 16.
52  */
53
54 /* Special value that no flush is necessary */
55 #define AMDGPU_VM_NO_FLUSH (~0ll)
56
57 /* Local structure. Encapsulate some VM table update parameters to reduce
58  * the number of function parameters
59  */
60 struct amdgpu_pte_update_params {
61         /* amdgpu device we do this update for */
62         struct amdgpu_device *adev;
63         /* address where to copy page table entries from */
64         uint64_t src;
65         /* DMA addresses to use for mapping */
66         dma_addr_t *pages_addr;
67         /* indirect buffer to fill with commands */
68         struct amdgpu_ib *ib;
69 };
70
71 /**
72  * amdgpu_vm_num_pde - return the number of page directory entries
73  *
74  * @adev: amdgpu_device pointer
75  *
76  * Calculate the number of page directory entries.
77  */
78 static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev)
79 {
80         return adev->vm_manager.max_pfn >> amdgpu_vm_block_size;
81 }
82
83 /**
84  * amdgpu_vm_directory_size - returns the size of the page directory in bytes
85  *
86  * @adev: amdgpu_device pointer
87  *
88  * Calculate the size of the page directory in bytes.
89  */
90 static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
91 {
92         return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8);
93 }
94
95 /**
96  * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
97  *
98  * @vm: vm providing the BOs
99  * @validated: head of validation list
100  * @entry: entry to add
101  *
102  * Add the page directory to the list of BOs to
103  * validate for command submission.
104  */
105 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
106                          struct list_head *validated,
107                          struct amdgpu_bo_list_entry *entry)
108 {
109         entry->robj = vm->page_directory;
110         entry->priority = 0;
111         entry->tv.bo = &vm->page_directory->tbo;
112         entry->tv.shared = true;
113         entry->user_pages = NULL;
114         list_add(&entry->tv.head, validated);
115 }
116
117 /**
118  * amdgpu_vm_get_bos - add the vm BOs to a duplicates list
119  *
120  * @adev: amdgpu device pointer
121  * @vm: vm providing the BOs
122  * @duplicates: head of duplicates list
123  *
124  * Add the page directory to the BO duplicates list
125  * for command submission.
126  */
127 void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
128                           struct list_head *duplicates)
129 {
130         uint64_t num_evictions;
131         unsigned i;
132
133         /* We only need to validate the page tables
134          * if they aren't already valid.
135          */
136         num_evictions = atomic64_read(&adev->num_evictions);
137         if (num_evictions == vm->last_eviction_counter)
138                 return;
139
140         /* add the vm page table to the list */
141         for (i = 0; i <= vm->max_pde_used; ++i) {
142                 struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry;
143
144                 if (!entry->robj)
145                         continue;
146
147                 list_add(&entry->tv.head, duplicates);
148         }
149
150 }
151
152 /**
153  * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
154  *
155  * @adev: amdgpu device instance
156  * @vm: vm providing the BOs
157  *
158  * Move the PT BOs to the tail of the LRU.
159  */
160 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
161                                   struct amdgpu_vm *vm)
162 {
163         struct ttm_bo_global *glob = adev->mman.bdev.glob;
164         unsigned i;
165
166         spin_lock(&glob->lru_lock);
167         for (i = 0; i <= vm->max_pde_used; ++i) {
168                 struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry;
169
170                 if (!entry->robj)
171                         continue;
172
173                 ttm_bo_move_to_lru_tail(&entry->robj->tbo);
174         }
175         spin_unlock(&glob->lru_lock);
176 }
177
178 static bool amdgpu_vm_is_gpu_reset(struct amdgpu_device *adev,
179                               struct amdgpu_vm_id *id)
180 {
181         return id->current_gpu_reset_count !=
182                 atomic_read(&adev->gpu_reset_counter) ? true : false;
183 }
184
185 /**
186  * amdgpu_vm_grab_id - allocate the next free VMID
187  *
188  * @vm: vm to allocate id for
189  * @ring: ring we want to submit job to
190  * @sync: sync object where we add dependencies
191  * @fence: fence protecting ID from reuse
192  *
193  * Allocate an id for the vm, adding fences to the sync obj as necessary.
194  */
195 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
196                       struct amdgpu_sync *sync, struct fence *fence,
197                       struct amdgpu_job *job)
198 {
199         struct amdgpu_device *adev = ring->adev;
200         uint64_t fence_context = adev->fence_context + ring->idx;
201         struct fence *updates = sync->last_vm_update;
202         struct amdgpu_vm_id *id, *idle;
203         struct fence **fences;
204         unsigned i;
205         int r = 0;
206
207         fences = kmalloc_array(sizeof(void *), adev->vm_manager.num_ids,
208                                GFP_KERNEL);
209         if (!fences)
210                 return -ENOMEM;
211
212         mutex_lock(&adev->vm_manager.lock);
213
214         /* Check if we have an idle VMID */
215         i = 0;
216         list_for_each_entry(idle, &adev->vm_manager.ids_lru, list) {
217                 fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
218                 if (!fences[i])
219                         break;
220                 ++i;
221         }
222
223         /* If we can't find a idle VMID to use, wait till one becomes available */
224         if (&idle->list == &adev->vm_manager.ids_lru) {
225                 u64 fence_context = adev->vm_manager.fence_context + ring->idx;
226                 unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
227                 struct fence_array *array;
228                 unsigned j;
229
230                 for (j = 0; j < i; ++j)
231                         fence_get(fences[j]);
232
233                 array = fence_array_create(i, fences, fence_context,
234                                            seqno, true);
235                 if (!array) {
236                         for (j = 0; j < i; ++j)
237                                 fence_put(fences[j]);
238                         kfree(fences);
239                         r = -ENOMEM;
240                         goto error;
241                 }
242
243
244                 r = amdgpu_sync_fence(ring->adev, sync, &array->base);
245                 fence_put(&array->base);
246                 if (r)
247                         goto error;
248
249                 mutex_unlock(&adev->vm_manager.lock);
250                 return 0;
251
252         }
253         kfree(fences);
254
255         job->vm_needs_flush = true;
256         /* Check if we can use a VMID already assigned to this VM */
257         i = ring->idx;
258         do {
259                 struct fence *flushed;
260
261                 id = vm->ids[i++];
262                 if (i == AMDGPU_MAX_RINGS)
263                         i = 0;
264
265                 /* Check all the prerequisites to using this VMID */
266                 if (!id)
267                         continue;
268                 if (amdgpu_vm_is_gpu_reset(adev, id))
269                         continue;
270
271                 if (atomic64_read(&id->owner) != vm->client_id)
272                         continue;
273
274                 if (job->vm_pd_addr != id->pd_gpu_addr)
275                         continue;
276
277                 if (!id->last_flush)
278                         continue;
279
280                 if (id->last_flush->context != fence_context &&
281                     !fence_is_signaled(id->last_flush))
282                         continue;
283
284                 flushed  = id->flushed_updates;
285                 if (updates &&
286                     (!flushed || fence_is_later(updates, flushed)))
287                         continue;
288
289                 /* Good we can use this VMID. Remember this submission as
290                  * user of the VMID.
291                  */
292                 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
293                 if (r)
294                         goto error;
295
296                 id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter);
297                 list_move_tail(&id->list, &adev->vm_manager.ids_lru);
298                 vm->ids[ring->idx] = id;
299
300                 job->vm_id = id - adev->vm_manager.ids;
301                 job->vm_needs_flush = false;
302                 trace_amdgpu_vm_grab_id(vm, ring->idx, job);
303
304                 mutex_unlock(&adev->vm_manager.lock);
305                 return 0;
306
307         } while (i != ring->idx);
308
309         /* Still no ID to use? Then use the idle one found earlier */
310         id = idle;
311
312         /* Remember this submission as user of the VMID */
313         r = amdgpu_sync_fence(ring->adev, &id->active, fence);
314         if (r)
315                 goto error;
316
317         fence_put(id->first);
318         id->first = fence_get(fence);
319
320         fence_put(id->last_flush);
321         id->last_flush = NULL;
322
323         fence_put(id->flushed_updates);
324         id->flushed_updates = fence_get(updates);
325
326         id->pd_gpu_addr = job->vm_pd_addr;
327         id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter);
328         list_move_tail(&id->list, &adev->vm_manager.ids_lru);
329         atomic64_set(&id->owner, vm->client_id);
330         vm->ids[ring->idx] = id;
331
332         job->vm_id = id - adev->vm_manager.ids;
333         trace_amdgpu_vm_grab_id(vm, ring->idx, job);
334
335 error:
336         mutex_unlock(&adev->vm_manager.lock);
337         return r;
338 }
339
340 static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring)
341 {
342         struct amdgpu_device *adev = ring->adev;
343         const struct amdgpu_ip_block_version *ip_block;
344
345         if (ring->type != AMDGPU_RING_TYPE_COMPUTE)
346                 /* only compute rings */
347                 return false;
348
349         ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
350         if (!ip_block)
351                 return false;
352
353         if (ip_block->major <= 7) {
354                 /* gfx7 has no workaround */
355                 return true;
356         } else if (ip_block->major == 8) {
357                 if (adev->gfx.mec_fw_version >= 673)
358                         /* gfx8 is fixed in MEC firmware 673 */
359                         return false;
360                 else
361                         return true;
362         }
363         return false;
364 }
365
366 /**
367  * amdgpu_vm_flush - hardware flush the vm
368  *
369  * @ring: ring to use for flush
370  * @vm_id: vmid number to use
371  * @pd_addr: address of the page directory
372  *
373  * Emit a VM flush when it is necessary.
374  */
375 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
376 {
377         struct amdgpu_device *adev = ring->adev;
378         struct amdgpu_vm_id *id = &adev->vm_manager.ids[job->vm_id];
379         bool gds_switch_needed = ring->funcs->emit_gds_switch && (
380                 id->gds_base != job->gds_base ||
381                 id->gds_size != job->gds_size ||
382                 id->gws_base != job->gws_base ||
383                 id->gws_size != job->gws_size ||
384                 id->oa_base != job->oa_base ||
385                 id->oa_size != job->oa_size);
386         int r;
387
388         if (ring->funcs->emit_pipeline_sync && (
389             job->vm_needs_flush || gds_switch_needed ||
390             amdgpu_vm_ring_has_compute_vm_bug(ring)))
391                 amdgpu_ring_emit_pipeline_sync(ring);
392
393         if (ring->funcs->emit_vm_flush && (job->vm_needs_flush ||
394             amdgpu_vm_is_gpu_reset(adev, id))) {
395                 struct fence *fence;
396
397                 trace_amdgpu_vm_flush(job->vm_pd_addr, ring->idx, job->vm_id);
398                 amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr);
399
400                 r = amdgpu_fence_emit(ring, &fence);
401                 if (r)
402                         return r;
403
404                 mutex_lock(&adev->vm_manager.lock);
405                 fence_put(id->last_flush);
406                 id->last_flush = fence;
407                 mutex_unlock(&adev->vm_manager.lock);
408         }
409
410         if (gds_switch_needed) {
411                 id->gds_base = job->gds_base;
412                 id->gds_size = job->gds_size;
413                 id->gws_base = job->gws_base;
414                 id->gws_size = job->gws_size;
415                 id->oa_base = job->oa_base;
416                 id->oa_size = job->oa_size;
417                 amdgpu_ring_emit_gds_switch(ring, job->vm_id,
418                                             job->gds_base, job->gds_size,
419                                             job->gws_base, job->gws_size,
420                                             job->oa_base, job->oa_size);
421         }
422
423         return 0;
424 }
425
426 /**
427  * amdgpu_vm_reset_id - reset VMID to zero
428  *
429  * @adev: amdgpu device structure
430  * @vm_id: vmid number to use
431  *
432  * Reset saved GDW, GWS and OA to force switch on next flush.
433  */
434 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id)
435 {
436         struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
437
438         id->gds_base = 0;
439         id->gds_size = 0;
440         id->gws_base = 0;
441         id->gws_size = 0;
442         id->oa_base = 0;
443         id->oa_size = 0;
444 }
445
446 /**
447  * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
448  *
449  * @vm: requested vm
450  * @bo: requested buffer object
451  *
452  * Find @bo inside the requested vm.
453  * Search inside the @bos vm list for the requested vm
454  * Returns the found bo_va or NULL if none is found
455  *
456  * Object has to be reserved!
457  */
458 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
459                                        struct amdgpu_bo *bo)
460 {
461         struct amdgpu_bo_va *bo_va;
462
463         list_for_each_entry(bo_va, &bo->va, bo_list) {
464                 if (bo_va->vm == vm) {
465                         return bo_va;
466                 }
467         }
468         return NULL;
469 }
470
471 /**
472  * amdgpu_vm_update_pages - helper to call the right asic function
473  *
474  * @params: see amdgpu_pte_update_params definition
475  * @pe: addr of the page entry
476  * @addr: dst addr to write into pe
477  * @count: number of page entries to update
478  * @incr: increase next addr by incr bytes
479  * @flags: hw access flags
480  *
481  * Traces the parameters and calls the right asic functions
482  * to setup the page table using the DMA.
483  */
484 static void amdgpu_vm_update_pages(struct amdgpu_pte_update_params *params,
485                                    uint64_t pe, uint64_t addr,
486                                    unsigned count, uint32_t incr,
487                                    uint32_t flags)
488 {
489         trace_amdgpu_vm_set_page(pe, addr, count, incr, flags);
490
491         if (params->src) {
492                 amdgpu_vm_copy_pte(params->adev, params->ib,
493                         pe, (params->src + (addr >> 12) * 8), count);
494
495         } else if (params->pages_addr) {
496                 amdgpu_vm_write_pte(params->adev, params->ib,
497                         params->pages_addr,
498                         pe, addr, count, incr, flags);
499
500         } else if (count < 3) {
501                 amdgpu_vm_write_pte(params->adev, params->ib, NULL, pe, addr,
502                                     count, incr, flags);
503
504         } else {
505                 amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr,
506                                       count, incr, flags);
507         }
508 }
509
510 /**
511  * amdgpu_vm_clear_bo - initially clear the page dir/table
512  *
513  * @adev: amdgpu_device pointer
514  * @bo: bo to clear
515  *
516  * need to reserve bo first before calling it.
517  */
518 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
519                               struct amdgpu_vm *vm,
520                               struct amdgpu_bo *bo)
521 {
522         struct amdgpu_ring *ring;
523         struct fence *fence = NULL;
524         struct amdgpu_job *job;
525         struct amdgpu_pte_update_params params;
526         unsigned entries;
527         uint64_t addr;
528         int r;
529
530         ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
531
532         r = reservation_object_reserve_shared(bo->tbo.resv);
533         if (r)
534                 return r;
535
536         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
537         if (r)
538                 goto error;
539
540         addr = amdgpu_bo_gpu_offset(bo);
541         entries = amdgpu_bo_size(bo) / 8;
542
543         r = amdgpu_job_alloc_with_ib(adev, 64, &job);
544         if (r)
545                 goto error;
546
547         memset(&params, 0, sizeof(params));
548         params.adev = adev;
549         params.ib = &job->ibs[0];
550         amdgpu_vm_update_pages(&params, addr, 0, entries, 0, 0);
551         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
552
553         WARN_ON(job->ibs[0].length_dw > 64);
554         r = amdgpu_job_submit(job, ring, &vm->entity,
555                               AMDGPU_FENCE_OWNER_VM, &fence);
556         if (r)
557                 goto error_free;
558
559         amdgpu_bo_fence(bo, fence, true);
560         fence_put(fence);
561         return 0;
562
563 error_free:
564         amdgpu_job_free(job);
565
566 error:
567         return r;
568 }
569
570 /**
571  * amdgpu_vm_map_gart - Resolve gart mapping of addr
572  *
573  * @pages_addr: optional DMA address to use for lookup
574  * @addr: the unmapped addr
575  *
576  * Look up the physical address of the page that the pte resolves
577  * to and return the pointer for the page table entry.
578  */
579 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
580 {
581         uint64_t result;
582
583         if (pages_addr) {
584                 /* page table offset */
585                 result = pages_addr[addr >> PAGE_SHIFT];
586
587                 /* in case cpu page size != gpu page size*/
588                 result |= addr & (~PAGE_MASK);
589
590         } else {
591                 /* No mapping required */
592                 result = addr;
593         }
594
595         result &= 0xFFFFFFFFFFFFF000ULL;
596
597         return result;
598 }
599
600 /**
601  * amdgpu_vm_update_pdes - make sure that page directory is valid
602  *
603  * @adev: amdgpu_device pointer
604  * @vm: requested vm
605  * @start: start of GPU address range
606  * @end: end of GPU address range
607  *
608  * Allocates new page tables if necessary
609  * and updates the page directory.
610  * Returns 0 for success, error for failure.
611  */
612 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
613                                     struct amdgpu_vm *vm)
614 {
615         struct amdgpu_ring *ring;
616         struct amdgpu_bo *pd = vm->page_directory;
617         uint64_t pd_addr = amdgpu_bo_gpu_offset(pd);
618         uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
619         uint64_t last_pde = ~0, last_pt = ~0;
620         unsigned count = 0, pt_idx, ndw;
621         struct amdgpu_job *job;
622         struct amdgpu_pte_update_params params;
623         struct fence *fence = NULL;
624
625         int r;
626
627         ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
628
629         /* padding, etc. */
630         ndw = 64;
631
632         /* assume the worst case */
633         ndw += vm->max_pde_used * 6;
634
635         r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
636         if (r)
637                 return r;
638
639         memset(&params, 0, sizeof(params));
640         params.adev = adev;
641         params.ib = &job->ibs[0];
642
643         /* walk over the address space and update the page directory */
644         for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
645                 struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj;
646                 uint64_t pde, pt;
647
648                 if (bo == NULL)
649                         continue;
650
651                 pt = amdgpu_bo_gpu_offset(bo);
652                 if (vm->page_tables[pt_idx].addr == pt)
653                         continue;
654                 vm->page_tables[pt_idx].addr = pt;
655
656                 pde = pd_addr + pt_idx * 8;
657                 if (((last_pde + 8 * count) != pde) ||
658                     ((last_pt + incr * count) != pt)) {
659
660                         if (count) {
661                                 amdgpu_vm_update_pages(&params, last_pde,
662                                                        last_pt, count, incr,
663                                                        AMDGPU_PTE_VALID);
664                         }
665
666                         count = 1;
667                         last_pde = pde;
668                         last_pt = pt;
669                 } else {
670                         ++count;
671                 }
672         }
673
674         if (count)
675                 amdgpu_vm_update_pages(&params, last_pde, last_pt,
676                                         count, incr, AMDGPU_PTE_VALID);
677
678         if (params.ib->length_dw != 0) {
679                 amdgpu_ring_pad_ib(ring, params.ib);
680                 amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv,
681                                  AMDGPU_FENCE_OWNER_VM);
682                 WARN_ON(params.ib->length_dw > ndw);
683                 r = amdgpu_job_submit(job, ring, &vm->entity,
684                                       AMDGPU_FENCE_OWNER_VM, &fence);
685                 if (r)
686                         goto error_free;
687
688                 amdgpu_bo_fence(pd, fence, true);
689                 fence_put(vm->page_directory_fence);
690                 vm->page_directory_fence = fence_get(fence);
691                 fence_put(fence);
692
693         } else {
694                 amdgpu_job_free(job);
695         }
696
697         return 0;
698
699 error_free:
700         amdgpu_job_free(job);
701         return r;
702 }
703
704 /**
705  * amdgpu_vm_update_ptes - make sure that page tables are valid
706  *
707  * @params: see amdgpu_pte_update_params definition
708  * @vm: requested vm
709  * @start: start of GPU address range
710  * @end: end of GPU address range
711  * @dst: destination address to map to, the next dst inside the function
712  * @flags: mapping flags
713  *
714  * Update the page tables in the range @start - @end.
715  */
716 static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
717                                   struct amdgpu_vm *vm,
718                                   uint64_t start, uint64_t end,
719                                   uint64_t dst, uint32_t flags)
720 {
721         const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
722
723         uint64_t cur_pe_start, cur_nptes, cur_dst;
724         uint64_t addr; /* next GPU address to be updated */
725         uint64_t pt_idx;
726         struct amdgpu_bo *pt;
727         unsigned nptes; /* next number of ptes to be updated */
728         uint64_t next_pe_start;
729
730         /* initialize the variables */
731         addr = start;
732         pt_idx = addr >> amdgpu_vm_block_size;
733         pt = vm->page_tables[pt_idx].entry.robj;
734
735         if ((addr & ~mask) == (end & ~mask))
736                 nptes = end - addr;
737         else
738                 nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
739
740         cur_pe_start = amdgpu_bo_gpu_offset(pt);
741         cur_pe_start += (addr & mask) * 8;
742         cur_nptes = nptes;
743         cur_dst = dst;
744
745         /* for next ptb*/
746         addr += nptes;
747         dst += nptes * AMDGPU_GPU_PAGE_SIZE;
748
749         /* walk over the address space and update the page tables */
750         while (addr < end) {
751                 pt_idx = addr >> amdgpu_vm_block_size;
752                 pt = vm->page_tables[pt_idx].entry.robj;
753
754                 if ((addr & ~mask) == (end & ~mask))
755                         nptes = end - addr;
756                 else
757                         nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
758
759                 next_pe_start = amdgpu_bo_gpu_offset(pt);
760                 next_pe_start += (addr & mask) * 8;
761
762                 if ((cur_pe_start + 8 * cur_nptes) == next_pe_start) {
763                         /* The next ptb is consecutive to current ptb.
764                          * Don't call amdgpu_vm_update_pages now.
765                          * Will update two ptbs together in future.
766                         */
767                         cur_nptes += nptes;
768                 } else {
769                         amdgpu_vm_update_pages(params, cur_pe_start, cur_dst,
770                                                cur_nptes, AMDGPU_GPU_PAGE_SIZE,
771                                                flags);
772
773                         cur_pe_start = next_pe_start;
774                         cur_nptes = nptes;
775                         cur_dst = dst;
776                 }
777
778                 /* for next ptb*/
779                 addr += nptes;
780                 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
781         }
782
783         amdgpu_vm_update_pages(params, cur_pe_start, cur_dst, cur_nptes,
784                                AMDGPU_GPU_PAGE_SIZE, flags);
785 }
786
787 /*
788  * amdgpu_vm_frag_ptes - add fragment information to PTEs
789  *
790  * @params: see amdgpu_pte_update_params definition
791  * @vm: requested vm
792  * @start: first PTE to handle
793  * @end: last PTE to handle
794  * @dst: addr those PTEs should point to
795  * @flags: hw mapping flags
796  */
797 static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
798                                 struct amdgpu_vm *vm,
799                                 uint64_t start, uint64_t end,
800                                 uint64_t dst, uint32_t flags)
801 {
802         /**
803          * The MC L1 TLB supports variable sized pages, based on a fragment
804          * field in the PTE. When this field is set to a non-zero value, page
805          * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
806          * flags are considered valid for all PTEs within the fragment range
807          * and corresponding mappings are assumed to be physically contiguous.
808          *
809          * The L1 TLB can store a single PTE for the whole fragment,
810          * significantly increasing the space available for translation
811          * caching. This leads to large improvements in throughput when the
812          * TLB is under pressure.
813          *
814          * The L2 TLB distributes small and large fragments into two
815          * asymmetric partitions. The large fragment cache is significantly
816          * larger. Thus, we try to use large fragments wherever possible.
817          * Userspace can support this by aligning virtual base address and
818          * allocation size to the fragment size.
819          */
820
821         const uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG;
822
823         uint64_t frag_start = ALIGN(start, frag_align);
824         uint64_t frag_end = end & ~(frag_align - 1);
825
826         uint32_t frag;
827
828         /* system pages are non continuously */
829         if (params->src || params->pages_addr || !(flags & AMDGPU_PTE_VALID) ||
830             (frag_start >= frag_end)) {
831
832                 amdgpu_vm_update_ptes(params, vm, start, end, dst, flags);
833                 return;
834         }
835
836         /* use more than 64KB fragment size if possible */
837         frag = lower_32_bits(frag_start | frag_end);
838         frag = likely(frag) ? __ffs(frag) : 31;
839
840         /* handle the 4K area at the beginning */
841         if (start != frag_start) {
842                 amdgpu_vm_update_ptes(params, vm, start, frag_start,
843                                       dst, flags);
844                 dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE;
845         }
846
847         /* handle the area in the middle */
848         amdgpu_vm_update_ptes(params, vm, frag_start, frag_end, dst,
849                               flags | AMDGPU_PTE_FRAG(frag));
850
851         /* handle the 4K area at the end */
852         if (frag_end != end) {
853                 dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE;
854                 amdgpu_vm_update_ptes(params, vm, frag_end, end, dst, flags);
855         }
856 }
857
858 /**
859  * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
860  *
861  * @adev: amdgpu_device pointer
862  * @exclusive: fence we need to sync to
863  * @src: address where to copy page table entries from
864  * @pages_addr: DMA addresses to use for mapping
865  * @vm: requested vm
866  * @start: start of mapped range
867  * @last: last mapped entry
868  * @flags: flags for the entries
869  * @addr: addr to set the area to
870  * @fence: optional resulting fence
871  *
872  * Fill in the page table entries between @start and @last.
873  * Returns 0 for success, -EINVAL for failure.
874  */
875 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
876                                        struct fence *exclusive,
877                                        uint64_t src,
878                                        dma_addr_t *pages_addr,
879                                        struct amdgpu_vm *vm,
880                                        uint64_t start, uint64_t last,
881                                        uint32_t flags, uint64_t addr,
882                                        struct fence **fence)
883 {
884         struct amdgpu_ring *ring;
885         void *owner = AMDGPU_FENCE_OWNER_VM;
886         unsigned nptes, ncmds, ndw;
887         struct amdgpu_job *job;
888         struct amdgpu_pte_update_params params;
889         struct fence *f = NULL;
890         int r;
891
892         ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
893
894         memset(&params, 0, sizeof(params));
895         params.adev = adev;
896         params.src = src;
897         params.pages_addr = pages_addr;
898
899         /* sync to everything on unmapping */
900         if (!(flags & AMDGPU_PTE_VALID))
901                 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
902
903         nptes = last - start + 1;
904
905         /*
906          * reserve space for one command every (1 << BLOCK_SIZE)
907          *  entries or 2k dwords (whatever is smaller)
908          */
909         ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1;
910
911         /* padding, etc. */
912         ndw = 64;
913
914         if (params.src) {
915                 /* only copy commands needed */
916                 ndw += ncmds * 7;
917
918         } else if (params.pages_addr) {
919                 /* header for write data commands */
920                 ndw += ncmds * 4;
921
922                 /* body of write data command */
923                 ndw += nptes * 2;
924
925         } else {
926                 /* set page commands needed */
927                 ndw += ncmds * 10;
928
929                 /* two extra commands for begin/end of fragment */
930                 ndw += 2 * 10;
931         }
932
933         r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
934         if (r)
935                 return r;
936
937         params.ib = &job->ibs[0];
938
939         r = amdgpu_sync_fence(adev, &job->sync, exclusive);
940         if (r)
941                 goto error_free;
942
943         r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv,
944                              owner);
945         if (r)
946                 goto error_free;
947
948         r = reservation_object_reserve_shared(vm->page_directory->tbo.resv);
949         if (r)
950                 goto error_free;
951
952         amdgpu_vm_frag_ptes(&params, vm, start, last + 1, addr, flags);
953
954         amdgpu_ring_pad_ib(ring, params.ib);
955         WARN_ON(params.ib->length_dw > ndw);
956         r = amdgpu_job_submit(job, ring, &vm->entity,
957                               AMDGPU_FENCE_OWNER_VM, &f);
958         if (r)
959                 goto error_free;
960
961         amdgpu_bo_fence(vm->page_directory, f, true);
962         if (fence) {
963                 fence_put(*fence);
964                 *fence = fence_get(f);
965         }
966         fence_put(f);
967         return 0;
968
969 error_free:
970         amdgpu_job_free(job);
971         return r;
972 }
973
974 /**
975  * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
976  *
977  * @adev: amdgpu_device pointer
978  * @exclusive: fence we need to sync to
979  * @gtt_flags: flags as they are used for GTT
980  * @pages_addr: DMA addresses to use for mapping
981  * @vm: requested vm
982  * @mapping: mapped range and flags to use for the update
983  * @addr: addr to set the area to
984  * @flags: HW flags for the mapping
985  * @fence: optional resulting fence
986  *
987  * Split the mapping into smaller chunks so that each update fits
988  * into a SDMA IB.
989  * Returns 0 for success, -EINVAL for failure.
990  */
991 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
992                                       struct fence *exclusive,
993                                       uint32_t gtt_flags,
994                                       dma_addr_t *pages_addr,
995                                       struct amdgpu_vm *vm,
996                                       struct amdgpu_bo_va_mapping *mapping,
997                                       uint32_t flags, uint64_t addr,
998                                       struct fence **fence)
999 {
1000         const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE;
1001
1002         uint64_t src = 0, start = mapping->it.start;
1003         int r;
1004
1005         /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1006          * but in case of something, we filter the flags in first place
1007          */
1008         if (!(mapping->flags & AMDGPU_PTE_READABLE))
1009                 flags &= ~AMDGPU_PTE_READABLE;
1010         if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1011                 flags &= ~AMDGPU_PTE_WRITEABLE;
1012
1013         trace_amdgpu_vm_bo_update(mapping);
1014
1015         if (pages_addr) {
1016                 if (flags == gtt_flags)
1017                         src = adev->gart.table_addr + (addr >> 12) * 8;
1018                 addr = 0;
1019         }
1020         addr += mapping->offset;
1021
1022         if (!pages_addr || src)
1023                 return amdgpu_vm_bo_update_mapping(adev, exclusive,
1024                                                    src, pages_addr, vm,
1025                                                    start, mapping->it.last,
1026                                                    flags, addr, fence);
1027
1028         while (start != mapping->it.last + 1) {
1029                 uint64_t last;
1030
1031                 last = min((uint64_t)mapping->it.last, start + max_size - 1);
1032                 r = amdgpu_vm_bo_update_mapping(adev, exclusive,
1033                                                 src, pages_addr, vm,
1034                                                 start, last, flags, addr,
1035                                                 fence);
1036                 if (r)
1037                         return r;
1038
1039                 start = last + 1;
1040                 addr += max_size * AMDGPU_GPU_PAGE_SIZE;
1041         }
1042
1043         return 0;
1044 }
1045
1046 /**
1047  * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1048  *
1049  * @adev: amdgpu_device pointer
1050  * @bo_va: requested BO and VM object
1051  * @mem: ttm mem
1052  *
1053  * Fill in the page table entries for @bo_va.
1054  * Returns 0 for success, -EINVAL for failure.
1055  *
1056  * Object have to be reserved and mutex must be locked!
1057  */
1058 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1059                         struct amdgpu_bo_va *bo_va,
1060                         struct ttm_mem_reg *mem)
1061 {
1062         struct amdgpu_vm *vm = bo_va->vm;
1063         struct amdgpu_bo_va_mapping *mapping;
1064         dma_addr_t *pages_addr = NULL;
1065         uint32_t gtt_flags, flags;
1066         struct fence *exclusive;
1067         uint64_t addr;
1068         int r;
1069
1070         if (mem) {
1071                 struct ttm_dma_tt *ttm;
1072
1073                 addr = (u64)mem->start << PAGE_SHIFT;
1074                 switch (mem->mem_type) {
1075                 case TTM_PL_TT:
1076                         ttm = container_of(bo_va->bo->tbo.ttm, struct
1077                                            ttm_dma_tt, ttm);
1078                         pages_addr = ttm->dma_address;
1079                         break;
1080
1081                 case TTM_PL_VRAM:
1082                         addr += adev->vm_manager.vram_base_offset;
1083                         break;
1084
1085                 default:
1086                         break;
1087                 }
1088
1089                 exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv);
1090         } else {
1091                 addr = 0;
1092                 exclusive = NULL;
1093         }
1094
1095         flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
1096         gtt_flags = (adev == bo_va->bo->adev) ? flags : 0;
1097
1098         spin_lock(&vm->status_lock);
1099         if (!list_empty(&bo_va->vm_status))
1100                 list_splice_init(&bo_va->valids, &bo_va->invalids);
1101         spin_unlock(&vm->status_lock);
1102
1103         list_for_each_entry(mapping, &bo_va->invalids, list) {
1104                 r = amdgpu_vm_bo_split_mapping(adev, exclusive,
1105                                                gtt_flags, pages_addr, vm,
1106                                                mapping, flags, addr,
1107                                                &bo_va->last_pt_update);
1108                 if (r)
1109                         return r;
1110         }
1111
1112         if (trace_amdgpu_vm_bo_mapping_enabled()) {
1113                 list_for_each_entry(mapping, &bo_va->valids, list)
1114                         trace_amdgpu_vm_bo_mapping(mapping);
1115
1116                 list_for_each_entry(mapping, &bo_va->invalids, list)
1117                         trace_amdgpu_vm_bo_mapping(mapping);
1118         }
1119
1120         spin_lock(&vm->status_lock);
1121         list_splice_init(&bo_va->invalids, &bo_va->valids);
1122         list_del_init(&bo_va->vm_status);
1123         if (!mem)
1124                 list_add(&bo_va->vm_status, &vm->cleared);
1125         spin_unlock(&vm->status_lock);
1126
1127         return 0;
1128 }
1129
1130 /**
1131  * amdgpu_vm_clear_freed - clear freed BOs in the PT
1132  *
1133  * @adev: amdgpu_device pointer
1134  * @vm: requested vm
1135  *
1136  * Make sure all freed BOs are cleared in the PT.
1137  * Returns 0 for success.
1138  *
1139  * PTs have to be reserved and mutex must be locked!
1140  */
1141 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1142                           struct amdgpu_vm *vm)
1143 {
1144         struct amdgpu_bo_va_mapping *mapping;
1145         int r;
1146
1147         while (!list_empty(&vm->freed)) {
1148                 mapping = list_first_entry(&vm->freed,
1149                         struct amdgpu_bo_va_mapping, list);
1150                 list_del(&mapping->list);
1151
1152                 r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, NULL, vm, mapping,
1153                                                0, 0, NULL);
1154                 kfree(mapping);
1155                 if (r)
1156                         return r;
1157
1158         }
1159         return 0;
1160
1161 }
1162
1163 /**
1164  * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
1165  *
1166  * @adev: amdgpu_device pointer
1167  * @vm: requested vm
1168  *
1169  * Make sure all invalidated BOs are cleared in the PT.
1170  * Returns 0 for success.
1171  *
1172  * PTs have to be reserved and mutex must be locked!
1173  */
1174 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
1175                              struct amdgpu_vm *vm, struct amdgpu_sync *sync)
1176 {
1177         struct amdgpu_bo_va *bo_va = NULL;
1178         int r = 0;
1179
1180         spin_lock(&vm->status_lock);
1181         while (!list_empty(&vm->invalidated)) {
1182                 bo_va = list_first_entry(&vm->invalidated,
1183                         struct amdgpu_bo_va, vm_status);
1184                 spin_unlock(&vm->status_lock);
1185
1186                 r = amdgpu_vm_bo_update(adev, bo_va, NULL);
1187                 if (r)
1188                         return r;
1189
1190                 spin_lock(&vm->status_lock);
1191         }
1192         spin_unlock(&vm->status_lock);
1193
1194         if (bo_va)
1195                 r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update);
1196
1197         return r;
1198 }
1199
1200 /**
1201  * amdgpu_vm_bo_add - add a bo to a specific vm
1202  *
1203  * @adev: amdgpu_device pointer
1204  * @vm: requested vm
1205  * @bo: amdgpu buffer object
1206  *
1207  * Add @bo into the requested vm.
1208  * Add @bo to the list of bos associated with the vm
1209  * Returns newly added bo_va or NULL for failure
1210  *
1211  * Object has to be reserved!
1212  */
1213 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1214                                       struct amdgpu_vm *vm,
1215                                       struct amdgpu_bo *bo)
1216 {
1217         struct amdgpu_bo_va *bo_va;
1218
1219         bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1220         if (bo_va == NULL) {
1221                 return NULL;
1222         }
1223         bo_va->vm = vm;
1224         bo_va->bo = bo;
1225         bo_va->ref_count = 1;
1226         INIT_LIST_HEAD(&bo_va->bo_list);
1227         INIT_LIST_HEAD(&bo_va->valids);
1228         INIT_LIST_HEAD(&bo_va->invalids);
1229         INIT_LIST_HEAD(&bo_va->vm_status);
1230
1231         list_add_tail(&bo_va->bo_list, &bo->va);
1232
1233         return bo_va;
1234 }
1235
1236 /**
1237  * amdgpu_vm_bo_map - map bo inside a vm
1238  *
1239  * @adev: amdgpu_device pointer
1240  * @bo_va: bo_va to store the address
1241  * @saddr: where to map the BO
1242  * @offset: requested offset in the BO
1243  * @flags: attributes of pages (read/write/valid/etc.)
1244  *
1245  * Add a mapping of the BO at the specefied addr into the VM.
1246  * Returns 0 for success, error for failure.
1247  *
1248  * Object has to be reserved and unreserved outside!
1249  */
1250 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1251                      struct amdgpu_bo_va *bo_va,
1252                      uint64_t saddr, uint64_t offset,
1253                      uint64_t size, uint32_t flags)
1254 {
1255         struct amdgpu_bo_va_mapping *mapping;
1256         struct amdgpu_vm *vm = bo_va->vm;
1257         struct interval_tree_node *it;
1258         unsigned last_pfn, pt_idx;
1259         uint64_t eaddr;
1260         int r;
1261
1262         /* validate the parameters */
1263         if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1264             size == 0 || size & AMDGPU_GPU_PAGE_MASK)
1265                 return -EINVAL;
1266
1267         /* make sure object fit at this offset */
1268         eaddr = saddr + size - 1;
1269         if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo)))
1270                 return -EINVAL;
1271
1272         last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
1273         if (last_pfn >= adev->vm_manager.max_pfn) {
1274                 dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n",
1275                         last_pfn, adev->vm_manager.max_pfn);
1276                 return -EINVAL;
1277         }
1278
1279         saddr /= AMDGPU_GPU_PAGE_SIZE;
1280         eaddr /= AMDGPU_GPU_PAGE_SIZE;
1281
1282         it = interval_tree_iter_first(&vm->va, saddr, eaddr);
1283         if (it) {
1284                 struct amdgpu_bo_va_mapping *tmp;
1285                 tmp = container_of(it, struct amdgpu_bo_va_mapping, it);
1286                 /* bo and tmp overlap, invalid addr */
1287                 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1288                         "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr,
1289                         tmp->it.start, tmp->it.last + 1);
1290                 r = -EINVAL;
1291                 goto error;
1292         }
1293
1294         mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1295         if (!mapping) {
1296                 r = -ENOMEM;
1297                 goto error;
1298         }
1299
1300         INIT_LIST_HEAD(&mapping->list);
1301         mapping->it.start = saddr;
1302         mapping->it.last = eaddr;
1303         mapping->offset = offset;
1304         mapping->flags = flags;
1305
1306         list_add(&mapping->list, &bo_va->invalids);
1307         interval_tree_insert(&mapping->it, &vm->va);
1308
1309         /* Make sure the page tables are allocated */
1310         saddr >>= amdgpu_vm_block_size;
1311         eaddr >>= amdgpu_vm_block_size;
1312
1313         BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev));
1314
1315         if (eaddr > vm->max_pde_used)
1316                 vm->max_pde_used = eaddr;
1317
1318         /* walk over the address space and allocate the page tables */
1319         for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) {
1320                 struct reservation_object *resv = vm->page_directory->tbo.resv;
1321                 struct amdgpu_bo_list_entry *entry;
1322                 struct amdgpu_bo *pt;
1323
1324                 entry = &vm->page_tables[pt_idx].entry;
1325                 if (entry->robj)
1326                         continue;
1327
1328                 r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
1329                                      AMDGPU_GPU_PAGE_SIZE, true,
1330                                      AMDGPU_GEM_DOMAIN_VRAM,
1331                                      AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
1332                                      NULL, resv, &pt);
1333                 if (r)
1334                         goto error_free;
1335
1336                 /* Keep a reference to the page table to avoid freeing
1337                  * them up in the wrong order.
1338                  */
1339                 pt->parent = amdgpu_bo_ref(vm->page_directory);
1340
1341                 r = amdgpu_vm_clear_bo(adev, vm, pt);
1342                 if (r) {
1343                         amdgpu_bo_unref(&pt);
1344                         goto error_free;
1345                 }
1346
1347                 entry->robj = pt;
1348                 entry->priority = 0;
1349                 entry->tv.bo = &entry->robj->tbo;
1350                 entry->tv.shared = true;
1351                 entry->user_pages = NULL;
1352                 vm->page_tables[pt_idx].addr = 0;
1353         }
1354
1355         return 0;
1356
1357 error_free:
1358         list_del(&mapping->list);
1359         interval_tree_remove(&mapping->it, &vm->va);
1360         trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1361         kfree(mapping);
1362
1363 error:
1364         return r;
1365 }
1366
1367 /**
1368  * amdgpu_vm_bo_unmap - remove bo mapping from vm
1369  *
1370  * @adev: amdgpu_device pointer
1371  * @bo_va: bo_va to remove the address from
1372  * @saddr: where to the BO is mapped
1373  *
1374  * Remove a mapping of the BO at the specefied addr from the VM.
1375  * Returns 0 for success, error for failure.
1376  *
1377  * Object has to be reserved and unreserved outside!
1378  */
1379 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1380                        struct amdgpu_bo_va *bo_va,
1381                        uint64_t saddr)
1382 {
1383         struct amdgpu_bo_va_mapping *mapping;
1384         struct amdgpu_vm *vm = bo_va->vm;
1385         bool valid = true;
1386
1387         saddr /= AMDGPU_GPU_PAGE_SIZE;
1388
1389         list_for_each_entry(mapping, &bo_va->valids, list) {
1390                 if (mapping->it.start == saddr)
1391                         break;
1392         }
1393
1394         if (&mapping->list == &bo_va->valids) {
1395                 valid = false;
1396
1397                 list_for_each_entry(mapping, &bo_va->invalids, list) {
1398                         if (mapping->it.start == saddr)
1399                                 break;
1400                 }
1401
1402                 if (&mapping->list == &bo_va->invalids)
1403                         return -ENOENT;
1404         }
1405
1406         list_del(&mapping->list);
1407         interval_tree_remove(&mapping->it, &vm->va);
1408         trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1409
1410         if (valid)
1411                 list_add(&mapping->list, &vm->freed);
1412         else
1413                 kfree(mapping);
1414
1415         return 0;
1416 }
1417
1418 /**
1419  * amdgpu_vm_bo_rmv - remove a bo to a specific vm
1420  *
1421  * @adev: amdgpu_device pointer
1422  * @bo_va: requested bo_va
1423  *
1424  * Remove @bo_va->bo from the requested vm.
1425  *
1426  * Object have to be reserved!
1427  */
1428 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1429                       struct amdgpu_bo_va *bo_va)
1430 {
1431         struct amdgpu_bo_va_mapping *mapping, *next;
1432         struct amdgpu_vm *vm = bo_va->vm;
1433
1434         list_del(&bo_va->bo_list);
1435
1436         spin_lock(&vm->status_lock);
1437         list_del(&bo_va->vm_status);
1438         spin_unlock(&vm->status_lock);
1439
1440         list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
1441                 list_del(&mapping->list);
1442                 interval_tree_remove(&mapping->it, &vm->va);
1443                 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1444                 list_add(&mapping->list, &vm->freed);
1445         }
1446         list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
1447                 list_del(&mapping->list);
1448                 interval_tree_remove(&mapping->it, &vm->va);
1449                 kfree(mapping);
1450         }
1451
1452         fence_put(bo_va->last_pt_update);
1453         kfree(bo_va);
1454 }
1455
1456 /**
1457  * amdgpu_vm_bo_invalidate - mark the bo as invalid
1458  *
1459  * @adev: amdgpu_device pointer
1460  * @vm: requested vm
1461  * @bo: amdgpu buffer object
1462  *
1463  * Mark @bo as invalid.
1464  */
1465 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1466                              struct amdgpu_bo *bo)
1467 {
1468         struct amdgpu_bo_va *bo_va;
1469
1470         list_for_each_entry(bo_va, &bo->va, bo_list) {
1471                 spin_lock(&bo_va->vm->status_lock);
1472                 if (list_empty(&bo_va->vm_status))
1473                         list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
1474                 spin_unlock(&bo_va->vm->status_lock);
1475         }
1476 }
1477
1478 /**
1479  * amdgpu_vm_init - initialize a vm instance
1480  *
1481  * @adev: amdgpu_device pointer
1482  * @vm: requested vm
1483  *
1484  * Init @vm fields.
1485  */
1486 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1487 {
1488         const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
1489                 AMDGPU_VM_PTE_COUNT * 8);
1490         unsigned pd_size, pd_entries;
1491         unsigned ring_instance;
1492         struct amdgpu_ring *ring;
1493         struct amd_sched_rq *rq;
1494         int i, r;
1495
1496         for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
1497                 vm->ids[i] = NULL;
1498         vm->va = RB_ROOT;
1499         vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
1500         spin_lock_init(&vm->status_lock);
1501         INIT_LIST_HEAD(&vm->invalidated);
1502         INIT_LIST_HEAD(&vm->cleared);
1503         INIT_LIST_HEAD(&vm->freed);
1504
1505         pd_size = amdgpu_vm_directory_size(adev);
1506         pd_entries = amdgpu_vm_num_pdes(adev);
1507
1508         /* allocate page table array */
1509         vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt));
1510         if (vm->page_tables == NULL) {
1511                 DRM_ERROR("Cannot allocate memory for page table array\n");
1512                 return -ENOMEM;
1513         }
1514
1515         /* create scheduler entity for page table updates */
1516
1517         ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
1518         ring_instance %= adev->vm_manager.vm_pte_num_rings;
1519         ring = adev->vm_manager.vm_pte_rings[ring_instance];
1520         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
1521         r = amd_sched_entity_init(&ring->sched, &vm->entity,
1522                                   rq, amdgpu_sched_jobs);
1523         if (r)
1524                 return r;
1525
1526         vm->page_directory_fence = NULL;
1527
1528         r = amdgpu_bo_create(adev, pd_size, align, true,
1529                              AMDGPU_GEM_DOMAIN_VRAM,
1530                              AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
1531                              NULL, NULL, &vm->page_directory);
1532         if (r)
1533                 goto error_free_sched_entity;
1534
1535         r = amdgpu_bo_reserve(vm->page_directory, false);
1536         if (r)
1537                 goto error_free_page_directory;
1538
1539         r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory);
1540         amdgpu_bo_unreserve(vm->page_directory);
1541         if (r)
1542                 goto error_free_page_directory;
1543         vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
1544
1545         return 0;
1546
1547 error_free_page_directory:
1548         amdgpu_bo_unref(&vm->page_directory);
1549         vm->page_directory = NULL;
1550
1551 error_free_sched_entity:
1552         amd_sched_entity_fini(&ring->sched, &vm->entity);
1553
1554         return r;
1555 }
1556
1557 /**
1558  * amdgpu_vm_fini - tear down a vm instance
1559  *
1560  * @adev: amdgpu_device pointer
1561  * @vm: requested vm
1562  *
1563  * Tear down @vm.
1564  * Unbind the VM and remove all bos from the vm bo list
1565  */
1566 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1567 {
1568         struct amdgpu_bo_va_mapping *mapping, *tmp;
1569         int i;
1570
1571         amd_sched_entity_fini(vm->entity.sched, &vm->entity);
1572
1573         if (!RB_EMPTY_ROOT(&vm->va)) {
1574                 dev_err(adev->dev, "still active bo inside vm\n");
1575         }
1576         rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) {
1577                 list_del(&mapping->list);
1578                 interval_tree_remove(&mapping->it, &vm->va);
1579                 kfree(mapping);
1580         }
1581         list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
1582                 list_del(&mapping->list);
1583                 kfree(mapping);
1584         }
1585
1586         for (i = 0; i < amdgpu_vm_num_pdes(adev); i++)
1587                 amdgpu_bo_unref(&vm->page_tables[i].entry.robj);
1588         drm_free_large(vm->page_tables);
1589
1590         amdgpu_bo_unref(&vm->page_directory);
1591         fence_put(vm->page_directory_fence);
1592 }
1593
1594 /**
1595  * amdgpu_vm_manager_init - init the VM manager
1596  *
1597  * @adev: amdgpu_device pointer
1598  *
1599  * Initialize the VM manager structures
1600  */
1601 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
1602 {
1603         unsigned i;
1604
1605         INIT_LIST_HEAD(&adev->vm_manager.ids_lru);
1606
1607         /* skip over VMID 0, since it is the system VM */
1608         for (i = 1; i < adev->vm_manager.num_ids; ++i) {
1609                 amdgpu_vm_reset_id(adev, i);
1610                 amdgpu_sync_create(&adev->vm_manager.ids[i].active);
1611                 list_add_tail(&adev->vm_manager.ids[i].list,
1612                               &adev->vm_manager.ids_lru);
1613         }
1614
1615         adev->vm_manager.fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1616         for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
1617                 adev->vm_manager.seqno[i] = 0;
1618
1619         atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
1620         atomic64_set(&adev->vm_manager.client_counter, 0);
1621 }
1622
1623 /**
1624  * amdgpu_vm_manager_fini - cleanup VM manager
1625  *
1626  * @adev: amdgpu_device pointer
1627  *
1628  * Cleanup the VM manager and free resources.
1629  */
1630 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
1631 {
1632         unsigned i;
1633
1634         for (i = 0; i < AMDGPU_NUM_VM; ++i) {
1635                 struct amdgpu_vm_id *id = &adev->vm_manager.ids[i];
1636
1637                 fence_put(adev->vm_manager.ids[i].first);
1638                 amdgpu_sync_free(&adev->vm_manager.ids[i].active);
1639                 fence_put(id->flushed_updates);
1640         }
1641 }
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