drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <[email protected]>
  25  *    Zou Nan hai <[email protected]>
  26  *    Xiang Hai hao<[email protected]>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34
  35 #include "i915_drv.h"
  36 #include "i915_gem_render_state.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /* Rough estimate of the typical request size, performing a flush,
  41  * set-context and then emitting the batch.
  42  */
  43 #define LEGACY_REQUEST_SIZE 200
  44
  45 static unsigned int __intel_ring_space(unsigned int head,
  46                                        unsigned int tail,
  47                                        unsigned int size)
  48 {
  49         /*
  50          * "If the Ring Buffer Head Pointer and the Tail Pointer are on the
  51          * same cacheline, the Head Pointer must not be greater than the Tail
  52          * Pointer."
  53          */
  54         GEM_BUG_ON(!is_power_of_2(size));
  55         return (head - tail - CACHELINE_BYTES) & (size - 1);
  56 }
  57
  58 unsigned int intel_ring_update_space(struct intel_ring *ring)
  59 {
  60         unsigned int space;
  61
  62         space = __intel_ring_space(ring->head, ring->emit, ring->size);
  63
  64         ring->space = space;
  65         return space;
  66 }
  67
  68 static int
  69 gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
  70 {
  71         u32 cmd, *cs;
  72
  73         cmd = MI_FLUSH;
  74
  75         if (mode & EMIT_INVALIDATE)
  76                 cmd |= MI_READ_FLUSH;
  77
  78         cs = intel_ring_begin(req, 2);
  79         if (IS_ERR(cs))
  80                 return PTR_ERR(cs);
  81
  82         *cs++ = cmd;
  83         *cs++ = MI_NOOP;
  84         intel_ring_advance(req, cs);
  85
  86         return 0;
  87 }
  88
  89 static int
  90 gen4_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
  91 {
  92         u32 cmd, *cs;
  93
  94         /*
  95          * read/write caches:
  96          *
  97          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  98          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  99          * also flushed at 2d versus 3d pipeline switches.
 100          *
 101          * read-only caches:
 102          *
 103          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 104          * MI_READ_FLUSH is set, and is always flushed on 965.
 105          *
 106          * I915_GEM_DOMAIN_COMMAND may not exist?
 107          *
 108          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 109          * invalidated when MI_EXE_FLUSH is set.
 110          *
 111          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 112          * invalidated with every MI_FLUSH.
 113          *
 114          * TLBs:
 115          *
 116          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 117          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 118          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 119          * are flushed at any MI_FLUSH.
 120          */
 121
 122         cmd = MI_FLUSH;
 123         if (mode & EMIT_INVALIDATE) {
 124                 cmd |= MI_EXE_FLUSH;
 125                 if (IS_G4X(req->i915) || IS_GEN5(req->i915))
 126                         cmd |= MI_INVALIDATE_ISP;
 127         }
 128
 129         cs = intel_ring_begin(req, 2);
 130         if (IS_ERR(cs))
 131                 return PTR_ERR(cs);
 132
 133         *cs++ = cmd;
 134         *cs++ = MI_NOOP;
 135         intel_ring_advance(req, cs);
 136
 137         return 0;
 138 }
 139
 140 /**
 141  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 142  * implementing two workarounds on gen6.  From section 1.4.7.1
 143  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 144  *
 145  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 146  * produced by non-pipelined state commands), software needs to first
 147  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 148  * 0.
 149  *
 150  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 151  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 152  *
 153  * And the workaround for these two requires this workaround first:
 154  *
 155  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 156  * BEFORE the pipe-control with a post-sync op and no write-cache
 157  * flushes.
 158  *
 159  * And this last workaround is tricky because of the requirements on
 160  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 161  * volume 2 part 1:
 162  *
 163  *     "1 of the following must also be set:
 164  *      - Render Target Cache Flush Enable ([12] of DW1)
 165  *      - Depth Cache Flush Enable ([0] of DW1)
 166  *      - Stall at Pixel Scoreboard ([1] of DW1)
 167  *      - Depth Stall ([13] of DW1)
 168  *      - Post-Sync Operation ([13] of DW1)
 169  *      - Notify Enable ([8] of DW1)"
 170  *
 171  * The cache flushes require the workaround flush that triggered this
 172  * one, so we can't use it.  Depth stall would trigger the same.
 173  * Post-sync nonzero is what triggered this second workaround, so we
 174  * can't use that one either.  Notify enable is IRQs, which aren't
 175  * really our business.  That leaves only stall at scoreboard.
 176  */
 177 static int
 178 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 179 {
 180         u32 scratch_addr =
 181                 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES;
 182         u32 *cs;
 183
 184         cs = intel_ring_begin(req, 6);
 185         if (IS_ERR(cs))
 186                 return PTR_ERR(cs);
 187
 188         *cs++ = GFX_OP_PIPE_CONTROL(5);
 189         *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
 190         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 191         *cs++ = 0; /* low dword */
 192         *cs++ = 0; /* high dword */
 193         *cs++ = MI_NOOP;
 194         intel_ring_advance(req, cs);
 195
 196         cs = intel_ring_begin(req, 6);
 197         if (IS_ERR(cs))
 198                 return PTR_ERR(cs);
 199
 200         *cs++ = GFX_OP_PIPE_CONTROL(5);
 201         *cs++ = PIPE_CONTROL_QW_WRITE;
 202         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 203         *cs++ = 0;
 204         *cs++ = 0;
 205         *cs++ = MI_NOOP;
 206         intel_ring_advance(req, cs);
 207
 208         return 0;
 209 }
 210
 211 static int
 212 gen6_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
 213 {
 214         u32 scratch_addr =
 215                 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES;
 216         u32 *cs, flags = 0;
 217         int ret;
 218
 219         /* Force SNB workarounds for PIPE_CONTROL flushes */
 220         ret = intel_emit_post_sync_nonzero_flush(req);
 221         if (ret)
 222                 return ret;
 223
 224         /* Just flush everything.  Experiments have shown that reducing the
 225          * number of bits based on the write domains has little performance
 226          * impact.
 227          */
 228         if (mode & EMIT_FLUSH) {
 229                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 230                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 231                 /*
 232                  * Ensure that any following seqno writes only happen
 233                  * when the render cache is indeed flushed.
 234                  */
 235                 flags |= PIPE_CONTROL_CS_STALL;
 236         }
 237         if (mode & EMIT_INVALIDATE) {
 238                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 239                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 240                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 244                 /*
 245                  * TLB invalidate requires a post-sync write.
 246                  */
 247                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 248         }
 249
 250         cs = intel_ring_begin(req, 4);
 251         if (IS_ERR(cs))
 252                 return PTR_ERR(cs);
 253
 254         *cs++ = GFX_OP_PIPE_CONTROL(4);
 255         *cs++ = flags;
 256         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 257         *cs++ = 0;
 258         intel_ring_advance(req, cs);
 259
 260         return 0;
 261 }
 262
 263 static int
 264 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 265 {
 266         u32 *cs;
 267
 268         cs = intel_ring_begin(req, 4);
 269         if (IS_ERR(cs))
 270                 return PTR_ERR(cs);
 271
 272         *cs++ = GFX_OP_PIPE_CONTROL(4);
 273         *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
 274         *cs++ = 0;
 275         *cs++ = 0;
 276         intel_ring_advance(req, cs);
 277
 278         return 0;
 279 }
 280
 281 static int
 282 gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
 283 {
 284         u32 scratch_addr =
 285                 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES;
 286         u32 *cs, flags = 0;
 287
 288         /*
 289          * Ensure that any following seqno writes only happen when the render
 290          * cache is indeed flushed.
 291          *
 292          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 293          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 294          * don't try to be clever and just set it unconditionally.
 295          */
 296         flags |= PIPE_CONTROL_CS_STALL;
 297
 298         /* Just flush everything.  Experiments have shown that reducing the
 299          * number of bits based on the write domains has little performance
 300          * impact.
 301          */
 302         if (mode & EMIT_FLUSH) {
 303                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 304                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 305                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 306                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 307         }
 308         if (mode & EMIT_INVALIDATE) {
 309                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 310                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 311                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 312                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 313                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 314                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 315                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 316                 /*
 317                  * TLB invalidate requires a post-sync write.
 318                  */
 319                 flags |= PIPE_CONTROL_QW_WRITE;
 320                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 321
 322                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 323
 324                 /* Workaround: we must issue a pipe_control with CS-stall bit
 325                  * set before a pipe_control command that has the state cache
 326                  * invalidate bit set. */
 327                 gen7_render_ring_cs_stall_wa(req);
 328         }
 329
 330         cs = intel_ring_begin(req, 4);
 331         if (IS_ERR(cs))
 332                 return PTR_ERR(cs);
 333
 334         *cs++ = GFX_OP_PIPE_CONTROL(4);
 335         *cs++ = flags;
 336         *cs++ = scratch_addr;
 337         *cs++ = 0;
 338         intel_ring_advance(req, cs);
 339
 340         return 0;
 341 }
 342
 343 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 344 {
 345         struct drm_i915_private *dev_priv = engine->i915;
 346         u32 addr;
 347
 348         addr = dev_priv->status_page_dmah->busaddr;
 349         if (INTEL_GEN(dev_priv) >= 4)
 350                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 351         I915_WRITE(HWS_PGA, addr);
 352 }
 353
 354 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 355 {
 356         struct drm_i915_private *dev_priv = engine->i915;
 357         i915_reg_t mmio;
 358
 359         /* The ring status page addresses are no longer next to the rest of
 360          * the ring registers as of gen7.
 361          */
 362         if (IS_GEN7(dev_priv)) {
 363                 switch (engine->id) {
 364                 /*
 365                  * No more rings exist on Gen7. Default case is only to shut up
 366                  * gcc switch check warning.
 367                  */
 368                 default:
 369                         GEM_BUG_ON(engine->id);
 370                 case RCS:
 371                         mmio = RENDER_HWS_PGA_GEN7;
 372                         break;
 373                 case BCS:
 374                         mmio = BLT_HWS_PGA_GEN7;
 375                         break;
 376                 case VCS:
 377                         mmio = BSD_HWS_PGA_GEN7;
 378                         break;
 379                 case VECS:
 380                         mmio = VEBOX_HWS_PGA_GEN7;
 381                         break;
 382                 }
 383         } else if (IS_GEN6(dev_priv)) {
 384                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 385         } else {
 386                 mmio = RING_HWS_PGA(engine->mmio_base);
 387         }
 388
 389         if (INTEL_GEN(dev_priv) >= 6)
 390                 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
 391
 392         I915_WRITE(mmio, engine->status_page.ggtt_offset);
 393         POSTING_READ(mmio);
 394
 395         /* Flush the TLB for this page */
 396         if (IS_GEN(dev_priv, 6, 7)) {
 397                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 398
 399                 /* ring should be idle before issuing a sync flush*/
 400                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 401
 402                 I915_WRITE(reg,
 403                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 404                                               INSTPM_SYNC_FLUSH));
 405                 if (intel_wait_for_register(dev_priv,
 406                                             reg, INSTPM_SYNC_FLUSH, 0,
 407                                             1000))
 408                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 409                                   engine->name);
 410         }
 411 }
 412
 413 static bool stop_ring(struct intel_engine_cs *engine)
 414 {
 415         struct drm_i915_private *dev_priv = engine->i915;
 416
 417         if (INTEL_GEN(dev_priv) > 2) {
 418                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 419                 if (intel_wait_for_register(dev_priv,
 420                                             RING_MI_MODE(engine->mmio_base),
 421                                             MODE_IDLE,
 422                                             MODE_IDLE,
 423                                             1000)) {
 424                         DRM_ERROR("%s : timed out trying to stop ring\n",
 425                                   engine->name);
 426                         /* Sometimes we observe that the idle flag is not
 427                          * set even though the ring is empty. So double
 428                          * check before giving up.
 429                          */
 430                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 431                                 return false;
 432                 }
 433         }
 434
 435         I915_WRITE_HEAD(engine, I915_READ_TAIL(engine));
 436
 437         I915_WRITE_HEAD(engine, 0);
 438         I915_WRITE_TAIL(engine, 0);
 439
 440         /* The ring must be empty before it is disabled */
 441         I915_WRITE_CTL(engine, 0);
 442
 443         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 444 }
 445
 446 static int init_ring_common(struct intel_engine_cs *engine)
 447 {
 448         struct drm_i915_private *dev_priv = engine->i915;
 449         struct intel_ring *ring = engine->buffer;
 450         int ret = 0;
 451
 452         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 453
 454         if (!stop_ring(engine)) {
 455                 /* G45 ring initialization often fails to reset head to zero */
 456                 DRM_DEBUG_KMS("%s head not reset to zero "
 457                               "ctl %08x head %08x tail %08x start %08x\n",
 458                               engine->name,
 459                               I915_READ_CTL(engine),
 460                               I915_READ_HEAD(engine),
 461                               I915_READ_TAIL(engine),
 462                               I915_READ_START(engine));
 463
 464                 if (!stop_ring(engine)) {
 465                         DRM_ERROR("failed to set %s head to zero "
 466                                   "ctl %08x head %08x tail %08x start %08x\n",
 467                                   engine->name,
 468                                   I915_READ_CTL(engine),
 469                                   I915_READ_HEAD(engine),
 470                                   I915_READ_TAIL(engine),
 471                                   I915_READ_START(engine));
 472                         ret = -EIO;
 473                         goto out;
 474                 }
 475         }
 476
 477         if (HWS_NEEDS_PHYSICAL(dev_priv))
 478                 ring_setup_phys_status_page(engine);
 479         else
 480                 intel_ring_setup_status_page(engine);
 481
 482         intel_engine_reset_breadcrumbs(engine);
 483
 484         /* Enforce ordering by reading HEAD register back */
 485         I915_READ_HEAD(engine);
 486
 487         /* Initialize the ring. This must happen _after_ we've cleared the ring
 488          * registers with the above sequence (the readback of the HEAD registers
 489          * also enforces ordering), otherwise the hw might lose the new ring
 490          * register values. */
 491         I915_WRITE_START(engine, i915_ggtt_offset(ring->vma));
 492
 493         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 494         if (I915_READ_HEAD(engine))
 495                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 496                           engine->name, I915_READ_HEAD(engine));
 497
 498         intel_ring_update_space(ring);
 499         I915_WRITE_HEAD(engine, ring->head);
 500         I915_WRITE_TAIL(engine, ring->tail);
 501         (void)I915_READ_TAIL(engine);
 502
 503         I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID);
 504
 505         /* If the head is still not zero, the ring is dead */
 506         if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base),
 507                                     RING_VALID, RING_VALID,
 508                                     50)) {
 509                 DRM_ERROR("%s initialization failed "
 510                           "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",
 511                           engine->name,
 512                           I915_READ_CTL(engine),
 513                           I915_READ_CTL(engine) & RING_VALID,
 514                           I915_READ_HEAD(engine), ring->head,
 515                           I915_READ_TAIL(engine), ring->tail,
 516                           I915_READ_START(engine),
 517                           i915_ggtt_offset(ring->vma));
 518                 ret = -EIO;
 519                 goto out;
 520         }
 521
 522         intel_engine_init_hangcheck(engine);
 523
 524         if (INTEL_GEN(dev_priv) > 2)
 525                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 526
 527 out:
 528         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 529
 530         return ret;
 531 }
 532
 533 static void reset_ring_common(struct intel_engine_cs *engine,
 534                               struct drm_i915_gem_request *request)
 535 {
 536         /*
 537          * RC6 must be prevented until the reset is complete and the engine
 538          * reinitialised. If it occurs in the middle of this sequence, the
 539          * state written to/loaded from the power context is ill-defined (e.g.
 540          * the PP_BASE_DIR may be lost).
 541          */
 542         assert_forcewakes_active(engine->i915, FORCEWAKE_ALL);
 543
 544         /*
 545          * Try to restore the logical GPU state to match the continuation
 546          * of the request queue. If we skip the context/PD restore, then
 547          * the next request may try to execute assuming that its context
 548          * is valid and loaded on the GPU and so may try to access invalid
 549          * memory, prompting repeated GPU hangs.
 550          *
 551          * If the request was guilty, we still restore the logical state
 552          * in case the next request requires it (e.g. the aliasing ppgtt),
 553          * but skip over the hung batch.
 554          *
 555          * If the request was innocent, we try to replay the request with
 556          * the restored context.
 557          */
 558         if (request) {
 559                 struct drm_i915_private *dev_priv = request->i915;
 560                 struct intel_context *ce = &request->ctx->engine[engine->id];
 561                 struct i915_hw_ppgtt *ppgtt;
 562
 563                 if (ce->state) {
 564                         I915_WRITE(CCID,
 565                                    i915_ggtt_offset(ce->state) |
 566                                    BIT(8) /* must be set! */ |
 567                                    CCID_EXTENDED_STATE_SAVE |
 568                                    CCID_EXTENDED_STATE_RESTORE |
 569                                    CCID_EN);
 570                 }
 571
 572                 ppgtt = request->ctx->ppgtt ?: engine->i915->mm.aliasing_ppgtt;
 573                 if (ppgtt) {
 574                         u32 pd_offset = ppgtt->pd.base.ggtt_offset << 10;
 575
 576                         I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
 577                         I915_WRITE(RING_PP_DIR_BASE(engine), pd_offset);
 578
 579                         /* Wait for the PD reload to complete */
 580                         if (intel_wait_for_register(dev_priv,
 581                                                     RING_PP_DIR_BASE(engine),
 582                                                     BIT(0), 0,
 583                                                     10))
 584                                 DRM_ERROR("Wait for reload of ppgtt page-directory timed out\n");
 585
 586                         ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
 587                 }
 588
 589                 /* If the rq hung, jump to its breadcrumb and skip the batch */
 590                 if (request->fence.error == -EIO)
 591                         request->ring->head = request->postfix;
 592         } else {
 593                 engine->legacy_active_context = NULL;
 594                 engine->legacy_active_ppgtt = NULL;
 595         }
 596 }
 597
 598 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 599 {
 600         int ret;
 601
 602         ret = intel_ring_workarounds_emit(req);
 603         if (ret != 0)
 604                 return ret;
 605
 606         ret = i915_gem_render_state_emit(req);
 607         if (ret)
 608                 return ret;
 609
 610         return 0;
 611 }
 612
 613 static int init_render_ring(struct intel_engine_cs *engine)
 614 {
 615         struct drm_i915_private *dev_priv = engine->i915;
 616         int ret = init_ring_common(engine);
 617         if (ret)
 618                 return ret;
 619
 620         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
 621         if (IS_GEN(dev_priv, 4, 6))
 622                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 623
 624         /* We need to disable the AsyncFlip performance optimisations in order
 625          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 626          * programmed to '1' on all products.
 627          *
 628          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
 629          */
 630         if (IS_GEN(dev_priv, 6, 7))
 631                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 632
 633         /* Required for the hardware to program scanline values for waiting */
 634         /* WaEnableFlushTlbInvalidationMode:snb */
 635         if (IS_GEN6(dev_priv))
 636                 I915_WRITE(GFX_MODE,
 637                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
 638
 639         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
 640         if (IS_GEN7(dev_priv))
 641                 I915_WRITE(GFX_MODE_GEN7,
 642                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
 643                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 644
 645         if (IS_GEN6(dev_priv)) {
 646                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 647                  * "If this bit is set, STCunit will have LRA as replacement
 648                  *  policy. [...] This bit must be reset.  LRA replacement
 649                  *  policy is not supported."
 650                  */
 651                 I915_WRITE(CACHE_MODE_0,
 652                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 653         }
 654
 655         if (IS_GEN(dev_priv, 6, 7))
 656                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 657
 658         if (INTEL_INFO(dev_priv)->gen >= 6)
 659                 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 660
 661         return init_workarounds_ring(engine);
 662 }
 663
 664 static u32 *gen6_signal(struct drm_i915_gem_request *req, u32 *cs)
 665 {
 666         struct drm_i915_private *dev_priv = req->i915;
 667         struct intel_engine_cs *engine;
 668         enum intel_engine_id id;
 669         int num_rings = 0;
 670
 671         for_each_engine(engine, dev_priv, id) {
 672                 i915_reg_t mbox_reg;
 673
 674                 if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK))
 675                         continue;
 676
 677                 mbox_reg = req->engine->semaphore.mbox.signal[engine->hw_id];
 678                 if (i915_mmio_reg_valid(mbox_reg)) {
 679                         *cs++ = MI_LOAD_REGISTER_IMM(1);
 680                         *cs++ = i915_mmio_reg_offset(mbox_reg);
 681                         *cs++ = req->global_seqno;
 682                         num_rings++;
 683                 }
 684         }
 685         if (num_rings & 1)
 686                 *cs++ = MI_NOOP;
 687
 688         return cs;
 689 }
 690
 691 static void cancel_requests(struct intel_engine_cs *engine)
 692 {
 693         struct drm_i915_gem_request *request;
 694         unsigned long flags;
 695
 696         spin_lock_irqsave(&engine->timeline->lock, flags);
 697
 698         /* Mark all submitted requests as skipped. */
 699         list_for_each_entry(request, &engine->timeline->requests, link) {
 700                 GEM_BUG_ON(!request->global_seqno);
 701                 if (!i915_gem_request_completed(request))
 702                         dma_fence_set_error(&request->fence, -EIO);
 703         }
 704         /* Remaining _unready_ requests will be nop'ed when submitted */
 705
 706         spin_unlock_irqrestore(&engine->timeline->lock, flags);
 707 }
 708
 709 static void i9xx_submit_request(struct drm_i915_gem_request *request)
 710 {
 711         struct drm_i915_private *dev_priv = request->i915;
 712
 713         i915_gem_request_submit(request);
 714
 715         I915_WRITE_TAIL(request->engine,
 716                         intel_ring_set_tail(request->ring, request->tail));
 717 }
 718
 719 static void i9xx_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs)
 720 {
 721         *cs++ = MI_STORE_DWORD_INDEX;
 722         *cs++ = I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT;
 723         *cs++ = req->global_seqno;
 724         *cs++ = MI_USER_INTERRUPT;
 725
 726         req->tail = intel_ring_offset(req, cs);
 727         assert_ring_tail_valid(req->ring, req->tail);
 728 }
 729
 730 static const int i9xx_emit_breadcrumb_sz = 4;
 731
 732 /**
 733  * gen6_sema_emit_breadcrumb - Update the semaphore mailbox registers
 734  *
 735  * @request - request to write to the ring
 736  *
 737  * Update the mailbox registers in the *other* rings with the current seqno.
 738  * This acts like a signal in the canonical semaphore.
 739  */
 740 static void gen6_sema_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs)
 741 {
 742         return i9xx_emit_breadcrumb(req,
 743                                     req->engine->semaphore.signal(req, cs));
 744 }
 745
 746 static int
 747 gen6_ring_sync_to(struct drm_i915_gem_request *req,
 748                   struct drm_i915_gem_request *signal)
 749 {
 750         u32 dw1 = MI_SEMAPHORE_MBOX |
 751                   MI_SEMAPHORE_COMPARE |
 752                   MI_SEMAPHORE_REGISTER;
 753         u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->hw_id];
 754         u32 *cs;
 755
 756         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
 757
 758         cs = intel_ring_begin(req, 4);
 759         if (IS_ERR(cs))
 760                 return PTR_ERR(cs);
 761
 762         *cs++ = dw1 | wait_mbox;
 763         /* Throughout all of the GEM code, seqno passed implies our current
 764          * seqno is >= the last seqno executed. However for hardware the
 765          * comparison is strictly greater than.
 766          */
 767         *cs++ = signal->global_seqno - 1;
 768         *cs++ = 0;
 769         *cs++ = MI_NOOP;
 770         intel_ring_advance(req, cs);
 771
 772         return 0;
 773 }
 774
 775 static void
 776 gen5_seqno_barrier(struct intel_engine_cs *engine)
 777 {
 778         /* MI_STORE are internally buffered by the GPU and not flushed
 779          * either by MI_FLUSH or SyncFlush or any other combination of
 780          * MI commands.
 781          *
 782          * "Only the submission of the store operation is guaranteed.
 783          * The write result will be complete (coherent) some time later
 784          * (this is practically a finite period but there is no guaranteed
 785          * latency)."
 786          *
 787          * Empirically, we observe that we need a delay of at least 75us to
 788          * be sure that the seqno write is visible by the CPU.
 789          */
 790         usleep_range(125, 250);
 791 }
 792
 793 static void
 794 gen6_seqno_barrier(struct intel_engine_cs *engine)
 795 {
 796         struct drm_i915_private *dev_priv = engine->i915;
 797
 798         /* Workaround to force correct ordering between irq and seqno writes on
 799          * ivb (and maybe also on snb) by reading from a CS register (like
 800          * ACTHD) before reading the status page.
 801          *
 802          * Note that this effectively stalls the read by the time it takes to
 803          * do a memory transaction, which more or less ensures that the write
 804          * from the GPU has sufficient time to invalidate the CPU cacheline.
 805          * Alternatively we could delay the interrupt from the CS ring to give
 806          * the write time to land, but that would incur a delay after every
 807          * batch i.e. much more frequent than a delay when waiting for the
 808          * interrupt (with the same net latency).
 809          *
 810          * Also note that to prevent whole machine hangs on gen7, we have to
 811          * take the spinlock to guard against concurrent cacheline access.
 812          */
 813         spin_lock_irq(&dev_priv->uncore.lock);
 814         POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
 815         spin_unlock_irq(&dev_priv->uncore.lock);
 816 }
 817
 818 static void
 819 gen5_irq_enable(struct intel_engine_cs *engine)
 820 {
 821         gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask);
 822 }
 823
 824 static void
 825 gen5_irq_disable(struct intel_engine_cs *engine)
 826 {
 827         gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask);
 828 }
 829
 830 static void
 831 i9xx_irq_enable(struct intel_engine_cs *engine)
 832 {
 833         struct drm_i915_private *dev_priv = engine->i915;
 834
 835         dev_priv->irq_mask &= ~engine->irq_enable_mask;
 836         I915_WRITE(IMR, dev_priv->irq_mask);
 837         POSTING_READ_FW(RING_IMR(engine->mmio_base));
 838 }
 839
 840 static void
 841 i9xx_irq_disable(struct intel_engine_cs *engine)
 842 {
 843         struct drm_i915_private *dev_priv = engine->i915;
 844
 845         dev_priv->irq_mask |= engine->irq_enable_mask;
 846         I915_WRITE(IMR, dev_priv->irq_mask);
 847 }
 848
 849 static void
 850 i8xx_irq_enable(struct intel_engine_cs *engine)
 851 {
 852         struct drm_i915_private *dev_priv = engine->i915;
 853
 854         dev_priv->irq_mask &= ~engine->irq_enable_mask;
 855         I915_WRITE16(IMR, dev_priv->irq_mask);
 856         POSTING_READ16(RING_IMR(engine->mmio_base));
 857 }
 858
 859 static void
 860 i8xx_irq_disable(struct intel_engine_cs *engine)
 861 {
 862         struct drm_i915_private *dev_priv = engine->i915;
 863
 864         dev_priv->irq_mask |= engine->irq_enable_mask;
 865         I915_WRITE16(IMR, dev_priv->irq_mask);
 866 }
 867
 868 static int
 869 bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode)
 870 {
 871         u32 *cs;
 872
 873         cs = intel_ring_begin(req, 2);
 874         if (IS_ERR(cs))
 875                 return PTR_ERR(cs);
 876
 877         *cs++ = MI_FLUSH;
 878         *cs++ = MI_NOOP;
 879         intel_ring_advance(req, cs);
 880         return 0;
 881 }
 882
 883 static void
 884 gen6_irq_enable(struct intel_engine_cs *engine)
 885 {
 886         struct drm_i915_private *dev_priv = engine->i915;
 887
 888         I915_WRITE_IMR(engine,
 889                        ~(engine->irq_enable_mask |
 890                          engine->irq_keep_mask));
 891         gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
 892 }
 893
 894 static void
 895 gen6_irq_disable(struct intel_engine_cs *engine)
 896 {
 897         struct drm_i915_private *dev_priv = engine->i915;
 898
 899         I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 900         gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
 901 }
 902
 903 static void
 904 hsw_vebox_irq_enable(struct intel_engine_cs *engine)
 905 {
 906         struct drm_i915_private *dev_priv = engine->i915;
 907
 908         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
 909         gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask);
 910 }
 911
 912 static void
 913 hsw_vebox_irq_disable(struct intel_engine_cs *engine)
 914 {
 915         struct drm_i915_private *dev_priv = engine->i915;
 916
 917         I915_WRITE_IMR(engine, ~0);
 918         gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask);
 919 }
 920
 921 static int
 922 i965_emit_bb_start(struct drm_i915_gem_request *req,
 923                    u64 offset, u32 length,
 924                    unsigned int dispatch_flags)
 925 {
 926         u32 *cs;
 927
 928         cs = intel_ring_begin(req, 2);
 929         if (IS_ERR(cs))
 930                 return PTR_ERR(cs);
 931
 932         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags &
 933                 I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965);
 934         *cs++ = offset;
 935         intel_ring_advance(req, cs);
 936
 937         return 0;
 938 }
 939
 940 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
 941 #define I830_BATCH_LIMIT (256*1024)
 942 #define I830_TLB_ENTRIES (2)
 943 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
 944 static int
 945 i830_emit_bb_start(struct drm_i915_gem_request *req,
 946                    u64 offset, u32 len,
 947                    unsigned int dispatch_flags)
 948 {
 949         u32 *cs, cs_offset = i915_ggtt_offset(req->engine->scratch);
 950
 951         cs = intel_ring_begin(req, 6);
 952         if (IS_ERR(cs))
 953                 return PTR_ERR(cs);
 954
 955         /* Evict the invalid PTE TLBs */
 956         *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA;
 957         *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096;
 958         *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */
 959         *cs++ = cs_offset;
 960         *cs++ = 0xdeadbeef;
 961         *cs++ = MI_NOOP;
 962         intel_ring_advance(req, cs);
 963
 964         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
 965                 if (len > I830_BATCH_LIMIT)
 966                         return -ENOSPC;
 967
 968                 cs = intel_ring_begin(req, 6 + 2);
 969                 if (IS_ERR(cs))
 970                         return PTR_ERR(cs);
 971
 972                 /* Blit the batch (which has now all relocs applied) to the
 973                  * stable batch scratch bo area (so that the CS never
 974                  * stumbles over its tlb invalidation bug) ...
 975                  */
 976                 *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA;
 977                 *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096;
 978                 *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096;
 979                 *cs++ = cs_offset;
 980                 *cs++ = 4096;
 981                 *cs++ = offset;
 982
 983                 *cs++ = MI_FLUSH;
 984                 *cs++ = MI_NOOP;
 985                 intel_ring_advance(req, cs);
 986
 987                 /* ... and execute it. */
 988                 offset = cs_offset;
 989         }
 990
 991         cs = intel_ring_begin(req, 2);
 992         if (IS_ERR(cs))
 993                 return PTR_ERR(cs);
 994
 995         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
 996         *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
 997                 MI_BATCH_NON_SECURE);
 998         intel_ring_advance(req, cs);
 999
1000         return 0;
1001 }
1002
1003 static int
1004 i915_emit_bb_start(struct drm_i915_gem_request *req,
1005                    u64 offset, u32 len,
1006                    unsigned int dispatch_flags)
1007 {
1008         u32 *cs;
1009
1010         cs = intel_ring_begin(req, 2);
1011         if (IS_ERR(cs))
1012                 return PTR_ERR(cs);
1013
1014         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
1015         *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
1016                 MI_BATCH_NON_SECURE);
1017         intel_ring_advance(req, cs);
1018
1019         return 0;
1020 }
1021
1022
1023
1024 int intel_ring_pin(struct intel_ring *ring,
1025                    struct drm_i915_private *i915,
1026                    unsigned int offset_bias)
1027 {
1028         enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
1029         struct i915_vma *vma = ring->vma;
1030         unsigned int flags;
1031         void *addr;
1032         int ret;
1033
1034         GEM_BUG_ON(ring->vaddr);
1035
1036
1037         flags = PIN_GLOBAL;
1038         if (offset_bias)
1039                 flags |= PIN_OFFSET_BIAS | offset_bias;
1040         if (vma->obj->stolen)
1041                 flags |= PIN_MAPPABLE;
1042
1043         if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1044                 if (flags & PIN_MAPPABLE || map == I915_MAP_WC)
1045                         ret = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1046                 else
1047                         ret = i915_gem_object_set_to_cpu_domain(vma->obj, true);
1048                 if (unlikely(ret))
1049                         return ret;
1050         }
1051
1052         ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags);
1053         if (unlikely(ret))
1054                 return ret;
1055
1056         if (i915_vma_is_map_and_fenceable(vma))
1057                 addr = (void __force *)i915_vma_pin_iomap(vma);
1058         else
1059                 addr = i915_gem_object_pin_map(vma->obj, map);
1060         if (IS_ERR(addr))
1061                 goto err;
1062
1063         vma->obj->pin_global++;
1064
1065         ring->vaddr = addr;
1066         return 0;
1067
1068 err:
1069         i915_vma_unpin(vma);
1070         return PTR_ERR(addr);
1071 }
1072
1073 void intel_ring_reset(struct intel_ring *ring, u32 tail)
1074 {
1075         GEM_BUG_ON(!list_empty(&ring->request_list));
1076         ring->tail = tail;
1077         ring->head = tail;
1078         ring->emit = tail;
1079         intel_ring_update_space(ring);
1080 }
1081
1082 void intel_ring_unpin(struct intel_ring *ring)
1083 {
1084         GEM_BUG_ON(!ring->vma);
1085         GEM_BUG_ON(!ring->vaddr);
1086
1087         /* Discard any unused bytes beyond that submitted to hw. */
1088         intel_ring_reset(ring, ring->tail);
1089
1090         if (i915_vma_is_map_and_fenceable(ring->vma))
1091                 i915_vma_unpin_iomap(ring->vma);
1092         else
1093                 i915_gem_object_unpin_map(ring->vma->obj);
1094         ring->vaddr = NULL;
1095
1096         ring->vma->obj->pin_global--;
1097         i915_vma_unpin(ring->vma);
1098 }
1099
1100 static struct i915_vma *
1101 intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
1102 {
1103         struct drm_i915_gem_object *obj;
1104         struct i915_vma *vma;
1105
1106         obj = i915_gem_object_create_stolen(dev_priv, size);
1107         if (!obj)
1108                 obj = i915_gem_object_create_internal(dev_priv, size);
1109         if (IS_ERR(obj))
1110                 return ERR_CAST(obj);
1111
1112         /* mark ring buffers as read-only from GPU side by default */
1113         obj->gt_ro = 1;
1114
1115         vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
1116         if (IS_ERR(vma))
1117                 goto err;
1118
1119         return vma;
1120
1121 err:
1122         i915_gem_object_put(obj);
1123         return vma;
1124 }
1125
1126 struct intel_ring *
1127 intel_engine_create_ring(struct intel_engine_cs *engine, int size)
1128 {
1129         struct intel_ring *ring;
1130         struct i915_vma *vma;
1131
1132         GEM_BUG_ON(!is_power_of_2(size));
1133         GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES);
1134
1135         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1136         if (!ring)
1137                 return ERR_PTR(-ENOMEM);
1138
1139         INIT_LIST_HEAD(&ring->request_list);
1140
1141         ring->size = size;
1142         /* Workaround an erratum on the i830 which causes a hang if
1143          * the TAIL pointer points to within the last 2 cachelines
1144          * of the buffer.
1145          */
1146         ring->effective_size = size;
1147         if (IS_I830(engine->i915) || IS_I845G(engine->i915))
1148                 ring->effective_size -= 2 * CACHELINE_BYTES;
1149
1150         intel_ring_update_space(ring);
1151
1152         vma = intel_ring_create_vma(engine->i915, size);
1153         if (IS_ERR(vma)) {
1154                 kfree(ring);
1155                 return ERR_CAST(vma);
1156         }
1157         ring->vma = vma;
1158
1159         return ring;
1160 }
1161
1162 void
1163 intel_ring_free(struct intel_ring *ring)
1164 {
1165         struct drm_i915_gem_object *obj = ring->vma->obj;
1166
1167         i915_vma_close(ring->vma);
1168         __i915_gem_object_release_unless_active(obj);
1169
1170         kfree(ring);
1171 }
1172
1173 static int context_pin(struct i915_gem_context *ctx)
1174 {
1175         struct i915_vma *vma = ctx->engine[RCS].state;
1176         int ret;
1177
1178         /*
1179          * Clear this page out of any CPU caches for coherent swap-in/out.
1180          * We only want to do this on the first bind so that we do not stall
1181          * on an active context (which by nature is already on the GPU).
1182          */
1183         if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1184                 ret = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1185                 if (ret)
1186                         return ret;
1187         }
1188
1189         return i915_vma_pin(vma, 0, I915_GTT_MIN_ALIGNMENT,
1190                             PIN_GLOBAL | PIN_HIGH);
1191 }
1192
1193 static struct i915_vma *
1194 alloc_context_vma(struct intel_engine_cs *engine)
1195 {
1196         struct drm_i915_private *i915 = engine->i915;
1197         struct drm_i915_gem_object *obj;
1198         struct i915_vma *vma;
1199         int err;
1200
1201         obj = i915_gem_object_create(i915, engine->context_size);
1202         if (IS_ERR(obj))
1203                 return ERR_CAST(obj);
1204
1205         if (engine->default_state) {
1206                 void *defaults, *vaddr;
1207
1208                 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
1209                 if (IS_ERR(vaddr)) {
1210                         err = PTR_ERR(vaddr);
1211                         goto err_obj;
1212                 }
1213
1214                 defaults = i915_gem_object_pin_map(engine->default_state,
1215                                                    I915_MAP_WB);
1216                 if (IS_ERR(defaults)) {
1217                         err = PTR_ERR(defaults);
1218                         goto err_map;
1219                 }
1220
1221                 memcpy(vaddr, defaults, engine->context_size);
1222
1223                 i915_gem_object_unpin_map(engine->default_state);
1224                 i915_gem_object_unpin_map(obj);
1225         }
1226
1227         /*
1228          * Try to make the context utilize L3 as well as LLC.
1229          *
1230          * On VLV we don't have L3 controls in the PTEs so we
1231          * shouldn't touch the cache level, especially as that
1232          * would make the object snooped which might have a
1233          * negative performance impact.
1234          *
1235          * Snooping is required on non-llc platforms in execlist
1236          * mode, but since all GGTT accesses use PAT entry 0 we
1237          * get snooping anyway regardless of cache_level.
1238          *
1239          * This is only applicable for Ivy Bridge devices since
1240          * later platforms don't have L3 control bits in the PTE.
1241          */
1242         if (IS_IVYBRIDGE(i915)) {
1243                 /* Ignore any error, regard it as a simple optimisation */
1244                 i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
1245         }
1246
1247         vma = i915_vma_instance(obj, &i915->ggtt.base, NULL);
1248         if (IS_ERR(vma)) {
1249                 err = PTR_ERR(vma);
1250                 goto err_obj;
1251         }
1252
1253         return vma;
1254
1255 err_map:
1256         i915_gem_object_unpin_map(obj);
1257 err_obj:
1258         i915_gem_object_put(obj);
1259         return ERR_PTR(err);
1260 }
1261
1262 static struct intel_ring *
1263 intel_ring_context_pin(struct intel_engine_cs *engine,
1264                        struct i915_gem_context *ctx)
1265 {
1266         struct intel_context *ce = &ctx->engine[engine->id];
1267         int ret;
1268
1269         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1270
1271         if (likely(ce->pin_count++))
1272                 goto out;
1273         GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
1274
1275         if (!ce->state && engine->context_size) {
1276                 struct i915_vma *vma;
1277
1278                 vma = alloc_context_vma(engine);
1279                 if (IS_ERR(vma)) {
1280                         ret = PTR_ERR(vma);
1281                         goto err;
1282                 }
1283
1284                 ce->state = vma;
1285         }
1286
1287         if (ce->state) {
1288                 ret = context_pin(ctx);
1289                 if (ret)
1290                         goto err;
1291
1292                 ce->state->obj->pin_global++;
1293         }
1294
1295         i915_gem_context_get(ctx);
1296
1297 out:
1298         /* One ringbuffer to rule them all */
1299         return engine->buffer;
1300
1301 err:
1302         ce->pin_count = 0;
1303         return ERR_PTR(ret);
1304 }
1305
1306 static void intel_ring_context_unpin(struct intel_engine_cs *engine,
1307                                      struct i915_gem_context *ctx)
1308 {
1309         struct intel_context *ce = &ctx->engine[engine->id];
1310
1311         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1312         GEM_BUG_ON(ce->pin_count == 0);
1313
1314         if (--ce->pin_count)
1315                 return;
1316
1317         if (ce->state) {
1318                 ce->state->obj->pin_global--;
1319                 i915_vma_unpin(ce->state);
1320         }
1321
1322         i915_gem_context_put(ctx);
1323 }
1324
1325 static int intel_init_ring_buffer(struct intel_engine_cs *engine)
1326 {
1327         struct intel_ring *ring;
1328         int err;
1329
1330         intel_engine_setup_common(engine);
1331
1332         err = intel_engine_init_common(engine);
1333         if (err)
1334                 goto err;
1335
1336         ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE);
1337         if (IS_ERR(ring)) {
1338                 err = PTR_ERR(ring);
1339                 goto err;
1340         }
1341
1342         /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
1343         err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE);
1344         if (err)
1345                 goto err_ring;
1346
1347         GEM_BUG_ON(engine->buffer);
1348         engine->buffer = ring;
1349
1350         return 0;
1351
1352 err_ring:
1353         intel_ring_free(ring);
1354 err:
1355         intel_engine_cleanup_common(engine);
1356         return err;
1357 }
1358
1359 void intel_engine_cleanup(struct intel_engine_cs *engine)
1360 {
1361         struct drm_i915_private *dev_priv = engine->i915;
1362
1363         WARN_ON(INTEL_GEN(dev_priv) > 2 &&
1364                 (I915_READ_MODE(engine) & MODE_IDLE) == 0);
1365
1366         intel_ring_unpin(engine->buffer);
1367         intel_ring_free(engine->buffer);
1368
1369         if (engine->cleanup)
1370                 engine->cleanup(engine);
1371
1372         intel_engine_cleanup_common(engine);
1373
1374         dev_priv->engine[engine->id] = NULL;
1375         kfree(engine);
1376 }
1377
1378 void intel_legacy_submission_resume(struct drm_i915_private *dev_priv)
1379 {
1380         struct intel_engine_cs *engine;
1381         enum intel_engine_id id;
1382
1383         /* Restart from the beginning of the rings for convenience */
1384         for_each_engine(engine, dev_priv, id)
1385                 intel_ring_reset(engine->buffer, 0);
1386 }
1387
1388 static inline int mi_set_context(struct drm_i915_gem_request *rq, u32 flags)
1389 {
1390         struct drm_i915_private *i915 = rq->i915;
1391         struct intel_engine_cs *engine = rq->engine;
1392         enum intel_engine_id id;
1393         const int num_rings =
1394                 /* Use an extended w/a on gen7 if signalling from other rings */
1395                 (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
1396                 INTEL_INFO(i915)->num_rings - 1 :
1397                 0;
1398         int len;
1399         u32 *cs;
1400
1401         flags |= MI_MM_SPACE_GTT;
1402         if (IS_HASWELL(i915))
1403                 /* These flags are for resource streamer on HSW+ */
1404                 flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
1405         else
1406                 flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
1407
1408         len = 4;
1409         if (IS_GEN7(i915))
1410                 len += 2 + (num_rings ? 4*num_rings + 6 : 0);
1411
1412         cs = intel_ring_begin(rq, len);
1413         if (IS_ERR(cs))
1414                 return PTR_ERR(cs);
1415
1416         /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
1417         if (IS_GEN7(i915)) {
1418                 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1419                 if (num_rings) {
1420                         struct intel_engine_cs *signaller;
1421
1422                         *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
1423                         for_each_engine(signaller, i915, id) {
1424                                 if (signaller == engine)
1425                                         continue;
1426
1427                                 *cs++ = i915_mmio_reg_offset(
1428                                            RING_PSMI_CTL(signaller->mmio_base));
1429                                 *cs++ = _MASKED_BIT_ENABLE(
1430                                                 GEN6_PSMI_SLEEP_MSG_DISABLE);
1431                         }
1432                 }
1433         }
1434
1435         *cs++ = MI_NOOP;
1436         *cs++ = MI_SET_CONTEXT;
1437         *cs++ = i915_ggtt_offset(rq->ctx->engine[RCS].state) | flags;
1438         /*
1439          * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
1440          * WaMiSetContext_Hang:snb,ivb,vlv
1441          */
1442         *cs++ = MI_NOOP;
1443
1444         if (IS_GEN7(i915)) {
1445                 if (num_rings) {
1446                         struct intel_engine_cs *signaller;
1447                         i915_reg_t last_reg = {}; /* keep gcc quiet */
1448
1449                         *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
1450                         for_each_engine(signaller, i915, id) {
1451                                 if (signaller == engine)
1452                                         continue;
1453
1454                                 last_reg = RING_PSMI_CTL(signaller->mmio_base);
1455                                 *cs++ = i915_mmio_reg_offset(last_reg);
1456                                 *cs++ = _MASKED_BIT_DISABLE(
1457                                                 GEN6_PSMI_SLEEP_MSG_DISABLE);
1458                         }
1459
1460                         /* Insert a delay before the next switch! */
1461                         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1462                         *cs++ = i915_mmio_reg_offset(last_reg);
1463                         *cs++ = i915_ggtt_offset(engine->scratch);
1464                         *cs++ = MI_NOOP;
1465                 }
1466                 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1467         }
1468
1469         intel_ring_advance(rq, cs);
1470
1471         return 0;
1472 }
1473
1474 static int remap_l3(struct drm_i915_gem_request *rq, int slice)
1475 {
1476         u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
1477         int i;
1478
1479         if (!remap_info)
1480                 return 0;
1481
1482         cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2);
1483         if (IS_ERR(cs))
1484                 return PTR_ERR(cs);
1485
1486         /*
1487          * Note: We do not worry about the concurrent register cacheline hang
1488          * here because no other code should access these registers other than
1489          * at initialization time.
1490          */
1491         *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
1492         for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
1493                 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
1494                 *cs++ = remap_info[i];
1495         }
1496         *cs++ = MI_NOOP;
1497         intel_ring_advance(rq, cs);
1498
1499         return 0;
1500 }
1501
1502 static int switch_context(struct drm_i915_gem_request *rq)
1503 {
1504         struct intel_engine_cs *engine = rq->engine;
1505         struct i915_gem_context *to_ctx = rq->ctx;
1506         struct i915_hw_ppgtt *to_mm =
1507                 to_ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
1508         struct i915_gem_context *from_ctx = engine->legacy_active_context;
1509         struct i915_hw_ppgtt *from_mm = engine->legacy_active_ppgtt;
1510         u32 hw_flags = 0;
1511         int ret, i;
1512
1513         lockdep_assert_held(&rq->i915->drm.struct_mutex);
1514         GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
1515
1516         if (to_mm != from_mm ||
1517             (to_mm && intel_engine_flag(engine) & to_mm->pd_dirty_rings)) {
1518                 trace_switch_mm(engine, to_ctx);
1519                 ret = to_mm->switch_mm(to_mm, rq);
1520                 if (ret)
1521                         goto err;
1522
1523                 to_mm->pd_dirty_rings &= ~intel_engine_flag(engine);
1524                 engine->legacy_active_ppgtt = to_mm;
1525                 hw_flags = MI_FORCE_RESTORE;
1526         }
1527
1528         if (to_ctx->engine[engine->id].state &&
1529             (to_ctx != from_ctx || hw_flags & MI_FORCE_RESTORE)) {
1530                 GEM_BUG_ON(engine->id != RCS);
1531
1532                 /*
1533                  * The kernel context(s) is treated as pure scratch and is not
1534                  * expected to retain any state (as we sacrifice it during
1535                  * suspend and on resume it may be corrupted). This is ok,
1536                  * as nothing actually executes using the kernel context; it
1537                  * is purely used for flushing user contexts.
1538                  */
1539                 if (i915_gem_context_is_kernel(to_ctx))
1540                         hw_flags = MI_RESTORE_INHIBIT;
1541
1542                 ret = mi_set_context(rq, hw_flags);
1543                 if (ret)
1544                         goto err_mm;
1545
1546                 engine->legacy_active_context = to_ctx;
1547         }
1548
1549         if (to_ctx->remap_slice) {
1550                 for (i = 0; i < MAX_L3_SLICES; i++) {
1551                         if (!(to_ctx->remap_slice & BIT(i)))
1552                                 continue;
1553
1554                         ret = remap_l3(rq, i);
1555                         if (ret)
1556                                 goto err_ctx;
1557                 }
1558
1559                 to_ctx->remap_slice = 0;
1560         }
1561
1562         return 0;
1563
1564 err_ctx:
1565         engine->legacy_active_context = from_ctx;
1566 err_mm:
1567         engine->legacy_active_ppgtt = from_mm;
1568 err:
1569         return ret;
1570 }
1571
1572 static int ring_request_alloc(struct drm_i915_gem_request *request)
1573 {
1574         int ret;
1575
1576         GEM_BUG_ON(!request->ctx->engine[request->engine->id].pin_count);
1577
1578         /* Flush enough space to reduce the likelihood of waiting after
1579          * we start building the request - in which case we will just
1580          * have to repeat work.
1581          */
1582         request->reserved_space += LEGACY_REQUEST_SIZE;
1583
1584         ret = intel_ring_wait_for_space(request->ring, request->reserved_space);
1585         if (ret)
1586                 return ret;
1587
1588         ret = switch_context(request);
1589         if (ret)
1590                 return ret;
1591
1592         request->reserved_space -= LEGACY_REQUEST_SIZE;
1593         return 0;
1594 }
1595
1596 static noinline int wait_for_space(struct intel_ring *ring, unsigned int bytes)
1597 {
1598         struct drm_i915_gem_request *target;
1599         long timeout;
1600
1601         lockdep_assert_held(&ring->vma->vm->i915->drm.struct_mutex);
1602
1603         if (intel_ring_update_space(ring) >= bytes)
1604                 return 0;
1605
1606         list_for_each_entry(target, &ring->request_list, ring_link) {
1607                 /* Would completion of this request free enough space? */
1608                 if (bytes <= __intel_ring_space(target->postfix,
1609                                                 ring->emit, ring->size))
1610                         break;
1611         }
1612
1613         if (WARN_ON(&target->ring_link == &ring->request_list))
1614                 return -ENOSPC;
1615
1616         timeout = i915_wait_request(target,
1617                                     I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED,
1618                                     MAX_SCHEDULE_TIMEOUT);
1619         if (timeout < 0)
1620                 return timeout;
1621
1622         i915_gem_request_retire_upto(target);
1623
1624         intel_ring_update_space(ring);
1625         GEM_BUG_ON(ring->space < bytes);
1626         return 0;
1627 }
1628
1629 int intel_ring_wait_for_space(struct intel_ring *ring, unsigned int bytes)
1630 {
1631         GEM_BUG_ON(bytes > ring->effective_size);
1632         if (unlikely(bytes > ring->effective_size - ring->emit))
1633                 bytes += ring->size - ring->emit;
1634
1635         if (unlikely(bytes > ring->space)) {
1636                 int ret = wait_for_space(ring, bytes);
1637                 if (unlikely(ret))
1638                         return ret;
1639         }
1640
1641         GEM_BUG_ON(ring->space < bytes);
1642         return 0;
1643 }
1644
1645 u32 *intel_ring_begin(struct drm_i915_gem_request *req,
1646                       unsigned int num_dwords)
1647 {
1648         struct intel_ring *ring = req->ring;
1649         const unsigned int remain_usable = ring->effective_size - ring->emit;
1650         const unsigned int bytes = num_dwords * sizeof(u32);
1651         unsigned int need_wrap = 0;
1652         unsigned int total_bytes;
1653         u32 *cs;
1654
1655         /* Packets must be qword aligned. */
1656         GEM_BUG_ON(num_dwords & 1);
1657
1658         total_bytes = bytes + req->reserved_space;
1659         GEM_BUG_ON(total_bytes > ring->effective_size);
1660
1661         if (unlikely(total_bytes > remain_usable)) {
1662                 const int remain_actual = ring->size - ring->emit;
1663
1664                 if (bytes > remain_usable) {
1665                         /*
1666                          * Not enough space for the basic request. So need to
1667                          * flush out the remainder and then wait for
1668                          * base + reserved.
1669                          */
1670                         total_bytes += remain_actual;
1671                         need_wrap = remain_actual | 1;
1672                 } else  {
1673                         /*
1674                          * The base request will fit but the reserved space
1675                          * falls off the end. So we don't need an immediate
1676                          * wrap and only need to effectively wait for the
1677                          * reserved size from the start of ringbuffer.
1678                          */
1679                         total_bytes = req->reserved_space + remain_actual;
1680                 }
1681         }
1682
1683         if (unlikely(total_bytes > ring->space)) {
1684                 int ret;
1685
1686                 /*
1687                  * Space is reserved in the ringbuffer for finalising the
1688                  * request, as that cannot be allowed to fail. During request
1689                  * finalisation, reserved_space is set to 0 to stop the
1690                  * overallocation and the assumption is that then we never need
1691                  * to wait (which has the risk of failing with EINTR).
1692                  *
1693                  * See also i915_gem_request_alloc() and i915_add_request().
1694                  */
1695                 GEM_BUG_ON(!req->reserved_space);
1696
1697                 ret = wait_for_space(ring, total_bytes);
1698                 if (unlikely(ret))
1699                         return ERR_PTR(ret);
1700         }
1701
1702         if (unlikely(need_wrap)) {
1703                 need_wrap &= ~1;
1704                 GEM_BUG_ON(need_wrap > ring->space);
1705                 GEM_BUG_ON(ring->emit + need_wrap > ring->size);
1706
1707                 /* Fill the tail with MI_NOOP */
1708                 memset(ring->vaddr + ring->emit, 0, need_wrap);
1709                 ring->emit = 0;
1710                 ring->space -= need_wrap;
1711         }
1712
1713         GEM_BUG_ON(ring->emit > ring->size - bytes);
1714         GEM_BUG_ON(ring->space < bytes);
1715         cs = ring->vaddr + ring->emit;
1716         GEM_DEBUG_EXEC(memset(cs, POISON_INUSE, bytes));
1717         ring->emit += bytes;
1718         ring->space -= bytes;
1719
1720         return cs;
1721 }
1722
1723 /* Align the ring tail to a cacheline boundary */
1724 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
1725 {
1726         int num_dwords =
1727                 (req->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
1728         u32 *cs;
1729
1730         if (num_dwords == 0)
1731                 return 0;
1732
1733         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
1734         cs = intel_ring_begin(req, num_dwords);
1735         if (IS_ERR(cs))
1736                 return PTR_ERR(cs);
1737
1738         while (num_dwords--)
1739                 *cs++ = MI_NOOP;
1740
1741         intel_ring_advance(req, cs);
1742
1743         return 0;
1744 }
1745
1746 static void gen6_bsd_submit_request(struct drm_i915_gem_request *request)
1747 {
1748         struct drm_i915_private *dev_priv = request->i915;
1749
1750         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1751
1752        /* Every tail move must follow the sequence below */
1753
1754         /* Disable notification that the ring is IDLE. The GT
1755          * will then assume that it is busy and bring it out of rc6.
1756          */
1757         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
1758                       _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1759
1760         /* Clear the context id. Here be magic! */
1761         I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0);
1762
1763         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1764         if (__intel_wait_for_register_fw(dev_priv,
1765                                          GEN6_BSD_SLEEP_PSMI_CONTROL,
1766                                          GEN6_BSD_SLEEP_INDICATOR,
1767                                          0,
1768                                          1000, 0, NULL))
1769                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1770
1771         /* Now that the ring is fully powered up, update the tail */
1772         i9xx_submit_request(request);
1773
1774         /* Let the ring send IDLE messages to the GT again,
1775          * and so let it sleep to conserve power when idle.
1776          */
1777         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
1778                       _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1779
1780         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1781 }
1782
1783 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode)
1784 {
1785         u32 cmd, *cs;
1786
1787         cs = intel_ring_begin(req, 4);
1788         if (IS_ERR(cs))
1789                 return PTR_ERR(cs);
1790
1791         cmd = MI_FLUSH_DW;
1792
1793         /* We always require a command barrier so that subsequent
1794          * commands, such as breadcrumb interrupts, are strictly ordered
1795          * wrt the contents of the write cache being flushed to memory
1796          * (and thus being coherent from the CPU).
1797          */
1798         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1799
1800         /*
1801          * Bspec vol 1c.5 - video engine command streamer:
1802          * "If ENABLED, all TLBs will be invalidated once the flush
1803          * operation is complete. This bit is only valid when the
1804          * Post-Sync Operation field is a value of 1h or 3h."
1805          */
1806         if (mode & EMIT_INVALIDATE)
1807                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1808
1809         *cs++ = cmd;
1810         *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1811         *cs++ = 0;
1812         *cs++ = MI_NOOP;
1813         intel_ring_advance(req, cs);
1814         return 0;
1815 }
1816
1817 static int
1818 hsw_emit_bb_start(struct drm_i915_gem_request *req,
1819                   u64 offset, u32 len,
1820                   unsigned int dispatch_flags)
1821 {
1822         u32 *cs;
1823
1824         cs = intel_ring_begin(req, 2);
1825         if (IS_ERR(cs))
1826                 return PTR_ERR(cs);
1827
1828         *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
1829                 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
1830                 (dispatch_flags & I915_DISPATCH_RS ?
1831                 MI_BATCH_RESOURCE_STREAMER : 0);
1832         /* bit0-7 is the length on GEN6+ */
1833         *cs++ = offset;
1834         intel_ring_advance(req, cs);
1835
1836         return 0;
1837 }
1838
1839 static int
1840 gen6_emit_bb_start(struct drm_i915_gem_request *req,
1841                    u64 offset, u32 len,
1842                    unsigned int dispatch_flags)
1843 {
1844         u32 *cs;
1845
1846         cs = intel_ring_begin(req, 2);
1847         if (IS_ERR(cs))
1848                 return PTR_ERR(cs);
1849
1850         *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
1851                 0 : MI_BATCH_NON_SECURE_I965);
1852         /* bit0-7 is the length on GEN6+ */
1853         *cs++ = offset;
1854         intel_ring_advance(req, cs);
1855
1856         return 0;
1857 }
1858
1859 /* Blitter support (SandyBridge+) */
1860
1861 static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode)
1862 {
1863         u32 cmd, *cs;
1864
1865         cs = intel_ring_begin(req, 4);
1866         if (IS_ERR(cs))
1867                 return PTR_ERR(cs);
1868
1869         cmd = MI_FLUSH_DW;
1870
1871         /* We always require a command barrier so that subsequent
1872          * commands, such as breadcrumb interrupts, are strictly ordered
1873          * wrt the contents of the write cache being flushed to memory
1874          * (and thus being coherent from the CPU).
1875          */
1876         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1877
1878         /*
1879          * Bspec vol 1c.3 - blitter engine command streamer:
1880          * "If ENABLED, all TLBs will be invalidated once the flush
1881          * operation is complete. This bit is only valid when the
1882          * Post-Sync Operation field is a value of 1h or 3h."
1883          */
1884         if (mode & EMIT_INVALIDATE)
1885                 cmd |= MI_INVALIDATE_TLB;
1886         *cs++ = cmd;
1887         *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1888         *cs++ = 0;
1889         *cs++ = MI_NOOP;
1890         intel_ring_advance(req, cs);
1891
1892         return 0;
1893 }
1894
1895 static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
1896                                        struct intel_engine_cs *engine)
1897 {
1898         int i;
1899
1900         if (!HAS_LEGACY_SEMAPHORES(dev_priv))
1901                 return;
1902
1903         GEM_BUG_ON(INTEL_GEN(dev_priv) < 6);
1904         engine->semaphore.sync_to = gen6_ring_sync_to;
1905         engine->semaphore.signal = gen6_signal;
1906
1907         /*
1908          * The current semaphore is only applied on pre-gen8
1909          * platform.  And there is no VCS2 ring on the pre-gen8
1910          * platform. So the semaphore between RCS and VCS2 is
1911          * initialized as INVALID.
1912          */
1913         for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) {
1914                 static const struct {
1915                         u32 wait_mbox;
1916                         i915_reg_t mbox_reg;
1917                 } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = {
1918                         [RCS_HW] = {
1919                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RV,  .mbox_reg = GEN6_VRSYNC },
1920                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RB,  .mbox_reg = GEN6_BRSYNC },
1921                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
1922                         },
1923                         [VCS_HW] = {
1924                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VR,  .mbox_reg = GEN6_RVSYNC },
1925                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VB,  .mbox_reg = GEN6_BVSYNC },
1926                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
1927                         },
1928                         [BCS_HW] = {
1929                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BR,  .mbox_reg = GEN6_RBSYNC },
1930                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BV,  .mbox_reg = GEN6_VBSYNC },
1931                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
1932                         },
1933                         [VECS_HW] = {
1934                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
1935                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
1936                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
1937                         },
1938                 };
1939                 u32 wait_mbox;
1940                 i915_reg_t mbox_reg;
1941
1942                 if (i == engine->hw_id) {
1943                         wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
1944                         mbox_reg = GEN6_NOSYNC;
1945                 } else {
1946                         wait_mbox = sem_data[engine->hw_id][i].wait_mbox;
1947                         mbox_reg = sem_data[engine->hw_id][i].mbox_reg;
1948                 }
1949
1950                 engine->semaphore.mbox.wait[i] = wait_mbox;
1951                 engine->semaphore.mbox.signal[i] = mbox_reg;
1952         }
1953 }
1954
1955 static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
1956                                 struct intel_engine_cs *engine)
1957 {
1958         engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift;
1959
1960         if (INTEL_GEN(dev_priv) >= 6) {
1961                 engine->irq_enable = gen6_irq_enable;
1962                 engine->irq_disable = gen6_irq_disable;
1963                 engine->irq_seqno_barrier = gen6_seqno_barrier;
1964         } else if (INTEL_GEN(dev_priv) >= 5) {
1965                 engine->irq_enable = gen5_irq_enable;
1966                 engine->irq_disable = gen5_irq_disable;
1967                 engine->irq_seqno_barrier = gen5_seqno_barrier;
1968         } else if (INTEL_GEN(dev_priv) >= 3) {
1969                 engine->irq_enable = i9xx_irq_enable;
1970                 engine->irq_disable = i9xx_irq_disable;
1971         } else {
1972                 engine->irq_enable = i8xx_irq_enable;
1973                 engine->irq_disable = i8xx_irq_disable;
1974         }
1975 }
1976
1977 static void i9xx_set_default_submission(struct intel_engine_cs *engine)
1978 {
1979         engine->submit_request = i9xx_submit_request;
1980         engine->cancel_requests = cancel_requests;
1981
1982         engine->park = NULL;
1983         engine->unpark = NULL;
1984 }
1985
1986 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
1987 {
1988         i9xx_set_default_submission(engine);
1989         engine->submit_request = gen6_bsd_submit_request;
1990 }
1991
1992 static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
1993                                       struct intel_engine_cs *engine)
1994 {
1995         /* gen8+ are only supported with execlists */
1996         GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8);
1997
1998         intel_ring_init_irq(dev_priv, engine);
1999         intel_ring_init_semaphores(dev_priv, engine);
2000
2001         engine->init_hw = init_ring_common;
2002         engine->reset_hw = reset_ring_common;
2003
2004         engine->context_pin = intel_ring_context_pin;
2005         engine->context_unpin = intel_ring_context_unpin;
2006
2007         engine->request_alloc = ring_request_alloc;
2008
2009         engine->emit_breadcrumb = i9xx_emit_breadcrumb;
2010         engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz;
2011         if (HAS_LEGACY_SEMAPHORES(dev_priv)) {
2012                 int num_rings;
2013
2014                 engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
2015
2016                 num_rings = INTEL_INFO(dev_priv)->num_rings - 1;
2017                 engine->emit_breadcrumb_sz += num_rings * 3;
2018                 if (num_rings & 1)
2019                         engine->emit_breadcrumb_sz++;
2020         }
2021
2022         engine->set_default_submission = i9xx_set_default_submission;
2023
2024         if (INTEL_GEN(dev_priv) >= 6)
2025                 engine->emit_bb_start = gen6_emit_bb_start;
2026         else if (INTEL_GEN(dev_priv) >= 4)
2027                 engine->emit_bb_start = i965_emit_bb_start;
2028         else if (IS_I830(dev_priv) || IS_I845G(dev_priv))
2029                 engine->emit_bb_start = i830_emit_bb_start;
2030         else
2031                 engine->emit_bb_start = i915_emit_bb_start;
2032 }
2033
2034 int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
2035 {
2036         struct drm_i915_private *dev_priv = engine->i915;
2037         int ret;
2038
2039         intel_ring_default_vfuncs(dev_priv, engine);
2040
2041         if (HAS_L3_DPF(dev_priv))
2042                 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2043
2044         if (INTEL_GEN(dev_priv) >= 6) {
2045                 engine->init_context = intel_rcs_ctx_init;
2046                 engine->emit_flush = gen7_render_ring_flush;
2047                 if (IS_GEN6(dev_priv))
2048                         engine->emit_flush = gen6_render_ring_flush;
2049         } else if (IS_GEN5(dev_priv)) {
2050                 engine->emit_flush = gen4_render_ring_flush;
2051         } else {
2052                 if (INTEL_GEN(dev_priv) < 4)
2053                         engine->emit_flush = gen2_render_ring_flush;
2054                 else
2055                         engine->emit_flush = gen4_render_ring_flush;
2056                 engine->irq_enable_mask = I915_USER_INTERRUPT;
2057         }
2058
2059         if (IS_HASWELL(dev_priv))
2060                 engine->emit_bb_start = hsw_emit_bb_start;
2061
2062         engine->init_hw = init_render_ring;
2063
2064         ret = intel_init_ring_buffer(engine);
2065         if (ret)
2066                 return ret;
2067
2068         if (INTEL_GEN(dev_priv) >= 6) {
2069                 ret = intel_engine_create_scratch(engine, PAGE_SIZE);
2070                 if (ret)
2071                         return ret;
2072         } else if (HAS_BROKEN_CS_TLB(dev_priv)) {
2073                 ret = intel_engine_create_scratch(engine, I830_WA_SIZE);
2074                 if (ret)
2075                         return ret;
2076         }
2077
2078         return 0;
2079 }
2080
2081 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
2082 {
2083         struct drm_i915_private *dev_priv = engine->i915;
2084
2085         intel_ring_default_vfuncs(dev_priv, engine);
2086
2087         if (INTEL_GEN(dev_priv) >= 6) {
2088                 /* gen6 bsd needs a special wa for tail updates */
2089                 if (IS_GEN6(dev_priv))
2090                         engine->set_default_submission = gen6_bsd_set_default_submission;
2091                 engine->emit_flush = gen6_bsd_ring_flush;
2092                 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2093         } else {
2094                 engine->mmio_base = BSD_RING_BASE;
2095                 engine->emit_flush = bsd_ring_flush;
2096                 if (IS_GEN5(dev_priv))
2097                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2098                 else
2099                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2100         }
2101
2102         return intel_init_ring_buffer(engine);
2103 }
2104
2105 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
2106 {
2107         struct drm_i915_private *dev_priv = engine->i915;
2108
2109         intel_ring_default_vfuncs(dev_priv, engine);
2110
2111         engine->emit_flush = gen6_ring_flush;
2112         engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2113
2114         return intel_init_ring_buffer(engine);
2115 }
2116
2117 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
2118 {
2119         struct drm_i915_private *dev_priv = engine->i915;
2120
2121         intel_ring_default_vfuncs(dev_priv, engine);
2122
2123         engine->emit_flush = gen6_ring_flush;
2124         engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2125         engine->irq_enable = hsw_vebox_irq_enable;
2126         engine->irq_disable = hsw_vebox_irq_disable;
2127
2128         return intel_init_ring_buffer(engine);
2129 }