2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/device.h>
24 #include <linux/export.h>
25 #include <linux/err.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/uaccess.h>
30 #include <linux/compat.h>
31 #include <uapi/linux/kfd_ioctl.h>
32 #include <linux/time.h>
34 #include <linux/mman.h>
35 #include <asm/processor.h>
37 #include "kfd_device_queue_manager.h"
38 #include "kfd_dbgmgr.h"
40 static long kfd_ioctl(struct file *, unsigned int, unsigned long);
41 static int kfd_open(struct inode *, struct file *);
42 static int kfd_mmap(struct file *, struct vm_area_struct *);
44 static const char kfd_dev_name[] = "kfd";
46 static const struct file_operations kfd_fops = {
48 .unlocked_ioctl = kfd_ioctl,
49 .compat_ioctl = kfd_ioctl,
54 static int kfd_char_dev_major = -1;
55 static struct class *kfd_class;
56 struct device *kfd_device;
58 int kfd_chardev_init(void)
62 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops);
63 err = kfd_char_dev_major;
65 goto err_register_chrdev;
67 kfd_class = class_create(THIS_MODULE, kfd_dev_name);
68 err = PTR_ERR(kfd_class);
69 if (IS_ERR(kfd_class))
70 goto err_class_create;
72 kfd_device = device_create(kfd_class, NULL,
73 MKDEV(kfd_char_dev_major, 0),
75 err = PTR_ERR(kfd_device);
76 if (IS_ERR(kfd_device))
77 goto err_device_create;
82 class_destroy(kfd_class);
84 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
89 void kfd_chardev_exit(void)
91 device_destroy(kfd_class, MKDEV(kfd_char_dev_major, 0));
92 class_destroy(kfd_class);
93 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
96 struct device *kfd_chardev(void)
102 static int kfd_open(struct inode *inode, struct file *filep)
104 struct kfd_process *process;
105 bool is_32bit_user_mode;
107 if (iminor(inode) != 0)
110 is_32bit_user_mode = in_compat_syscall();
112 if (is_32bit_user_mode) {
114 "Process %d (32-bit) failed to open /dev/kfd\n"
115 "32-bit processes are not supported by amdkfd\n",
120 process = kfd_create_process(filep);
122 return PTR_ERR(process);
124 dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n",
125 process->pasid, process->is_32bit_user_mode);
130 static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
133 struct kfd_ioctl_get_version_args *args = data;
135 args->major_version = KFD_IOCTL_MAJOR_VERSION;
136 args->minor_version = KFD_IOCTL_MINOR_VERSION;
141 static int set_queue_properties_from_user(struct queue_properties *q_properties,
142 struct kfd_ioctl_create_queue_args *args)
144 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
145 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
149 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
150 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
154 if ((args->ring_base_address) &&
155 (!access_ok(VERIFY_WRITE,
156 (const void __user *) args->ring_base_address,
157 sizeof(uint64_t)))) {
158 pr_err("Can't access ring base address\n");
162 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
163 pr_err("Ring size must be a power of 2 or 0\n");
167 if (!access_ok(VERIFY_WRITE,
168 (const void __user *) args->read_pointer_address,
170 pr_err("Can't access read pointer\n");
174 if (!access_ok(VERIFY_WRITE,
175 (const void __user *) args->write_pointer_address,
177 pr_err("Can't access write pointer\n");
181 if (args->eop_buffer_address &&
182 !access_ok(VERIFY_WRITE,
183 (const void __user *) args->eop_buffer_address,
185 pr_debug("Can't access eop buffer");
189 if (args->ctx_save_restore_address &&
190 !access_ok(VERIFY_WRITE,
191 (const void __user *) args->ctx_save_restore_address,
193 pr_debug("Can't access ctx save restore buffer");
197 q_properties->is_interop = false;
198 q_properties->queue_percent = args->queue_percentage;
199 q_properties->priority = args->queue_priority;
200 q_properties->queue_address = args->ring_base_address;
201 q_properties->queue_size = args->ring_size;
202 q_properties->read_ptr = (uint32_t *) args->read_pointer_address;
203 q_properties->write_ptr = (uint32_t *) args->write_pointer_address;
204 q_properties->eop_ring_buffer_address = args->eop_buffer_address;
205 q_properties->eop_ring_buffer_size = args->eop_buffer_size;
206 q_properties->ctx_save_restore_area_address =
207 args->ctx_save_restore_address;
208 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size;
209 q_properties->ctl_stack_size = args->ctl_stack_size;
210 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE ||
211 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
212 q_properties->type = KFD_QUEUE_TYPE_COMPUTE;
213 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA)
214 q_properties->type = KFD_QUEUE_TYPE_SDMA;
218 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
219 q_properties->format = KFD_QUEUE_FORMAT_AQL;
221 q_properties->format = KFD_QUEUE_FORMAT_PM4;
223 pr_debug("Queue Percentage: %d, %d\n",
224 q_properties->queue_percent, args->queue_percentage);
226 pr_debug("Queue Priority: %d, %d\n",
227 q_properties->priority, args->queue_priority);
229 pr_debug("Queue Address: 0x%llX, 0x%llX\n",
230 q_properties->queue_address, args->ring_base_address);
232 pr_debug("Queue Size: 0x%llX, %u\n",
233 q_properties->queue_size, args->ring_size);
235 pr_debug("Queue r/w Pointers: %p, %p\n",
236 q_properties->read_ptr,
237 q_properties->write_ptr);
239 pr_debug("Queue Format: %d\n", q_properties->format);
241 pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address);
243 pr_debug("Queue CTX save area: 0x%llX\n",
244 q_properties->ctx_save_restore_area_address);
249 static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
252 struct kfd_ioctl_create_queue_args *args = data;
255 unsigned int queue_id;
256 struct kfd_process_device *pdd;
257 struct queue_properties q_properties;
259 memset(&q_properties, 0, sizeof(struct queue_properties));
261 pr_debug("Creating queue ioctl\n");
263 err = set_queue_properties_from_user(&q_properties, args);
267 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id);
268 dev = kfd_device_by_id(args->gpu_id);
270 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
274 mutex_lock(&p->mutex);
276 pdd = kfd_bind_process_to_device(dev, p);
279 goto err_bind_process;
282 pr_debug("Creating queue for PASID %d on gpu 0x%x\n",
286 err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id);
288 goto err_create_queue;
290 args->queue_id = queue_id;
293 /* Return gpu_id as doorbell offset for mmap usage */
294 args->doorbell_offset = (KFD_MMAP_DOORBELL_MASK | args->gpu_id);
295 args->doorbell_offset <<= PAGE_SHIFT;
297 mutex_unlock(&p->mutex);
299 pr_debug("Queue id %d was created successfully\n", args->queue_id);
301 pr_debug("Ring buffer address == 0x%016llX\n",
302 args->ring_base_address);
304 pr_debug("Read ptr address == 0x%016llX\n",
305 args->read_pointer_address);
307 pr_debug("Write ptr address == 0x%016llX\n",
308 args->write_pointer_address);
314 mutex_unlock(&p->mutex);
318 static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p,
322 struct kfd_ioctl_destroy_queue_args *args = data;
324 pr_debug("Destroying queue id %d for pasid %d\n",
328 mutex_lock(&p->mutex);
330 retval = pqm_destroy_queue(&p->pqm, args->queue_id);
332 mutex_unlock(&p->mutex);
336 static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,
340 struct kfd_ioctl_update_queue_args *args = data;
341 struct queue_properties properties;
343 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
344 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
348 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
349 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
353 if ((args->ring_base_address) &&
354 (!access_ok(VERIFY_WRITE,
355 (const void __user *) args->ring_base_address,
356 sizeof(uint64_t)))) {
357 pr_err("Can't access ring base address\n");
361 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
362 pr_err("Ring size must be a power of 2 or 0\n");
366 properties.queue_address = args->ring_base_address;
367 properties.queue_size = args->ring_size;
368 properties.queue_percent = args->queue_percentage;
369 properties.priority = args->queue_priority;
371 pr_debug("Updating queue id %d for pasid %d\n",
372 args->queue_id, p->pasid);
374 mutex_lock(&p->mutex);
376 retval = pqm_update_queue(&p->pqm, args->queue_id, &properties);
378 mutex_unlock(&p->mutex);
383 static int kfd_ioctl_set_memory_policy(struct file *filep,
384 struct kfd_process *p, void *data)
386 struct kfd_ioctl_set_memory_policy_args *args = data;
389 struct kfd_process_device *pdd;
390 enum cache_policy default_policy, alternate_policy;
392 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT
393 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
397 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT
398 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
402 dev = kfd_device_by_id(args->gpu_id);
406 mutex_lock(&p->mutex);
408 pdd = kfd_bind_process_to_device(dev, p);
414 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT)
415 ? cache_policy_coherent : cache_policy_noncoherent;
418 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT)
419 ? cache_policy_coherent : cache_policy_noncoherent;
421 if (!dev->dqm->ops.set_cache_memory_policy(dev->dqm,
425 (void __user *)args->alternate_aperture_base,
426 args->alternate_aperture_size))
430 mutex_unlock(&p->mutex);
435 static int kfd_ioctl_set_trap_handler(struct file *filep,
436 struct kfd_process *p, void *data)
438 struct kfd_ioctl_set_trap_handler_args *args = data;
441 struct kfd_process_device *pdd;
443 dev = kfd_device_by_id(args->gpu_id);
447 mutex_lock(&p->mutex);
449 pdd = kfd_bind_process_to_device(dev, p);
455 if (dev->dqm->ops.set_trap_handler(dev->dqm,
462 mutex_unlock(&p->mutex);
467 static int kfd_ioctl_dbg_register(struct file *filep,
468 struct kfd_process *p, void *data)
470 struct kfd_ioctl_dbg_register_args *args = data;
472 struct kfd_dbgmgr *dbgmgr_ptr;
473 struct kfd_process_device *pdd;
477 dev = kfd_device_by_id(args->gpu_id);
481 if (dev->device_info->asic_family == CHIP_CARRIZO) {
482 pr_debug("kfd_ioctl_dbg_register not supported on CZ\n");
486 mutex_lock(&p->mutex);
487 mutex_lock(kfd_get_dbgmgr_mutex());
490 * make sure that we have pdd, if this the first queue created for
493 pdd = kfd_bind_process_to_device(dev, p);
495 status = PTR_ERR(pdd);
500 /* In case of a legal call, we have no dbgmgr yet */
501 create_ok = kfd_dbgmgr_create(&dbgmgr_ptr, dev);
503 status = kfd_dbgmgr_register(dbgmgr_ptr, p);
505 kfd_dbgmgr_destroy(dbgmgr_ptr);
507 dev->dbgmgr = dbgmgr_ptr;
510 pr_debug("debugger already registered\n");
515 mutex_unlock(kfd_get_dbgmgr_mutex());
516 mutex_unlock(&p->mutex);
521 static int kfd_ioctl_dbg_unregister(struct file *filep,
522 struct kfd_process *p, void *data)
524 struct kfd_ioctl_dbg_unregister_args *args = data;
528 dev = kfd_device_by_id(args->gpu_id);
529 if (!dev || !dev->dbgmgr)
532 if (dev->device_info->asic_family == CHIP_CARRIZO) {
533 pr_debug("kfd_ioctl_dbg_unregister not supported on CZ\n");
537 mutex_lock(kfd_get_dbgmgr_mutex());
539 status = kfd_dbgmgr_unregister(dev->dbgmgr, p);
541 kfd_dbgmgr_destroy(dev->dbgmgr);
545 mutex_unlock(kfd_get_dbgmgr_mutex());
551 * Parse and generate variable size data structure for address watch.
552 * Total size of the buffer and # watch points is limited in order
553 * to prevent kernel abuse. (no bearing to the much smaller HW limitation
554 * which is enforced by dbgdev module)
555 * please also note that the watch address itself are not "copied from user",
556 * since it be set into the HW in user mode values.
559 static int kfd_ioctl_dbg_address_watch(struct file *filep,
560 struct kfd_process *p, void *data)
562 struct kfd_ioctl_dbg_address_watch_args *args = data;
564 struct dbg_address_watch_info aw_info;
565 unsigned char *args_buff;
567 void __user *cmd_from_user;
568 uint64_t watch_mask_value = 0;
569 unsigned int args_idx = 0;
571 memset((void *) &aw_info, 0, sizeof(struct dbg_address_watch_info));
573 dev = kfd_device_by_id(args->gpu_id);
577 if (dev->device_info->asic_family == CHIP_CARRIZO) {
578 pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n");
582 cmd_from_user = (void __user *) args->content_ptr;
584 /* Validate arguments */
586 if ((args->buf_size_in_bytes > MAX_ALLOWED_AW_BUFF_SIZE) ||
587 (args->buf_size_in_bytes <= sizeof(*args) + sizeof(int) * 2) ||
588 (cmd_from_user == NULL))
591 /* this is the actual buffer to work with */
592 args_buff = memdup_user(cmd_from_user,
593 args->buf_size_in_bytes - sizeof(*args));
594 if (IS_ERR(args_buff))
595 return PTR_ERR(args_buff);
599 aw_info.num_watch_points = *((uint32_t *)(&args_buff[args_idx]));
600 args_idx += sizeof(aw_info.num_watch_points);
602 aw_info.watch_mode = (enum HSA_DBG_WATCH_MODE *) &args_buff[args_idx];
603 args_idx += sizeof(enum HSA_DBG_WATCH_MODE) * aw_info.num_watch_points;
606 * set watch address base pointer to point on the array base
609 aw_info.watch_address = (uint64_t *) &args_buff[args_idx];
611 /* skip over the addresses buffer */
612 args_idx += sizeof(aw_info.watch_address) * aw_info.num_watch_points;
614 if (args_idx >= args->buf_size_in_bytes - sizeof(*args)) {
619 watch_mask_value = (uint64_t) args_buff[args_idx];
621 if (watch_mask_value > 0) {
623 * There is an array of masks.
624 * set watch mask base pointer to point on the array base
627 aw_info.watch_mask = (uint64_t *) &args_buff[args_idx];
629 /* skip over the masks buffer */
630 args_idx += sizeof(aw_info.watch_mask) *
631 aw_info.num_watch_points;
633 /* just the NULL mask, set to NULL and skip over it */
634 aw_info.watch_mask = NULL;
635 args_idx += sizeof(aw_info.watch_mask);
638 if (args_idx >= args->buf_size_in_bytes - sizeof(args)) {
643 /* Currently HSA Event is not supported for DBG */
644 aw_info.watch_event = NULL;
646 mutex_lock(kfd_get_dbgmgr_mutex());
648 status = kfd_dbgmgr_address_watch(dev->dbgmgr, &aw_info);
650 mutex_unlock(kfd_get_dbgmgr_mutex());
658 /* Parse and generate fixed size data structure for wave control */
659 static int kfd_ioctl_dbg_wave_control(struct file *filep,
660 struct kfd_process *p, void *data)
662 struct kfd_ioctl_dbg_wave_control_args *args = data;
664 struct dbg_wave_control_info wac_info;
665 unsigned char *args_buff;
666 uint32_t computed_buff_size;
668 void __user *cmd_from_user;
669 unsigned int args_idx = 0;
671 memset((void *) &wac_info, 0, sizeof(struct dbg_wave_control_info));
673 /* we use compact form, independent of the packing attribute value */
674 computed_buff_size = sizeof(*args) +
675 sizeof(wac_info.mode) +
676 sizeof(wac_info.operand) +
677 sizeof(wac_info.dbgWave_msg.DbgWaveMsg) +
678 sizeof(wac_info.dbgWave_msg.MemoryVA) +
679 sizeof(wac_info.trapId);
681 dev = kfd_device_by_id(args->gpu_id);
685 if (dev->device_info->asic_family == CHIP_CARRIZO) {
686 pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n");
690 /* input size must match the computed "compact" size */
691 if (args->buf_size_in_bytes != computed_buff_size) {
692 pr_debug("size mismatch, computed : actual %u : %u\n",
693 args->buf_size_in_bytes, computed_buff_size);
697 cmd_from_user = (void __user *) args->content_ptr;
699 if (cmd_from_user == NULL)
702 /* copy the entire buffer from user */
704 args_buff = memdup_user(cmd_from_user,
705 args->buf_size_in_bytes - sizeof(*args));
706 if (IS_ERR(args_buff))
707 return PTR_ERR(args_buff);
709 /* move ptr to the start of the "pay-load" area */
710 wac_info.process = p;
712 wac_info.operand = *((enum HSA_DBG_WAVEOP *)(&args_buff[args_idx]));
713 args_idx += sizeof(wac_info.operand);
715 wac_info.mode = *((enum HSA_DBG_WAVEMODE *)(&args_buff[args_idx]));
716 args_idx += sizeof(wac_info.mode);
718 wac_info.trapId = *((uint32_t *)(&args_buff[args_idx]));
719 args_idx += sizeof(wac_info.trapId);
721 wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value =
722 *((uint32_t *)(&args_buff[args_idx]));
723 wac_info.dbgWave_msg.MemoryVA = NULL;
725 mutex_lock(kfd_get_dbgmgr_mutex());
727 pr_debug("Calling dbg manager process %p, operand %u, mode %u, trapId %u, message %u\n",
728 wac_info.process, wac_info.operand,
729 wac_info.mode, wac_info.trapId,
730 wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value);
732 status = kfd_dbgmgr_wave_control(dev->dbgmgr, &wac_info);
734 pr_debug("Returned status of dbg manager is %ld\n", status);
736 mutex_unlock(kfd_get_dbgmgr_mutex());
743 static int kfd_ioctl_get_clock_counters(struct file *filep,
744 struct kfd_process *p, void *data)
746 struct kfd_ioctl_get_clock_counters_args *args = data;
748 struct timespec64 time;
750 dev = kfd_device_by_id(args->gpu_id);
754 /* Reading GPU clock counter from KGD */
755 args->gpu_clock_counter =
756 dev->kfd2kgd->get_gpu_clock_counter(dev->kgd);
758 /* No access to rdtsc. Using raw monotonic time */
759 getrawmonotonic64(&time);
760 args->cpu_clock_counter = (uint64_t)timespec64_to_ns(&time);
762 get_monotonic_boottime64(&time);
763 args->system_clock_counter = (uint64_t)timespec64_to_ns(&time);
765 /* Since the counter is in nano-seconds we use 1GHz frequency */
766 args->system_clock_freq = 1000000000;
772 static int kfd_ioctl_get_process_apertures(struct file *filp,
773 struct kfd_process *p, void *data)
775 struct kfd_ioctl_get_process_apertures_args *args = data;
776 struct kfd_process_device_apertures *pAperture;
777 struct kfd_process_device *pdd;
779 dev_dbg(kfd_device, "get apertures for PASID %d", p->pasid);
781 args->num_of_nodes = 0;
783 mutex_lock(&p->mutex);
785 /*if the process-device list isn't empty*/
786 if (kfd_has_process_device_data(p)) {
787 /* Run over all pdd of the process */
788 pdd = kfd_get_first_process_device_data(p);
791 &args->process_apertures[args->num_of_nodes];
792 pAperture->gpu_id = pdd->dev->id;
793 pAperture->lds_base = pdd->lds_base;
794 pAperture->lds_limit = pdd->lds_limit;
795 pAperture->gpuvm_base = pdd->gpuvm_base;
796 pAperture->gpuvm_limit = pdd->gpuvm_limit;
797 pAperture->scratch_base = pdd->scratch_base;
798 pAperture->scratch_limit = pdd->scratch_limit;
801 "node id %u\n", args->num_of_nodes);
803 "gpu id %u\n", pdd->dev->id);
805 "lds_base %llX\n", pdd->lds_base);
807 "lds_limit %llX\n", pdd->lds_limit);
809 "gpuvm_base %llX\n", pdd->gpuvm_base);
811 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
813 "scratch_base %llX\n", pdd->scratch_base);
815 "scratch_limit %llX\n", pdd->scratch_limit);
817 args->num_of_nodes++;
819 pdd = kfd_get_next_process_device_data(p, pdd);
820 } while (pdd && (args->num_of_nodes < NUM_OF_SUPPORTED_GPUS));
823 mutex_unlock(&p->mutex);
828 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p,
831 struct kfd_ioctl_create_event_args *args = data;
834 err = kfd_event_create(filp, p, args->event_type,
835 args->auto_reset != 0, args->node_id,
836 &args->event_id, &args->event_trigger_data,
837 &args->event_page_offset,
838 &args->event_slot_index);
843 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p,
846 struct kfd_ioctl_destroy_event_args *args = data;
848 return kfd_event_destroy(p, args->event_id);
851 static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p,
854 struct kfd_ioctl_set_event_args *args = data;
856 return kfd_set_event(p, args->event_id);
859 static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p,
862 struct kfd_ioctl_reset_event_args *args = data;
864 return kfd_reset_event(p, args->event_id);
867 static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p,
870 struct kfd_ioctl_wait_events_args *args = data;
873 err = kfd_wait_on_events(p, args->num_events,
874 (void __user *)args->events_ptr,
875 (args->wait_for_all != 0),
876 args->timeout, &args->wait_result);
880 static int kfd_ioctl_set_scratch_backing_va(struct file *filep,
881 struct kfd_process *p, void *data)
883 struct kfd_ioctl_set_scratch_backing_va_args *args = data;
884 struct kfd_process_device *pdd;
888 dev = kfd_device_by_id(args->gpu_id);
892 mutex_lock(&p->mutex);
894 pdd = kfd_bind_process_to_device(dev, p);
897 goto bind_process_to_device_fail;
900 pdd->qpd.sh_hidden_private_base = args->va_addr;
902 mutex_unlock(&p->mutex);
904 if (sched_policy == KFD_SCHED_POLICY_NO_HWS && pdd->qpd.vmid != 0)
905 dev->kfd2kgd->set_scratch_backing_va(
906 dev->kgd, args->va_addr, pdd->qpd.vmid);
910 bind_process_to_device_fail:
911 mutex_unlock(&p->mutex);
915 static int kfd_ioctl_get_tile_config(struct file *filep,
916 struct kfd_process *p, void *data)
918 struct kfd_ioctl_get_tile_config_args *args = data;
920 struct tile_config config;
923 dev = kfd_device_by_id(args->gpu_id);
927 dev->kfd2kgd->get_tile_config(dev->kgd, &config);
929 args->gb_addr_config = config.gb_addr_config;
930 args->num_banks = config.num_banks;
931 args->num_ranks = config.num_ranks;
933 if (args->num_tile_configs > config.num_tile_configs)
934 args->num_tile_configs = config.num_tile_configs;
935 err = copy_to_user((void __user *)args->tile_config_ptr,
936 config.tile_config_ptr,
937 args->num_tile_configs * sizeof(uint32_t));
939 args->num_tile_configs = 0;
943 if (args->num_macro_tile_configs > config.num_macro_tile_configs)
944 args->num_macro_tile_configs =
945 config.num_macro_tile_configs;
946 err = copy_to_user((void __user *)args->macro_tile_config_ptr,
947 config.macro_tile_config_ptr,
948 args->num_macro_tile_configs * sizeof(uint32_t));
950 args->num_macro_tile_configs = 0;
957 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
958 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
959 .cmd_drv = 0, .name = #ioctl}
962 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
963 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION,
964 kfd_ioctl_get_version, 0),
966 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE,
967 kfd_ioctl_create_queue, 0),
969 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE,
970 kfd_ioctl_destroy_queue, 0),
972 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY,
973 kfd_ioctl_set_memory_policy, 0),
975 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS,
976 kfd_ioctl_get_clock_counters, 0),
978 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES,
979 kfd_ioctl_get_process_apertures, 0),
981 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE,
982 kfd_ioctl_update_queue, 0),
984 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT,
985 kfd_ioctl_create_event, 0),
987 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT,
988 kfd_ioctl_destroy_event, 0),
990 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT,
991 kfd_ioctl_set_event, 0),
993 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT,
994 kfd_ioctl_reset_event, 0),
996 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS,
997 kfd_ioctl_wait_events, 0),
999 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER,
1000 kfd_ioctl_dbg_register, 0),
1002 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER,
1003 kfd_ioctl_dbg_unregister, 0),
1005 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH,
1006 kfd_ioctl_dbg_address_watch, 0),
1008 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL,
1009 kfd_ioctl_dbg_wave_control, 0),
1011 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA,
1012 kfd_ioctl_set_scratch_backing_va, 0),
1014 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG,
1015 kfd_ioctl_get_tile_config, 0),
1017 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER,
1018 kfd_ioctl_set_trap_handler, 0),
1021 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
1023 static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
1025 struct kfd_process *process;
1026 amdkfd_ioctl_t *func;
1027 const struct amdkfd_ioctl_desc *ioctl = NULL;
1028 unsigned int nr = _IOC_NR(cmd);
1029 char stack_kdata[128];
1031 unsigned int usize, asize;
1032 int retcode = -EINVAL;
1034 if (nr >= AMDKFD_CORE_IOCTL_COUNT)
1037 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) {
1040 ioctl = &amdkfd_ioctls[nr];
1042 amdkfd_size = _IOC_SIZE(ioctl->cmd);
1043 usize = asize = _IOC_SIZE(cmd);
1044 if (amdkfd_size > asize)
1045 asize = amdkfd_size;
1051 dev_dbg(kfd_device, "ioctl cmd 0x%x (#%d), arg 0x%lx\n", cmd, nr, arg);
1053 process = kfd_get_process(current);
1054 if (IS_ERR(process)) {
1055 dev_dbg(kfd_device, "no process\n");
1059 /* Do not trust userspace, use our own definition */
1062 if (unlikely(!func)) {
1063 dev_dbg(kfd_device, "no function\n");
1068 if (cmd & (IOC_IN | IOC_OUT)) {
1069 if (asize <= sizeof(stack_kdata)) {
1070 kdata = stack_kdata;
1072 kdata = kmalloc(asize, GFP_KERNEL);
1079 memset(kdata + usize, 0, asize - usize);
1083 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) {
1087 } else if (cmd & IOC_OUT) {
1088 memset(kdata, 0, usize);
1091 retcode = func(filep, process, kdata);
1094 if (copy_to_user((void __user *)arg, kdata, usize) != 0)
1099 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n",
1100 task_pid_nr(current), cmd, nr);
1102 if (kdata != stack_kdata)
1106 dev_dbg(kfd_device, "ret = %d\n", retcode);
1111 static int kfd_mmap(struct file *filp, struct vm_area_struct *vma)
1113 struct kfd_process *process;
1115 process = kfd_get_process(current);
1116 if (IS_ERR(process))
1117 return PTR_ERR(process);
1119 if ((vma->vm_pgoff & KFD_MMAP_DOORBELL_MASK) ==
1120 KFD_MMAP_DOORBELL_MASK) {
1121 vma->vm_pgoff = vma->vm_pgoff ^ KFD_MMAP_DOORBELL_MASK;
1122 return kfd_doorbell_mmap(process, vma);
1123 } else if ((vma->vm_pgoff & KFD_MMAP_EVENTS_MASK) ==
1124 KFD_MMAP_EVENTS_MASK) {
1125 vma->vm_pgoff = vma->vm_pgoff ^ KFD_MMAP_EVENTS_MASK;
1126 return kfd_event_mmap(process, vma);
1127 } else if ((vma->vm_pgoff & KFD_MMAP_RESERVED_MEM_MASK) ==
1128 KFD_MMAP_RESERVED_MEM_MASK) {
1129 vma->vm_pgoff = vma->vm_pgoff ^ KFD_MMAP_RESERVED_MEM_MASK;
1130 return kfd_reserved_mem_mmap(process, vma);