drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #define SWSMU_CODE_LAYER_L1
  24
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_smu.h"
  30 #include "smu_internal.h"
  31 #include "atom.h"
  32 #include "arcturus_ppt.h"
  33 #include "navi10_ppt.h"
  34 #include "sienna_cichlid_ppt.h"
  35 #include "renoir_ppt.h"
  36 #include "vangogh_ppt.h"
  37 #include "amd_pcie.h"
  38
  39 /*
  40  * DO NOT use these for err/warn/info/debug messages.
  41  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  42  * They are more MGPU friendly.
  43  */
  44 #undef pr_err
  45 #undef pr_warn
  46 #undef pr_info
  47 #undef pr_debug
  48
  49 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
  50 {
  51         size_t size = 0;
  52
  53         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  54                 return -EOPNOTSUPP;
  55
  56         mutex_lock(&smu->mutex);
  57
  58         size = smu_get_pp_feature_mask(smu, buf);
  59
  60         mutex_unlock(&smu->mutex);
  61
  62         return size;
  63 }
  64
  65 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
  66 {
  67         int ret = 0;
  68
  69         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  70                 return -EOPNOTSUPP;
  71
  72         mutex_lock(&smu->mutex);
  73
  74         ret = smu_set_pp_feature_mask(smu, new_mask);
  75
  76         mutex_unlock(&smu->mutex);
  77
  78         return ret;
  79 }
  80
  81 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
  82 {
  83         int ret = 0;
  84         struct smu_context *smu = &adev->smu;
  85
  86         if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status)
  87                 *value = smu_get_gfx_off_status(smu);
  88         else
  89                 ret = -EINVAL;
  90
  91         return ret;
  92 }
  93
  94 int smu_set_soft_freq_range(struct smu_context *smu,
  95                             enum smu_clk_type clk_type,
  96                             uint32_t min,
  97                             uint32_t max)
  98 {
  99         int ret = 0;
 100
 101         mutex_lock(&smu->mutex);
 102
 103         if (smu->ppt_funcs->set_soft_freq_limited_range)
 104                 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
 105                                                                   clk_type,
 106                                                                   min,
 107                                                                   max);
 108
 109         mutex_unlock(&smu->mutex);
 110
 111         return ret;
 112 }
 113
 114 int smu_get_dpm_freq_range(struct smu_context *smu,
 115                            enum smu_clk_type clk_type,
 116                            uint32_t *min,
 117                            uint32_t *max)
 118 {
 119         int ret = 0;
 120
 121         if (!min && !max)
 122                 return -EINVAL;
 123
 124         mutex_lock(&smu->mutex);
 125
 126         if (smu->ppt_funcs->get_dpm_ultimate_freq)
 127                 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
 128                                                             clk_type,
 129                                                             min,
 130                                                             max);
 131
 132         mutex_unlock(&smu->mutex);
 133
 134         return ret;
 135 }
 136
 137 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu,
 138                                          bool enable)
 139 {
 140         struct smu_power_context *smu_power = &smu->smu_power;
 141         struct smu_power_gate *power_gate = &smu_power->power_gate;
 142         int ret = 0;
 143
 144         if (!smu->ppt_funcs->dpm_set_vcn_enable)
 145                 return 0;
 146
 147         if (atomic_read(&power_gate->vcn_gated) ^ enable)
 148                 return 0;
 149
 150         ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
 151         if (!ret)
 152                 atomic_set(&power_gate->vcn_gated, !enable);
 153
 154         return ret;
 155 }
 156
 157 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
 158                                   bool enable)
 159 {
 160         struct smu_power_context *smu_power = &smu->smu_power;
 161         struct smu_power_gate *power_gate = &smu_power->power_gate;
 162         int ret = 0;
 163
 164         mutex_lock(&power_gate->vcn_gate_lock);
 165
 166         ret = smu_dpm_set_vcn_enable_locked(smu, enable);
 167
 168         mutex_unlock(&power_gate->vcn_gate_lock);
 169
 170         return ret;
 171 }
 172
 173 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu,
 174                                           bool enable)
 175 {
 176         struct smu_power_context *smu_power = &smu->smu_power;
 177         struct smu_power_gate *power_gate = &smu_power->power_gate;
 178         int ret = 0;
 179
 180         if (!smu->ppt_funcs->dpm_set_jpeg_enable)
 181                 return 0;
 182
 183         if (atomic_read(&power_gate->jpeg_gated) ^ enable)
 184                 return 0;
 185
 186         ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
 187         if (!ret)
 188                 atomic_set(&power_gate->jpeg_gated, !enable);
 189
 190         return ret;
 191 }
 192
 193 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
 194                                    bool enable)
 195 {
 196         struct smu_power_context *smu_power = &smu->smu_power;
 197         struct smu_power_gate *power_gate = &smu_power->power_gate;
 198         int ret = 0;
 199
 200         mutex_lock(&power_gate->jpeg_gate_lock);
 201
 202         ret = smu_dpm_set_jpeg_enable_locked(smu, enable);
 203
 204         mutex_unlock(&power_gate->jpeg_gate_lock);
 205
 206         return ret;
 207 }
 208
 209 /**
 210  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 211  *
 212  * @smu:        smu_context pointer
 213  * @block_type: the IP block to power gate/ungate
 214  * @gate:       to power gate if true, ungate otherwise
 215  *
 216  * This API uses no smu->mutex lock protection due to:
 217  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 218  *    This is guarded to be race condition free by the caller.
 219  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 220  *    Under this case, the smu->mutex lock protection is already enforced on
 221  *    the parent API smu_force_performance_level of the call path.
 222  */
 223 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 224                            bool gate)
 225 {
 226         int ret = 0;
 227
 228         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 229                 return -EOPNOTSUPP;
 230
 231         switch (block_type) {
 232         /*
 233          * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
 234          * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
 235          */
 236         case AMD_IP_BLOCK_TYPE_UVD:
 237         case AMD_IP_BLOCK_TYPE_VCN:
 238                 ret = smu_dpm_set_vcn_enable(smu, !gate);
 239                 if (ret)
 240                         dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
 241                                 gate ? "gate" : "ungate");
 242                 break;
 243         case AMD_IP_BLOCK_TYPE_GFX:
 244                 ret = smu_gfx_off_control(smu, gate);
 245                 if (ret)
 246                         dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
 247                                 gate ? "enable" : "disable");
 248                 break;
 249         case AMD_IP_BLOCK_TYPE_SDMA:
 250                 ret = smu_powergate_sdma(smu, gate);
 251                 if (ret)
 252                         dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
 253                                 gate ? "gate" : "ungate");
 254                 break;
 255         case AMD_IP_BLOCK_TYPE_JPEG:
 256                 ret = smu_dpm_set_jpeg_enable(smu, !gate);
 257                 if (ret)
 258                         dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
 259                                 gate ? "gate" : "ungate");
 260                 break;
 261         default:
 262                 dev_err(smu->adev->dev, "Unsupported block type!\n");
 263                 return -EINVAL;
 264         }
 265
 266         return ret;
 267 }
 268
 269 /**
 270  * smu_set_user_clk_dependencies - set user profile clock dependencies
 271  *
 272  * @smu:        smu_context pointer
 273  * @clk:        enum smu_clk_type type
 274  *
 275  * Enable/Disable the clock dependency for the @clk type.
 276  */
 277 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)
 278 {
 279         if (smu->adev->in_suspend)
 280                 return;
 281
 282         /*
 283          * mclk, fclk and socclk are interdependent
 284          * on each other
 285          */
 286         if (clk == SMU_MCLK) {
 287                 /* reset clock dependency */
 288                 smu->user_dpm_profile.clk_dependency = 0;
 289                 /* set mclk dependent clocks(fclk and socclk) */
 290                 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
 291         } else if (clk == SMU_FCLK) {
 292                 /* give priority to mclk, if mclk dependent clocks are set */
 293                 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
 294                         return;
 295
 296                 /* reset clock dependency */
 297                 smu->user_dpm_profile.clk_dependency = 0;
 298                 /* set fclk dependent clocks(mclk and socclk) */
 299                 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
 300         } else if (clk == SMU_SOCCLK) {
 301                 /* give priority to mclk, if mclk dependent clocks are set */
 302                 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
 303                         return;
 304
 305                 /* reset clock dependency */
 306                 smu->user_dpm_profile.clk_dependency = 0;
 307                 /* set socclk dependent clocks(mclk and fclk) */
 308                 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
 309         } else
 310                 /* add clk dependencies here, if any */
 311                 return;
 312 }
 313
 314 /**
 315  * smu_restore_dpm_user_profile - reinstate user dpm profile
 316  *
 317  * @smu:        smu_context pointer
 318  *
 319  * Restore the saved user power configurations include power limit,
 320  * clock frequencies, fan control mode and fan speed.
 321  */
 322 static void smu_restore_dpm_user_profile(struct smu_context *smu)
 323 {
 324         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 325         int ret = 0;
 326
 327         if (!smu->adev->in_suspend)
 328                 return;
 329
 330         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 331                 return;
 332
 333         /* Enable restore flag */
 334         smu->user_dpm_profile.flags = SMU_DPM_USER_PROFILE_RESTORE;
 335
 336         /* set the user dpm power limit */
 337         if (smu->user_dpm_profile.power_limit) {
 338                 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit);
 339                 if (ret)
 340                         dev_err(smu->adev->dev, "Failed to set power limit value\n");
 341         }
 342
 343         /* set the user dpm clock configurations */
 344         if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 345                 enum smu_clk_type clk_type;
 346
 347                 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
 348                         /*
 349                          * Iterate over smu clk type and force the saved user clk
 350                          * configs, skip if clock dependency is enabled
 351                          */
 352                         if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
 353                                         smu->user_dpm_profile.clk_mask[clk_type]) {
 354                                 ret = smu_force_clk_levels(smu, clk_type,
 355                                                 smu->user_dpm_profile.clk_mask[clk_type]);
 356                                 if (ret)
 357                                         dev_err(smu->adev->dev, "Failed to set clock type = %d\n",
 358                                                         clk_type);
 359                         }
 360                 }
 361         }
 362
 363         /* set the user dpm fan configurations */
 364         if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL) {
 365                 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode);
 366                 if (ret) {
 367                         dev_err(smu->adev->dev, "Failed to set manual fan control mode\n");
 368                         return;
 369                 }
 370
 371                 if (!ret && smu->user_dpm_profile.fan_speed_percent) {
 372                         ret = smu_set_fan_speed_percent(smu, smu->user_dpm_profile.fan_speed_percent);
 373                         if (ret)
 374                                 dev_err(smu->adev->dev, "Failed to set manual fan speed\n");
 375                 }
 376         }
 377
 378         /* Disable restore flag */
 379         smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
 380 }
 381
 382 int smu_get_power_num_states(struct smu_context *smu,
 383                              struct pp_states_info *state_info)
 384 {
 385         if (!state_info)
 386                 return -EINVAL;
 387
 388         /* not support power state */
 389         memset(state_info, 0, sizeof(struct pp_states_info));
 390         state_info->nums = 1;
 391         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 392
 393         return 0;
 394 }
 395
 396 bool is_support_sw_smu(struct amdgpu_device *adev)
 397 {
 398         if (adev->asic_type >= CHIP_ARCTURUS)
 399                 return true;
 400
 401         return false;
 402 }
 403
 404 bool is_support_cclk_dpm(struct amdgpu_device *adev)
 405 {
 406         struct smu_context *smu = &adev->smu;
 407
 408         if (!is_support_sw_smu(adev))
 409                 return false;
 410
 411         if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
 412                 return false;
 413
 414         return true;
 415 }
 416
 417
 418 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 419 {
 420         struct smu_table_context *smu_table = &smu->smu_table;
 421         uint32_t powerplay_table_size;
 422
 423         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 424                 return -EOPNOTSUPP;
 425
 426         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 427                 return -EINVAL;
 428
 429         mutex_lock(&smu->mutex);
 430
 431         if (smu_table->hardcode_pptable)
 432                 *table = smu_table->hardcode_pptable;
 433         else
 434                 *table = smu_table->power_play_table;
 435
 436         powerplay_table_size = smu_table->power_play_table_size;
 437
 438         mutex_unlock(&smu->mutex);
 439
 440         return powerplay_table_size;
 441 }
 442
 443 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 444 {
 445         struct smu_table_context *smu_table = &smu->smu_table;
 446         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 447         int ret = 0;
 448
 449         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 450                 return -EOPNOTSUPP;
 451
 452         if (header->usStructureSize != size) {
 453                 dev_err(smu->adev->dev, "pp table size not matched !\n");
 454                 return -EIO;
 455         }
 456
 457         mutex_lock(&smu->mutex);
 458         if (!smu_table->hardcode_pptable)
 459                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 460         if (!smu_table->hardcode_pptable) {
 461                 ret = -ENOMEM;
 462                 goto failed;
 463         }
 464
 465         memcpy(smu_table->hardcode_pptable, buf, size);
 466         smu_table->power_play_table = smu_table->hardcode_pptable;
 467         smu_table->power_play_table_size = size;
 468
 469         /*
 470          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 471          * skipped) may be needed for custom pptable uploading.
 472          */
 473         smu->uploading_custom_pp_table = true;
 474
 475         ret = smu_reset(smu);
 476         if (ret)
 477                 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
 478
 479         smu->uploading_custom_pp_table = false;
 480
 481 failed:
 482         mutex_unlock(&smu->mutex);
 483         return ret;
 484 }
 485
 486 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
 487 {
 488         struct smu_feature *feature = &smu->smu_feature;
 489         int ret = 0;
 490         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 491
 492         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 493
 494         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 495                                              SMU_FEATURE_MAX/32);
 496         if (ret)
 497                 return ret;
 498
 499         bitmap_or(feature->allowed, feature->allowed,
 500                       (unsigned long *)allowed_feature_mask,
 501                       feature->feature_num);
 502
 503         return ret;
 504 }
 505
 506 static int smu_set_funcs(struct amdgpu_device *adev)
 507 {
 508         struct smu_context *smu = &adev->smu;
 509
 510         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 511                 smu->od_enabled = true;
 512
 513         switch (adev->asic_type) {
 514         case CHIP_NAVI10:
 515         case CHIP_NAVI14:
 516         case CHIP_NAVI12:
 517                 navi10_set_ppt_funcs(smu);
 518                 break;
 519         case CHIP_ARCTURUS:
 520                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 521                 arcturus_set_ppt_funcs(smu);
 522                 /* OD is not supported on Arcturus */
 523                 smu->od_enabled =false;
 524                 break;
 525         case CHIP_SIENNA_CICHLID:
 526         case CHIP_NAVY_FLOUNDER:
 527         case CHIP_DIMGREY_CAVEFISH:
 528                 sienna_cichlid_set_ppt_funcs(smu);
 529                 break;
 530         case CHIP_RENOIR:
 531                 renoir_set_ppt_funcs(smu);
 532                 break;
 533         case CHIP_VANGOGH:
 534                 vangogh_set_ppt_funcs(smu);
 535                 break;
 536         default:
 537                 return -EINVAL;
 538         }
 539
 540         return 0;
 541 }
 542
 543 static int smu_early_init(void *handle)
 544 {
 545         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 546         struct smu_context *smu = &adev->smu;
 547
 548         smu->adev = adev;
 549         smu->pm_enabled = !!amdgpu_dpm;
 550         smu->is_apu = false;
 551         mutex_init(&smu->mutex);
 552         mutex_init(&smu->smu_baco.mutex);
 553         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 554         smu->smu_baco.platform_support = false;
 555
 556         return smu_set_funcs(adev);
 557 }
 558
 559 static int smu_set_default_dpm_table(struct smu_context *smu)
 560 {
 561         struct smu_power_context *smu_power = &smu->smu_power;
 562         struct smu_power_gate *power_gate = &smu_power->power_gate;
 563         int vcn_gate, jpeg_gate;
 564         int ret = 0;
 565
 566         if (!smu->ppt_funcs->set_default_dpm_table)
 567                 return 0;
 568
 569         mutex_lock(&power_gate->vcn_gate_lock);
 570         mutex_lock(&power_gate->jpeg_gate_lock);
 571
 572         vcn_gate = atomic_read(&power_gate->vcn_gated);
 573         jpeg_gate = atomic_read(&power_gate->jpeg_gated);
 574
 575         ret = smu_dpm_set_vcn_enable_locked(smu, true);
 576         if (ret)
 577                 goto err0_out;
 578
 579         ret = smu_dpm_set_jpeg_enable_locked(smu, true);
 580         if (ret)
 581                 goto err1_out;
 582
 583         ret = smu->ppt_funcs->set_default_dpm_table(smu);
 584         if (ret)
 585                 dev_err(smu->adev->dev,
 586                         "Failed to setup default dpm clock tables!\n");
 587
 588         smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate);
 589 err1_out:
 590         smu_dpm_set_vcn_enable_locked(smu, !vcn_gate);
 591 err0_out:
 592         mutex_unlock(&power_gate->jpeg_gate_lock);
 593         mutex_unlock(&power_gate->vcn_gate_lock);
 594
 595         return ret;
 596 }
 597
 598 static int smu_late_init(void *handle)
 599 {
 600         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 601         struct smu_context *smu = &adev->smu;
 602         int ret = 0;
 603
 604         smu_set_fine_grain_gfx_freq_parameters(smu);
 605
 606         if (!smu->pm_enabled)
 607                 return 0;
 608
 609         ret = smu_post_init(smu);
 610         if (ret) {
 611                 dev_err(adev->dev, "Failed to post smu init!\n");
 612                 return ret;
 613         }
 614
 615         ret = smu_set_default_od_settings(smu);
 616         if (ret) {
 617                 dev_err(adev->dev, "Failed to setup default OD settings!\n");
 618                 return ret;
 619         }
 620
 621         ret = smu_populate_umd_state_clk(smu);
 622         if (ret) {
 623                 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
 624                 return ret;
 625         }
 626
 627         ret = smu_get_asic_power_limits(smu);
 628         if (ret) {
 629                 dev_err(adev->dev, "Failed to get asic power limits!\n");
 630                 return ret;
 631         }
 632
 633         smu_get_unique_id(smu);
 634
 635         smu_get_fan_parameters(smu);
 636
 637         smu_handle_task(&adev->smu,
 638                         smu->smu_dpm.dpm_level,
 639                         AMD_PP_TASK_COMPLETE_INIT,
 640                         false);
 641
 642         smu_restore_dpm_user_profile(smu);
 643
 644         return 0;
 645 }
 646
 647 static int smu_init_fb_allocations(struct smu_context *smu)
 648 {
 649         struct amdgpu_device *adev = smu->adev;
 650         struct smu_table_context *smu_table = &smu->smu_table;
 651         struct smu_table *tables = smu_table->tables;
 652         struct smu_table *driver_table = &(smu_table->driver_table);
 653         uint32_t max_table_size = 0;
 654         int ret, i;
 655
 656         /* VRAM allocation for tool table */
 657         if (tables[SMU_TABLE_PMSTATUSLOG].size) {
 658                 ret = amdgpu_bo_create_kernel(adev,
 659                                               tables[SMU_TABLE_PMSTATUSLOG].size,
 660                                               tables[SMU_TABLE_PMSTATUSLOG].align,
 661                                               tables[SMU_TABLE_PMSTATUSLOG].domain,
 662                                               &tables[SMU_TABLE_PMSTATUSLOG].bo,
 663                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 664                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 665                 if (ret) {
 666                         dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
 667                         return ret;
 668                 }
 669         }
 670
 671         /* VRAM allocation for driver table */
 672         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 673                 if (tables[i].size == 0)
 674                         continue;
 675
 676                 if (i == SMU_TABLE_PMSTATUSLOG)
 677                         continue;
 678
 679                 if (max_table_size < tables[i].size)
 680                         max_table_size = tables[i].size;
 681         }
 682
 683         driver_table->size = max_table_size;
 684         driver_table->align = PAGE_SIZE;
 685         driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 686
 687         ret = amdgpu_bo_create_kernel(adev,
 688                                       driver_table->size,
 689                                       driver_table->align,
 690                                       driver_table->domain,
 691                                       &driver_table->bo,
 692                                       &driver_table->mc_address,
 693                                       &driver_table->cpu_addr);
 694         if (ret) {
 695                 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
 696                 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 697                         amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 698                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 699                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 700         }
 701
 702         return ret;
 703 }
 704
 705 static int smu_fini_fb_allocations(struct smu_context *smu)
 706 {
 707         struct smu_table_context *smu_table = &smu->smu_table;
 708         struct smu_table *tables = smu_table->tables;
 709         struct smu_table *driver_table = &(smu_table->driver_table);
 710
 711         if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 712                 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 713                                       &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 714                                       &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 715
 716         amdgpu_bo_free_kernel(&driver_table->bo,
 717                               &driver_table->mc_address,
 718                               &driver_table->cpu_addr);
 719
 720         return 0;
 721 }
 722
 723 /**
 724  * smu_alloc_memory_pool - allocate memory pool in the system memory
 725  *
 726  * @smu: amdgpu_device pointer
 727  *
 728  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 729  * and DramLogSetDramAddr can notify it changed.
 730  *
 731  * Returns 0 on success, error on failure.
 732  */
 733 static int smu_alloc_memory_pool(struct smu_context *smu)
 734 {
 735         struct amdgpu_device *adev = smu->adev;
 736         struct smu_table_context *smu_table = &smu->smu_table;
 737         struct smu_table *memory_pool = &smu_table->memory_pool;
 738         uint64_t pool_size = smu->pool_size;
 739         int ret = 0;
 740
 741         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 742                 return ret;
 743
 744         memory_pool->size = pool_size;
 745         memory_pool->align = PAGE_SIZE;
 746         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 747
 748         switch (pool_size) {
 749         case SMU_MEMORY_POOL_SIZE_256_MB:
 750         case SMU_MEMORY_POOL_SIZE_512_MB:
 751         case SMU_MEMORY_POOL_SIZE_1_GB:
 752         case SMU_MEMORY_POOL_SIZE_2_GB:
 753                 ret = amdgpu_bo_create_kernel(adev,
 754                                               memory_pool->size,
 755                                               memory_pool->align,
 756                                               memory_pool->domain,
 757                                               &memory_pool->bo,
 758                                               &memory_pool->mc_address,
 759                                               &memory_pool->cpu_addr);
 760                 if (ret)
 761                         dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
 762                 break;
 763         default:
 764                 break;
 765         }
 766
 767         return ret;
 768 }
 769
 770 static int smu_free_memory_pool(struct smu_context *smu)
 771 {
 772         struct smu_table_context *smu_table = &smu->smu_table;
 773         struct smu_table *memory_pool = &smu_table->memory_pool;
 774
 775         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 776                 return 0;
 777
 778         amdgpu_bo_free_kernel(&memory_pool->bo,
 779                               &memory_pool->mc_address,
 780                               &memory_pool->cpu_addr);
 781
 782         memset(memory_pool, 0, sizeof(struct smu_table));
 783
 784         return 0;
 785 }
 786
 787 static int smu_alloc_dummy_read_table(struct smu_context *smu)
 788 {
 789         struct smu_table_context *smu_table = &smu->smu_table;
 790         struct smu_table *dummy_read_1_table =
 791                         &smu_table->dummy_read_1_table;
 792         struct amdgpu_device *adev = smu->adev;
 793         int ret = 0;
 794
 795         dummy_read_1_table->size = 0x40000;
 796         dummy_read_1_table->align = PAGE_SIZE;
 797         dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 798
 799         ret = amdgpu_bo_create_kernel(adev,
 800                                       dummy_read_1_table->size,
 801                                       dummy_read_1_table->align,
 802                                       dummy_read_1_table->domain,
 803                                       &dummy_read_1_table->bo,
 804                                       &dummy_read_1_table->mc_address,
 805                                       &dummy_read_1_table->cpu_addr);
 806         if (ret)
 807                 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
 808
 809         return ret;
 810 }
 811
 812 static void smu_free_dummy_read_table(struct smu_context *smu)
 813 {
 814         struct smu_table_context *smu_table = &smu->smu_table;
 815         struct smu_table *dummy_read_1_table =
 816                         &smu_table->dummy_read_1_table;
 817
 818
 819         amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
 820                               &dummy_read_1_table->mc_address,
 821                               &dummy_read_1_table->cpu_addr);
 822
 823         memset(dummy_read_1_table, 0, sizeof(struct smu_table));
 824 }
 825
 826 static int smu_smc_table_sw_init(struct smu_context *smu)
 827 {
 828         int ret;
 829
 830         /**
 831          * Create smu_table structure, and init smc tables such as
 832          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 833          */
 834         ret = smu_init_smc_tables(smu);
 835         if (ret) {
 836                 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
 837                 return ret;
 838         }
 839
 840         /**
 841          * Create smu_power_context structure, and allocate smu_dpm_context and
 842          * context size to fill the smu_power_context data.
 843          */
 844         ret = smu_init_power(smu);
 845         if (ret) {
 846                 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
 847                 return ret;
 848         }
 849
 850         /*
 851          * allocate vram bos to store smc table contents.
 852          */
 853         ret = smu_init_fb_allocations(smu);
 854         if (ret)
 855                 return ret;
 856
 857         ret = smu_alloc_memory_pool(smu);
 858         if (ret)
 859                 return ret;
 860
 861         ret = smu_alloc_dummy_read_table(smu);
 862         if (ret)
 863                 return ret;
 864
 865         ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c);
 866         if (ret)
 867                 return ret;
 868
 869         return 0;
 870 }
 871
 872 static int smu_smc_table_sw_fini(struct smu_context *smu)
 873 {
 874         int ret;
 875
 876         smu_i2c_fini(smu, &smu->adev->pm.smu_i2c);
 877
 878         smu_free_dummy_read_table(smu);
 879
 880         ret = smu_free_memory_pool(smu);
 881         if (ret)
 882                 return ret;
 883
 884         ret = smu_fini_fb_allocations(smu);
 885         if (ret)
 886                 return ret;
 887
 888         ret = smu_fini_power(smu);
 889         if (ret) {
 890                 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
 891                 return ret;
 892         }
 893
 894         ret = smu_fini_smc_tables(smu);
 895         if (ret) {
 896                 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
 897                 return ret;
 898         }
 899
 900         return 0;
 901 }
 902
 903 static void smu_throttling_logging_work_fn(struct work_struct *work)
 904 {
 905         struct smu_context *smu = container_of(work, struct smu_context,
 906                                                throttling_logging_work);
 907
 908         smu_log_thermal_throttling(smu);
 909 }
 910
 911 static void smu_interrupt_work_fn(struct work_struct *work)
 912 {
 913         struct smu_context *smu = container_of(work, struct smu_context,
 914                                                interrupt_work);
 915
 916         mutex_lock(&smu->mutex);
 917
 918         if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
 919                 smu->ppt_funcs->interrupt_work(smu);
 920
 921         mutex_unlock(&smu->mutex);
 922 }
 923
 924 static int smu_sw_init(void *handle)
 925 {
 926         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 927         struct smu_context *smu = &adev->smu;
 928         int ret;
 929
 930         smu->pool_size = adev->pm.smu_prv_buffer_size;
 931         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 932         mutex_init(&smu->smu_feature.mutex);
 933         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 934         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 935         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 936
 937         mutex_init(&smu->sensor_lock);
 938         mutex_init(&smu->metrics_lock);
 939         mutex_init(&smu->message_lock);
 940
 941         INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
 942         INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
 943         atomic64_set(&smu->throttle_int_counter, 0);
 944         smu->watermarks_bitmap = 0;
 945         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 946         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 947
 948         atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
 949         atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
 950         mutex_init(&smu->smu_power.power_gate.vcn_gate_lock);
 951         mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock);
 952
 953         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 954         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 955         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 956         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 957         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 958         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 959         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 960         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 961
 962         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 963         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 964         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 965         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 966         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 967         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 968         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 969         smu->display_config = &adev->pm.pm_display_cfg;
 970
 971         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 972         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 973
 974         ret = smu_init_microcode(smu);
 975         if (ret) {
 976                 dev_err(adev->dev, "Failed to load smu firmware!\n");
 977                 return ret;
 978         }
 979
 980         ret = smu_smc_table_sw_init(smu);
 981         if (ret) {
 982                 dev_err(adev->dev, "Failed to sw init smc table!\n");
 983                 return ret;
 984         }
 985
 986         ret = smu_register_irq_handler(smu);
 987         if (ret) {
 988                 dev_err(adev->dev, "Failed to register smc irq handler!\n");
 989                 return ret;
 990         }
 991
 992         return 0;
 993 }
 994
 995 static int smu_sw_fini(void *handle)
 996 {
 997         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 998         struct smu_context *smu = &adev->smu;
 999         int ret;
1000
1001         ret = smu_smc_table_sw_fini(smu);
1002         if (ret) {
1003                 dev_err(adev->dev, "Failed to sw fini smc table!\n");
1004                 return ret;
1005         }
1006
1007         smu_fini_microcode(smu);
1008
1009         return 0;
1010 }
1011
1012 static int smu_get_thermal_temperature_range(struct smu_context *smu)
1013 {
1014         struct amdgpu_device *adev = smu->adev;
1015         struct smu_temperature_range *range =
1016                                 &smu->thermal_range;
1017         int ret = 0;
1018
1019         if (!smu->ppt_funcs->get_thermal_temperature_range)
1020                 return 0;
1021
1022         ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
1023         if (ret)
1024                 return ret;
1025
1026         adev->pm.dpm.thermal.min_temp = range->min;
1027         adev->pm.dpm.thermal.max_temp = range->max;
1028         adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
1029         adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
1030         adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
1031         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
1032         adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
1033         adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
1034         adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
1035
1036         return ret;
1037 }
1038
1039 static int smu_smc_hw_setup(struct smu_context *smu)
1040 {
1041         struct amdgpu_device *adev = smu->adev;
1042         uint32_t pcie_gen = 0, pcie_width = 0;
1043         int ret = 0;
1044
1045         if (adev->in_suspend && smu_is_dpm_running(smu)) {
1046                 dev_info(adev->dev, "dpm has been enabled\n");
1047                 /* this is needed specifically */
1048                 if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
1049                     (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
1050                         ret = smu_system_features_control(smu, true);
1051                 return ret;
1052         }
1053
1054         ret = smu_init_display_count(smu, 0);
1055         if (ret) {
1056                 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1057                 return ret;
1058         }
1059
1060         ret = smu_set_driver_table_location(smu);
1061         if (ret) {
1062                 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1063                 return ret;
1064         }
1065
1066         /*
1067          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1068          */
1069         ret = smu_set_tool_table_location(smu);
1070         if (ret) {
1071                 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1072                 return ret;
1073         }
1074
1075         /*
1076          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1077          * pool location.
1078          */
1079         ret = smu_notify_memory_pool_location(smu);
1080         if (ret) {
1081                 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1082                 return ret;
1083         }
1084
1085         /* smu_dump_pptable(smu); */
1086         /*
1087          * Copy pptable bo in the vram to smc with SMU MSGs such as
1088          * SetDriverDramAddr and TransferTableDram2Smu.
1089          */
1090         ret = smu_write_pptable(smu);
1091         if (ret) {
1092                 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1093                 return ret;
1094         }
1095
1096         /* issue Run*Btc msg */
1097         ret = smu_run_btc(smu);
1098         if (ret)
1099                 return ret;
1100
1101         ret = smu_feature_set_allowed_mask(smu);
1102         if (ret) {
1103                 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1104                 return ret;
1105         }
1106
1107         ret = smu_system_features_control(smu, true);
1108         if (ret) {
1109                 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1110                 return ret;
1111         }
1112
1113         if (!smu_is_dpm_running(smu))
1114                 dev_info(adev->dev, "dpm has been disabled\n");
1115
1116         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1117                 pcie_gen = 3;
1118         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1119                 pcie_gen = 2;
1120         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1121                 pcie_gen = 1;
1122         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1123                 pcie_gen = 0;
1124
1125         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1126          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1127          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
1128          */
1129         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1130                 pcie_width = 6;
1131         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1132                 pcie_width = 5;
1133         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1134                 pcie_width = 4;
1135         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1136                 pcie_width = 3;
1137         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1138                 pcie_width = 2;
1139         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1140                 pcie_width = 1;
1141         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1142         if (ret) {
1143                 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1144                 return ret;
1145         }
1146
1147         ret = smu_get_thermal_temperature_range(smu);
1148         if (ret) {
1149                 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1150                 return ret;
1151         }
1152
1153         ret = smu_enable_thermal_alert(smu);
1154         if (ret) {
1155                 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1156                 return ret;
1157         }
1158
1159         /*
1160          * Set initialized values (get from vbios) to dpm tables context such as
1161          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1162          * type of clks.
1163          */
1164         ret = smu_set_default_dpm_table(smu);
1165         if (ret) {
1166                 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1167                 return ret;
1168         }
1169
1170         ret = smu_notify_display_change(smu);
1171         if (ret)
1172                 return ret;
1173
1174         /*
1175          * Set min deep sleep dce fclk with bootup value from vbios via
1176          * SetMinDeepSleepDcefclk MSG.
1177          */
1178         ret = smu_set_min_dcef_deep_sleep(smu,
1179                                           smu->smu_table.boot_values.dcefclk / 100);
1180         if (ret)
1181                 return ret;
1182
1183         return ret;
1184 }
1185
1186 static int smu_start_smc_engine(struct smu_context *smu)
1187 {
1188         struct amdgpu_device *adev = smu->adev;
1189         int ret = 0;
1190
1191         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1192                 if (adev->asic_type < CHIP_NAVI10) {
1193                         if (smu->ppt_funcs->load_microcode) {
1194                                 ret = smu->ppt_funcs->load_microcode(smu);
1195                                 if (ret)
1196                                         return ret;
1197                         }
1198                 }
1199         }
1200
1201         if (smu->ppt_funcs->check_fw_status) {
1202                 ret = smu->ppt_funcs->check_fw_status(smu);
1203                 if (ret) {
1204                         dev_err(adev->dev, "SMC is not ready\n");
1205                         return ret;
1206                 }
1207         }
1208
1209         /*
1210          * Send msg GetDriverIfVersion to check if the return value is equal
1211          * with DRIVER_IF_VERSION of smc header.
1212          */
1213         ret = smu_check_fw_version(smu);
1214         if (ret)
1215                 return ret;
1216
1217         return ret;
1218 }
1219
1220 static int smu_hw_init(void *handle)
1221 {
1222         int ret;
1223         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1224         struct smu_context *smu = &adev->smu;
1225
1226         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1227                 smu->pm_enabled = false;
1228                 return 0;
1229         }
1230
1231         ret = smu_start_smc_engine(smu);
1232         if (ret) {
1233                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1234                 return ret;
1235         }
1236
1237         if (smu->is_apu) {
1238                 smu_powergate_sdma(&adev->smu, false);
1239                 smu_dpm_set_vcn_enable(smu, true);
1240                 smu_dpm_set_jpeg_enable(smu, true);
1241                 smu_set_gfx_cgpg(&adev->smu, true);
1242         }
1243
1244         if (!smu->pm_enabled)
1245                 return 0;
1246
1247         /* get boot_values from vbios to set revision, gfxclk, and etc. */
1248         ret = smu_get_vbios_bootup_values(smu);
1249         if (ret) {
1250                 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1251                 return ret;
1252         }
1253
1254         ret = smu_setup_pptable(smu);
1255         if (ret) {
1256                 dev_err(adev->dev, "Failed to setup pptable!\n");
1257                 return ret;
1258         }
1259
1260         ret = smu_get_driver_allowed_feature_mask(smu);
1261         if (ret)
1262                 return ret;
1263
1264         ret = smu_smc_hw_setup(smu);
1265         if (ret) {
1266                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1267                 return ret;
1268         }
1269
1270         /*
1271          * Move maximum sustainable clock retrieving here considering
1272          * 1. It is not needed on resume(from S3).
1273          * 2. DAL settings come between .hw_init and .late_init of SMU.
1274          *    And DAL needs to know the maximum sustainable clocks. Thus
1275          *    it cannot be put in .late_init().
1276          */
1277         ret = smu_init_max_sustainable_clocks(smu);
1278         if (ret) {
1279                 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1280                 return ret;
1281         }
1282
1283         adev->pm.dpm_enabled = true;
1284
1285         dev_info(adev->dev, "SMU is initialized successfully!\n");
1286
1287         return 0;
1288 }
1289
1290 static int smu_disable_dpms(struct smu_context *smu)
1291 {
1292         struct amdgpu_device *adev = smu->adev;
1293         int ret = 0;
1294         bool use_baco = !smu->is_apu &&
1295                 ((amdgpu_in_reset(adev) &&
1296                   (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1297                  ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
1298
1299         /*
1300          * For custom pptable uploading, skip the DPM features
1301          * disable process on Navi1x ASICs.
1302          *   - As the gfx related features are under control of
1303          *     RLC on those ASICs. RLC reinitialization will be
1304          *     needed to reenable them. That will cost much more
1305          *     efforts.
1306          *
1307          *   - SMU firmware can handle the DPM reenablement
1308          *     properly.
1309          */
1310         if (smu->uploading_custom_pp_table &&
1311             (adev->asic_type >= CHIP_NAVI10) &&
1312             (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
1313                 return 0;
1314
1315         /*
1316          * For Sienna_Cichlid, PMFW will handle the features disablement properly
1317          * on BACO in. Driver involvement is unnecessary.
1318          */
1319         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1320              use_baco)
1321                 return 0;
1322
1323         /*
1324          * For gpu reset, runpm and hibernation through BACO,
1325          * BACO feature has to be kept enabled.
1326          */
1327         if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1328                 ret = smu_disable_all_features_with_exception(smu,
1329                                                               SMU_FEATURE_BACO_BIT);
1330                 if (ret)
1331                         dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1332         } else {
1333                 ret = smu_system_features_control(smu, false);
1334                 if (ret)
1335                         dev_err(adev->dev, "Failed to disable smu features.\n");
1336         }
1337
1338         if (adev->asic_type >= CHIP_NAVI10 &&
1339             adev->gfx.rlc.funcs->stop)
1340                 adev->gfx.rlc.funcs->stop(adev);
1341
1342         return ret;
1343 }
1344
1345 static int smu_smc_hw_cleanup(struct smu_context *smu)
1346 {
1347         struct amdgpu_device *adev = smu->adev;
1348         int ret = 0;
1349
1350         cancel_work_sync(&smu->throttling_logging_work);
1351         cancel_work_sync(&smu->interrupt_work);
1352
1353         ret = smu_disable_thermal_alert(smu);
1354         if (ret) {
1355                 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1356                 return ret;
1357         }
1358
1359         ret = smu_disable_dpms(smu);
1360         if (ret) {
1361                 dev_err(adev->dev, "Fail to disable dpm features!\n");
1362                 return ret;
1363         }
1364
1365         return 0;
1366 }
1367
1368 static int smu_hw_fini(void *handle)
1369 {
1370         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1371         struct smu_context *smu = &adev->smu;
1372
1373         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1374                 return 0;
1375
1376         if (smu->is_apu) {
1377                 smu_powergate_sdma(&adev->smu, true);
1378                 smu_dpm_set_vcn_enable(smu, false);
1379                 smu_dpm_set_jpeg_enable(smu, false);
1380         }
1381
1382         if (!smu->pm_enabled)
1383                 return 0;
1384
1385         adev->pm.dpm_enabled = false;
1386
1387         return smu_smc_hw_cleanup(smu);
1388 }
1389
1390 int smu_reset(struct smu_context *smu)
1391 {
1392         struct amdgpu_device *adev = smu->adev;
1393         int ret;
1394
1395         amdgpu_gfx_off_ctrl(smu->adev, false);
1396
1397         ret = smu_hw_fini(adev);
1398         if (ret)
1399                 return ret;
1400
1401         ret = smu_hw_init(adev);
1402         if (ret)
1403                 return ret;
1404
1405         ret = smu_late_init(adev);
1406         if (ret)
1407                 return ret;
1408
1409         amdgpu_gfx_off_ctrl(smu->adev, true);
1410
1411         return 0;
1412 }
1413
1414 static int smu_suspend(void *handle)
1415 {
1416         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1417         struct smu_context *smu = &adev->smu;
1418         int ret;
1419
1420         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1421                 return 0;
1422
1423         if (!smu->pm_enabled)
1424                 return 0;
1425
1426         adev->pm.dpm_enabled = false;
1427
1428         ret = smu_smc_hw_cleanup(smu);
1429         if (ret)
1430                 return ret;
1431
1432         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1433
1434         /* skip CGPG when in S0ix */
1435         if (smu->is_apu && !adev->in_s0ix)
1436                 smu_set_gfx_cgpg(&adev->smu, false);
1437
1438         return 0;
1439 }
1440
1441 static int smu_resume(void *handle)
1442 {
1443         int ret;
1444         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1445         struct smu_context *smu = &adev->smu;
1446
1447         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1448                 return 0;
1449
1450         if (!smu->pm_enabled)
1451                 return 0;
1452
1453         dev_info(adev->dev, "SMU is resuming...\n");
1454
1455         ret = smu_start_smc_engine(smu);
1456         if (ret) {
1457                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1458                 return ret;
1459         }
1460
1461         ret = smu_smc_hw_setup(smu);
1462         if (ret) {
1463                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1464                 return ret;
1465         }
1466
1467         if (smu->is_apu)
1468                 smu_set_gfx_cgpg(&adev->smu, true);
1469
1470         smu->disable_uclk_switch = 0;
1471
1472         adev->pm.dpm_enabled = true;
1473
1474         dev_info(adev->dev, "SMU is resumed successfully!\n");
1475
1476         return 0;
1477 }
1478
1479 int smu_display_configuration_change(struct smu_context *smu,
1480                                      const struct amd_pp_display_configuration *display_config)
1481 {
1482         int index = 0;
1483         int num_of_active_display = 0;
1484
1485         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1486                 return -EOPNOTSUPP;
1487
1488         if (!display_config)
1489                 return -EINVAL;
1490
1491         mutex_lock(&smu->mutex);
1492
1493         smu_set_min_dcef_deep_sleep(smu,
1494                                     display_config->min_dcef_deep_sleep_set_clk / 100);
1495
1496         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1497                 if (display_config->displays[index].controller_id != 0)
1498                         num_of_active_display++;
1499         }
1500
1501         mutex_unlock(&smu->mutex);
1502
1503         return 0;
1504 }
1505
1506 static int smu_set_clockgating_state(void *handle,
1507                                      enum amd_clockgating_state state)
1508 {
1509         return 0;
1510 }
1511
1512 static int smu_set_powergating_state(void *handle,
1513                                      enum amd_powergating_state state)
1514 {
1515         return 0;
1516 }
1517
1518 static int smu_enable_umd_pstate(void *handle,
1519                       enum amd_dpm_forced_level *level)
1520 {
1521         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1522                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1523                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1524                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1525
1526         struct smu_context *smu = (struct smu_context*)(handle);
1527         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1528
1529         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1530                 return -EINVAL;
1531
1532         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1533                 /* enter umd pstate, save current level, disable gfx cg*/
1534                 if (*level & profile_mode_mask) {
1535                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1536                         smu_dpm_ctx->enable_umd_pstate = true;
1537                         smu_gpo_control(smu, false);
1538                         amdgpu_device_ip_set_powergating_state(smu->adev,
1539                                                                AMD_IP_BLOCK_TYPE_GFX,
1540                                                                AMD_PG_STATE_UNGATE);
1541                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1542                                                                AMD_IP_BLOCK_TYPE_GFX,
1543                                                                AMD_CG_STATE_UNGATE);
1544                         smu_gfx_ulv_control(smu, false);
1545                         smu_deep_sleep_control(smu, false);
1546                         amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
1547                 }
1548         } else {
1549                 /* exit umd pstate, restore level, enable gfx cg*/
1550                 if (!(*level & profile_mode_mask)) {
1551                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1552                                 *level = smu_dpm_ctx->saved_dpm_level;
1553                         smu_dpm_ctx->enable_umd_pstate = false;
1554                         amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
1555                         smu_deep_sleep_control(smu, true);
1556                         smu_gfx_ulv_control(smu, true);
1557                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1558                                                                AMD_IP_BLOCK_TYPE_GFX,
1559                                                                AMD_CG_STATE_GATE);
1560                         amdgpu_device_ip_set_powergating_state(smu->adev,
1561                                                                AMD_IP_BLOCK_TYPE_GFX,
1562                                                                AMD_PG_STATE_GATE);
1563                         smu_gpo_control(smu, true);
1564                 }
1565         }
1566
1567         return 0;
1568 }
1569
1570 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1571                                    enum amd_dpm_forced_level level,
1572                                    bool skip_display_settings)
1573 {
1574         int ret = 0;
1575         int index = 0;
1576         long workload;
1577         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1578
1579         if (!skip_display_settings) {
1580                 ret = smu_display_config_changed(smu);
1581                 if (ret) {
1582                         dev_err(smu->adev->dev, "Failed to change display config!");
1583                         return ret;
1584                 }
1585         }
1586
1587         ret = smu_apply_clocks_adjust_rules(smu);
1588         if (ret) {
1589                 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1590                 return ret;
1591         }
1592
1593         if (!skip_display_settings) {
1594                 ret = smu_notify_smc_display_config(smu);
1595                 if (ret) {
1596                         dev_err(smu->adev->dev, "Failed to notify smc display config!");
1597                         return ret;
1598                 }
1599         }
1600
1601         if (smu_dpm_ctx->dpm_level != level) {
1602                 ret = smu_asic_set_performance_level(smu, level);
1603                 if (ret) {
1604                         dev_err(smu->adev->dev, "Failed to set performance level!");
1605                         return ret;
1606                 }
1607
1608                 /* update the saved copy */
1609                 smu_dpm_ctx->dpm_level = level;
1610         }
1611
1612         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1613                 index = fls(smu->workload_mask);
1614                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1615                 workload = smu->workload_setting[index];
1616
1617                 if (smu->power_profile_mode != workload)
1618                         smu_set_power_profile_mode(smu, &workload, 0, false);
1619         }
1620
1621         return ret;
1622 }
1623
1624 int smu_handle_task(struct smu_context *smu,
1625                     enum amd_dpm_forced_level level,
1626                     enum amd_pp_task task_id,
1627                     bool lock_needed)
1628 {
1629         int ret = 0;
1630
1631         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1632                 return -EOPNOTSUPP;
1633
1634         if (lock_needed)
1635                 mutex_lock(&smu->mutex);
1636
1637         switch (task_id) {
1638         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1639                 ret = smu_pre_display_config_changed(smu);
1640                 if (ret)
1641                         goto out;
1642                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1643                 break;
1644         case AMD_PP_TASK_COMPLETE_INIT:
1645         case AMD_PP_TASK_READJUST_POWER_STATE:
1646                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1647                 break;
1648         default:
1649                 break;
1650         }
1651
1652 out:
1653         if (lock_needed)
1654                 mutex_unlock(&smu->mutex);
1655
1656         return ret;
1657 }
1658
1659 int smu_switch_power_profile(struct smu_context *smu,
1660                              enum PP_SMC_POWER_PROFILE type,
1661                              bool en)
1662 {
1663         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1664         long workload;
1665         uint32_t index;
1666
1667         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1668                 return -EOPNOTSUPP;
1669
1670         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1671                 return -EINVAL;
1672
1673         mutex_lock(&smu->mutex);
1674
1675         if (!en) {
1676                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1677                 index = fls(smu->workload_mask);
1678                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1679                 workload = smu->workload_setting[index];
1680         } else {
1681                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1682                 index = fls(smu->workload_mask);
1683                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1684                 workload = smu->workload_setting[index];
1685         }
1686
1687         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1688                 smu_set_power_profile_mode(smu, &workload, 0, false);
1689
1690         mutex_unlock(&smu->mutex);
1691
1692         return 0;
1693 }
1694
1695 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1696 {
1697         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1698         enum amd_dpm_forced_level level;
1699
1700         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1701                 return -EOPNOTSUPP;
1702
1703         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1704                 return -EINVAL;
1705
1706         mutex_lock(&(smu->mutex));
1707         level = smu_dpm_ctx->dpm_level;
1708         mutex_unlock(&(smu->mutex));
1709
1710         return level;
1711 }
1712
1713 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1714 {
1715         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1716         int ret = 0;
1717
1718         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1719                 return -EOPNOTSUPP;
1720
1721         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1722                 return -EINVAL;
1723
1724         mutex_lock(&smu->mutex);
1725
1726         ret = smu_enable_umd_pstate(smu, &level);
1727         if (ret) {
1728                 mutex_unlock(&smu->mutex);
1729                 return ret;
1730         }
1731
1732         ret = smu_handle_task(smu, level,
1733                               AMD_PP_TASK_READJUST_POWER_STATE,
1734                               false);
1735
1736         mutex_unlock(&smu->mutex);
1737
1738         /* reset user dpm clock state */
1739         if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1740                 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask));
1741                 smu->user_dpm_profile.clk_dependency = 0;
1742         }
1743
1744         return ret;
1745 }
1746
1747 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1748 {
1749         int ret = 0;
1750
1751         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1752                 return -EOPNOTSUPP;
1753
1754         mutex_lock(&smu->mutex);
1755         ret = smu_init_display_count(smu, count);
1756         mutex_unlock(&smu->mutex);
1757
1758         return ret;
1759 }
1760
1761 int smu_force_clk_levels(struct smu_context *smu,
1762                          enum smu_clk_type clk_type,
1763                          uint32_t mask)
1764 {
1765         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1766         int ret = 0;
1767
1768         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1769                 return -EOPNOTSUPP;
1770
1771         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1772                 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1773                 return -EINVAL;
1774         }
1775
1776         mutex_lock(&smu->mutex);
1777
1778         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
1779                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1780                 if (!ret && smu->user_dpm_profile.flags != SMU_DPM_USER_PROFILE_RESTORE) {
1781                         smu->user_dpm_profile.clk_mask[clk_type] = mask;
1782                         smu_set_user_clk_dependencies(smu, clk_type);
1783                 }
1784         }
1785
1786         mutex_unlock(&smu->mutex);
1787
1788         return ret;
1789 }
1790
1791 /*
1792  * On system suspending or resetting, the dpm_enabled
1793  * flag will be cleared. So that those SMU services which
1794  * are not supported will be gated.
1795  * However, the mp1 state setting should still be granted
1796  * even if the dpm_enabled cleared.
1797  */
1798 int smu_set_mp1_state(struct smu_context *smu,
1799                       enum pp_mp1_state mp1_state)
1800 {
1801         uint16_t msg;
1802         int ret;
1803
1804         if (!smu->pm_enabled)
1805                 return -EOPNOTSUPP;
1806
1807         mutex_lock(&smu->mutex);
1808
1809         switch (mp1_state) {
1810         case PP_MP1_STATE_SHUTDOWN:
1811                 msg = SMU_MSG_PrepareMp1ForShutdown;
1812                 break;
1813         case PP_MP1_STATE_UNLOAD:
1814                 msg = SMU_MSG_PrepareMp1ForUnload;
1815                 break;
1816         case PP_MP1_STATE_RESET:
1817                 msg = SMU_MSG_PrepareMp1ForReset;
1818                 break;
1819         case PP_MP1_STATE_NONE:
1820         default:
1821                 mutex_unlock(&smu->mutex);
1822                 return 0;
1823         }
1824
1825         ret = smu_send_smc_msg(smu, msg, NULL);
1826         /* some asics may not support those messages */
1827         if (ret == -EINVAL)
1828                 ret = 0;
1829         if (ret)
1830                 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
1831
1832         mutex_unlock(&smu->mutex);
1833
1834         return ret;
1835 }
1836
1837 int smu_set_df_cstate(struct smu_context *smu,
1838                       enum pp_df_cstate state)
1839 {
1840         int ret = 0;
1841
1842         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1843                 return -EOPNOTSUPP;
1844
1845         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1846                 return 0;
1847
1848         mutex_lock(&smu->mutex);
1849
1850         ret = smu->ppt_funcs->set_df_cstate(smu, state);
1851         if (ret)
1852                 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
1853
1854         mutex_unlock(&smu->mutex);
1855
1856         return ret;
1857 }
1858
1859 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
1860 {
1861         int ret = 0;
1862
1863         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1864                 return -EOPNOTSUPP;
1865
1866         if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
1867                 return 0;
1868
1869         mutex_lock(&smu->mutex);
1870
1871         ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
1872         if (ret)
1873                 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
1874
1875         mutex_unlock(&smu->mutex);
1876
1877         return ret;
1878 }
1879
1880 int smu_write_watermarks_table(struct smu_context *smu)
1881 {
1882         int ret = 0;
1883
1884         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1885                 return -EOPNOTSUPP;
1886
1887         mutex_lock(&smu->mutex);
1888
1889         ret = smu_set_watermarks_table(smu, NULL);
1890
1891         mutex_unlock(&smu->mutex);
1892
1893         return ret;
1894 }
1895
1896 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
1897                 struct pp_smu_wm_range_sets *clock_ranges)
1898 {
1899         int ret = 0;
1900
1901         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1902                 return -EOPNOTSUPP;
1903
1904         if (smu->disable_watermark)
1905                 return 0;
1906
1907         mutex_lock(&smu->mutex);
1908
1909         ret = smu_set_watermarks_table(smu, clock_ranges);
1910
1911         mutex_unlock(&smu->mutex);
1912
1913         return ret;
1914 }
1915
1916 int smu_set_ac_dc(struct smu_context *smu)
1917 {
1918         int ret = 0;
1919
1920         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1921                 return -EOPNOTSUPP;
1922
1923         /* controlled by firmware */
1924         if (smu->dc_controlled_by_gpio)
1925                 return 0;
1926
1927         mutex_lock(&smu->mutex);
1928         ret = smu_set_power_source(smu,
1929                                    smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
1930                                    SMU_POWER_SOURCE_DC);
1931         if (ret)
1932                 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
1933                        smu->adev->pm.ac_power ? "AC" : "DC");
1934         mutex_unlock(&smu->mutex);
1935
1936         return ret;
1937 }
1938
1939 const struct amd_ip_funcs smu_ip_funcs = {
1940         .name = "smu",
1941         .early_init = smu_early_init,
1942         .late_init = smu_late_init,
1943         .sw_init = smu_sw_init,
1944         .sw_fini = smu_sw_fini,
1945         .hw_init = smu_hw_init,
1946         .hw_fini = smu_hw_fini,
1947         .suspend = smu_suspend,
1948         .resume = smu_resume,
1949         .is_idle = NULL,
1950         .check_soft_reset = NULL,
1951         .wait_for_idle = NULL,
1952         .soft_reset = NULL,
1953         .set_clockgating_state = smu_set_clockgating_state,
1954         .set_powergating_state = smu_set_powergating_state,
1955         .enable_umd_pstate = smu_enable_umd_pstate,
1956 };
1957
1958 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1959 {
1960         .type = AMD_IP_BLOCK_TYPE_SMC,
1961         .major = 11,
1962         .minor = 0,
1963         .rev = 0,
1964         .funcs = &smu_ip_funcs,
1965 };
1966
1967 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
1968 {
1969         .type = AMD_IP_BLOCK_TYPE_SMC,
1970         .major = 12,
1971         .minor = 0,
1972         .rev = 0,
1973         .funcs = &smu_ip_funcs,
1974 };
1975
1976 int smu_load_microcode(struct smu_context *smu)
1977 {
1978         int ret = 0;
1979
1980         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1981                 return -EOPNOTSUPP;
1982
1983         mutex_lock(&smu->mutex);
1984
1985         if (smu->ppt_funcs->load_microcode)
1986                 ret = smu->ppt_funcs->load_microcode(smu);
1987
1988         mutex_unlock(&smu->mutex);
1989
1990         return ret;
1991 }
1992
1993 int smu_check_fw_status(struct smu_context *smu)
1994 {
1995         int ret = 0;
1996
1997         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1998                 return -EOPNOTSUPP;
1999
2000         mutex_lock(&smu->mutex);
2001
2002         if (smu->ppt_funcs->check_fw_status)
2003                 ret = smu->ppt_funcs->check_fw_status(smu);
2004
2005         mutex_unlock(&smu->mutex);
2006
2007         return ret;
2008 }
2009
2010 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2011 {
2012         int ret = 0;
2013
2014         mutex_lock(&smu->mutex);
2015
2016         if (smu->ppt_funcs->set_gfx_cgpg)
2017                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2018
2019         mutex_unlock(&smu->mutex);
2020
2021         return ret;
2022 }
2023
2024 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
2025 {
2026         u32 percent;
2027         int ret = 0;
2028
2029         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2030                 return -EOPNOTSUPP;
2031
2032         mutex_lock(&smu->mutex);
2033
2034         if (smu->ppt_funcs->set_fan_speed_percent) {
2035                 percent = speed * 100 / smu->fan_max_rpm;
2036                 ret = smu->ppt_funcs->set_fan_speed_percent(smu, percent);
2037                 if (!ret && smu->user_dpm_profile.flags != SMU_DPM_USER_PROFILE_RESTORE)
2038                         smu->user_dpm_profile.fan_speed_percent = percent;
2039         }
2040
2041         mutex_unlock(&smu->mutex);
2042
2043         return ret;
2044 }
2045
2046 int smu_get_power_limit(struct smu_context *smu,
2047                         uint32_t *limit,
2048                         enum smu_ppt_limit_level limit_level)
2049 {
2050         uint32_t limit_type = *limit >> 24;
2051         int ret = 0;
2052
2053         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2054                 return -EOPNOTSUPP;
2055
2056         mutex_lock(&smu->mutex);
2057
2058         if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
2059                 if (smu->ppt_funcs->get_ppt_limit)
2060                         ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
2061         } else {
2062                 switch (limit_level) {
2063                 case SMU_PPT_LIMIT_CURRENT:
2064                         *limit = smu->current_power_limit;
2065                         break;
2066                 case SMU_PPT_LIMIT_MAX:
2067                         *limit = smu->max_power_limit;
2068                         break;
2069                 default:
2070                         break;
2071                 }
2072         }
2073
2074         mutex_unlock(&smu->mutex);
2075
2076         return ret;
2077 }
2078
2079 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
2080 {
2081         uint32_t limit_type = limit >> 24;
2082         int ret = 0;
2083
2084         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2085                 return -EOPNOTSUPP;
2086
2087         mutex_lock(&smu->mutex);
2088
2089         if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2090                 if (smu->ppt_funcs->set_power_limit) {
2091                         ret = smu->ppt_funcs->set_power_limit(smu, limit);
2092                         goto out;
2093                 }
2094
2095         if (limit > smu->max_power_limit) {
2096                 dev_err(smu->adev->dev,
2097                         "New power limit (%d) is over the max allowed %d\n",
2098                         limit, smu->max_power_limit);
2099                 goto out;
2100         }
2101
2102         if (!limit)
2103                 limit = smu->current_power_limit;
2104
2105         if (smu->ppt_funcs->set_power_limit) {
2106                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2107                 if (!ret && smu->user_dpm_profile.flags != SMU_DPM_USER_PROFILE_RESTORE)
2108                         smu->user_dpm_profile.power_limit = limit;
2109         }
2110
2111 out:
2112         mutex_unlock(&smu->mutex);
2113
2114         return ret;
2115 }
2116
2117 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2118 {
2119         int ret = 0;
2120
2121         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2122                 return -EOPNOTSUPP;
2123
2124         mutex_lock(&smu->mutex);
2125
2126         if (smu->ppt_funcs->print_clk_levels)
2127                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2128
2129         mutex_unlock(&smu->mutex);
2130
2131         return ret;
2132 }
2133
2134 int smu_od_edit_dpm_table(struct smu_context *smu,
2135                           enum PP_OD_DPM_TABLE_COMMAND type,
2136                           long *input, uint32_t size)
2137 {
2138         int ret = 0;
2139
2140         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2141                 return -EOPNOTSUPP;
2142
2143         mutex_lock(&smu->mutex);
2144
2145         if (smu->ppt_funcs->od_edit_dpm_table) {
2146                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2147                 if (!ret && (type == PP_OD_COMMIT_DPM_TABLE))
2148                         ret = smu_handle_task(smu,
2149                                               smu->smu_dpm.dpm_level,
2150                                               AMD_PP_TASK_READJUST_POWER_STATE,
2151                                               false);
2152         }
2153
2154         mutex_unlock(&smu->mutex);
2155
2156         return ret;
2157 }
2158
2159 int smu_read_sensor(struct smu_context *smu,
2160                     enum amd_pp_sensors sensor,
2161                     void *data, uint32_t *size)
2162 {
2163         struct smu_umd_pstate_table *pstate_table =
2164                                 &smu->pstate_table;
2165         int ret = 0;
2166
2167         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2168                 return -EOPNOTSUPP;
2169
2170         if (!data || !size)
2171                 return -EINVAL;
2172
2173         mutex_lock(&smu->mutex);
2174
2175         if (smu->ppt_funcs->read_sensor)
2176                 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2177                         goto unlock;
2178
2179         switch (sensor) {
2180         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2181                 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2182                 *size = 4;
2183                 break;
2184         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2185                 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2186                 *size = 4;
2187                 break;
2188         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2189                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
2190                 *size = 8;
2191                 break;
2192         case AMDGPU_PP_SENSOR_UVD_POWER:
2193                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2194                 *size = 4;
2195                 break;
2196         case AMDGPU_PP_SENSOR_VCE_POWER:
2197                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2198                 *size = 4;
2199                 break;
2200         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2201                 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2202                 *size = 4;
2203                 break;
2204         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2205                 *(uint32_t *)data = 0;
2206                 *size = 4;
2207                 break;
2208         default:
2209                 *size = 0;
2210                 ret = -EOPNOTSUPP;
2211                 break;
2212         }
2213
2214 unlock:
2215         mutex_unlock(&smu->mutex);
2216
2217         return ret;
2218 }
2219
2220 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2221 {
2222         int ret = 0;
2223
2224         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2225                 return -EOPNOTSUPP;
2226
2227         mutex_lock(&smu->mutex);
2228
2229         if (smu->ppt_funcs->get_power_profile_mode)
2230                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2231
2232         mutex_unlock(&smu->mutex);
2233
2234         return ret;
2235 }
2236
2237 int smu_set_power_profile_mode(struct smu_context *smu,
2238                                long *param,
2239                                uint32_t param_size,
2240                                bool lock_needed)
2241 {
2242         int ret = 0;
2243
2244         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2245                 return -EOPNOTSUPP;
2246
2247         if (lock_needed)
2248                 mutex_lock(&smu->mutex);
2249
2250         if (smu->ppt_funcs->set_power_profile_mode)
2251                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2252
2253         if (lock_needed)
2254                 mutex_unlock(&smu->mutex);
2255
2256         return ret;
2257 }
2258
2259
2260 int smu_get_fan_control_mode(struct smu_context *smu)
2261 {
2262         int ret = 0;
2263
2264         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2265                 return -EOPNOTSUPP;
2266
2267         mutex_lock(&smu->mutex);
2268
2269         if (smu->ppt_funcs->get_fan_control_mode)
2270                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2271
2272         mutex_unlock(&smu->mutex);
2273
2274         return ret;
2275 }
2276
2277 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2278 {
2279         int ret = 0;
2280
2281         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2282                 return -EOPNOTSUPP;
2283
2284         mutex_lock(&smu->mutex);
2285
2286         if (smu->ppt_funcs->set_fan_control_mode) {
2287                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2288                 if (!ret && smu->user_dpm_profile.flags != SMU_DPM_USER_PROFILE_RESTORE)
2289                         smu->user_dpm_profile.fan_mode = value;
2290         }
2291
2292         mutex_unlock(&smu->mutex);
2293
2294         /* reset user dpm fan speed */
2295         if (!ret && value != AMD_FAN_CTRL_MANUAL &&
2296                         smu->user_dpm_profile.flags != SMU_DPM_USER_PROFILE_RESTORE)
2297                 smu->user_dpm_profile.fan_speed_percent = 0;
2298
2299         return ret;
2300 }
2301
2302 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2303 {
2304         int ret = 0;
2305         uint32_t percent;
2306
2307         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2308                 return -EOPNOTSUPP;
2309
2310         mutex_lock(&smu->mutex);
2311
2312         if (smu->ppt_funcs->get_fan_speed_percent) {
2313                 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent);
2314                 if (!ret) {
2315                         *speed = percent > 100 ? 100 : percent;
2316                 }
2317         }
2318
2319         mutex_unlock(&smu->mutex);
2320
2321
2322         return ret;
2323 }
2324
2325 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2326 {
2327         int ret = 0;
2328
2329         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2330                 return -EOPNOTSUPP;
2331
2332         mutex_lock(&smu->mutex);
2333
2334         if (smu->ppt_funcs->set_fan_speed_percent) {
2335                 if (speed > 100)
2336                         speed = 100;
2337                 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
2338                 if (!ret && smu->user_dpm_profile.flags != SMU_DPM_USER_PROFILE_RESTORE)
2339                         smu->user_dpm_profile.fan_speed_percent = speed;
2340         }
2341
2342         mutex_unlock(&smu->mutex);
2343
2344         return ret;
2345 }
2346
2347 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2348 {
2349         int ret = 0;
2350         u32 percent;
2351
2352         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2353                 return -EOPNOTSUPP;
2354
2355         mutex_lock(&smu->mutex);
2356
2357         if (smu->ppt_funcs->get_fan_speed_percent) {
2358                 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent);
2359                 *speed = percent * smu->fan_max_rpm / 100;
2360         }
2361
2362         mutex_unlock(&smu->mutex);
2363
2364         return ret;
2365 }
2366
2367 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2368 {
2369         int ret = 0;
2370
2371         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2372                 return -EOPNOTSUPP;
2373
2374         mutex_lock(&smu->mutex);
2375
2376         ret = smu_set_min_dcef_deep_sleep(smu, clk);
2377
2378         mutex_unlock(&smu->mutex);
2379
2380         return ret;
2381 }
2382
2383 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2384                                        enum smu_clk_type clk_type,
2385                                        struct pp_clock_levels_with_latency *clocks)
2386 {
2387         int ret = 0;
2388
2389         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2390                 return -EOPNOTSUPP;
2391
2392         mutex_lock(&smu->mutex);
2393
2394         if (smu->ppt_funcs->get_clock_by_type_with_latency)
2395                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2396
2397         mutex_unlock(&smu->mutex);
2398
2399         return ret;
2400 }
2401
2402 int smu_display_clock_voltage_request(struct smu_context *smu,
2403                                       struct pp_display_clock_request *clock_req)
2404 {
2405         int ret = 0;
2406
2407         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2408                 return -EOPNOTSUPP;
2409
2410         mutex_lock(&smu->mutex);
2411
2412         if (smu->ppt_funcs->display_clock_voltage_request)
2413                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2414
2415         mutex_unlock(&smu->mutex);
2416
2417         return ret;
2418 }
2419
2420
2421 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2422 {
2423         int ret = -EINVAL;
2424
2425         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2426                 return -EOPNOTSUPP;
2427
2428         mutex_lock(&smu->mutex);
2429
2430         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2431                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2432
2433         mutex_unlock(&smu->mutex);
2434
2435         return ret;
2436 }
2437
2438 int smu_set_xgmi_pstate(struct smu_context *smu,
2439                         uint32_t pstate)
2440 {
2441         int ret = 0;
2442
2443         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2444                 return -EOPNOTSUPP;
2445
2446         mutex_lock(&smu->mutex);
2447
2448         if (smu->ppt_funcs->set_xgmi_pstate)
2449                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2450
2451         mutex_unlock(&smu->mutex);
2452
2453         if(ret)
2454                 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2455
2456         return ret;
2457 }
2458
2459 int smu_set_azalia_d3_pme(struct smu_context *smu)
2460 {
2461         int ret = 0;
2462
2463         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2464                 return -EOPNOTSUPP;
2465
2466         mutex_lock(&smu->mutex);
2467
2468         if (smu->ppt_funcs->set_azalia_d3_pme)
2469                 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2470
2471         mutex_unlock(&smu->mutex);
2472
2473         return ret;
2474 }
2475
2476 /*
2477  * On system suspending or resetting, the dpm_enabled
2478  * flag will be cleared. So that those SMU services which
2479  * are not supported will be gated.
2480  *
2481  * However, the baco/mode1 reset should still be granted
2482  * as they are still supported and necessary.
2483  */
2484 bool smu_baco_is_support(struct smu_context *smu)
2485 {
2486         bool ret = false;
2487
2488         if (!smu->pm_enabled)
2489                 return false;
2490
2491         mutex_lock(&smu->mutex);
2492
2493         if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2494                 ret = smu->ppt_funcs->baco_is_support(smu);
2495
2496         mutex_unlock(&smu->mutex);
2497
2498         return ret;
2499 }
2500
2501 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2502 {
2503         if (smu->ppt_funcs->baco_get_state)
2504                 return -EINVAL;
2505
2506         mutex_lock(&smu->mutex);
2507         *state = smu->ppt_funcs->baco_get_state(smu);
2508         mutex_unlock(&smu->mutex);
2509
2510         return 0;
2511 }
2512
2513 int smu_baco_enter(struct smu_context *smu)
2514 {
2515         int ret = 0;
2516
2517         if (!smu->pm_enabled)
2518                 return -EOPNOTSUPP;
2519
2520         mutex_lock(&smu->mutex);
2521
2522         if (smu->ppt_funcs->baco_enter)
2523                 ret = smu->ppt_funcs->baco_enter(smu);
2524
2525         mutex_unlock(&smu->mutex);
2526
2527         if (ret)
2528                 dev_err(smu->adev->dev, "Failed to enter BACO state!\n");
2529
2530         return ret;
2531 }
2532
2533 int smu_baco_exit(struct smu_context *smu)
2534 {
2535         int ret = 0;
2536
2537         if (!smu->pm_enabled)
2538                 return -EOPNOTSUPP;
2539
2540         mutex_lock(&smu->mutex);
2541
2542         if (smu->ppt_funcs->baco_exit)
2543                 ret = smu->ppt_funcs->baco_exit(smu);
2544
2545         mutex_unlock(&smu->mutex);
2546
2547         if (ret)
2548                 dev_err(smu->adev->dev, "Failed to exit BACO state!\n");
2549
2550         return ret;
2551 }
2552
2553 bool smu_mode1_reset_is_support(struct smu_context *smu)
2554 {
2555         bool ret = false;
2556
2557         if (!smu->pm_enabled)
2558                 return false;
2559
2560         mutex_lock(&smu->mutex);
2561
2562         if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2563                 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2564
2565         mutex_unlock(&smu->mutex);
2566
2567         return ret;
2568 }
2569
2570 int smu_mode1_reset(struct smu_context *smu)
2571 {
2572         int ret = 0;
2573
2574         if (!smu->pm_enabled)
2575                 return -EOPNOTSUPP;
2576
2577         mutex_lock(&smu->mutex);
2578
2579         if (smu->ppt_funcs->mode1_reset)
2580                 ret = smu->ppt_funcs->mode1_reset(smu);
2581
2582         mutex_unlock(&smu->mutex);
2583
2584         return ret;
2585 }
2586
2587 int smu_mode2_reset(struct smu_context *smu)
2588 {
2589         int ret = 0;
2590
2591         if (!smu->pm_enabled)
2592                 return -EOPNOTSUPP;
2593
2594         mutex_lock(&smu->mutex);
2595
2596         if (smu->ppt_funcs->mode2_reset)
2597                 ret = smu->ppt_funcs->mode2_reset(smu);
2598
2599         mutex_unlock(&smu->mutex);
2600
2601         if (ret)
2602                 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2603
2604         return ret;
2605 }
2606
2607 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2608                                          struct pp_smu_nv_clock_table *max_clocks)
2609 {
2610         int ret = 0;
2611
2612         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2613                 return -EOPNOTSUPP;
2614
2615         mutex_lock(&smu->mutex);
2616
2617         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2618                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2619
2620         mutex_unlock(&smu->mutex);
2621
2622         return ret;
2623 }
2624
2625 int smu_get_uclk_dpm_states(struct smu_context *smu,
2626                             unsigned int *clock_values_in_khz,
2627                             unsigned int *num_states)
2628 {
2629         int ret = 0;
2630
2631         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2632                 return -EOPNOTSUPP;
2633
2634         mutex_lock(&smu->mutex);
2635
2636         if (smu->ppt_funcs->get_uclk_dpm_states)
2637                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2638
2639         mutex_unlock(&smu->mutex);
2640
2641         return ret;
2642 }
2643
2644 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2645 {
2646         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2647
2648         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2649                 return -EOPNOTSUPP;
2650
2651         mutex_lock(&smu->mutex);
2652
2653         if (smu->ppt_funcs->get_current_power_state)
2654                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2655
2656         mutex_unlock(&smu->mutex);
2657
2658         return pm_state;
2659 }
2660
2661 int smu_get_dpm_clock_table(struct smu_context *smu,
2662                             struct dpm_clocks *clock_table)
2663 {
2664         int ret = 0;
2665
2666         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2667                 return -EOPNOTSUPP;
2668
2669         mutex_lock(&smu->mutex);
2670
2671         if (smu->ppt_funcs->get_dpm_clock_table)
2672                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2673
2674         mutex_unlock(&smu->mutex);
2675
2676         return ret;
2677 }
2678
2679 ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu,
2680                                 void **table)
2681 {
2682         ssize_t size;
2683
2684         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2685                 return -EOPNOTSUPP;
2686
2687         if (!smu->ppt_funcs->get_gpu_metrics)
2688                 return -EOPNOTSUPP;
2689
2690         mutex_lock(&smu->mutex);
2691
2692         size = smu->ppt_funcs->get_gpu_metrics(smu, table);
2693
2694         mutex_unlock(&smu->mutex);
2695
2696         return size;
2697 }
2698
2699 int smu_enable_mgpu_fan_boost(struct smu_context *smu)
2700 {
2701         int ret = 0;
2702
2703         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2704                 return -EOPNOTSUPP;
2705
2706         mutex_lock(&smu->mutex);
2707
2708         if (smu->ppt_funcs->enable_mgpu_fan_boost)
2709                 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
2710
2711         mutex_unlock(&smu->mutex);
2712
2713         return ret;
2714 }
2715
2716 int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state)
2717 {
2718         int ret = 0;
2719
2720         mutex_lock(&smu->mutex);
2721         if (smu->ppt_funcs->gfx_state_change_set)
2722                 ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
2723         mutex_unlock(&smu->mutex);
2724
2725         return ret;
2726 }