drivers/gpu/drm/amd/amdkfd/kfd_topology.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #ifndef __KFD_TOPOLOGY_H__
  24 #define __KFD_TOPOLOGY_H__
  25
  26 #include <linux/types.h>
  27 #include <linux/list.h>
  28 #include "kfd_priv.h"
  29
  30 #define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 128
  31
  32 #define HSA_CAP_HOT_PLUGGABLE                   0x00000001
  33 #define HSA_CAP_ATS_PRESENT                     0x00000002
  34 #define HSA_CAP_SHARED_WITH_GRAPHICS            0x00000004
  35 #define HSA_CAP_QUEUE_SIZE_POW2                 0x00000008
  36 #define HSA_CAP_QUEUE_SIZE_32BIT                0x00000010
  37 #define HSA_CAP_QUEUE_IDLE_EVENT                0x00000020
  38 #define HSA_CAP_VA_LIMIT                        0x00000040
  39 #define HSA_CAP_WATCH_POINTS_SUPPORTED          0x00000080
  40 #define HSA_CAP_WATCH_POINTS_TOTALBITS_MASK     0x00000f00
  41 #define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT    8
  42 #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK    0x00003000
  43 #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT   12
  44 #define HSA_CAP_RESERVED                        0xffffc000
  45
  46 #define HSA_CAP_DOORBELL_TYPE_PRE_1_0           0x0
  47 #define HSA_CAP_DOORBELL_TYPE_1_0               0x1
  48 #define HSA_CAP_AQL_QUEUE_DOUBLE_MAP            0x00004000
  49
  50 struct kfd_node_properties {
  51         uint32_t cpu_cores_count;
  52         uint32_t simd_count;
  53         uint32_t mem_banks_count;
  54         uint32_t caches_count;
  55         uint32_t io_links_count;
  56         uint32_t cpu_core_id_base;
  57         uint32_t simd_id_base;
  58         uint32_t capability;
  59         uint32_t max_waves_per_simd;
  60         uint32_t lds_size_in_kb;
  61         uint32_t gds_size_in_kb;
  62         uint32_t wave_front_size;
  63         uint32_t array_count;
  64         uint32_t simd_arrays_per_engine;
  65         uint32_t cu_per_simd_array;
  66         uint32_t simd_per_cu;
  67         uint32_t max_slots_scratch_cu;
  68         uint32_t engine_id;
  69         uint32_t vendor_id;
  70         uint32_t device_id;
  71         uint32_t location_id;
  72         uint32_t max_engine_clk_fcompute;
  73         uint32_t max_engine_clk_ccompute;
  74         uint16_t marketing_name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
  75 };
  76
  77 #define HSA_MEM_HEAP_TYPE_SYSTEM        0
  78 #define HSA_MEM_HEAP_TYPE_FB_PUBLIC     1
  79 #define HSA_MEM_HEAP_TYPE_FB_PRIVATE    2
  80 #define HSA_MEM_HEAP_TYPE_GPU_GDS       3
  81 #define HSA_MEM_HEAP_TYPE_GPU_LDS       4
  82 #define HSA_MEM_HEAP_TYPE_GPU_SCRATCH   5
  83
  84 #define HSA_MEM_FLAGS_HOT_PLUGGABLE     0x00000001
  85 #define HSA_MEM_FLAGS_NON_VOLATILE      0x00000002
  86 #define HSA_MEM_FLAGS_RESERVED          0xfffffffc
  87
  88 struct kfd_mem_properties {
  89         struct list_head        list;
  90         uint32_t                heap_type;
  91         uint64_t                size_in_bytes;
  92         uint32_t                flags;
  93         uint32_t                width;
  94         uint32_t                mem_clk_max;
  95         struct kobject          *kobj;
  96         struct attribute        attr;
  97 };
  98
  99 #define HSA_CACHE_TYPE_DATA             0x00000001
 100 #define HSA_CACHE_TYPE_INSTRUCTION      0x00000002
 101 #define HSA_CACHE_TYPE_CPU              0x00000004
 102 #define HSA_CACHE_TYPE_HSACU            0x00000008
 103 #define HSA_CACHE_TYPE_RESERVED         0xfffffff0
 104
 105 struct kfd_cache_properties {
 106         struct list_head        list;
 107         uint32_t                processor_id_low;
 108         uint32_t                cache_level;
 109         uint32_t                cache_size;
 110         uint32_t                cacheline_size;
 111         uint32_t                cachelines_per_tag;
 112         uint32_t                cache_assoc;
 113         uint32_t                cache_latency;
 114         uint32_t                cache_type;
 115         uint8_t                 sibling_map[CRAT_SIBLINGMAP_SIZE];
 116         struct kobject          *kobj;
 117         struct attribute        attr;
 118 };
 119
 120 struct kfd_iolink_properties {
 121         struct list_head        list;
 122         uint32_t                iolink_type;
 123         uint32_t                ver_maj;
 124         uint32_t                ver_min;
 125         uint32_t                node_from;
 126         uint32_t                node_to;
 127         uint32_t                weight;
 128         uint32_t                min_latency;
 129         uint32_t                max_latency;
 130         uint32_t                min_bandwidth;
 131         uint32_t                max_bandwidth;
 132         uint32_t                rec_transfer_size;
 133         uint32_t                flags;
 134         struct kobject          *kobj;
 135         struct attribute        attr;
 136 };
 137
 138 struct kfd_perf_properties {
 139         struct list_head        list;
 140         char                    block_name[16];
 141         uint32_t                max_concurrent;
 142         struct attribute_group  *attr_group;
 143 };
 144
 145 struct kfd_topology_device {
 146         struct list_head                list;
 147         uint32_t                        gpu_id;
 148         uint32_t                        proximity_domain;
 149         struct kfd_node_properties      node_props;
 150         struct list_head                mem_props;
 151         uint32_t                        cache_count;
 152         struct list_head                cache_props;
 153         uint32_t                        io_link_count;
 154         struct list_head                io_link_props;
 155         struct list_head                perf_props;
 156         struct kfd_dev                  *gpu;
 157         struct kobject                  *kobj_node;
 158         struct kobject                  *kobj_mem;
 159         struct kobject                  *kobj_cache;
 160         struct kobject                  *kobj_iolink;
 161         struct kobject                  *kobj_perf;
 162         struct attribute                attr_gpuid;
 163         struct attribute                attr_name;
 164         struct attribute                attr_props;
 165         uint8_t                         oem_id[CRAT_OEMID_LENGTH];
 166         uint8_t                         oem_table_id[CRAT_OEMTABLEID_LENGTH];
 167         uint32_t                        oem_revision;
 168 };
 169
 170 struct kfd_system_properties {
 171         uint32_t                num_devices;     /* Number of H-NUMA nodes */
 172         uint32_t                generation_count;
 173         uint64_t                platform_oem;
 174         uint64_t                platform_id;
 175         uint64_t                platform_rev;
 176         struct kobject          *kobj_topology;
 177         struct kobject          *kobj_nodes;
 178         struct attribute        attr_genid;
 179         struct attribute        attr_props;
 180 };
 181
 182 struct kfd_topology_device *kfd_create_topology_device(
 183                 struct list_head *device_list);
 184 void kfd_release_topology_device_list(struct list_head *device_list);
 185
 186 extern bool amd_iommu_pc_supported(void);
 187 extern u8 amd_iommu_pc_get_max_banks(u16 devid);
 188 extern u8 amd_iommu_pc_get_max_counters(u16 devid);
 189
 190 #endif /* __KFD_TOPOLOGY_H__ */