kernel/dma/direct.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Christoph Hellwig.
   4  *
   5  * DMA operations that map physical memory directly without using an IOMMU.
   6  */
   7 #include <linux/memblock.h> /* for max_pfn */
   8 #include <linux/export.h>
   9 #include <linux/mm.h>
  10 #include <linux/dma-direct.h>
  11 #include <linux/scatterlist.h>
  12 #include <linux/dma-contiguous.h>
  13 #include <linux/pfn.h>
  14 #include <linux/vmalloc.h>
  15 #include <linux/set_memory.h>
  16 #include <linux/slab.h>
  17
  18 /*
  19  * Most architectures use ZONE_DMA for the first 16 Megabytes, but some use it
  20  * it for entirely different regions. In that case the arch code needs to
  21  * override the variable below for dma-direct to work properly.
  22  */
  23 unsigned int zone_dma_bits __ro_after_init = 24;
  24
  25 static inline dma_addr_t phys_to_dma_direct(struct device *dev,
  26                 phys_addr_t phys)
  27 {
  28         if (force_dma_unencrypted(dev))
  29                 return phys_to_dma_unencrypted(dev, phys);
  30         return phys_to_dma(dev, phys);
  31 }
  32
  33 static inline struct page *dma_direct_to_page(struct device *dev,
  34                 dma_addr_t dma_addr)
  35 {
  36         return pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_addr)));
  37 }
  38
  39 u64 dma_direct_get_required_mask(struct device *dev)
  40 {
  41         phys_addr_t phys = (phys_addr_t)(max_pfn - 1) << PAGE_SHIFT;
  42         u64 max_dma = phys_to_dma_direct(dev, phys);
  43
  44         return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
  45 }
  46
  47 static gfp_t dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
  48                                   u64 *phys_limit)
  49 {
  50         u64 dma_limit = min_not_zero(dma_mask, dev->bus_dma_limit);
  51
  52         /*
  53          * Optimistically try the zone that the physical address mask falls
  54          * into first.  If that returns memory that isn't actually addressable
  55          * we will fallback to the next lower zone and try again.
  56          *
  57          * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
  58          * zones.
  59          */
  60         *phys_limit = dma_to_phys(dev, dma_limit);
  61         if (*phys_limit <= DMA_BIT_MASK(zone_dma_bits))
  62                 return GFP_DMA;
  63         if (*phys_limit <= DMA_BIT_MASK(32))
  64                 return GFP_DMA32;
  65         return 0;
  66 }
  67
  68 static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
  69 {
  70         dma_addr_t dma_addr = phys_to_dma_direct(dev, phys);
  71
  72         if (dma_addr == DMA_MAPPING_ERROR)
  73                 return false;
  74         return dma_addr + size - 1 <=
  75                 min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
  76 }
  77
  78 /*
  79  * Decrypting memory is allowed to block, so if this device requires
  80  * unencrypted memory it must come from atomic pools.
  81  */
  82 static inline bool dma_should_alloc_from_pool(struct device *dev, gfp_t gfp,
  83                                               unsigned long attrs)
  84 {
  85         if (!IS_ENABLED(CONFIG_DMA_COHERENT_POOL))
  86                 return false;
  87         if (gfpflags_allow_blocking(gfp))
  88                 return false;
  89         if (force_dma_unencrypted(dev))
  90                 return true;
  91         if (!IS_ENABLED(CONFIG_DMA_DIRECT_REMAP))
  92                 return false;
  93         if (dma_alloc_need_uncached(dev, attrs))
  94                 return true;
  95         return false;
  96 }
  97
  98 static inline bool dma_should_free_from_pool(struct device *dev,
  99                                              unsigned long attrs)
 100 {
 101         if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL))
 102                 return true;
 103         if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
 104             !force_dma_unencrypted(dev))
 105                 return false;
 106         if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP))
 107                 return true;
 108         return false;
 109 }
 110
 111 static struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
 112                 gfp_t gfp)
 113 {
 114         int node = dev_to_node(dev);
 115         struct page *page = NULL;
 116         u64 phys_limit;
 117
 118         WARN_ON_ONCE(!PAGE_ALIGNED(size));
 119
 120         gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
 121                                            &phys_limit);
 122         page = dma_alloc_contiguous(dev, size, gfp);
 123         if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
 124                 dma_free_contiguous(dev, page, size);
 125                 page = NULL;
 126         }
 127 again:
 128         if (!page)
 129                 page = alloc_pages_node(node, gfp, get_order(size));
 130         if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
 131                 dma_free_contiguous(dev, page, size);
 132                 page = NULL;
 133
 134                 if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
 135                     phys_limit < DMA_BIT_MASK(64) &&
 136                     !(gfp & (GFP_DMA32 | GFP_DMA))) {
 137                         gfp |= GFP_DMA32;
 138                         goto again;
 139                 }
 140
 141                 if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) {
 142                         gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
 143                         goto again;
 144                 }
 145         }
 146
 147         return page;
 148 }
 149
 150 void *dma_direct_alloc(struct device *dev, size_t size,
 151                 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
 152 {
 153         struct page *page;
 154         void *ret;
 155         int err;
 156
 157         if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
 158             !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
 159             dma_alloc_need_uncached(dev, attrs))
 160                 return arch_dma_alloc(dev, size, dma_handle, gfp, attrs);
 161
 162         size = PAGE_ALIGN(size);
 163         if (attrs & DMA_ATTR_NO_WARN)
 164                 gfp |= __GFP_NOWARN;
 165
 166         if (dma_should_alloc_from_pool(dev, gfp, attrs)) {
 167                 u64 phys_mask;
 168
 169                 gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
 170                                 &phys_mask);
 171                 page = dma_alloc_from_pool(dev, size, &ret, gfp,
 172                                 dma_coherent_ok);
 173                 if (!page)
 174                         return NULL;
 175                 goto done;
 176         }
 177
 178         /* we always manually zero the memory once we are done */
 179         page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO);
 180         if (!page)
 181                 return NULL;
 182
 183         if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
 184             !force_dma_unencrypted(dev)) {
 185                 /* remove any dirty cache lines on the kernel alias */
 186                 if (!PageHighMem(page))
 187                         arch_dma_prep_coherent(page, size);
 188                 /* return the page pointer as the opaque cookie */
 189                 ret = page;
 190                 goto done;
 191         }
 192
 193         if ((IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
 194              dma_alloc_need_uncached(dev, attrs)) ||
 195             (IS_ENABLED(CONFIG_DMA_REMAP) && PageHighMem(page))) {
 196                 /* remove any dirty cache lines on the kernel alias */
 197                 arch_dma_prep_coherent(page, size);
 198
 199                 /* create a coherent mapping */
 200                 ret = dma_common_contiguous_remap(page, size,
 201                                 dma_pgprot(dev, PAGE_KERNEL, attrs),
 202                                 __builtin_return_address(0));
 203                 if (!ret)
 204                         goto out_free_pages;
 205                 if (force_dma_unencrypted(dev)) {
 206                         err = set_memory_decrypted((unsigned long)ret,
 207                                                    1 << get_order(size));
 208                         if (err)
 209                                 goto out_free_pages;
 210                 }
 211                 memset(ret, 0, size);
 212                 goto done;
 213         }
 214
 215         if (PageHighMem(page)) {
 216                 /*
 217                  * Depending on the cma= arguments and per-arch setup
 218                  * dma_alloc_contiguous could return highmem pages.
 219                  * Without remapping there is no way to return them here,
 220                  * so log an error and fail.
 221                  */
 222                 dev_info(dev, "Rejecting highmem page from CMA.\n");
 223                 goto out_free_pages;
 224         }
 225
 226         ret = page_address(page);
 227         if (force_dma_unencrypted(dev)) {
 228                 err = set_memory_decrypted((unsigned long)ret,
 229                                            1 << get_order(size));
 230                 if (err)
 231                         goto out_free_pages;
 232         }
 233
 234         memset(ret, 0, size);
 235
 236         if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
 237             dma_alloc_need_uncached(dev, attrs)) {
 238                 arch_dma_prep_coherent(page, size);
 239                 ret = arch_dma_set_uncached(ret, size);
 240                 if (IS_ERR(ret))
 241                         goto out_encrypt_pages;
 242         }
 243 done:
 244         *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
 245         return ret;
 246
 247 out_encrypt_pages:
 248         if (force_dma_unencrypted(dev)) {
 249                 err = set_memory_encrypted((unsigned long)page_address(page),
 250                                            1 << get_order(size));
 251                 /* If memory cannot be re-encrypted, it must be leaked */
 252                 if (err)
 253                         return NULL;
 254         }
 255 out_free_pages:
 256         dma_free_contiguous(dev, page, size);
 257         return NULL;
 258 }
 259
 260 void dma_direct_free(struct device *dev, size_t size,
 261                 void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
 262 {
 263         unsigned int page_order = get_order(size);
 264
 265         if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
 266             !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
 267             dma_alloc_need_uncached(dev, attrs)) {
 268                 arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
 269                 return;
 270         }
 271
 272         /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
 273         if (dma_should_free_from_pool(dev, attrs) &&
 274             dma_free_from_pool(dev, cpu_addr, PAGE_ALIGN(size)))
 275                 return;
 276
 277         if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
 278             !force_dma_unencrypted(dev)) {
 279                 /* cpu_addr is a struct page cookie, not a kernel address */
 280                 dma_free_contiguous(dev, cpu_addr, size);
 281                 return;
 282         }
 283
 284         if (force_dma_unencrypted(dev))
 285                 set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
 286
 287         if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr))
 288                 vunmap(cpu_addr);
 289         else if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CLEAR_UNCACHED))
 290                 arch_dma_clear_uncached(cpu_addr, size);
 291
 292         dma_free_contiguous(dev, dma_direct_to_page(dev, dma_addr), size);
 293 }
 294
 295 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
 296     defined(CONFIG_SWIOTLB)
 297 void dma_direct_sync_sg_for_device(struct device *dev,
 298                 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
 299 {
 300         struct scatterlist *sg;
 301         int i;
 302
 303         for_each_sg(sgl, sg, nents, i) {
 304                 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
 305
 306                 if (unlikely(is_swiotlb_buffer(paddr)))
 307                         swiotlb_tbl_sync_single(dev, paddr, sg->length,
 308                                         dir, SYNC_FOR_DEVICE);
 309
 310                 if (!dev_is_dma_coherent(dev))
 311                         arch_sync_dma_for_device(paddr, sg->length,
 312                                         dir);
 313         }
 314 }
 315 #endif
 316
 317 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
 318     defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
 319     defined(CONFIG_SWIOTLB)
 320 void dma_direct_sync_sg_for_cpu(struct device *dev,
 321                 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
 322 {
 323         struct scatterlist *sg;
 324         int i;
 325
 326         for_each_sg(sgl, sg, nents, i) {
 327                 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
 328
 329                 if (!dev_is_dma_coherent(dev))
 330                         arch_sync_dma_for_cpu(paddr, sg->length, dir);
 331
 332                 if (unlikely(is_swiotlb_buffer(paddr)))
 333                         swiotlb_tbl_sync_single(dev, paddr, sg->length, dir,
 334                                         SYNC_FOR_CPU);
 335
 336                 if (dir == DMA_FROM_DEVICE)
 337                         arch_dma_mark_clean(paddr, sg->length);
 338         }
 339
 340         if (!dev_is_dma_coherent(dev))
 341                 arch_sync_dma_for_cpu_all();
 342 }
 343
 344 void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
 345                 int nents, enum dma_data_direction dir, unsigned long attrs)
 346 {
 347         struct scatterlist *sg;
 348         int i;
 349
 350         for_each_sg(sgl, sg, nents, i)
 351                 dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir,
 352                              attrs);
 353 }
 354 #endif
 355
 356 int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
 357                 enum dma_data_direction dir, unsigned long attrs)
 358 {
 359         int i;
 360         struct scatterlist *sg;
 361
 362         for_each_sg(sgl, sg, nents, i) {
 363                 sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
 364                                 sg->offset, sg->length, dir, attrs);
 365                 if (sg->dma_address == DMA_MAPPING_ERROR)
 366                         goto out_unmap;
 367                 sg_dma_len(sg) = sg->length;
 368         }
 369
 370         return nents;
 371
 372 out_unmap:
 373         dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
 374         return 0;
 375 }
 376
 377 dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
 378                 size_t size, enum dma_data_direction dir, unsigned long attrs)
 379 {
 380         dma_addr_t dma_addr = paddr;
 381
 382         if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
 383                 dev_err_once(dev,
 384                              "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
 385                              &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
 386                 WARN_ON_ONCE(1);
 387                 return DMA_MAPPING_ERROR;
 388         }
 389
 390         return dma_addr;
 391 }
 392
 393 int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt,
 394                 void *cpu_addr, dma_addr_t dma_addr, size_t size,
 395                 unsigned long attrs)
 396 {
 397         struct page *page = dma_direct_to_page(dev, dma_addr);
 398         int ret;
 399
 400         ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
 401         if (!ret)
 402                 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
 403         return ret;
 404 }
 405
 406 bool dma_direct_can_mmap(struct device *dev)
 407 {
 408         return dev_is_dma_coherent(dev) ||
 409                 IS_ENABLED(CONFIG_DMA_NONCOHERENT_MMAP);
 410 }
 411
 412 int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma,
 413                 void *cpu_addr, dma_addr_t dma_addr, size_t size,
 414                 unsigned long attrs)
 415 {
 416         unsigned long user_count = vma_pages(vma);
 417         unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
 418         unsigned long pfn = PHYS_PFN(dma_to_phys(dev, dma_addr));
 419         int ret = -ENXIO;
 420
 421         vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
 422
 423         if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
 424                 return ret;
 425
 426         if (vma->vm_pgoff >= count || user_count > count - vma->vm_pgoff)
 427                 return -ENXIO;
 428         return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
 429                         user_count << PAGE_SHIFT, vma->vm_page_prot);
 430 }
 431
 432 int dma_direct_supported(struct device *dev, u64 mask)
 433 {
 434         u64 min_mask = (max_pfn - 1) << PAGE_SHIFT;
 435
 436         /*
 437          * Because 32-bit DMA masks are so common we expect every architecture
 438          * to be able to satisfy them - either by not supporting more physical
 439          * memory, or by providing a ZONE_DMA32.  If neither is the case, the
 440          * architecture needs to use an IOMMU instead of the direct mapping.
 441          */
 442         if (mask >= DMA_BIT_MASK(32))
 443                 return 1;
 444
 445         /*
 446          * This check needs to be against the actual bit mask value, so use
 447          * phys_to_dma_unencrypted() here so that the SME encryption mask isn't
 448          * part of the check.
 449          */
 450         if (IS_ENABLED(CONFIG_ZONE_DMA))
 451                 min_mask = min_t(u64, min_mask, DMA_BIT_MASK(zone_dma_bits));
 452         return mask >= phys_to_dma_unencrypted(dev, min_mask);
 453 }
 454
 455 size_t dma_direct_max_mapping_size(struct device *dev)
 456 {
 457         /* If SWIOTLB is active, use its maximum mapping size */
 458         if (is_swiotlb_active() &&
 459             (dma_addressing_limited(dev) || swiotlb_force == SWIOTLB_FORCE))
 460                 return swiotlb_max_mapping_size(dev);
 461         return SIZE_MAX;
 462 }
 463
 464 bool dma_direct_need_sync(struct device *dev, dma_addr_t dma_addr)
 465 {
 466         return !dev_is_dma_coherent(dev) ||
 467                 is_swiotlb_buffer(dma_to_phys(dev, dma_addr));
 468 }
 469
 470 /**
 471  * dma_direct_set_offset - Assign scalar offset for a single DMA range.
 472  * @dev:        device pointer; needed to "own" the alloced memory.
 473  * @cpu_start:  beginning of memory region covered by this offset.
 474  * @dma_start:  beginning of DMA/PCI region covered by this offset.
 475  * @size:       size of the region.
 476  *
 477  * This is for the simple case of a uniform offset which cannot
 478  * be discovered by "dma-ranges".
 479  *
 480  * It returns -ENOMEM if out of memory, -EINVAL if a map
 481  * already exists, 0 otherwise.
 482  *
 483  * Note: any call to this from a driver is a bug.  The mapping needs
 484  * to be described by the device tree or other firmware interfaces.
 485  */
 486 int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start,
 487                          dma_addr_t dma_start, u64 size)
 488 {
 489         struct bus_dma_region *map;
 490         u64 offset = (u64)cpu_start - (u64)dma_start;
 491
 492         if (dev->dma_range_map) {
 493                 dev_err(dev, "attempt to add DMA range to existing map\n");
 494                 return -EINVAL;
 495         }
 496
 497         if (!offset)
 498                 return 0;
 499
 500         map = kcalloc(2, sizeof(*map), GFP_KERNEL);
 501         if (!map)
 502                 return -ENOMEM;
 503         map[0].cpu_start = cpu_start;
 504         map[0].dma_start = dma_start;
 505         map[0].offset = offset;
 506         map[0].size = size;
 507         dev->dma_range_map = map;
 508         return 0;
 509 }
 510 EXPORT_SYMBOL_GPL(dma_direct_set_offset);