drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "amdgpu_dm_trace.h"
  41 #include "dpcd_defs.h"
  42 #include "link/protocols/link_dpcd.h"
  43 #include "link_service_types.h"
  44 #include "link/protocols/link_dp_capability.h"
  45 #include "link/protocols/link_ddc.h"
  46
  47 #include "vid.h"
  48 #include "amdgpu.h"
  49 #include "amdgpu_display.h"
  50 #include "amdgpu_ucode.h"
  51 #include "atom.h"
  52 #include "amdgpu_dm.h"
  53 #include "amdgpu_dm_plane.h"
  54 #include "amdgpu_dm_crtc.h"
  55 #include "amdgpu_dm_hdcp.h"
  56 #include <drm/display/drm_hdcp_helper.h>
  57 #include "amdgpu_dm_wb.h"
  58 #include "amdgpu_pm.h"
  59 #include "amdgpu_atombios.h"
  60
  61 #include "amd_shared.h"
  62 #include "amdgpu_dm_irq.h"
  63 #include "dm_helpers.h"
  64 #include "amdgpu_dm_mst_types.h"
  65 #if defined(CONFIG_DEBUG_FS)
  66 #include "amdgpu_dm_debugfs.h"
  67 #endif
  68 #include "amdgpu_dm_psr.h"
  69 #include "amdgpu_dm_replay.h"
  70
  71 #include "ivsrcid/ivsrcid_vislands30.h"
  72
  73 #include <linux/backlight.h>
  74 #include <linux/module.h>
  75 #include <linux/moduleparam.h>
  76 #include <linux/types.h>
  77 #include <linux/pm_runtime.h>
  78 #include <linux/pci.h>
  79 #include <linux/firmware.h>
  80 #include <linux/component.h>
  81 #include <linux/dmi.h>
  82
  83 #include <drm/display/drm_dp_mst_helper.h>
  84 #include <drm/display/drm_hdmi_helper.h>
  85 #include <drm/drm_atomic.h>
  86 #include <drm/drm_atomic_uapi.h>
  87 #include <drm/drm_atomic_helper.h>
  88 #include <drm/drm_blend.h>
  89 #include <drm/drm_fixed.h>
  90 #include <drm/drm_fourcc.h>
  91 #include <drm/drm_edid.h>
  92 #include <drm/drm_eld.h>
  93 #include <drm/drm_vblank.h>
  94 #include <drm/drm_audio_component.h>
  95 #include <drm/drm_gem_atomic_helper.h>
  96 #include <drm/drm_plane_helper.h>
  97
  98 #include <acpi/video.h>
  99
 100 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
 101
 102 #include "dcn/dcn_1_0_offset.h"
 103 #include "dcn/dcn_1_0_sh_mask.h"
 104 #include "soc15_hw_ip.h"
 105 #include "soc15_common.h"
 106 #include "vega10_ip_offset.h"
 107
 108 #include "gc/gc_11_0_0_offset.h"
 109 #include "gc/gc_11_0_0_sh_mask.h"
 110
 111 #include "modules/inc/mod_freesync.h"
 112 #include "modules/power/power_helpers.h"
 113
 114 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 115 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 116 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 117 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 118 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 119 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 120 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 121 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 122 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 123 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 124 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 125 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 126 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 127 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 128 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 129 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 130 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 131 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 132 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 133 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 134 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 135 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 136
 137 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 138 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 139 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 140 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 141
 142 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 143 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 144
 145 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 146 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 147
 148 #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin"
 149 MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB);
 150
 151 /* Number of bytes in PSP header for firmware. */
 152 #define PSP_HEADER_BYTES 0x100
 153
 154 /* Number of bytes in PSP footer for firmware. */
 155 #define PSP_FOOTER_BYTES 0x100
 156
 157 /**
 158  * DOC: overview
 159  *
 160  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 161  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 162  * requests into DC requests, and DC responses into DRM responses.
 163  *
 164  * The root control structure is &struct amdgpu_display_manager.
 165  */
 166
 167 /* basic init/fini API */
 168 static int amdgpu_dm_init(struct amdgpu_device *adev);
 169 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 170 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 171
 172 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 173 {
 174         switch (link->dpcd_caps.dongle_type) {
 175         case DISPLAY_DONGLE_NONE:
 176                 return DRM_MODE_SUBCONNECTOR_Native;
 177         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 178                 return DRM_MODE_SUBCONNECTOR_VGA;
 179         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 180         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 181                 return DRM_MODE_SUBCONNECTOR_DVID;
 182         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 183         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 184                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 185         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 186         default:
 187                 return DRM_MODE_SUBCONNECTOR_Unknown;
 188         }
 189 }
 190
 191 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 192 {
 193         struct dc_link *link = aconnector->dc_link;
 194         struct drm_connector *connector = &aconnector->base;
 195         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 196
 197         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 198                 return;
 199
 200         if (aconnector->dc_sink)
 201                 subconnector = get_subconnector_type(link);
 202
 203         drm_object_property_set_value(&connector->base,
 204                         connector->dev->mode_config.dp_subconnector_property,
 205                         subconnector);
 206 }
 207
 208 /*
 209  * initializes drm_device display related structures, based on the information
 210  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 211  * drm_encoder, drm_mode_config
 212  *
 213  * Returns 0 on success
 214  */
 215 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 216 /* removes and deallocates the drm structures, created by the above function */
 217 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 218
 219 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 220                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 221                                     u32 link_index,
 222                                     struct amdgpu_encoder *amdgpu_encoder);
 223 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 224                                   struct amdgpu_encoder *aencoder,
 225                                   uint32_t link_index);
 226
 227 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 228
 229 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 230
 231 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 232                                   struct drm_atomic_state *state);
 233
 234 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 235 static void handle_hpd_rx_irq(void *param);
 236
 237 static bool
 238 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 239                                  struct drm_crtc_state *new_crtc_state);
 240 /*
 241  * dm_vblank_get_counter
 242  *
 243  * @brief
 244  * Get counter for number of vertical blanks
 245  *
 246  * @param
 247  * struct amdgpu_device *adev - [in] desired amdgpu device
 248  * int disp_idx - [in] which CRTC to get the counter from
 249  *
 250  * @return
 251  * Counter for vertical blanks
 252  */
 253 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 254 {
 255         struct amdgpu_crtc *acrtc = NULL;
 256
 257         if (crtc >= adev->mode_info.num_crtc)
 258                 return 0;
 259
 260         acrtc = adev->mode_info.crtcs[crtc];
 261
 262         if (!acrtc->dm_irq_params.stream) {
 263                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 264                           crtc);
 265                 return 0;
 266         }
 267
 268         return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 269 }
 270
 271 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 272                                   u32 *vbl, u32 *position)
 273 {
 274         u32 v_blank_start, v_blank_end, h_position, v_position;
 275         struct amdgpu_crtc *acrtc = NULL;
 276
 277         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 278                 return -EINVAL;
 279
 280         acrtc = adev->mode_info.crtcs[crtc];
 281
 282         if (!acrtc->dm_irq_params.stream) {
 283                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 284                           crtc);
 285                 return 0;
 286         }
 287
 288         /*
 289          * TODO rework base driver to use values directly.
 290          * for now parse it back into reg-format
 291          */
 292         dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 293                                  &v_blank_start,
 294                                  &v_blank_end,
 295                                  &h_position,
 296                                  &v_position);
 297
 298         *position = v_position | (h_position << 16);
 299         *vbl = v_blank_start | (v_blank_end << 16);
 300
 301         return 0;
 302 }
 303
 304 static bool dm_is_idle(void *handle)
 305 {
 306         /* XXX todo */
 307         return true;
 308 }
 309
 310 static int dm_wait_for_idle(void *handle)
 311 {
 312         /* XXX todo */
 313         return 0;
 314 }
 315
 316 static bool dm_check_soft_reset(void *handle)
 317 {
 318         return false;
 319 }
 320
 321 static int dm_soft_reset(void *handle)
 322 {
 323         /* XXX todo */
 324         return 0;
 325 }
 326
 327 static struct amdgpu_crtc *
 328 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 329                      int otg_inst)
 330 {
 331         struct drm_device *dev = adev_to_drm(adev);
 332         struct drm_crtc *crtc;
 333         struct amdgpu_crtc *amdgpu_crtc;
 334
 335         if (WARN_ON(otg_inst == -1))
 336                 return adev->mode_info.crtcs[0];
 337
 338         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 339                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 340
 341                 if (amdgpu_crtc->otg_inst == otg_inst)
 342                         return amdgpu_crtc;
 343         }
 344
 345         return NULL;
 346 }
 347
 348 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 349                                               struct dm_crtc_state *new_state)
 350 {
 351         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 352                 return true;
 353         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 354                 return true;
 355         else
 356                 return false;
 357 }
 358
 359 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 360                                         int planes_count)
 361 {
 362         int i, j;
 363
 364         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 365                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 366 }
 367
 368 /**
 369  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 370  *
 371  * DC has a generic way to update planes and stream via
 372  * dc_update_planes_and_stream function; however, DM might need some
 373  * adjustments and preparation before calling it. This function is a wrapper
 374  * for the dc_update_planes_and_stream that does any required configuration
 375  * before passing control to DC.
 376  *
 377  * @dc: Display Core control structure
 378  * @update_type: specify whether it is FULL/MEDIUM/FAST update
 379  * @planes_count: planes count to update
 380  * @stream: stream state
 381  * @stream_update: stream update
 382  * @array_of_surface_update: dc surface update pointer
 383  *
 384  */
 385 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 386                                                     int update_type,
 387                                                     int planes_count,
 388                                                     struct dc_stream_state *stream,
 389                                                     struct dc_stream_update *stream_update,
 390                                                     struct dc_surface_update *array_of_surface_update)
 391 {
 392         reverse_planes_order(array_of_surface_update, planes_count);
 393
 394         /*
 395          * Previous frame finished and HW is ready for optimization.
 396          */
 397         if (update_type == UPDATE_TYPE_FAST)
 398                 dc_post_update_surfaces_to_stream(dc);
 399
 400         return dc_update_planes_and_stream(dc,
 401                                            array_of_surface_update,
 402                                            planes_count,
 403                                            stream,
 404                                            stream_update);
 405 }
 406
 407 /**
 408  * dm_pflip_high_irq() - Handle pageflip interrupt
 409  * @interrupt_params: ignored
 410  *
 411  * Handles the pageflip interrupt by notifying all interested parties
 412  * that the pageflip has been completed.
 413  */
 414 static void dm_pflip_high_irq(void *interrupt_params)
 415 {
 416         struct amdgpu_crtc *amdgpu_crtc;
 417         struct common_irq_params *irq_params = interrupt_params;
 418         struct amdgpu_device *adev = irq_params->adev;
 419         struct drm_device *dev = adev_to_drm(adev);
 420         unsigned long flags;
 421         struct drm_pending_vblank_event *e;
 422         u32 vpos, hpos, v_blank_start, v_blank_end;
 423         bool vrr_active;
 424
 425         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 426
 427         /* IRQ could occur when in initial stage */
 428         /* TODO work and BO cleanup */
 429         if (amdgpu_crtc == NULL) {
 430                 drm_dbg_state(dev, "CRTC is null, returning.\n");
 431                 return;
 432         }
 433
 434         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 435
 436         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
 437                 drm_dbg_state(dev,
 438                               "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",
 439                               amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED,
 440                               amdgpu_crtc->crtc_id, amdgpu_crtc);
 441                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 442                 return;
 443         }
 444
 445         /* page flip completed. */
 446         e = amdgpu_crtc->event;
 447         amdgpu_crtc->event = NULL;
 448
 449         WARN_ON(!e);
 450
 451         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 452
 453         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 454         if (!vrr_active ||
 455             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 456                                       &v_blank_end, &hpos, &vpos) ||
 457             (vpos < v_blank_start)) {
 458                 /* Update to correct count and vblank timestamp if racing with
 459                  * vblank irq. This also updates to the correct vblank timestamp
 460                  * even in VRR mode, as scanout is past the front-porch atm.
 461                  */
 462                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 463
 464                 /* Wake up userspace by sending the pageflip event with proper
 465                  * count and timestamp of vblank of flip completion.
 466                  */
 467                 if (e) {
 468                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 469
 470                         /* Event sent, so done with vblank for this flip */
 471                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 472                 }
 473         } else if (e) {
 474                 /* VRR active and inside front-porch: vblank count and
 475                  * timestamp for pageflip event will only be up to date after
 476                  * drm_crtc_handle_vblank() has been executed from late vblank
 477                  * irq handler after start of back-porch (vline 0). We queue the
 478                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 479                  * updated timestamp and count, once it runs after us.
 480                  *
 481                  * We need to open-code this instead of using the helper
 482                  * drm_crtc_arm_vblank_event(), as that helper would
 483                  * call drm_crtc_accurate_vblank_count(), which we must
 484                  * not call in VRR mode while we are in front-porch!
 485                  */
 486
 487                 /* sequence will be replaced by real count during send-out. */
 488                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 489                 e->pipe = amdgpu_crtc->crtc_id;
 490
 491                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 492                 e = NULL;
 493         }
 494
 495         /* Keep track of vblank of this flip for flip throttling. We use the
 496          * cooked hw counter, as that one incremented at start of this vblank
 497          * of pageflip completion, so last_flip_vblank is the forbidden count
 498          * for queueing new pageflips if vsync + VRR is enabled.
 499          */
 500         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 501                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 502
 503         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 504         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 505
 506         drm_dbg_state(dev,
 507                       "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 508                       amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e);
 509 }
 510
 511 static void dm_vupdate_high_irq(void *interrupt_params)
 512 {
 513         struct common_irq_params *irq_params = interrupt_params;
 514         struct amdgpu_device *adev = irq_params->adev;
 515         struct amdgpu_crtc *acrtc;
 516         struct drm_device *drm_dev;
 517         struct drm_vblank_crtc *vblank;
 518         ktime_t frame_duration_ns, previous_timestamp;
 519         unsigned long flags;
 520         int vrr_active;
 521
 522         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 523
 524         if (acrtc) {
 525                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 526                 drm_dev = acrtc->base.dev;
 527                 vblank = &drm_dev->vblank[acrtc->base.index];
 528                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 529                 frame_duration_ns = vblank->time - previous_timestamp;
 530
 531                 if (frame_duration_ns > 0) {
 532                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 533                                                 frame_duration_ns,
 534                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 535                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 536                 }
 537
 538                 drm_dbg_vbl(drm_dev,
 539                             "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
 540                             vrr_active);
 541
 542                 /* Core vblank handling is done here after end of front-porch in
 543                  * vrr mode, as vblank timestamping will give valid results
 544                  * while now done after front-porch. This will also deliver
 545                  * page-flip completion events that have been queued to us
 546                  * if a pageflip happened inside front-porch.
 547                  */
 548                 if (vrr_active) {
 549                         amdgpu_dm_crtc_handle_vblank(acrtc);
 550
 551                         /* BTR processing for pre-DCE12 ASICs */
 552                         if (acrtc->dm_irq_params.stream &&
 553                             adev->family < AMDGPU_FAMILY_AI) {
 554                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 555                                 mod_freesync_handle_v_update(
 556                                     adev->dm.freesync_module,
 557                                     acrtc->dm_irq_params.stream,
 558                                     &acrtc->dm_irq_params.vrr_params);
 559
 560                                 dc_stream_adjust_vmin_vmax(
 561                                     adev->dm.dc,
 562                                     acrtc->dm_irq_params.stream,
 563                                     &acrtc->dm_irq_params.vrr_params.adjust);
 564                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 565                         }
 566                 }
 567         }
 568 }
 569
 570 /**
 571  * dm_crtc_high_irq() - Handles CRTC interrupt
 572  * @interrupt_params: used for determining the CRTC instance
 573  *
 574  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 575  * event handler.
 576  */
 577 static void dm_crtc_high_irq(void *interrupt_params)
 578 {
 579         struct common_irq_params *irq_params = interrupt_params;
 580         struct amdgpu_device *adev = irq_params->adev;
 581         struct amdgpu_crtc *acrtc;
 582         unsigned long flags;
 583         int vrr_active;
 584
 585         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 586         if (!acrtc)
 587                 return;
 588
 589         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 590
 591         drm_dbg_vbl(adev_to_drm(adev),
 592                     "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 593                     vrr_active, acrtc->dm_irq_params.active_planes);
 594
 595         /**
 596          * Core vblank handling at start of front-porch is only possible
 597          * in non-vrr mode, as only there vblank timestamping will give
 598          * valid results while done in front-porch. Otherwise defer it
 599          * to dm_vupdate_high_irq after end of front-porch.
 600          */
 601         if (!vrr_active)
 602                 amdgpu_dm_crtc_handle_vblank(acrtc);
 603
 604         /**
 605          * Following stuff must happen at start of vblank, for crc
 606          * computation and below-the-range btr support in vrr mode.
 607          */
 608         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 609
 610         /* BTR updates need to happen before VUPDATE on Vega and above. */
 611         if (adev->family < AMDGPU_FAMILY_AI)
 612                 return;
 613
 614         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 615
 616         if (acrtc->dm_irq_params.stream &&
 617             acrtc->dm_irq_params.vrr_params.supported &&
 618             acrtc->dm_irq_params.freesync_config.state ==
 619                     VRR_STATE_ACTIVE_VARIABLE) {
 620                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 621                                              acrtc->dm_irq_params.stream,
 622                                              &acrtc->dm_irq_params.vrr_params);
 623
 624                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 625                                            &acrtc->dm_irq_params.vrr_params.adjust);
 626         }
 627
 628         /*
 629          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 630          * In that case, pageflip completion interrupts won't fire and pageflip
 631          * completion events won't get delivered. Prevent this by sending
 632          * pending pageflip events from here if a flip is still pending.
 633          *
 634          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 635          * avoid race conditions between flip programming and completion,
 636          * which could cause too early flip completion events.
 637          */
 638         if (adev->family >= AMDGPU_FAMILY_RV &&
 639             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 640             acrtc->dm_irq_params.active_planes == 0) {
 641                 if (acrtc->event) {
 642                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 643                         acrtc->event = NULL;
 644                         drm_crtc_vblank_put(&acrtc->base);
 645                 }
 646                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 647         }
 648
 649         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 650 }
 651
 652 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 653 /**
 654  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 655  * DCN generation ASICs
 656  * @interrupt_params: interrupt parameters
 657  *
 658  * Used to set crc window/read out crc value at vertical line 0 position
 659  */
 660 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 661 {
 662         struct common_irq_params *irq_params = interrupt_params;
 663         struct amdgpu_device *adev = irq_params->adev;
 664         struct amdgpu_crtc *acrtc;
 665
 666         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 667
 668         if (!acrtc)
 669                 return;
 670
 671         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 672 }
 673 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 674
 675 /**
 676  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 677  * @adev: amdgpu_device pointer
 678  * @notify: dmub notification structure
 679  *
 680  * Dmub AUX or SET_CONFIG command completion processing callback
 681  * Copies dmub notification to DM which is to be read by AUX command.
 682  * issuing thread and also signals the event to wake up the thread.
 683  */
 684 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 685                                         struct dmub_notification *notify)
 686 {
 687         if (adev->dm.dmub_notify)
 688                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 689         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 690                 complete(&adev->dm.dmub_aux_transfer_done);
 691 }
 692
 693 /**
 694  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 695  * @adev: amdgpu_device pointer
 696  * @notify: dmub notification structure
 697  *
 698  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 699  * ink index and calls helper to do the processing.
 700  */
 701 static void dmub_hpd_callback(struct amdgpu_device *adev,
 702                               struct dmub_notification *notify)
 703 {
 704         struct amdgpu_dm_connector *aconnector;
 705         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 706         struct drm_connector *connector;
 707         struct drm_connector_list_iter iter;
 708         struct dc_link *link;
 709         u8 link_index = 0;
 710         struct drm_device *dev;
 711
 712         if (adev == NULL)
 713                 return;
 714
 715         if (notify == NULL) {
 716                 DRM_ERROR("DMUB HPD callback notification was NULL");
 717                 return;
 718         }
 719
 720         if (notify->link_index > adev->dm.dc->link_count) {
 721                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 722                 return;
 723         }
 724
 725         link_index = notify->link_index;
 726         link = adev->dm.dc->links[link_index];
 727         dev = adev->dm.ddev;
 728
 729         drm_connector_list_iter_begin(dev, &iter);
 730         drm_for_each_connector_iter(connector, &iter) {
 731                 aconnector = to_amdgpu_dm_connector(connector);
 732                 if (link && aconnector->dc_link == link) {
 733                         if (notify->type == DMUB_NOTIFICATION_HPD)
 734                                 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 735                         else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 736                                 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
 737                         else
 738                                 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
 739                                                 notify->type, link_index);
 740
 741                         hpd_aconnector = aconnector;
 742                         break;
 743                 }
 744         }
 745         drm_connector_list_iter_end(&iter);
 746
 747         if (hpd_aconnector) {
 748                 if (notify->type == DMUB_NOTIFICATION_HPD)
 749                         handle_hpd_irq_helper(hpd_aconnector);
 750                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 751                         handle_hpd_rx_irq(hpd_aconnector);
 752         }
 753 }
 754
 755 /**
 756  * register_dmub_notify_callback - Sets callback for DMUB notify
 757  * @adev: amdgpu_device pointer
 758  * @type: Type of dmub notification
 759  * @callback: Dmub interrupt callback function
 760  * @dmub_int_thread_offload: offload indicator
 761  *
 762  * API to register a dmub callback handler for a dmub notification
 763  * Also sets indicator whether callback processing to be offloaded.
 764  * to dmub interrupt handling thread
 765  * Return: true if successfully registered, false if there is existing registration
 766  */
 767 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 768                                           enum dmub_notification_type type,
 769                                           dmub_notify_interrupt_callback_t callback,
 770                                           bool dmub_int_thread_offload)
 771 {
 772         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 773                 adev->dm.dmub_callback[type] = callback;
 774                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 775         } else
 776                 return false;
 777
 778         return true;
 779 }
 780
 781 static void dm_handle_hpd_work(struct work_struct *work)
 782 {
 783         struct dmub_hpd_work *dmub_hpd_wrk;
 784
 785         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 786
 787         if (!dmub_hpd_wrk->dmub_notify) {
 788                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 789                 return;
 790         }
 791
 792         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 793                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 794                 dmub_hpd_wrk->dmub_notify);
 795         }
 796
 797         kfree(dmub_hpd_wrk->dmub_notify);
 798         kfree(dmub_hpd_wrk);
 799
 800 }
 801
 802 #define DMUB_TRACE_MAX_READ 64
 803 /**
 804  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 805  * @interrupt_params: used for determining the Outbox instance
 806  *
 807  * Handles the Outbox Interrupt
 808  * event handler.
 809  */
 810 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 811 {
 812         struct dmub_notification notify;
 813         struct common_irq_params *irq_params = interrupt_params;
 814         struct amdgpu_device *adev = irq_params->adev;
 815         struct amdgpu_display_manager *dm = &adev->dm;
 816         struct dmcub_trace_buf_entry entry = { 0 };
 817         u32 count = 0;
 818         struct dmub_hpd_work *dmub_hpd_wrk;
 819         struct dc_link *plink = NULL;
 820
 821         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 822                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 823
 824                 do {
 825                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 826                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 827                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 828                                 continue;
 829                         }
 830                         if (!dm->dmub_callback[notify.type]) {
 831                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 832                                 continue;
 833                         }
 834                         if (dm->dmub_thread_offload[notify.type] == true) {
 835                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 836                                 if (!dmub_hpd_wrk) {
 837                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 838                                         return;
 839                                 }
 840                                 dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
 841                                                                     GFP_ATOMIC);
 842                                 if (!dmub_hpd_wrk->dmub_notify) {
 843                                         kfree(dmub_hpd_wrk);
 844                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 845                                         return;
 846                                 }
 847                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 848                                 dmub_hpd_wrk->adev = adev;
 849                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 850                                         plink = adev->dm.dc->links[notify.link_index];
 851                                         if (plink) {
 852                                                 plink->hpd_status =
 853                                                         notify.hpd_status == DP_HPD_PLUG;
 854                                         }
 855                                 }
 856                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 857                         } else {
 858                                 dm->dmub_callback[notify.type](adev, &notify);
 859                         }
 860                 } while (notify.pending_notification);
 861         }
 862
 863
 864         do {
 865                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 866                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 867                                                         entry.param0, entry.param1);
 868
 869                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 870                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 871                 } else
 872                         break;
 873
 874                 count++;
 875
 876         } while (count <= DMUB_TRACE_MAX_READ);
 877
 878         if (count > DMUB_TRACE_MAX_READ)
 879                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 880 }
 881
 882 static int dm_set_clockgating_state(void *handle,
 883                   enum amd_clockgating_state state)
 884 {
 885         return 0;
 886 }
 887
 888 static int dm_set_powergating_state(void *handle,
 889                   enum amd_powergating_state state)
 890 {
 891         return 0;
 892 }
 893
 894 /* Prototypes of private functions */
 895 static int dm_early_init(void *handle);
 896
 897 /* Allocate memory for FBC compressed data  */
 898 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 899 {
 900         struct amdgpu_device *adev = drm_to_adev(connector->dev);
 901         struct dm_compressor_info *compressor = &adev->dm.compressor;
 902         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 903         struct drm_display_mode *mode;
 904         unsigned long max_size = 0;
 905
 906         if (adev->dm.dc->fbc_compressor == NULL)
 907                 return;
 908
 909         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 910                 return;
 911
 912         if (compressor->bo_ptr)
 913                 return;
 914
 915
 916         list_for_each_entry(mode, &connector->modes, head) {
 917                 if (max_size < mode->htotal * mode->vtotal)
 918                         max_size = mode->htotal * mode->vtotal;
 919         }
 920
 921         if (max_size) {
 922                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 923                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 924                             &compressor->gpu_addr, &compressor->cpu_addr);
 925
 926                 if (r)
 927                         DRM_ERROR("DM: Failed to initialize FBC\n");
 928                 else {
 929                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 930                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 931                 }
 932
 933         }
 934
 935 }
 936
 937 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 938                                           int pipe, bool *enabled,
 939                                           unsigned char *buf, int max_bytes)
 940 {
 941         struct drm_device *dev = dev_get_drvdata(kdev);
 942         struct amdgpu_device *adev = drm_to_adev(dev);
 943         struct drm_connector *connector;
 944         struct drm_connector_list_iter conn_iter;
 945         struct amdgpu_dm_connector *aconnector;
 946         int ret = 0;
 947
 948         *enabled = false;
 949
 950         mutex_lock(&adev->dm.audio_lock);
 951
 952         drm_connector_list_iter_begin(dev, &conn_iter);
 953         drm_for_each_connector_iter(connector, &conn_iter) {
 954                 aconnector = to_amdgpu_dm_connector(connector);
 955                 if (aconnector->audio_inst != port)
 956                         continue;
 957
 958                 *enabled = true;
 959                 ret = drm_eld_size(connector->eld);
 960                 memcpy(buf, connector->eld, min(max_bytes, ret));
 961
 962                 break;
 963         }
 964         drm_connector_list_iter_end(&conn_iter);
 965
 966         mutex_unlock(&adev->dm.audio_lock);
 967
 968         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 969
 970         return ret;
 971 }
 972
 973 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 974         .get_eld = amdgpu_dm_audio_component_get_eld,
 975 };
 976
 977 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 978                                        struct device *hda_kdev, void *data)
 979 {
 980         struct drm_device *dev = dev_get_drvdata(kdev);
 981         struct amdgpu_device *adev = drm_to_adev(dev);
 982         struct drm_audio_component *acomp = data;
 983
 984         acomp->ops = &amdgpu_dm_audio_component_ops;
 985         acomp->dev = kdev;
 986         adev->dm.audio_component = acomp;
 987
 988         return 0;
 989 }
 990
 991 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 992                                           struct device *hda_kdev, void *data)
 993 {
 994         struct amdgpu_device *adev = drm_to_adev(dev_get_drvdata(kdev));
 995         struct drm_audio_component *acomp = data;
 996
 997         acomp->ops = NULL;
 998         acomp->dev = NULL;
 999         adev->dm.audio_component = NULL;
1000 }
1001
1002 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
1003         .bind   = amdgpu_dm_audio_component_bind,
1004         .unbind = amdgpu_dm_audio_component_unbind,
1005 };
1006
1007 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1008 {
1009         int i, ret;
1010
1011         if (!amdgpu_audio)
1012                 return 0;
1013
1014         adev->mode_info.audio.enabled = true;
1015
1016         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1017
1018         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1019                 adev->mode_info.audio.pin[i].channels = -1;
1020                 adev->mode_info.audio.pin[i].rate = -1;
1021                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1022                 adev->mode_info.audio.pin[i].status_bits = 0;
1023                 adev->mode_info.audio.pin[i].category_code = 0;
1024                 adev->mode_info.audio.pin[i].connected = false;
1025                 adev->mode_info.audio.pin[i].id =
1026                         adev->dm.dc->res_pool->audios[i]->inst;
1027                 adev->mode_info.audio.pin[i].offset = 0;
1028         }
1029
1030         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1031         if (ret < 0)
1032                 return ret;
1033
1034         adev->dm.audio_registered = true;
1035
1036         return 0;
1037 }
1038
1039 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1040 {
1041         if (!amdgpu_audio)
1042                 return;
1043
1044         if (!adev->mode_info.audio.enabled)
1045                 return;
1046
1047         if (adev->dm.audio_registered) {
1048                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1049                 adev->dm.audio_registered = false;
1050         }
1051
1052         /* TODO: Disable audio? */
1053
1054         adev->mode_info.audio.enabled = false;
1055 }
1056
1057 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1058 {
1059         struct drm_audio_component *acomp = adev->dm.audio_component;
1060
1061         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1062                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1063
1064                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1065                                                  pin, -1);
1066         }
1067 }
1068
1069 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1070 {
1071         const struct dmcub_firmware_header_v1_0 *hdr;
1072         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1073         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1074         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1075         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1076         struct abm *abm = adev->dm.dc->res_pool->abm;
1077         struct dc_context *ctx = adev->dm.dc->ctx;
1078         struct dmub_srv_hw_params hw_params;
1079         enum dmub_status status;
1080         const unsigned char *fw_inst_const, *fw_bss_data;
1081         u32 i, fw_inst_const_size, fw_bss_data_size;
1082         bool has_hw_support;
1083
1084         if (!dmub_srv)
1085                 /* DMUB isn't supported on the ASIC. */
1086                 return 0;
1087
1088         if (!fb_info) {
1089                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1090                 return -EINVAL;
1091         }
1092
1093         if (!dmub_fw) {
1094                 /* Firmware required for DMUB support. */
1095                 DRM_ERROR("No firmware provided for DMUB.\n");
1096                 return -EINVAL;
1097         }
1098
1099         /* initialize register offsets for ASICs with runtime initialization available */
1100         if (dmub_srv->hw_funcs.init_reg_offsets)
1101                 dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx);
1102
1103         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1104         if (status != DMUB_STATUS_OK) {
1105                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1106                 return -EINVAL;
1107         }
1108
1109         if (!has_hw_support) {
1110                 DRM_INFO("DMUB unsupported on ASIC\n");
1111                 return 0;
1112         }
1113
1114         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1115         status = dmub_srv_hw_reset(dmub_srv);
1116         if (status != DMUB_STATUS_OK)
1117                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1118
1119         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1120
1121         fw_inst_const = dmub_fw->data +
1122                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1123                         PSP_HEADER_BYTES;
1124
1125         fw_bss_data = dmub_fw->data +
1126                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1127                       le32_to_cpu(hdr->inst_const_bytes);
1128
1129         /* Copy firmware and bios info into FB memory. */
1130         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1131                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1132
1133         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1134
1135         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1136          * amdgpu_ucode_init_single_fw will load dmub firmware
1137          * fw_inst_const part to cw0; otherwise, the firmware back door load
1138          * will be done by dm_dmub_hw_init
1139          */
1140         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1141                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1142                                 fw_inst_const_size);
1143         }
1144
1145         if (fw_bss_data_size)
1146                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1147                        fw_bss_data, fw_bss_data_size);
1148
1149         /* Copy firmware bios info into FB memory. */
1150         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1151                adev->bios_size);
1152
1153         /* Reset regions that need to be reset. */
1154         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1155         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1156
1157         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1158                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1159
1160         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1161                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1162
1163         /* Initialize hardware. */
1164         memset(&hw_params, 0, sizeof(hw_params));
1165         hw_params.fb_base = adev->gmc.fb_start;
1166         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1167
1168         /* backdoor load firmware and trigger dmub running */
1169         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1170                 hw_params.load_inst_const = true;
1171
1172         if (dmcu)
1173                 hw_params.psp_version = dmcu->psp_version;
1174
1175         for (i = 0; i < fb_info->num_fb; ++i)
1176                 hw_params.fb[i] = &fb_info->fb[i];
1177
1178         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1179         case IP_VERSION(3, 1, 3):
1180         case IP_VERSION(3, 1, 4):
1181         case IP_VERSION(3, 5, 0):
1182                 hw_params.dpia_supported = true;
1183                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1184                 break;
1185         default:
1186                 break;
1187         }
1188
1189         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1190         if (status != DMUB_STATUS_OK) {
1191                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1192                 return -EINVAL;
1193         }
1194
1195         /* Wait for firmware load to finish. */
1196         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1197         if (status != DMUB_STATUS_OK)
1198                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1199
1200         /* Init DMCU and ABM if available. */
1201         if (dmcu && abm) {
1202                 dmcu->funcs->dmcu_init(dmcu);
1203                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1204         }
1205
1206         if (!adev->dm.dc->ctx->dmub_srv)
1207                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1208         if (!adev->dm.dc->ctx->dmub_srv) {
1209                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1210                 return -ENOMEM;
1211         }
1212
1213         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1214                  adev->dm.dmcub_fw_version);
1215
1216         return 0;
1217 }
1218
1219 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1220 {
1221         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1222         enum dmub_status status;
1223         bool init;
1224
1225         if (!dmub_srv) {
1226                 /* DMUB isn't supported on the ASIC. */
1227                 return;
1228         }
1229
1230         status = dmub_srv_is_hw_init(dmub_srv, &init);
1231         if (status != DMUB_STATUS_OK)
1232                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1233
1234         if (status == DMUB_STATUS_OK && init) {
1235                 /* Wait for firmware load to finish. */
1236                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1237                 if (status != DMUB_STATUS_OK)
1238                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1239         } else {
1240                 /* Perform the full hardware initialization. */
1241                 dm_dmub_hw_init(adev);
1242         }
1243 }
1244
1245 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1246 {
1247         u64 pt_base;
1248         u32 logical_addr_low;
1249         u32 logical_addr_high;
1250         u32 agp_base, agp_bot, agp_top;
1251         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1252
1253         memset(pa_config, 0, sizeof(*pa_config));
1254
1255         agp_base = 0;
1256         agp_bot = adev->gmc.agp_start >> 24;
1257         agp_top = adev->gmc.agp_end >> 24;
1258
1259         /* AGP aperture is disabled */
1260         if (agp_bot > agp_top) {
1261                 logical_addr_low = adev->gmc.fb_start >> 18;
1262                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1263                         /*
1264                          * Raven2 has a HW issue that it is unable to use the vram which
1265                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1266                          * workaround that increase system aperture high address (add 1)
1267                          * to get rid of the VM fault and hardware hang.
1268                          */
1269                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1270                 else
1271                         logical_addr_high = adev->gmc.fb_end >> 18;
1272         } else {
1273                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1274                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1275                         /*
1276                          * Raven2 has a HW issue that it is unable to use the vram which
1277                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1278                          * workaround that increase system aperture high address (add 1)
1279                          * to get rid of the VM fault and hardware hang.
1280                          */
1281                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1282                 else
1283                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1284         }
1285
1286         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1287
1288         page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>
1289                                                    AMDGPU_GPU_PAGE_SHIFT);
1290         page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
1291                                                   AMDGPU_GPU_PAGE_SHIFT);
1292         page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>
1293                                                  AMDGPU_GPU_PAGE_SHIFT);
1294         page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
1295                                                 AMDGPU_GPU_PAGE_SHIFT);
1296         page_table_base.high_part = upper_32_bits(pt_base);
1297         page_table_base.low_part = lower_32_bits(pt_base);
1298
1299         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1300         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1301
1302         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;
1303         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1304         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1305
1306         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1307         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1308         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1309
1310         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1311         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1312         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1313
1314         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1315
1316 }
1317
1318 static void force_connector_state(
1319         struct amdgpu_dm_connector *aconnector,
1320         enum drm_connector_force force_state)
1321 {
1322         struct drm_connector *connector = &aconnector->base;
1323
1324         mutex_lock(&connector->dev->mode_config.mutex);
1325         aconnector->base.force = force_state;
1326         mutex_unlock(&connector->dev->mode_config.mutex);
1327
1328         mutex_lock(&aconnector->hpd_lock);
1329         drm_kms_helper_connector_hotplug_event(connector);
1330         mutex_unlock(&aconnector->hpd_lock);
1331 }
1332
1333 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1334 {
1335         struct hpd_rx_irq_offload_work *offload_work;
1336         struct amdgpu_dm_connector *aconnector;
1337         struct dc_link *dc_link;
1338         struct amdgpu_device *adev;
1339         enum dc_connection_type new_connection_type = dc_connection_none;
1340         unsigned long flags;
1341         union test_response test_response;
1342
1343         memset(&test_response, 0, sizeof(test_response));
1344
1345         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1346         aconnector = offload_work->offload_wq->aconnector;
1347
1348         if (!aconnector) {
1349                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1350                 goto skip;
1351         }
1352
1353         adev = drm_to_adev(aconnector->base.dev);
1354         dc_link = aconnector->dc_link;
1355
1356         mutex_lock(&aconnector->hpd_lock);
1357         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1358                 DRM_ERROR("KMS: Failed to detect connector\n");
1359         mutex_unlock(&aconnector->hpd_lock);
1360
1361         if (new_connection_type == dc_connection_none)
1362                 goto skip;
1363
1364         if (amdgpu_in_reset(adev))
1365                 goto skip;
1366
1367         if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
1368                 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
1369                 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT);
1370                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1371                 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false;
1372                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1373                 goto skip;
1374         }
1375
1376         mutex_lock(&adev->dm.dc_lock);
1377         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1378                 dc_link_dp_handle_automated_test(dc_link);
1379
1380                 if (aconnector->timing_changed) {
1381                         /* force connector disconnect and reconnect */
1382                         force_connector_state(aconnector, DRM_FORCE_OFF);
1383                         msleep(100);
1384                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1385                 }
1386
1387                 test_response.bits.ACK = 1;
1388
1389                 core_link_write_dpcd(
1390                 dc_link,
1391                 DP_TEST_RESPONSE,
1392                 &test_response.raw,
1393                 sizeof(test_response));
1394         } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1395                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1396                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1397                 /* offload_work->data is from handle_hpd_rx_irq->
1398                  * schedule_hpd_rx_offload_work.this is defer handle
1399                  * for hpd short pulse. upon here, link status may be
1400                  * changed, need get latest link status from dpcd
1401                  * registers. if link status is good, skip run link
1402                  * training again.
1403                  */
1404                 union hpd_irq_data irq_data;
1405
1406                 memset(&irq_data, 0, sizeof(irq_data));
1407
1408                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1409                  * request be added to work queue if link lost at end of dc_link_
1410                  * dp_handle_link_loss
1411                  */
1412                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1413                 offload_work->offload_wq->is_handling_link_loss = false;
1414                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1415
1416                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1417                         dc_link_check_link_loss_status(dc_link, &irq_data))
1418                         dc_link_dp_handle_link_loss(dc_link);
1419         }
1420         mutex_unlock(&adev->dm.dc_lock);
1421
1422 skip:
1423         kfree(offload_work);
1424
1425 }
1426
1427 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1428 {
1429         int max_caps = dc->caps.max_links;
1430         int i = 0;
1431         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1432
1433         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1434
1435         if (!hpd_rx_offload_wq)
1436                 return NULL;
1437
1438
1439         for (i = 0; i < max_caps; i++) {
1440                 hpd_rx_offload_wq[i].wq =
1441                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1442
1443                 if (hpd_rx_offload_wq[i].wq == NULL) {
1444                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1445                         goto out_err;
1446                 }
1447
1448                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1449         }
1450
1451         return hpd_rx_offload_wq;
1452
1453 out_err:
1454         for (i = 0; i < max_caps; i++) {
1455                 if (hpd_rx_offload_wq[i].wq)
1456                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1457         }
1458         kfree(hpd_rx_offload_wq);
1459         return NULL;
1460 }
1461
1462 struct amdgpu_stutter_quirk {
1463         u16 chip_vendor;
1464         u16 chip_device;
1465         u16 subsys_vendor;
1466         u16 subsys_device;
1467         u8 revision;
1468 };
1469
1470 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1471         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1472         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1473         { 0, 0, 0, 0, 0 },
1474 };
1475
1476 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1477 {
1478         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1479
1480         while (p && p->chip_device != 0) {
1481                 if (pdev->vendor == p->chip_vendor &&
1482                     pdev->device == p->chip_device &&
1483                     pdev->subsystem_vendor == p->subsys_vendor &&
1484                     pdev->subsystem_device == p->subsys_device &&
1485                     pdev->revision == p->revision) {
1486                         return true;
1487                 }
1488                 ++p;
1489         }
1490         return false;
1491 }
1492
1493 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1494         {
1495                 .matches = {
1496                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1497                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1498                 },
1499         },
1500         {
1501                 .matches = {
1502                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1503                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1504                 },
1505         },
1506         {
1507                 .matches = {
1508                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1509                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1510                 },
1511         },
1512         {
1513                 .matches = {
1514                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1515                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1516                 },
1517         },
1518         {
1519                 .matches = {
1520                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1521                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1522                 },
1523         },
1524         {
1525                 .matches = {
1526                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1527                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1528                 },
1529         },
1530         {
1531                 .matches = {
1532                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1533                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1534                 },
1535         },
1536         {
1537                 .matches = {
1538                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1539                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1540                 },
1541         },
1542         {
1543                 .matches = {
1544                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1545                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1546                 },
1547         },
1548         {}
1549         /* TODO: refactor this from a fixed table to a dynamic option */
1550 };
1551
1552 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1553 {
1554         const struct dmi_system_id *dmi_id;
1555
1556         dm->aux_hpd_discon_quirk = false;
1557
1558         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1559         if (dmi_id) {
1560                 dm->aux_hpd_discon_quirk = true;
1561                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1562         }
1563 }
1564
1565 static int amdgpu_dm_init(struct amdgpu_device *adev)
1566 {
1567         struct dc_init_data init_data;
1568         struct dc_callback_init init_params;
1569         int r;
1570
1571         adev->dm.ddev = adev_to_drm(adev);
1572         adev->dm.adev = adev;
1573
1574         /* Zero all the fields */
1575         memset(&init_data, 0, sizeof(init_data));
1576         memset(&init_params, 0, sizeof(init_params));
1577
1578         mutex_init(&adev->dm.dpia_aux_lock);
1579         mutex_init(&adev->dm.dc_lock);
1580         mutex_init(&adev->dm.audio_lock);
1581
1582         if (amdgpu_dm_irq_init(adev)) {
1583                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1584                 goto error;
1585         }
1586
1587         init_data.asic_id.chip_family = adev->family;
1588
1589         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1590         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1591         init_data.asic_id.chip_id = adev->pdev->device;
1592
1593         init_data.asic_id.vram_width = adev->gmc.vram_width;
1594         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1595         init_data.asic_id.atombios_base_address =
1596                 adev->mode_info.atom_context->bios;
1597
1598         init_data.driver = adev;
1599
1600         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1601
1602         if (!adev->dm.cgs_device) {
1603                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1604                 goto error;
1605         }
1606
1607         init_data.cgs_device = adev->dm.cgs_device;
1608
1609         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1610
1611         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1612         case IP_VERSION(2, 1, 0):
1613                 switch (adev->dm.dmcub_fw_version) {
1614                 case 0: /* development */
1615                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1616                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1617                         init_data.flags.disable_dmcu = false;
1618                         break;
1619                 default:
1620                         init_data.flags.disable_dmcu = true;
1621                 }
1622                 break;
1623         case IP_VERSION(2, 0, 3):
1624                 init_data.flags.disable_dmcu = true;
1625                 break;
1626         default:
1627                 break;
1628         }
1629
1630         /* APU support S/G display by default except:
1631          * ASICs before Carrizo,
1632          * RAVEN1 (Users reported stability issue)
1633          */
1634
1635         if (adev->asic_type < CHIP_CARRIZO) {
1636                 init_data.flags.gpu_vm_support = false;
1637         } else if (adev->asic_type == CHIP_RAVEN) {
1638                 if (adev->apu_flags & AMD_APU_IS_RAVEN)
1639                         init_data.flags.gpu_vm_support = false;
1640                 else
1641                         init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0);
1642         } else {
1643                 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU);
1644         }
1645
1646         adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support;
1647
1648         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1649                 init_data.flags.fbc_support = true;
1650
1651         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1652                 init_data.flags.multi_mon_pp_mclk_switch = true;
1653
1654         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1655                 init_data.flags.disable_fractional_pwm = true;
1656
1657         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1658                 init_data.flags.edp_no_power_sequencing = true;
1659
1660         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1661                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1662         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1663                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1664
1665         init_data.flags.seamless_boot_edp_requested = false;
1666
1667         if (amdgpu_device_seamless_boot_supported(adev)) {
1668                 init_data.flags.seamless_boot_edp_requested = true;
1669                 init_data.flags.allow_seamless_boot_optimization = true;
1670                 DRM_INFO("Seamless boot condition check passed\n");
1671         }
1672
1673         init_data.flags.enable_mipi_converter_optimization = true;
1674
1675         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1676         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1677         init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];
1678
1679         /* Enable DWB for tested platforms only */
1680         if (adev->ip_versions[DCE_HWIP][0] >= IP_VERSION(3, 0, 0))
1681                 init_data.num_virtual_links = 1;
1682
1683         INIT_LIST_HEAD(&adev->dm.da_list);
1684
1685         retrieve_dmi_info(&adev->dm);
1686
1687         /* Display Core create. */
1688         adev->dm.dc = dc_create(&init_data);
1689
1690         if (adev->dm.dc) {
1691                 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
1692                          dce_version_to_string(adev->dm.dc->ctx->dce_version));
1693         } else {
1694                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1695                 goto error;
1696         }
1697
1698         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1699                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1700                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1701         }
1702
1703         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1704                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1705         if (dm_should_disable_stutter(adev->pdev))
1706                 adev->dm.dc->debug.disable_stutter = true;
1707
1708         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1709                 adev->dm.dc->debug.disable_stutter = true;
1710
1711         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1712                 adev->dm.dc->debug.disable_dsc = true;
1713
1714         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1715                 adev->dm.dc->debug.disable_clock_gate = true;
1716
1717         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1718                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1719
1720         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1721
1722         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1723         adev->dm.dc->debug.ignore_cable_id = true;
1724
1725         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1726                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1727
1728         r = dm_dmub_hw_init(adev);
1729         if (r) {
1730                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1731                 goto error;
1732         }
1733
1734         dc_hardware_init(adev->dm.dc);
1735
1736         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1737         if (!adev->dm.hpd_rx_offload_wq) {
1738                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1739                 goto error;
1740         }
1741
1742         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1743                 struct dc_phy_addr_space_config pa_config;
1744
1745                 mmhub_read_system_context(adev, &pa_config);
1746
1747                 // Call the DC init_memory func
1748                 dc_setup_system_context(adev->dm.dc, &pa_config);
1749         }
1750
1751         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1752         if (!adev->dm.freesync_module) {
1753                 DRM_ERROR(
1754                 "amdgpu: failed to initialize freesync_module.\n");
1755         } else
1756                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1757                                 adev->dm.freesync_module);
1758
1759         amdgpu_dm_init_color_mod();
1760
1761         if (adev->dm.dc->caps.max_links > 0) {
1762                 adev->dm.vblank_control_workqueue =
1763                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1764                 if (!adev->dm.vblank_control_workqueue)
1765                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1766         }
1767
1768         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1769                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1770
1771                 if (!adev->dm.hdcp_workqueue)
1772                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1773                 else
1774                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1775
1776                 dc_init_callbacks(adev->dm.dc, &init_params);
1777         }
1778         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1779                 init_completion(&adev->dm.dmub_aux_transfer_done);
1780                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1781                 if (!adev->dm.dmub_notify) {
1782                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1783                         goto error;
1784                 }
1785
1786                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1787                 if (!adev->dm.delayed_hpd_wq) {
1788                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1789                         goto error;
1790                 }
1791
1792                 amdgpu_dm_outbox_init(adev);
1793                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1794                         dmub_aux_setconfig_callback, false)) {
1795                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1796                         goto error;
1797                 }
1798                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1799                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1800                         goto error;
1801                 }
1802                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1803                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1804                         goto error;
1805                 }
1806         }
1807
1808         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1809          * It is expected that DMUB will resend any pending notifications at this point, for
1810          * example HPD from DPIA.
1811          */
1812         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1813                 dc_enable_dmub_outbox(adev->dm.dc);
1814
1815                 /* DPIA trace goes to dmesg logs only if outbox is enabled */
1816                 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE)
1817                         dc_dmub_srv_enable_dpia_trace(adev->dm.dc);
1818         }
1819
1820         if (amdgpu_dm_initialize_drm_device(adev)) {
1821                 DRM_ERROR(
1822                 "amdgpu: failed to initialize sw for display support.\n");
1823                 goto error;
1824         }
1825
1826         /* create fake encoders for MST */
1827         dm_dp_create_fake_mst_encoders(adev);
1828
1829         /* TODO: Add_display_info? */
1830
1831         /* TODO use dynamic cursor width */
1832         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1833         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1834
1835         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1836                 DRM_ERROR(
1837                 "amdgpu: failed to initialize sw for display support.\n");
1838                 goto error;
1839         }
1840
1841 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1842         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1843         if (!adev->dm.secure_display_ctxs)
1844                 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
1845 #endif
1846
1847         DRM_DEBUG_DRIVER("KMS initialized.\n");
1848
1849         return 0;
1850 error:
1851         amdgpu_dm_fini(adev);
1852
1853         return -EINVAL;
1854 }
1855
1856 static int amdgpu_dm_early_fini(void *handle)
1857 {
1858         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1859
1860         amdgpu_dm_audio_fini(adev);
1861
1862         return 0;
1863 }
1864
1865 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1866 {
1867         int i;
1868
1869         if (adev->dm.vblank_control_workqueue) {
1870                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1871                 adev->dm.vblank_control_workqueue = NULL;
1872         }
1873
1874         amdgpu_dm_destroy_drm_device(&adev->dm);
1875
1876 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1877         if (adev->dm.secure_display_ctxs) {
1878                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1879                         if (adev->dm.secure_display_ctxs[i].crtc) {
1880                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1881                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1882                         }
1883                 }
1884                 kfree(adev->dm.secure_display_ctxs);
1885                 adev->dm.secure_display_ctxs = NULL;
1886         }
1887 #endif
1888         if (adev->dm.hdcp_workqueue) {
1889                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1890                 adev->dm.hdcp_workqueue = NULL;
1891         }
1892
1893         if (adev->dm.dc)
1894                 dc_deinit_callbacks(adev->dm.dc);
1895
1896         if (adev->dm.dc)
1897                 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1898
1899         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1900                 kfree(adev->dm.dmub_notify);
1901                 adev->dm.dmub_notify = NULL;
1902                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1903                 adev->dm.delayed_hpd_wq = NULL;
1904         }
1905
1906         if (adev->dm.dmub_bo)
1907                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1908                                       &adev->dm.dmub_bo_gpu_addr,
1909                                       &adev->dm.dmub_bo_cpu_addr);
1910
1911         if (adev->dm.hpd_rx_offload_wq) {
1912                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1913                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1914                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1915                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1916                         }
1917                 }
1918
1919                 kfree(adev->dm.hpd_rx_offload_wq);
1920                 adev->dm.hpd_rx_offload_wq = NULL;
1921         }
1922
1923         /* DC Destroy TODO: Replace destroy DAL */
1924         if (adev->dm.dc)
1925                 dc_destroy(&adev->dm.dc);
1926         /*
1927          * TODO: pageflip, vlank interrupt
1928          *
1929          * amdgpu_dm_irq_fini(adev);
1930          */
1931
1932         if (adev->dm.cgs_device) {
1933                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1934                 adev->dm.cgs_device = NULL;
1935         }
1936         if (adev->dm.freesync_module) {
1937                 mod_freesync_destroy(adev->dm.freesync_module);
1938                 adev->dm.freesync_module = NULL;
1939         }
1940
1941         mutex_destroy(&adev->dm.audio_lock);
1942         mutex_destroy(&adev->dm.dc_lock);
1943         mutex_destroy(&adev->dm.dpia_aux_lock);
1944 }
1945
1946 static int load_dmcu_fw(struct amdgpu_device *adev)
1947 {
1948         const char *fw_name_dmcu = NULL;
1949         int r;
1950         const struct dmcu_firmware_header_v1_0 *hdr;
1951
1952         switch (adev->asic_type) {
1953 #if defined(CONFIG_DRM_AMD_DC_SI)
1954         case CHIP_TAHITI:
1955         case CHIP_PITCAIRN:
1956         case CHIP_VERDE:
1957         case CHIP_OLAND:
1958 #endif
1959         case CHIP_BONAIRE:
1960         case CHIP_HAWAII:
1961         case CHIP_KAVERI:
1962         case CHIP_KABINI:
1963         case CHIP_MULLINS:
1964         case CHIP_TONGA:
1965         case CHIP_FIJI:
1966         case CHIP_CARRIZO:
1967         case CHIP_STONEY:
1968         case CHIP_POLARIS11:
1969         case CHIP_POLARIS10:
1970         case CHIP_POLARIS12:
1971         case CHIP_VEGAM:
1972         case CHIP_VEGA10:
1973         case CHIP_VEGA12:
1974         case CHIP_VEGA20:
1975                 return 0;
1976         case CHIP_NAVI12:
1977                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1978                 break;
1979         case CHIP_RAVEN:
1980                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1981                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1982                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1983                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1984                 else
1985                         return 0;
1986                 break;
1987         default:
1988                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1989                 case IP_VERSION(2, 0, 2):
1990                 case IP_VERSION(2, 0, 3):
1991                 case IP_VERSION(2, 0, 0):
1992                 case IP_VERSION(2, 1, 0):
1993                 case IP_VERSION(3, 0, 0):
1994                 case IP_VERSION(3, 0, 2):
1995                 case IP_VERSION(3, 0, 3):
1996                 case IP_VERSION(3, 0, 1):
1997                 case IP_VERSION(3, 1, 2):
1998                 case IP_VERSION(3, 1, 3):
1999                 case IP_VERSION(3, 1, 4):
2000                 case IP_VERSION(3, 1, 5):
2001                 case IP_VERSION(3, 1, 6):
2002                 case IP_VERSION(3, 2, 0):
2003                 case IP_VERSION(3, 2, 1):
2004                 case IP_VERSION(3, 5, 0):
2005                         return 0;
2006                 default:
2007                         break;
2008                 }
2009                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2010                 return -EINVAL;
2011         }
2012
2013         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2014                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2015                 return 0;
2016         }
2017
2018         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2019         if (r == -ENODEV) {
2020                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2021                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2022                 adev->dm.fw_dmcu = NULL;
2023                 return 0;
2024         }
2025         if (r) {
2026                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2027                         fw_name_dmcu);
2028                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2029                 return r;
2030         }
2031
2032         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2033         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2034         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2035         adev->firmware.fw_size +=
2036                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2037
2038         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2039         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2040         adev->firmware.fw_size +=
2041                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2042
2043         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2044
2045         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2046
2047         return 0;
2048 }
2049
2050 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2051 {
2052         struct amdgpu_device *adev = ctx;
2053
2054         return dm_read_reg(adev->dm.dc->ctx, address);
2055 }
2056
2057 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2058                                      uint32_t value)
2059 {
2060         struct amdgpu_device *adev = ctx;
2061
2062         return dm_write_reg(adev->dm.dc->ctx, address, value);
2063 }
2064
2065 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2066 {
2067         struct dmub_srv_create_params create_params;
2068         struct dmub_srv_region_params region_params;
2069         struct dmub_srv_region_info region_info;
2070         struct dmub_srv_memory_params memory_params;
2071         struct dmub_srv_fb_info *fb_info;
2072         struct dmub_srv *dmub_srv;
2073         const struct dmcub_firmware_header_v1_0 *hdr;
2074         enum dmub_asic dmub_asic;
2075         enum dmub_status status;
2076         int r;
2077
2078         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2079         case IP_VERSION(2, 1, 0):
2080                 dmub_asic = DMUB_ASIC_DCN21;
2081                 break;
2082         case IP_VERSION(3, 0, 0):
2083                 dmub_asic = DMUB_ASIC_DCN30;
2084                 break;
2085         case IP_VERSION(3, 0, 1):
2086                 dmub_asic = DMUB_ASIC_DCN301;
2087                 break;
2088         case IP_VERSION(3, 0, 2):
2089                 dmub_asic = DMUB_ASIC_DCN302;
2090                 break;
2091         case IP_VERSION(3, 0, 3):
2092                 dmub_asic = DMUB_ASIC_DCN303;
2093                 break;
2094         case IP_VERSION(3, 1, 2):
2095         case IP_VERSION(3, 1, 3):
2096                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2097                 break;
2098         case IP_VERSION(3, 1, 4):
2099                 dmub_asic = DMUB_ASIC_DCN314;
2100                 break;
2101         case IP_VERSION(3, 1, 5):
2102                 dmub_asic = DMUB_ASIC_DCN315;
2103                 break;
2104         case IP_VERSION(3, 1, 6):
2105                 dmub_asic = DMUB_ASIC_DCN316;
2106                 break;
2107         case IP_VERSION(3, 2, 0):
2108                 dmub_asic = DMUB_ASIC_DCN32;
2109                 break;
2110         case IP_VERSION(3, 2, 1):
2111                 dmub_asic = DMUB_ASIC_DCN321;
2112                 break;
2113         case IP_VERSION(3, 5, 0):
2114                 dmub_asic = DMUB_ASIC_DCN35;
2115                 break;
2116         default:
2117                 /* ASIC doesn't support DMUB. */
2118                 return 0;
2119         }
2120
2121         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2122         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2123
2124         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2125                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2126                         AMDGPU_UCODE_ID_DMCUB;
2127                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2128                         adev->dm.dmub_fw;
2129                 adev->firmware.fw_size +=
2130                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2131
2132                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2133                          adev->dm.dmcub_fw_version);
2134         }
2135
2136
2137         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2138         dmub_srv = adev->dm.dmub_srv;
2139
2140         if (!dmub_srv) {
2141                 DRM_ERROR("Failed to allocate DMUB service!\n");
2142                 return -ENOMEM;
2143         }
2144
2145         memset(&create_params, 0, sizeof(create_params));
2146         create_params.user_ctx = adev;
2147         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2148         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2149         create_params.asic = dmub_asic;
2150
2151         /* Create the DMUB service. */
2152         status = dmub_srv_create(dmub_srv, &create_params);
2153         if (status != DMUB_STATUS_OK) {
2154                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2155                 return -EINVAL;
2156         }
2157
2158         /* Calculate the size of all the regions for the DMUB service. */
2159         memset(&region_params, 0, sizeof(region_params));
2160
2161         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2162                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2163         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2164         region_params.vbios_size = adev->bios_size;
2165         region_params.fw_bss_data = region_params.bss_data_size ?
2166                 adev->dm.dmub_fw->data +
2167                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2168                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2169         region_params.fw_inst_const =
2170                 adev->dm.dmub_fw->data +
2171                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2172                 PSP_HEADER_BYTES;
2173         region_params.is_mailbox_in_inbox = false;
2174
2175         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2176                                            &region_info);
2177
2178         if (status != DMUB_STATUS_OK) {
2179                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2180                 return -EINVAL;
2181         }
2182
2183         /*
2184          * Allocate a framebuffer based on the total size of all the regions.
2185          * TODO: Move this into GART.
2186          */
2187         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2188                                     AMDGPU_GEM_DOMAIN_VRAM |
2189                                     AMDGPU_GEM_DOMAIN_GTT,
2190                                     &adev->dm.dmub_bo,
2191                                     &adev->dm.dmub_bo_gpu_addr,
2192                                     &adev->dm.dmub_bo_cpu_addr);
2193         if (r)
2194                 return r;
2195
2196         /* Rebase the regions on the framebuffer address. */
2197         memset(&memory_params, 0, sizeof(memory_params));
2198         memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr;
2199         memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr;
2200         memory_params.region_info = &region_info;
2201
2202         adev->dm.dmub_fb_info =
2203                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2204         fb_info = adev->dm.dmub_fb_info;
2205
2206         if (!fb_info) {
2207                 DRM_ERROR(
2208                         "Failed to allocate framebuffer info for DMUB service!\n");
2209                 return -ENOMEM;
2210         }
2211
2212         status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info);
2213         if (status != DMUB_STATUS_OK) {
2214                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2215                 return -EINVAL;
2216         }
2217
2218         return 0;
2219 }
2220
2221 static int dm_sw_init(void *handle)
2222 {
2223         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2224         int r;
2225
2226         r = dm_dmub_sw_init(adev);
2227         if (r)
2228                 return r;
2229
2230         return load_dmcu_fw(adev);
2231 }
2232
2233 static int dm_sw_fini(void *handle)
2234 {
2235         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2236
2237         kfree(adev->dm.dmub_fb_info);
2238         adev->dm.dmub_fb_info = NULL;
2239
2240         if (adev->dm.dmub_srv) {
2241                 dmub_srv_destroy(adev->dm.dmub_srv);
2242                 adev->dm.dmub_srv = NULL;
2243         }
2244
2245         amdgpu_ucode_release(&adev->dm.dmub_fw);
2246         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2247
2248         return 0;
2249 }
2250
2251 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2252 {
2253         struct amdgpu_dm_connector *aconnector;
2254         struct drm_connector *connector;
2255         struct drm_connector_list_iter iter;
2256         int ret = 0;
2257
2258         drm_connector_list_iter_begin(dev, &iter);
2259         drm_for_each_connector_iter(connector, &iter) {
2260                 aconnector = to_amdgpu_dm_connector(connector);
2261                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2262                     aconnector->mst_mgr.aux) {
2263                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2264                                          aconnector,
2265                                          aconnector->base.base.id);
2266
2267                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2268                         if (ret < 0) {
2269                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2270                                 aconnector->dc_link->type =
2271                                         dc_connection_single;
2272                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2273                                                                      aconnector->dc_link);
2274                                 break;
2275                         }
2276                 }
2277         }
2278         drm_connector_list_iter_end(&iter);
2279
2280         return ret;
2281 }
2282
2283 static int dm_late_init(void *handle)
2284 {
2285         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2286
2287         struct dmcu_iram_parameters params;
2288         unsigned int linear_lut[16];
2289         int i;
2290         struct dmcu *dmcu = NULL;
2291
2292         dmcu = adev->dm.dc->res_pool->dmcu;
2293
2294         for (i = 0; i < 16; i++)
2295                 linear_lut[i] = 0xFFFF * i / 15;
2296
2297         params.set = 0;
2298         params.backlight_ramping_override = false;
2299         params.backlight_ramping_start = 0xCCCC;
2300         params.backlight_ramping_reduction = 0xCCCCCCCC;
2301         params.backlight_lut_array_size = 16;
2302         params.backlight_lut_array = linear_lut;
2303
2304         /* Min backlight level after ABM reduction,  Don't allow below 1%
2305          * 0xFFFF x 0.01 = 0x28F
2306          */
2307         params.min_abm_backlight = 0x28F;
2308         /* In the case where abm is implemented on dmcub,
2309          * dmcu object will be null.
2310          * ABM 2.4 and up are implemented on dmcub.
2311          */
2312         if (dmcu) {
2313                 if (!dmcu_load_iram(dmcu, params))
2314                         return -EINVAL;
2315         } else if (adev->dm.dc->ctx->dmub_srv) {
2316                 struct dc_link *edp_links[MAX_NUM_EDP];
2317                 int edp_num;
2318
2319                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2320                 for (i = 0; i < edp_num; i++) {
2321                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2322                                 return -EINVAL;
2323                 }
2324         }
2325
2326         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2327 }
2328
2329 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
2330 {
2331         int ret;
2332         u8 guid[16];
2333         u64 tmp64;
2334
2335         mutex_lock(&mgr->lock);
2336         if (!mgr->mst_primary)
2337                 goto out_fail;
2338
2339         if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
2340                 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2341                 goto out_fail;
2342         }
2343
2344         ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
2345                                  DP_MST_EN |
2346                                  DP_UP_REQ_EN |
2347                                  DP_UPSTREAM_IS_SRC);
2348         if (ret < 0) {
2349                 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");
2350                 goto out_fail;
2351         }
2352
2353         /* Some hubs forget their guids after they resume */
2354         ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
2355         if (ret != 16) {
2356                 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2357                 goto out_fail;
2358         }
2359
2360         if (memchr_inv(guid, 0, 16) == NULL) {
2361                 tmp64 = get_jiffies_64();
2362                 memcpy(&guid[0], &tmp64, sizeof(u64));
2363                 memcpy(&guid[8], &tmp64, sizeof(u64));
2364
2365                 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
2366
2367                 if (ret != 16) {
2368                         drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n");
2369                         goto out_fail;
2370                 }
2371         }
2372
2373         memcpy(mgr->mst_primary->guid, guid, 16);
2374
2375 out_fail:
2376         mutex_unlock(&mgr->lock);
2377 }
2378
2379 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2380 {
2381         struct amdgpu_dm_connector *aconnector;
2382         struct drm_connector *connector;
2383         struct drm_connector_list_iter iter;
2384         struct drm_dp_mst_topology_mgr *mgr;
2385
2386         drm_connector_list_iter_begin(dev, &iter);
2387         drm_for_each_connector_iter(connector, &iter) {
2388                 aconnector = to_amdgpu_dm_connector(connector);
2389                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2390                     aconnector->mst_root)
2391                         continue;
2392
2393                 mgr = &aconnector->mst_mgr;
2394
2395                 if (suspend) {
2396                         drm_dp_mst_topology_mgr_suspend(mgr);
2397                 } else {
2398                         /* if extended timeout is supported in hardware,
2399                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2400                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2401                          */
2402                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2403                         if (!dp_is_lttpr_present(aconnector->dc_link))
2404                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2405
2406                         /* TODO: move resume_mst_branch_status() into drm mst resume again
2407                          * once topology probing work is pulled out from mst resume into mst
2408                          * resume 2nd step. mst resume 2nd step should be called after old
2409                          * state getting restored (i.e. drm_atomic_helper_resume()).
2410                          */
2411                         resume_mst_branch_status(mgr);
2412                 }
2413         }
2414         drm_connector_list_iter_end(&iter);
2415 }
2416
2417 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2418 {
2419         int ret = 0;
2420
2421         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2422          * on window driver dc implementation.
2423          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2424          * should be passed to smu during boot up and resume from s3.
2425          * boot up: dc calculate dcn watermark clock settings within dc_create,
2426          * dcn20_resource_construct
2427          * then call pplib functions below to pass the settings to smu:
2428          * smu_set_watermarks_for_clock_ranges
2429          * smu_set_watermarks_table
2430          * navi10_set_watermarks_table
2431          * smu_write_watermarks_table
2432          *
2433          * For Renoir, clock settings of dcn watermark are also fixed values.
2434          * dc has implemented different flow for window driver:
2435          * dc_hardware_init / dc_set_power_state
2436          * dcn10_init_hw
2437          * notify_wm_ranges
2438          * set_wm_ranges
2439          * -- Linux
2440          * smu_set_watermarks_for_clock_ranges
2441          * renoir_set_watermarks_table
2442          * smu_write_watermarks_table
2443          *
2444          * For Linux,
2445          * dc_hardware_init -> amdgpu_dm_init
2446          * dc_set_power_state --> dm_resume
2447          *
2448          * therefore, this function apply to navi10/12/14 but not Renoir
2449          * *
2450          */
2451         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2452         case IP_VERSION(2, 0, 2):
2453         case IP_VERSION(2, 0, 0):
2454                 break;
2455         default:
2456                 return 0;
2457         }
2458
2459         ret = amdgpu_dpm_write_watermarks_table(adev);
2460         if (ret) {
2461                 DRM_ERROR("Failed to update WMTABLE!\n");
2462                 return ret;
2463         }
2464
2465         return 0;
2466 }
2467
2468 /**
2469  * dm_hw_init() - Initialize DC device
2470  * @handle: The base driver device containing the amdgpu_dm device.
2471  *
2472  * Initialize the &struct amdgpu_display_manager device. This involves calling
2473  * the initializers of each DM component, then populating the struct with them.
2474  *
2475  * Although the function implies hardware initialization, both hardware and
2476  * software are initialized here. Splitting them out to their relevant init
2477  * hooks is a future TODO item.
2478  *
2479  * Some notable things that are initialized here:
2480  *
2481  * - Display Core, both software and hardware
2482  * - DC modules that we need (freesync and color management)
2483  * - DRM software states
2484  * - Interrupt sources and handlers
2485  * - Vblank support
2486  * - Debug FS entries, if enabled
2487  */
2488 static int dm_hw_init(void *handle)
2489 {
2490         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2491         /* Create DAL display manager */
2492         amdgpu_dm_init(adev);
2493         amdgpu_dm_hpd_init(adev);
2494
2495         return 0;
2496 }
2497
2498 /**
2499  * dm_hw_fini() - Teardown DC device
2500  * @handle: The base driver device containing the amdgpu_dm device.
2501  *
2502  * Teardown components within &struct amdgpu_display_manager that require
2503  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2504  * were loaded. Also flush IRQ workqueues and disable them.
2505  */
2506 static int dm_hw_fini(void *handle)
2507 {
2508         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2509
2510         amdgpu_dm_hpd_fini(adev);
2511
2512         amdgpu_dm_irq_fini(adev);
2513         amdgpu_dm_fini(adev);
2514         return 0;
2515 }
2516
2517
2518 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2519                                  struct dc_state *state, bool enable)
2520 {
2521         enum dc_irq_source irq_source;
2522         struct amdgpu_crtc *acrtc;
2523         int rc = -EBUSY;
2524         int i = 0;
2525
2526         for (i = 0; i < state->stream_count; i++) {
2527                 acrtc = get_crtc_by_otg_inst(
2528                                 adev, state->stream_status[i].primary_otg_inst);
2529
2530                 if (acrtc && state->stream_status[i].plane_count != 0) {
2531                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2532                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2533                         if (rc)
2534                                 DRM_WARN("Failed to %s pflip interrupts\n",
2535                                          enable ? "enable" : "disable");
2536
2537                         if (enable) {
2538                                 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2539                                         rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2540                         } else
2541                                 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2542
2543                         if (rc)
2544                                 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
2545
2546                         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2547                         /* During gpu-reset we disable and then enable vblank irq, so
2548                          * don't use amdgpu_irq_get/put() to avoid refcount change.
2549                          */
2550                         if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
2551                                 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
2552                 }
2553         }
2554
2555 }
2556
2557 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2558 {
2559         struct dc_state *context = NULL;
2560         enum dc_status res = DC_ERROR_UNEXPECTED;
2561         int i;
2562         struct dc_stream_state *del_streams[MAX_PIPES];
2563         int del_streams_count = 0;
2564
2565         memset(del_streams, 0, sizeof(del_streams));
2566
2567         context = dc_create_state(dc);
2568         if (context == NULL)
2569                 goto context_alloc_fail;
2570
2571         dc_resource_state_copy_construct_current(dc, context);
2572
2573         /* First remove from context all streams */
2574         for (i = 0; i < context->stream_count; i++) {
2575                 struct dc_stream_state *stream = context->streams[i];
2576
2577                 del_streams[del_streams_count++] = stream;
2578         }
2579
2580         /* Remove all planes for removed streams and then remove the streams */
2581         for (i = 0; i < del_streams_count; i++) {
2582                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2583                         res = DC_FAIL_DETACH_SURFACES;
2584                         goto fail;
2585                 }
2586
2587                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2588                 if (res != DC_OK)
2589                         goto fail;
2590         }
2591
2592         res = dc_commit_streams(dc, context->streams, context->stream_count);
2593
2594 fail:
2595         dc_release_state(context);
2596
2597 context_alloc_fail:
2598         return res;
2599 }
2600
2601 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2602 {
2603         int i;
2604
2605         if (dm->hpd_rx_offload_wq) {
2606                 for (i = 0; i < dm->dc->caps.max_links; i++)
2607                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2608         }
2609 }
2610
2611 static int dm_suspend(void *handle)
2612 {
2613         struct amdgpu_device *adev = handle;
2614         struct amdgpu_display_manager *dm = &adev->dm;
2615         int ret = 0;
2616
2617         if (amdgpu_in_reset(adev)) {
2618                 mutex_lock(&dm->dc_lock);
2619
2620                 dc_allow_idle_optimizations(adev->dm.dc, false);
2621
2622                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2623
2624                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2625
2626                 amdgpu_dm_commit_zero_streams(dm->dc);
2627
2628                 amdgpu_dm_irq_suspend(adev);
2629
2630                 hpd_rx_irq_work_suspend(dm);
2631
2632                 return ret;
2633         }
2634
2635         WARN_ON(adev->dm.cached_state);
2636         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2637         if (IS_ERR(adev->dm.cached_state))
2638                 return PTR_ERR(adev->dm.cached_state);
2639
2640         s3_handle_mst(adev_to_drm(adev), true);
2641
2642         amdgpu_dm_irq_suspend(adev);
2643
2644         hpd_rx_irq_work_suspend(dm);
2645
2646         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2647
2648         return 0;
2649 }
2650
2651 struct amdgpu_dm_connector *
2652 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2653                                              struct drm_crtc *crtc)
2654 {
2655         u32 i;
2656         struct drm_connector_state *new_con_state;
2657         struct drm_connector *connector;
2658         struct drm_crtc *crtc_from_state;
2659
2660         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2661                 crtc_from_state = new_con_state->crtc;
2662
2663                 if (crtc_from_state == crtc)
2664                         return to_amdgpu_dm_connector(connector);
2665         }
2666
2667         return NULL;
2668 }
2669
2670 static void emulated_link_detect(struct dc_link *link)
2671 {
2672         struct dc_sink_init_data sink_init_data = { 0 };
2673         struct display_sink_capability sink_caps = { 0 };
2674         enum dc_edid_status edid_status;
2675         struct dc_context *dc_ctx = link->ctx;
2676         struct drm_device *dev = adev_to_drm(dc_ctx->driver_context);
2677         struct dc_sink *sink = NULL;
2678         struct dc_sink *prev_sink = NULL;
2679
2680         link->type = dc_connection_none;
2681         prev_sink = link->local_sink;
2682
2683         if (prev_sink)
2684                 dc_sink_release(prev_sink);
2685
2686         switch (link->connector_signal) {
2687         case SIGNAL_TYPE_HDMI_TYPE_A: {
2688                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2689                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2690                 break;
2691         }
2692
2693         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2694                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2695                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2696                 break;
2697         }
2698
2699         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2700                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2701                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2702                 break;
2703         }
2704
2705         case SIGNAL_TYPE_LVDS: {
2706                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2707                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2708                 break;
2709         }
2710
2711         case SIGNAL_TYPE_EDP: {
2712                 sink_caps.transaction_type =
2713                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2714                 sink_caps.signal = SIGNAL_TYPE_EDP;
2715                 break;
2716         }
2717
2718         case SIGNAL_TYPE_DISPLAY_PORT: {
2719                 sink_caps.transaction_type =
2720                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2721                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2722                 break;
2723         }
2724
2725         default:
2726                 drm_err(dev, "Invalid connector type! signal:%d\n",
2727                         link->connector_signal);
2728                 return;
2729         }
2730
2731         sink_init_data.link = link;
2732         sink_init_data.sink_signal = sink_caps.signal;
2733
2734         sink = dc_sink_create(&sink_init_data);
2735         if (!sink) {
2736                 drm_err(dev, "Failed to create sink!\n");
2737                 return;
2738         }
2739
2740         /* dc_sink_create returns a new reference */
2741         link->local_sink = sink;
2742
2743         edid_status = dm_helpers_read_local_edid(
2744                         link->ctx,
2745                         link,
2746                         sink);
2747
2748         if (edid_status != EDID_OK)
2749                 drm_err(dev, "Failed to read EDID\n");
2750
2751 }
2752
2753 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2754                                      struct amdgpu_display_manager *dm)
2755 {
2756         struct {
2757                 struct dc_surface_update surface_updates[MAX_SURFACES];
2758                 struct dc_plane_info plane_infos[MAX_SURFACES];
2759                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2760                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2761                 struct dc_stream_update stream_update;
2762         } *bundle;
2763         int k, m;
2764
2765         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2766
2767         if (!bundle) {
2768                 drm_err(dm->ddev, "Failed to allocate update bundle\n");
2769                 goto cleanup;
2770         }
2771
2772         for (k = 0; k < dc_state->stream_count; k++) {
2773                 bundle->stream_update.stream = dc_state->streams[k];
2774
2775                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2776                         bundle->surface_updates[m].surface =
2777                                 dc_state->stream_status->plane_states[m];
2778                         bundle->surface_updates[m].surface->force_full_update =
2779                                 true;
2780                 }
2781
2782                 update_planes_and_stream_adapter(dm->dc,
2783                                          UPDATE_TYPE_FULL,
2784                                          dc_state->stream_status->plane_count,
2785                                          dc_state->streams[k],
2786                                          &bundle->stream_update,
2787                                          bundle->surface_updates);
2788         }
2789
2790 cleanup:
2791         kfree(bundle);
2792 }
2793
2794 static int dm_resume(void *handle)
2795 {
2796         struct amdgpu_device *adev = handle;
2797         struct drm_device *ddev = adev_to_drm(adev);
2798         struct amdgpu_display_manager *dm = &adev->dm;
2799         struct amdgpu_dm_connector *aconnector;
2800         struct drm_connector *connector;
2801         struct drm_connector_list_iter iter;
2802         struct drm_crtc *crtc;
2803         struct drm_crtc_state *new_crtc_state;
2804         struct dm_crtc_state *dm_new_crtc_state;
2805         struct drm_plane *plane;
2806         struct drm_plane_state *new_plane_state;
2807         struct dm_plane_state *dm_new_plane_state;
2808         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2809         enum dc_connection_type new_connection_type = dc_connection_none;
2810         struct dc_state *dc_state;
2811         int i, r, j, ret;
2812         bool need_hotplug = false;
2813
2814         if (dm->dc->caps.ips_support) {
2815                 dc_dmub_srv_exit_low_power_state(dm->dc);
2816         }
2817
2818         if (amdgpu_in_reset(adev)) {
2819                 dc_state = dm->cached_dc_state;
2820
2821                 /*
2822                  * The dc->current_state is backed up into dm->cached_dc_state
2823                  * before we commit 0 streams.
2824                  *
2825                  * DC will clear link encoder assignments on the real state
2826                  * but the changes won't propagate over to the copy we made
2827                  * before the 0 streams commit.
2828                  *
2829                  * DC expects that link encoder assignments are *not* valid
2830                  * when committing a state, so as a workaround we can copy
2831                  * off of the current state.
2832                  *
2833                  * We lose the previous assignments, but we had already
2834                  * commit 0 streams anyway.
2835                  */
2836                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2837
2838                 r = dm_dmub_hw_init(adev);
2839                 if (r)
2840                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2841
2842                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2843
2844                 dc_resume(dm->dc);
2845
2846                 amdgpu_dm_irq_resume_early(adev);
2847
2848                 for (i = 0; i < dc_state->stream_count; i++) {
2849                         dc_state->streams[i]->mode_changed = true;
2850                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2851                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2852                                         = 0xffffffff;
2853                         }
2854                 }
2855
2856                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2857                         amdgpu_dm_outbox_init(adev);
2858                         dc_enable_dmub_outbox(adev->dm.dc);
2859                 }
2860
2861                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2862
2863                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2864
2865                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2866
2867                 dc_release_state(dm->cached_dc_state);
2868                 dm->cached_dc_state = NULL;
2869
2870                 amdgpu_dm_irq_resume_late(adev);
2871
2872                 mutex_unlock(&dm->dc_lock);
2873
2874                 return 0;
2875         }
2876         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2877         dc_release_state(dm_state->context);
2878         dm_state->context = dc_create_state(dm->dc);
2879         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2880         dc_resource_state_construct(dm->dc, dm_state->context);
2881
2882         /* Before powering on DC we need to re-initialize DMUB. */
2883         dm_dmub_hw_resume(adev);
2884
2885         /* Re-enable outbox interrupts for DPIA. */
2886         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2887                 amdgpu_dm_outbox_init(adev);
2888                 dc_enable_dmub_outbox(adev->dm.dc);
2889         }
2890
2891         /* power on hardware */
2892         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2893
2894         /* program HPD filter */
2895         dc_resume(dm->dc);
2896
2897         /*
2898          * early enable HPD Rx IRQ, should be done before set mode as short
2899          * pulse interrupts are used for MST
2900          */
2901         amdgpu_dm_irq_resume_early(adev);
2902
2903         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2904         s3_handle_mst(ddev, false);
2905
2906         /* Do detection*/
2907         drm_connector_list_iter_begin(ddev, &iter);
2908         drm_for_each_connector_iter(connector, &iter) {
2909                 aconnector = to_amdgpu_dm_connector(connector);
2910
2911                 if (!aconnector->dc_link)
2912                         continue;
2913
2914                 /*
2915                  * this is the case when traversing through already created end sink
2916                  * MST connectors, should be skipped
2917                  */
2918                 if (aconnector && aconnector->mst_root)
2919                         continue;
2920
2921                 mutex_lock(&aconnector->hpd_lock);
2922                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2923                         DRM_ERROR("KMS: Failed to detect connector\n");
2924
2925                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2926                         emulated_link_detect(aconnector->dc_link);
2927                 } else {
2928                         mutex_lock(&dm->dc_lock);
2929                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2930                         mutex_unlock(&dm->dc_lock);
2931                 }
2932
2933                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2934                         aconnector->fake_enable = false;
2935
2936                 if (aconnector->dc_sink)
2937                         dc_sink_release(aconnector->dc_sink);
2938                 aconnector->dc_sink = NULL;
2939                 amdgpu_dm_update_connector_after_detect(aconnector);
2940                 mutex_unlock(&aconnector->hpd_lock);
2941         }
2942         drm_connector_list_iter_end(&iter);
2943
2944         /* Force mode set in atomic commit */
2945         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2946                 new_crtc_state->active_changed = true;
2947
2948         /*
2949          * atomic_check is expected to create the dc states. We need to release
2950          * them here, since they were duplicated as part of the suspend
2951          * procedure.
2952          */
2953         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2954                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2955                 if (dm_new_crtc_state->stream) {
2956                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2957                         dc_stream_release(dm_new_crtc_state->stream);
2958                         dm_new_crtc_state->stream = NULL;
2959                 }
2960         }
2961
2962         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2963                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2964                 if (dm_new_plane_state->dc_state) {
2965                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2966                         dc_plane_state_release(dm_new_plane_state->dc_state);
2967                         dm_new_plane_state->dc_state = NULL;
2968                 }
2969         }
2970
2971         drm_atomic_helper_resume(ddev, dm->cached_state);
2972
2973         dm->cached_state = NULL;
2974
2975         /* Do mst topology probing after resuming cached state*/
2976         drm_connector_list_iter_begin(ddev, &iter);
2977         drm_for_each_connector_iter(connector, &iter) {
2978                 aconnector = to_amdgpu_dm_connector(connector);
2979                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2980                     aconnector->mst_root)
2981                         continue;
2982
2983                 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true);
2984
2985                 if (ret < 0) {
2986                         dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2987                                         aconnector->dc_link);
2988                         need_hotplug = true;
2989                 }
2990         }
2991         drm_connector_list_iter_end(&iter);
2992
2993         if (need_hotplug)
2994                 drm_kms_helper_hotplug_event(ddev);
2995
2996         amdgpu_dm_irq_resume_late(adev);
2997
2998         amdgpu_dm_smu_write_watermarks_table(adev);
2999
3000         return 0;
3001 }
3002
3003 /**
3004  * DOC: DM Lifecycle
3005  *
3006  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
3007  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
3008  * the base driver's device list to be initialized and torn down accordingly.
3009  *
3010  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
3011  */
3012
3013 static const struct amd_ip_funcs amdgpu_dm_funcs = {
3014         .name = "dm",
3015         .early_init = dm_early_init,
3016         .late_init = dm_late_init,
3017         .sw_init = dm_sw_init,
3018         .sw_fini = dm_sw_fini,
3019         .early_fini = amdgpu_dm_early_fini,
3020         .hw_init = dm_hw_init,
3021         .hw_fini = dm_hw_fini,
3022         .suspend = dm_suspend,
3023         .resume = dm_resume,
3024         .is_idle = dm_is_idle,
3025         .wait_for_idle = dm_wait_for_idle,
3026         .check_soft_reset = dm_check_soft_reset,
3027         .soft_reset = dm_soft_reset,
3028         .set_clockgating_state = dm_set_clockgating_state,
3029         .set_powergating_state = dm_set_powergating_state,
3030 };
3031
3032 const struct amdgpu_ip_block_version dm_ip_block = {
3033         .type = AMD_IP_BLOCK_TYPE_DCE,
3034         .major = 1,
3035         .minor = 0,
3036         .rev = 0,
3037         .funcs = &amdgpu_dm_funcs,
3038 };
3039
3040
3041 /**
3042  * DOC: atomic
3043  *
3044  * *WIP*
3045  */
3046
3047 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
3048         .fb_create = amdgpu_display_user_framebuffer_create,
3049         .get_format_info = amdgpu_dm_plane_get_format_info,
3050         .atomic_check = amdgpu_dm_atomic_check,
3051         .atomic_commit = drm_atomic_helper_commit,
3052 };
3053
3054 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
3055         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
3056         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
3057 };
3058
3059 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
3060 {
3061         struct amdgpu_dm_backlight_caps *caps;
3062         struct drm_connector *conn_base;
3063         struct amdgpu_device *adev;
3064         struct drm_luminance_range_info *luminance_range;
3065
3066         if (aconnector->bl_idx == -1 ||
3067             aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
3068                 return;
3069
3070         conn_base = &aconnector->base;
3071         adev = drm_to_adev(conn_base->dev);
3072
3073         caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3074         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3075         caps->aux_support = false;
3076
3077         if (caps->ext_caps->bits.oled == 1
3078             /*
3079              * ||
3080              * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3081              * caps->ext_caps->bits.hdr_aux_backlight_control == 1
3082              */)
3083                 caps->aux_support = true;
3084
3085         if (amdgpu_backlight == 0)
3086                 caps->aux_support = false;
3087         else if (amdgpu_backlight == 1)
3088                 caps->aux_support = true;
3089
3090         luminance_range = &conn_base->display_info.luminance_range;
3091
3092         if (luminance_range->max_luminance) {
3093                 caps->aux_min_input_signal = luminance_range->min_luminance;
3094                 caps->aux_max_input_signal = luminance_range->max_luminance;
3095         } else {
3096                 caps->aux_min_input_signal = 0;
3097                 caps->aux_max_input_signal = 512;
3098         }
3099 }
3100
3101 void amdgpu_dm_update_connector_after_detect(
3102                 struct amdgpu_dm_connector *aconnector)
3103 {
3104         struct drm_connector *connector = &aconnector->base;
3105         struct drm_device *dev = connector->dev;
3106         struct dc_sink *sink;
3107
3108         /* MST handled by drm_mst framework */
3109         if (aconnector->mst_mgr.mst_state == true)
3110                 return;
3111
3112         sink = aconnector->dc_link->local_sink;
3113         if (sink)
3114                 dc_sink_retain(sink);
3115
3116         /*
3117          * Edid mgmt connector gets first update only in mode_valid hook and then
3118          * the connector sink is set to either fake or physical sink depends on link status.
3119          * Skip if already done during boot.
3120          */
3121         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3122                         && aconnector->dc_em_sink) {
3123
3124                 /*
3125                  * For S3 resume with headless use eml_sink to fake stream
3126                  * because on resume connector->sink is set to NULL
3127                  */
3128                 mutex_lock(&dev->mode_config.mutex);
3129
3130                 if (sink) {
3131                         if (aconnector->dc_sink) {
3132                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3133                                 /*
3134                                  * retain and release below are used to
3135                                  * bump up refcount for sink because the link doesn't point
3136                                  * to it anymore after disconnect, so on next crtc to connector
3137                                  * reshuffle by UMD we will get into unwanted dc_sink release
3138                                  */
3139                                 dc_sink_release(aconnector->dc_sink);
3140                         }
3141                         aconnector->dc_sink = sink;
3142                         dc_sink_retain(aconnector->dc_sink);
3143                         amdgpu_dm_update_freesync_caps(connector,
3144                                         aconnector->edid);
3145                 } else {
3146                         amdgpu_dm_update_freesync_caps(connector, NULL);
3147                         if (!aconnector->dc_sink) {
3148                                 aconnector->dc_sink = aconnector->dc_em_sink;
3149                                 dc_sink_retain(aconnector->dc_sink);
3150                         }
3151                 }
3152
3153                 mutex_unlock(&dev->mode_config.mutex);
3154
3155                 if (sink)
3156                         dc_sink_release(sink);
3157                 return;
3158         }
3159
3160         /*
3161          * TODO: temporary guard to look for proper fix
3162          * if this sink is MST sink, we should not do anything
3163          */
3164         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3165                 dc_sink_release(sink);
3166                 return;
3167         }
3168
3169         if (aconnector->dc_sink == sink) {
3170                 /*
3171                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3172                  * Do nothing!!
3173                  */
3174                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3175                                 aconnector->connector_id);
3176                 if (sink)
3177                         dc_sink_release(sink);
3178                 return;
3179         }
3180
3181         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3182                 aconnector->connector_id, aconnector->dc_sink, sink);
3183
3184         mutex_lock(&dev->mode_config.mutex);
3185
3186         /*
3187          * 1. Update status of the drm connector
3188          * 2. Send an event and let userspace tell us what to do
3189          */
3190         if (sink) {
3191                 /*
3192                  * TODO: check if we still need the S3 mode update workaround.
3193                  * If yes, put it here.
3194                  */
3195                 if (aconnector->dc_sink) {
3196                         amdgpu_dm_update_freesync_caps(connector, NULL);
3197                         dc_sink_release(aconnector->dc_sink);
3198                 }
3199
3200                 aconnector->dc_sink = sink;
3201                 dc_sink_retain(aconnector->dc_sink);
3202                 if (sink->dc_edid.length == 0) {
3203                         aconnector->edid = NULL;
3204                         if (aconnector->dc_link->aux_mode) {
3205                                 drm_dp_cec_unset_edid(
3206                                         &aconnector->dm_dp_aux.aux);
3207                         }
3208                 } else {
3209                         aconnector->edid =
3210                                 (struct edid *)sink->dc_edid.raw_edid;
3211
3212                         if (aconnector->dc_link->aux_mode)
3213                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3214                                                     aconnector->edid);
3215                 }
3216
3217                 if (!aconnector->timing_requested) {
3218                         aconnector->timing_requested =
3219                                 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3220                         if (!aconnector->timing_requested)
3221                                 drm_err(dev,
3222                                         "failed to create aconnector->requested_timing\n");
3223                 }
3224
3225                 drm_connector_update_edid_property(connector, aconnector->edid);
3226                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3227                 update_connector_ext_caps(aconnector);
3228         } else {
3229                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3230                 amdgpu_dm_update_freesync_caps(connector, NULL);
3231                 drm_connector_update_edid_property(connector, NULL);
3232                 aconnector->num_modes = 0;
3233                 dc_sink_release(aconnector->dc_sink);
3234                 aconnector->dc_sink = NULL;
3235                 aconnector->edid = NULL;
3236                 kfree(aconnector->timing_requested);
3237                 aconnector->timing_requested = NULL;
3238                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3239                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3240                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3241         }
3242
3243         mutex_unlock(&dev->mode_config.mutex);
3244
3245         update_subconnector_property(aconnector);
3246
3247         if (sink)
3248                 dc_sink_release(sink);
3249 }
3250
3251 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3252 {
3253         struct drm_connector *connector = &aconnector->base;
3254         struct drm_device *dev = connector->dev;
3255         enum dc_connection_type new_connection_type = dc_connection_none;
3256         struct amdgpu_device *adev = drm_to_adev(dev);
3257         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3258         bool ret = false;
3259
3260         if (adev->dm.disable_hpd_irq)
3261                 return;
3262
3263         /*
3264          * In case of failure or MST no need to update connector status or notify the OS
3265          * since (for MST case) MST does this in its own context.
3266          */
3267         mutex_lock(&aconnector->hpd_lock);
3268
3269         if (adev->dm.hdcp_workqueue) {
3270                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3271                 dm_con_state->update_hdcp = true;
3272         }
3273         if (aconnector->fake_enable)
3274                 aconnector->fake_enable = false;
3275
3276         aconnector->timing_changed = false;
3277
3278         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3279                 DRM_ERROR("KMS: Failed to detect connector\n");
3280
3281         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3282                 emulated_link_detect(aconnector->dc_link);
3283
3284                 drm_modeset_lock_all(dev);
3285                 dm_restore_drm_connector_state(dev, connector);
3286                 drm_modeset_unlock_all(dev);
3287
3288                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3289                         drm_kms_helper_connector_hotplug_event(connector);
3290         } else {
3291                 mutex_lock(&adev->dm.dc_lock);
3292                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3293                 mutex_unlock(&adev->dm.dc_lock);
3294                 if (ret) {
3295                         amdgpu_dm_update_connector_after_detect(aconnector);
3296
3297                         drm_modeset_lock_all(dev);
3298                         dm_restore_drm_connector_state(dev, connector);
3299                         drm_modeset_unlock_all(dev);
3300
3301                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3302                                 drm_kms_helper_connector_hotplug_event(connector);
3303                 }
3304         }
3305         mutex_unlock(&aconnector->hpd_lock);
3306
3307 }
3308
3309 static void handle_hpd_irq(void *param)
3310 {
3311         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3312
3313         handle_hpd_irq_helper(aconnector);
3314
3315 }
3316
3317 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3318                                                         union hpd_irq_data hpd_irq_data)
3319 {
3320         struct hpd_rx_irq_offload_work *offload_work =
3321                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3322
3323         if (!offload_work) {
3324                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3325                 return;
3326         }
3327
3328         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3329         offload_work->data = hpd_irq_data;
3330         offload_work->offload_wq = offload_wq;
3331
3332         queue_work(offload_wq->wq, &offload_work->work);
3333         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3334 }
3335
3336 static void handle_hpd_rx_irq(void *param)
3337 {
3338         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3339         struct drm_connector *connector = &aconnector->base;
3340         struct drm_device *dev = connector->dev;
3341         struct dc_link *dc_link = aconnector->dc_link;
3342         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3343         bool result = false;
3344         enum dc_connection_type new_connection_type = dc_connection_none;
3345         struct amdgpu_device *adev = drm_to_adev(dev);
3346         union hpd_irq_data hpd_irq_data;
3347         bool link_loss = false;
3348         bool has_left_work = false;
3349         int idx = dc_link->link_index;
3350         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3351
3352         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3353
3354         if (adev->dm.disable_hpd_irq)
3355                 return;
3356
3357         /*
3358          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3359          * conflict, after implement i2c helper, this mutex should be
3360          * retired.
3361          */
3362         mutex_lock(&aconnector->hpd_lock);
3363
3364         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3365                                                 &link_loss, true, &has_left_work);
3366
3367         if (!has_left_work)
3368                 goto out;
3369
3370         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3371                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3372                 goto out;
3373         }
3374
3375         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3376                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3377                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3378                         bool skip = false;
3379
3380                         /*
3381                          * DOWN_REP_MSG_RDY is also handled by polling method
3382                          * mgr->cbs->poll_hpd_irq()
3383                          */
3384                         spin_lock(&offload_wq->offload_lock);
3385                         skip = offload_wq->is_handling_mst_msg_rdy_event;
3386
3387                         if (!skip)
3388                                 offload_wq->is_handling_mst_msg_rdy_event = true;
3389
3390                         spin_unlock(&offload_wq->offload_lock);
3391
3392                         if (!skip)
3393                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3394
3395                         goto out;
3396                 }
3397
3398                 if (link_loss) {
3399                         bool skip = false;
3400
3401                         spin_lock(&offload_wq->offload_lock);
3402                         skip = offload_wq->is_handling_link_loss;
3403
3404                         if (!skip)
3405                                 offload_wq->is_handling_link_loss = true;
3406
3407                         spin_unlock(&offload_wq->offload_lock);
3408
3409                         if (!skip)
3410                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3411
3412                         goto out;
3413                 }
3414         }
3415
3416 out:
3417         if (result && !is_mst_root_connector) {
3418                 /* Downstream Port status changed. */
3419                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3420                         DRM_ERROR("KMS: Failed to detect connector\n");
3421
3422                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3423                         emulated_link_detect(dc_link);
3424
3425                         if (aconnector->fake_enable)
3426                                 aconnector->fake_enable = false;
3427
3428                         amdgpu_dm_update_connector_after_detect(aconnector);
3429
3430
3431                         drm_modeset_lock_all(dev);
3432                         dm_restore_drm_connector_state(dev, connector);
3433                         drm_modeset_unlock_all(dev);
3434
3435                         drm_kms_helper_connector_hotplug_event(connector);
3436                 } else {
3437                         bool ret = false;
3438
3439                         mutex_lock(&adev->dm.dc_lock);
3440                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3441                         mutex_unlock(&adev->dm.dc_lock);
3442
3443                         if (ret) {
3444                                 if (aconnector->fake_enable)
3445                                         aconnector->fake_enable = false;
3446
3447                                 amdgpu_dm_update_connector_after_detect(aconnector);
3448
3449                                 drm_modeset_lock_all(dev);
3450                                 dm_restore_drm_connector_state(dev, connector);
3451                                 drm_modeset_unlock_all(dev);
3452
3453                                 drm_kms_helper_connector_hotplug_event(connector);
3454                         }
3455                 }
3456         }
3457         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3458                 if (adev->dm.hdcp_workqueue)
3459                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3460         }
3461
3462         if (dc_link->type != dc_connection_mst_branch)
3463                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3464
3465         mutex_unlock(&aconnector->hpd_lock);
3466 }
3467
3468 static void register_hpd_handlers(struct amdgpu_device *adev)
3469 {
3470         struct drm_device *dev = adev_to_drm(adev);
3471         struct drm_connector *connector;
3472         struct amdgpu_dm_connector *aconnector;
3473         const struct dc_link *dc_link;
3474         struct dc_interrupt_params int_params = {0};
3475
3476         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3477         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3478
3479         list_for_each_entry(connector,
3480                         &dev->mode_config.connector_list, head) {
3481
3482                 aconnector = to_amdgpu_dm_connector(connector);
3483                 dc_link = aconnector->dc_link;
3484
3485                 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
3486                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3487                         int_params.irq_source = dc_link->irq_source_hpd;
3488
3489                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3490                                         handle_hpd_irq,
3491                                         (void *) aconnector);
3492                 }
3493
3494                 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
3495
3496                         /* Also register for DP short pulse (hpd_rx). */
3497                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3498                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3499
3500                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3501                                         handle_hpd_rx_irq,
3502                                         (void *) aconnector);
3503                 }
3504
3505                 if (adev->dm.hpd_rx_offload_wq)
3506                         adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3507                                 aconnector;
3508         }
3509 }
3510
3511 #if defined(CONFIG_DRM_AMD_DC_SI)
3512 /* Register IRQ sources and initialize IRQ callbacks */
3513 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3514 {
3515         struct dc *dc = adev->dm.dc;
3516         struct common_irq_params *c_irq_params;
3517         struct dc_interrupt_params int_params = {0};
3518         int r;
3519         int i;
3520         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3521
3522         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3523         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3524
3525         /*
3526          * Actions of amdgpu_irq_add_id():
3527          * 1. Register a set() function with base driver.
3528          *    Base driver will call set() function to enable/disable an
3529          *    interrupt in DC hardware.
3530          * 2. Register amdgpu_dm_irq_handler().
3531          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3532          *    coming from DC hardware.
3533          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3534          *    for acknowledging and handling.
3535          */
3536
3537         /* Use VBLANK interrupt */
3538         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3539                 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
3540                 if (r) {
3541                         DRM_ERROR("Failed to add crtc irq id!\n");
3542                         return r;
3543                 }
3544
3545                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3546                 int_params.irq_source =
3547                         dc_interrupt_to_irq_source(dc, i + 1, 0);
3548
3549                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3550
3551                 c_irq_params->adev = adev;
3552                 c_irq_params->irq_src = int_params.irq_source;
3553
3554                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3555                                 dm_crtc_high_irq, c_irq_params);
3556         }
3557
3558         /* Use GRPH_PFLIP interrupt */
3559         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3560                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3561                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3562                 if (r) {
3563                         DRM_ERROR("Failed to add page flip irq id!\n");
3564                         return r;
3565                 }
3566
3567                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3568                 int_params.irq_source =
3569                         dc_interrupt_to_irq_source(dc, i, 0);
3570
3571                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3572
3573                 c_irq_params->adev = adev;
3574                 c_irq_params->irq_src = int_params.irq_source;
3575
3576                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3577                                 dm_pflip_high_irq, c_irq_params);
3578
3579         }
3580
3581         /* HPD */
3582         r = amdgpu_irq_add_id(adev, client_id,
3583                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3584         if (r) {
3585                 DRM_ERROR("Failed to add hpd irq id!\n");
3586                 return r;
3587         }
3588
3589         register_hpd_handlers(adev);
3590
3591         return 0;
3592 }
3593 #endif
3594
3595 /* Register IRQ sources and initialize IRQ callbacks */
3596 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3597 {
3598         struct dc *dc = adev->dm.dc;
3599         struct common_irq_params *c_irq_params;
3600         struct dc_interrupt_params int_params = {0};
3601         int r;
3602         int i;
3603         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3604
3605         if (adev->family >= AMDGPU_FAMILY_AI)
3606                 client_id = SOC15_IH_CLIENTID_DCE;
3607
3608         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3609         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3610
3611         /*
3612          * Actions of amdgpu_irq_add_id():
3613          * 1. Register a set() function with base driver.
3614          *    Base driver will call set() function to enable/disable an
3615          *    interrupt in DC hardware.
3616          * 2. Register amdgpu_dm_irq_handler().
3617          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3618          *    coming from DC hardware.
3619          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3620          *    for acknowledging and handling.
3621          */
3622
3623         /* Use VBLANK interrupt */
3624         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3625                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3626                 if (r) {
3627                         DRM_ERROR("Failed to add crtc irq id!\n");
3628                         return r;
3629                 }
3630
3631                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3632                 int_params.irq_source =
3633                         dc_interrupt_to_irq_source(dc, i, 0);
3634
3635                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3636
3637                 c_irq_params->adev = adev;
3638                 c_irq_params->irq_src = int_params.irq_source;
3639
3640                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3641                                 dm_crtc_high_irq, c_irq_params);
3642         }
3643
3644         /* Use VUPDATE interrupt */
3645         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3646                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3647                 if (r) {
3648                         DRM_ERROR("Failed to add vupdate irq id!\n");
3649                         return r;
3650                 }
3651
3652                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3653                 int_params.irq_source =
3654                         dc_interrupt_to_irq_source(dc, i, 0);
3655
3656                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3657
3658                 c_irq_params->adev = adev;
3659                 c_irq_params->irq_src = int_params.irq_source;
3660
3661                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3662                                 dm_vupdate_high_irq, c_irq_params);
3663         }
3664
3665         /* Use GRPH_PFLIP interrupt */
3666         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3667                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3668                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3669                 if (r) {
3670                         DRM_ERROR("Failed to add page flip irq id!\n");
3671                         return r;
3672                 }
3673
3674                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3675                 int_params.irq_source =
3676                         dc_interrupt_to_irq_source(dc, i, 0);
3677
3678                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3679
3680                 c_irq_params->adev = adev;
3681                 c_irq_params->irq_src = int_params.irq_source;
3682
3683                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3684                                 dm_pflip_high_irq, c_irq_params);
3685
3686         }
3687
3688         /* HPD */
3689         r = amdgpu_irq_add_id(adev, client_id,
3690                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3691         if (r) {
3692                 DRM_ERROR("Failed to add hpd irq id!\n");
3693                 return r;
3694         }
3695
3696         register_hpd_handlers(adev);
3697
3698         return 0;
3699 }
3700
3701 /* Register IRQ sources and initialize IRQ callbacks */
3702 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3703 {
3704         struct dc *dc = adev->dm.dc;
3705         struct common_irq_params *c_irq_params;
3706         struct dc_interrupt_params int_params = {0};
3707         int r;
3708         int i;
3709 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3710         static const unsigned int vrtl_int_srcid[] = {
3711                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3712                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3713                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3714                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3715                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3716                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3717         };
3718 #endif
3719
3720         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3721         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3722
3723         /*
3724          * Actions of amdgpu_irq_add_id():
3725          * 1. Register a set() function with base driver.
3726          *    Base driver will call set() function to enable/disable an
3727          *    interrupt in DC hardware.
3728          * 2. Register amdgpu_dm_irq_handler().
3729          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3730          *    coming from DC hardware.
3731          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3732          *    for acknowledging and handling.
3733          */
3734
3735         /* Use VSTARTUP interrupt */
3736         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3737                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3738                         i++) {
3739                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3740
3741                 if (r) {
3742                         DRM_ERROR("Failed to add crtc irq id!\n");
3743                         return r;
3744                 }
3745
3746                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3747                 int_params.irq_source =
3748                         dc_interrupt_to_irq_source(dc, i, 0);
3749
3750                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3751
3752                 c_irq_params->adev = adev;
3753                 c_irq_params->irq_src = int_params.irq_source;
3754
3755                 amdgpu_dm_irq_register_interrupt(
3756                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3757         }
3758
3759         /* Use otg vertical line interrupt */
3760 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3761         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3762                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3763                                 vrtl_int_srcid[i], &adev->vline0_irq);
3764
3765                 if (r) {
3766                         DRM_ERROR("Failed to add vline0 irq id!\n");
3767                         return r;
3768                 }
3769
3770                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3771                 int_params.irq_source =
3772                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3773
3774                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3775                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3776                         break;
3777                 }
3778
3779                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3780                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3781
3782                 c_irq_params->adev = adev;
3783                 c_irq_params->irq_src = int_params.irq_source;
3784
3785                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3786                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3787         }
3788 #endif
3789
3790         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3791          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3792          * to trigger at end of each vblank, regardless of state of the lock,
3793          * matching DCE behaviour.
3794          */
3795         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3796              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3797              i++) {
3798                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3799
3800                 if (r) {
3801                         DRM_ERROR("Failed to add vupdate irq id!\n");
3802                         return r;
3803                 }
3804
3805                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3806                 int_params.irq_source =
3807                         dc_interrupt_to_irq_source(dc, i, 0);
3808
3809                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3810
3811                 c_irq_params->adev = adev;
3812                 c_irq_params->irq_src = int_params.irq_source;
3813
3814                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3815                                 dm_vupdate_high_irq, c_irq_params);
3816         }
3817
3818         /* Use GRPH_PFLIP interrupt */
3819         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3820                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3821                         i++) {
3822                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3823                 if (r) {
3824                         DRM_ERROR("Failed to add page flip irq id!\n");
3825                         return r;
3826                 }
3827
3828                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3829                 int_params.irq_source =
3830                         dc_interrupt_to_irq_source(dc, i, 0);
3831
3832                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3833
3834                 c_irq_params->adev = adev;
3835                 c_irq_params->irq_src = int_params.irq_source;
3836
3837                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3838                                 dm_pflip_high_irq, c_irq_params);
3839
3840         }
3841
3842         /* HPD */
3843         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3844                         &adev->hpd_irq);
3845         if (r) {
3846                 DRM_ERROR("Failed to add hpd irq id!\n");
3847                 return r;
3848         }
3849
3850         register_hpd_handlers(adev);
3851
3852         return 0;
3853 }
3854 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3855 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3856 {
3857         struct dc *dc = adev->dm.dc;
3858         struct common_irq_params *c_irq_params;
3859         struct dc_interrupt_params int_params = {0};
3860         int r, i;
3861
3862         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3863         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3864
3865         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3866                         &adev->dmub_outbox_irq);
3867         if (r) {
3868                 DRM_ERROR("Failed to add outbox irq id!\n");
3869                 return r;
3870         }
3871
3872         if (dc->ctx->dmub_srv) {
3873                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3874                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3875                 int_params.irq_source =
3876                 dc_interrupt_to_irq_source(dc, i, 0);
3877
3878                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3879
3880                 c_irq_params->adev = adev;
3881                 c_irq_params->irq_src = int_params.irq_source;
3882
3883                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3884                                 dm_dmub_outbox1_low_irq, c_irq_params);
3885         }
3886
3887         return 0;
3888 }
3889
3890 /*
3891  * Acquires the lock for the atomic state object and returns
3892  * the new atomic state.
3893  *
3894  * This should only be called during atomic check.
3895  */
3896 int dm_atomic_get_state(struct drm_atomic_state *state,
3897                         struct dm_atomic_state **dm_state)
3898 {
3899         struct drm_device *dev = state->dev;
3900         struct amdgpu_device *adev = drm_to_adev(dev);
3901         struct amdgpu_display_manager *dm = &adev->dm;
3902         struct drm_private_state *priv_state;
3903
3904         if (*dm_state)
3905                 return 0;
3906
3907         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3908         if (IS_ERR(priv_state))
3909                 return PTR_ERR(priv_state);
3910
3911         *dm_state = to_dm_atomic_state(priv_state);
3912
3913         return 0;
3914 }
3915
3916 static struct dm_atomic_state *
3917 dm_atomic_get_new_state(struct drm_atomic_state *state)
3918 {
3919         struct drm_device *dev = state->dev;
3920         struct amdgpu_device *adev = drm_to_adev(dev);
3921         struct amdgpu_display_manager *dm = &adev->dm;
3922         struct drm_private_obj *obj;
3923         struct drm_private_state *new_obj_state;
3924         int i;
3925
3926         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3927                 if (obj->funcs == dm->atomic_obj.funcs)
3928                         return to_dm_atomic_state(new_obj_state);
3929         }
3930
3931         return NULL;
3932 }
3933
3934 static struct drm_private_state *
3935 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3936 {
3937         struct dm_atomic_state *old_state, *new_state;
3938
3939         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3940         if (!new_state)
3941                 return NULL;
3942
3943         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3944
3945         old_state = to_dm_atomic_state(obj->state);
3946
3947         if (old_state && old_state->context)
3948                 new_state->context = dc_copy_state(old_state->context);
3949
3950         if (!new_state->context) {
3951                 kfree(new_state);
3952                 return NULL;
3953         }
3954
3955         return &new_state->base;
3956 }
3957
3958 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3959                                     struct drm_private_state *state)
3960 {
3961         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3962
3963         if (dm_state && dm_state->context)
3964                 dc_release_state(dm_state->context);
3965
3966         kfree(dm_state);
3967 }
3968
3969 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3970         .atomic_duplicate_state = dm_atomic_duplicate_state,
3971         .atomic_destroy_state = dm_atomic_destroy_state,
3972 };
3973
3974 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3975 {
3976         struct dm_atomic_state *state;
3977         int r;
3978
3979         adev->mode_info.mode_config_initialized = true;
3980
3981         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3982         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3983
3984         adev_to_drm(adev)->mode_config.max_width = 16384;
3985         adev_to_drm(adev)->mode_config.max_height = 16384;
3986
3987         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3988         if (adev->asic_type == CHIP_HAWAII)
3989                 /* disable prefer shadow for now due to hibernation issues */
3990                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3991         else
3992                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3993         /* indicates support for immediate flip */
3994         adev_to_drm(adev)->mode_config.async_page_flip = true;
3995
3996         state = kzalloc(sizeof(*state), GFP_KERNEL);
3997         if (!state)
3998                 return -ENOMEM;
3999
4000         state->context = dc_create_state(adev->dm.dc);
4001         if (!state->context) {
4002                 kfree(state);
4003                 return -ENOMEM;
4004         }
4005
4006         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
4007
4008         drm_atomic_private_obj_init(adev_to_drm(adev),
4009                                     &adev->dm.atomic_obj,
4010                                     &state->base,
4011                                     &dm_atomic_state_funcs);
4012
4013         r = amdgpu_display_modeset_create_props(adev);
4014         if (r) {
4015                 dc_release_state(state->context);
4016                 kfree(state);
4017                 return r;
4018         }
4019
4020         r = amdgpu_dm_audio_init(adev);
4021         if (r) {
4022                 dc_release_state(state->context);
4023                 kfree(state);
4024                 return r;
4025         }
4026
4027         return 0;
4028 }
4029
4030 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4031 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4032 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4033
4034 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4035                                             int bl_idx)
4036 {
4037 #if defined(CONFIG_ACPI)
4038         struct amdgpu_dm_backlight_caps caps;
4039
4040         memset(&caps, 0, sizeof(caps));
4041
4042         if (dm->backlight_caps[bl_idx].caps_valid)
4043                 return;
4044
4045         amdgpu_acpi_get_backlight_caps(&caps);
4046         if (caps.caps_valid) {
4047                 dm->backlight_caps[bl_idx].caps_valid = true;
4048                 if (caps.aux_support)
4049                         return;
4050                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4051                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4052         } else {
4053                 dm->backlight_caps[bl_idx].min_input_signal =
4054                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4055                 dm->backlight_caps[bl_idx].max_input_signal =
4056                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4057         }
4058 #else
4059         if (dm->backlight_caps[bl_idx].aux_support)
4060                 return;
4061
4062         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4063         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4064 #endif
4065 }
4066
4067 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4068                                 unsigned int *min, unsigned int *max)
4069 {
4070         if (!caps)
4071                 return 0;
4072
4073         if (caps->aux_support) {
4074                 // Firmware limits are in nits, DC API wants millinits.
4075                 *max = 1000 * caps->aux_max_input_signal;
4076                 *min = 1000 * caps->aux_min_input_signal;
4077         } else {
4078                 // Firmware limits are 8-bit, PWM control is 16-bit.
4079                 *max = 0x101 * caps->max_input_signal;
4080                 *min = 0x101 * caps->min_input_signal;
4081         }
4082         return 1;
4083 }
4084
4085 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4086                                         uint32_t brightness)
4087 {
4088         unsigned int min, max;
4089
4090         if (!get_brightness_range(caps, &min, &max))
4091                 return brightness;
4092
4093         // Rescale 0..255 to min..max
4094         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4095                                        AMDGPU_MAX_BL_LEVEL);
4096 }
4097
4098 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4099                                       uint32_t brightness)
4100 {
4101         unsigned int min, max;
4102
4103         if (!get_brightness_range(caps, &min, &max))
4104                 return brightness;
4105
4106         if (brightness < min)
4107                 return 0;
4108         // Rescale min..max to 0..255
4109         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4110                                  max - min);
4111 }
4112
4113 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4114                                          int bl_idx,
4115                                          u32 user_brightness)
4116 {
4117         struct amdgpu_dm_backlight_caps caps;
4118         struct dc_link *link;
4119         u32 brightness;
4120         bool rc;
4121
4122         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4123         caps = dm->backlight_caps[bl_idx];
4124
4125         dm->brightness[bl_idx] = user_brightness;
4126         /* update scratch register */
4127         if (bl_idx == 0)
4128                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4129         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4130         link = (struct dc_link *)dm->backlight_link[bl_idx];
4131
4132         /* Change brightness based on AUX property */
4133         if (caps.aux_support) {
4134                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4135                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4136                 if (!rc)
4137                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4138         } else {
4139                 rc = dc_link_set_backlight_level(link, brightness, 0);
4140                 if (!rc)
4141                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4142         }
4143
4144         if (rc)
4145                 dm->actual_brightness[bl_idx] = user_brightness;
4146 }
4147
4148 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4149 {
4150         struct amdgpu_display_manager *dm = bl_get_data(bd);
4151         int i;
4152
4153         for (i = 0; i < dm->num_of_edps; i++) {
4154                 if (bd == dm->backlight_dev[i])
4155                         break;
4156         }
4157         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4158                 i = 0;
4159         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4160
4161         return 0;
4162 }
4163
4164 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4165                                          int bl_idx)
4166 {
4167         int ret;
4168         struct amdgpu_dm_backlight_caps caps;
4169         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4170
4171         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4172         caps = dm->backlight_caps[bl_idx];
4173
4174         if (caps.aux_support) {
4175                 u32 avg, peak;
4176                 bool rc;
4177
4178                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4179                 if (!rc)
4180                         return dm->brightness[bl_idx];
4181                 return convert_brightness_to_user(&caps, avg);
4182         }
4183
4184         ret = dc_link_get_backlight_level(link);
4185
4186         if (ret == DC_ERROR_UNEXPECTED)
4187                 return dm->brightness[bl_idx];
4188
4189         return convert_brightness_to_user(&caps, ret);
4190 }
4191
4192 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4193 {
4194         struct amdgpu_display_manager *dm = bl_get_data(bd);
4195         int i;
4196
4197         for (i = 0; i < dm->num_of_edps; i++) {
4198                 if (bd == dm->backlight_dev[i])
4199                         break;
4200         }
4201         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4202                 i = 0;
4203         return amdgpu_dm_backlight_get_level(dm, i);
4204 }
4205
4206 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4207         .options = BL_CORE_SUSPENDRESUME,
4208         .get_brightness = amdgpu_dm_backlight_get_brightness,
4209         .update_status  = amdgpu_dm_backlight_update_status,
4210 };
4211
4212 static void
4213 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4214 {
4215         struct drm_device *drm = aconnector->base.dev;
4216         struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4217         struct backlight_properties props = { 0 };
4218         char bl_name[16];
4219
4220         if (aconnector->bl_idx == -1)
4221                 return;
4222
4223         if (!acpi_video_backlight_use_native()) {
4224                 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4225                 /* Try registering an ACPI video backlight device instead. */
4226                 acpi_video_register_backlight();
4227                 return;
4228         }
4229
4230         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4231         props.brightness = AMDGPU_MAX_BL_LEVEL;
4232         props.type = BACKLIGHT_RAW;
4233
4234         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4235                  drm->primary->index + aconnector->bl_idx);
4236
4237         dm->backlight_dev[aconnector->bl_idx] =
4238                 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4239                                           &amdgpu_dm_backlight_ops, &props);
4240
4241         if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4242                 DRM_ERROR("DM: Backlight registration failed!\n");
4243                 dm->backlight_dev[aconnector->bl_idx] = NULL;
4244         } else
4245                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4246 }
4247
4248 static int initialize_plane(struct amdgpu_display_manager *dm,
4249                             struct amdgpu_mode_info *mode_info, int plane_id,
4250                             enum drm_plane_type plane_type,
4251                             const struct dc_plane_cap *plane_cap)
4252 {
4253         struct drm_plane *plane;
4254         unsigned long possible_crtcs;
4255         int ret = 0;
4256
4257         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4258         if (!plane) {
4259                 DRM_ERROR("KMS: Failed to allocate plane\n");
4260                 return -ENOMEM;
4261         }
4262         plane->type = plane_type;
4263
4264         /*
4265          * HACK: IGT tests expect that the primary plane for a CRTC
4266          * can only have one possible CRTC. Only expose support for
4267          * any CRTC if they're not going to be used as a primary plane
4268          * for a CRTC - like overlay or underlay planes.
4269          */
4270         possible_crtcs = 1 << plane_id;
4271         if (plane_id >= dm->dc->caps.max_streams)
4272                 possible_crtcs = 0xff;
4273
4274         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4275
4276         if (ret) {
4277                 DRM_ERROR("KMS: Failed to initialize plane\n");
4278                 kfree(plane);
4279                 return ret;
4280         }
4281
4282         if (mode_info)
4283                 mode_info->planes[plane_id] = plane;
4284
4285         return ret;
4286 }
4287
4288
4289 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4290                                    struct amdgpu_dm_connector *aconnector)
4291 {
4292         struct dc_link *link = aconnector->dc_link;
4293         int bl_idx = dm->num_of_edps;
4294
4295         if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4296             link->type == dc_connection_none)
4297                 return;
4298
4299         if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4300                 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4301                 return;
4302         }
4303
4304         aconnector->bl_idx = bl_idx;
4305
4306         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4307         dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4308         dm->backlight_link[bl_idx] = link;
4309         dm->num_of_edps++;
4310
4311         update_connector_ext_caps(aconnector);
4312 }
4313
4314 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4315
4316 /*
4317  * In this architecture, the association
4318  * connector -> encoder -> crtc
4319  * id not really requried. The crtc and connector will hold the
4320  * display_index as an abstraction to use with DAL component
4321  *
4322  * Returns 0 on success
4323  */
4324 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4325 {
4326         struct amdgpu_display_manager *dm = &adev->dm;
4327         s32 i;
4328         struct amdgpu_dm_connector *aconnector = NULL;
4329         struct amdgpu_encoder *aencoder = NULL;
4330         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4331         u32 link_cnt;
4332         s32 primary_planes;
4333         enum dc_connection_type new_connection_type = dc_connection_none;
4334         const struct dc_plane_cap *plane;
4335         bool psr_feature_enabled = false;
4336         bool replay_feature_enabled = false;
4337         int max_overlay = dm->dc->caps.max_slave_planes;
4338
4339         dm->display_indexes_num = dm->dc->caps.max_streams;
4340         /* Update the actual used number of crtc */
4341         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4342
4343         amdgpu_dm_set_irq_funcs(adev);
4344
4345         link_cnt = dm->dc->caps.max_links;
4346         if (amdgpu_dm_mode_config_init(dm->adev)) {
4347                 DRM_ERROR("DM: Failed to initialize mode config\n");
4348                 return -EINVAL;
4349         }
4350
4351         /* There is one primary plane per CRTC */
4352         primary_planes = dm->dc->caps.max_streams;
4353         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4354
4355         /*
4356          * Initialize primary planes, implicit planes for legacy IOCTLS.
4357          * Order is reversed to match iteration order in atomic check.
4358          */
4359         for (i = (primary_planes - 1); i >= 0; i--) {
4360                 plane = &dm->dc->caps.planes[i];
4361
4362                 if (initialize_plane(dm, mode_info, i,
4363                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4364                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4365                         goto fail;
4366                 }
4367         }
4368
4369         /*
4370          * Initialize overlay planes, index starting after primary planes.
4371          * These planes have a higher DRM index than the primary planes since
4372          * they should be considered as having a higher z-order.
4373          * Order is reversed to match iteration order in atomic check.
4374          *
4375          * Only support DCN for now, and only expose one so we don't encourage
4376          * userspace to use up all the pipes.
4377          */
4378         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4379                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4380
4381                 /* Do not create overlay if MPO disabled */
4382                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4383                         break;
4384
4385                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4386                         continue;
4387
4388                 if (!plane->pixel_format_support.argb8888)
4389                         continue;
4390
4391                 if (max_overlay-- == 0)
4392                         break;
4393
4394                 if (initialize_plane(dm, NULL, primary_planes + i,
4395                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4396                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4397                         goto fail;
4398                 }
4399         }
4400
4401         for (i = 0; i < dm->dc->caps.max_streams; i++)
4402                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4403                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4404                         goto fail;
4405                 }
4406
4407         /* Use Outbox interrupt */
4408         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4409         case IP_VERSION(3, 0, 0):
4410         case IP_VERSION(3, 1, 2):
4411         case IP_VERSION(3, 1, 3):
4412         case IP_VERSION(3, 1, 4):
4413         case IP_VERSION(3, 1, 5):
4414         case IP_VERSION(3, 1, 6):
4415         case IP_VERSION(3, 2, 0):
4416         case IP_VERSION(3, 2, 1):
4417         case IP_VERSION(2, 1, 0):
4418         case IP_VERSION(3, 5, 0):
4419                 if (register_outbox_irq_handlers(dm->adev)) {
4420                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4421                         goto fail;
4422                 }
4423                 break;
4424         default:
4425                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4426                               amdgpu_ip_version(adev, DCE_HWIP, 0));
4427         }
4428
4429         /* Determine whether to enable PSR support by default. */
4430         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4431                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4432                 case IP_VERSION(3, 1, 2):
4433                 case IP_VERSION(3, 1, 3):
4434                 case IP_VERSION(3, 1, 4):
4435                 case IP_VERSION(3, 1, 5):
4436                 case IP_VERSION(3, 1, 6):
4437                 case IP_VERSION(3, 2, 0):
4438                 case IP_VERSION(3, 2, 1):
4439                 case IP_VERSION(3, 5, 0):
4440                         psr_feature_enabled = true;
4441                         break;
4442                 default:
4443                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4444                         break;
4445                 }
4446         }
4447
4448         if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
4449                 switch (adev->ip_versions[DCE_HWIP][0]) {
4450                 case IP_VERSION(3, 1, 4):
4451                 case IP_VERSION(3, 1, 5):
4452                 case IP_VERSION(3, 1, 6):
4453                 case IP_VERSION(3, 2, 0):
4454                 case IP_VERSION(3, 2, 1):
4455                         replay_feature_enabled = true;
4456                         break;
4457                 default:
4458                         replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK;
4459                         break;
4460                 }
4461         }
4462         /* loops over all connectors on the board */
4463         for (i = 0; i < link_cnt; i++) {
4464                 struct dc_link *link = NULL;
4465
4466                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4467                         DRM_ERROR(
4468                                 "KMS: Cannot support more than %d display indexes\n",
4469                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4470                         continue;
4471                 }
4472
4473                 link = dc_get_link_at_index(dm->dc, i);
4474
4475                 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) {
4476                         struct drm_writeback_connector *wbcon = kzalloc(sizeof(*wbcon), GFP_KERNEL);
4477
4478                         if (!wbcon) {
4479                                 DRM_ERROR("KMS: Failed to allocate writeback connector\n");
4480                                 continue;
4481                         }
4482
4483                         if (amdgpu_dm_wb_connector_init(dm, wbcon)) {
4484                                 DRM_ERROR("KMS: Failed to initialize writeback connector\n");
4485                                 kfree(wbcon);
4486                                 continue;
4487                         }
4488
4489                         link->psr_settings.psr_feature_enabled = false;
4490                         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
4491
4492                         continue;
4493                 }
4494
4495                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4496                 if (!aconnector)
4497                         goto fail;
4498
4499                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4500                 if (!aencoder)
4501                         goto fail;
4502
4503                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4504                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4505                         goto fail;
4506                 }
4507
4508                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4509                         DRM_ERROR("KMS: Failed to initialize connector\n");
4510                         goto fail;
4511                 }
4512
4513                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4514                         DRM_ERROR("KMS: Failed to detect connector\n");
4515
4516                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4517                         emulated_link_detect(link);
4518                         amdgpu_dm_update_connector_after_detect(aconnector);
4519                 } else {
4520                         bool ret = false;
4521
4522                         mutex_lock(&dm->dc_lock);
4523                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4524                         mutex_unlock(&dm->dc_lock);
4525
4526                         if (ret) {
4527                                 amdgpu_dm_update_connector_after_detect(aconnector);
4528                                 setup_backlight_device(dm, aconnector);
4529
4530                                 /*
4531                                  * Disable psr if replay can be enabled
4532                                  */
4533                                 if (replay_feature_enabled && amdgpu_dm_setup_replay(link, aconnector))
4534                                         psr_feature_enabled = false;
4535
4536                                 if (psr_feature_enabled)
4537                                         amdgpu_dm_set_psr_caps(link);
4538
4539                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4540                                  * PSR is also supported.
4541                                  */
4542                                 if (link->psr_settings.psr_feature_enabled)
4543                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4544                         }
4545                 }
4546                 amdgpu_set_panel_orientation(&aconnector->base);
4547         }
4548
4549         /* Software is initialized. Now we can register interrupt handlers. */
4550         switch (adev->asic_type) {
4551 #if defined(CONFIG_DRM_AMD_DC_SI)
4552         case CHIP_TAHITI:
4553         case CHIP_PITCAIRN:
4554         case CHIP_VERDE:
4555         case CHIP_OLAND:
4556                 if (dce60_register_irq_handlers(dm->adev)) {
4557                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4558                         goto fail;
4559                 }
4560                 break;
4561 #endif
4562         case CHIP_BONAIRE:
4563         case CHIP_HAWAII:
4564         case CHIP_KAVERI:
4565         case CHIP_KABINI:
4566         case CHIP_MULLINS:
4567         case CHIP_TONGA:
4568         case CHIP_FIJI:
4569         case CHIP_CARRIZO:
4570         case CHIP_STONEY:
4571         case CHIP_POLARIS11:
4572         case CHIP_POLARIS10:
4573         case CHIP_POLARIS12:
4574         case CHIP_VEGAM:
4575         case CHIP_VEGA10:
4576         case CHIP_VEGA12:
4577         case CHIP_VEGA20:
4578                 if (dce110_register_irq_handlers(dm->adev)) {
4579                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4580                         goto fail;
4581                 }
4582                 break;
4583         default:
4584                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4585                 case IP_VERSION(1, 0, 0):
4586                 case IP_VERSION(1, 0, 1):
4587                 case IP_VERSION(2, 0, 2):
4588                 case IP_VERSION(2, 0, 3):
4589                 case IP_VERSION(2, 0, 0):
4590                 case IP_VERSION(2, 1, 0):
4591                 case IP_VERSION(3, 0, 0):
4592                 case IP_VERSION(3, 0, 2):
4593                 case IP_VERSION(3, 0, 3):
4594                 case IP_VERSION(3, 0, 1):
4595                 case IP_VERSION(3, 1, 2):
4596                 case IP_VERSION(3, 1, 3):
4597                 case IP_VERSION(3, 1, 4):
4598                 case IP_VERSION(3, 1, 5):
4599                 case IP_VERSION(3, 1, 6):
4600                 case IP_VERSION(3, 2, 0):
4601                 case IP_VERSION(3, 2, 1):
4602                 case IP_VERSION(3, 5, 0):
4603                         if (dcn10_register_irq_handlers(dm->adev)) {
4604                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4605                                 goto fail;
4606                         }
4607                         break;
4608                 default:
4609                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4610                                         amdgpu_ip_version(adev, DCE_HWIP, 0));
4611                         goto fail;
4612                 }
4613                 break;
4614         }
4615
4616         return 0;
4617 fail:
4618         kfree(aencoder);
4619         kfree(aconnector);
4620
4621         return -EINVAL;
4622 }
4623
4624 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4625 {
4626         drm_atomic_private_obj_fini(&dm->atomic_obj);
4627 }
4628
4629 /******************************************************************************
4630  * amdgpu_display_funcs functions
4631  *****************************************************************************/
4632
4633 /*
4634  * dm_bandwidth_update - program display watermarks
4635  *
4636  * @adev: amdgpu_device pointer
4637  *
4638  * Calculate and program the display watermarks and line buffer allocation.
4639  */
4640 static void dm_bandwidth_update(struct amdgpu_device *adev)
4641 {
4642         /* TODO: implement later */
4643 }
4644
4645 static const struct amdgpu_display_funcs dm_display_funcs = {
4646         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4647         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4648         .backlight_set_level = NULL, /* never called for DC */
4649         .backlight_get_level = NULL, /* never called for DC */
4650         .hpd_sense = NULL,/* called unconditionally */
4651         .hpd_set_polarity = NULL, /* called unconditionally */
4652         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4653         .page_flip_get_scanoutpos =
4654                 dm_crtc_get_scanoutpos,/* called unconditionally */
4655         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4656         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4657 };
4658
4659 #if defined(CONFIG_DEBUG_KERNEL_DC)
4660
4661 static ssize_t s3_debug_store(struct device *device,
4662                               struct device_attribute *attr,
4663                               const char *buf,
4664                               size_t count)
4665 {
4666         int ret;
4667         int s3_state;
4668         struct drm_device *drm_dev = dev_get_drvdata(device);
4669         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4670
4671         ret = kstrtoint(buf, 0, &s3_state);
4672
4673         if (ret == 0) {
4674                 if (s3_state) {
4675                         dm_resume(adev);
4676                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4677                 } else
4678                         dm_suspend(adev);
4679         }
4680
4681         return ret == 0 ? count : 0;
4682 }
4683
4684 DEVICE_ATTR_WO(s3_debug);
4685
4686 #endif
4687
4688 static int dm_init_microcode(struct amdgpu_device *adev)
4689 {
4690         char *fw_name_dmub;
4691         int r;
4692
4693         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4694         case IP_VERSION(2, 1, 0):
4695                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4696                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4697                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4698                 break;
4699         case IP_VERSION(3, 0, 0):
4700                 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
4701                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4702                 else
4703                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4704                 break;
4705         case IP_VERSION(3, 0, 1):
4706                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4707                 break;
4708         case IP_VERSION(3, 0, 2):
4709                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4710                 break;
4711         case IP_VERSION(3, 0, 3):
4712                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4713                 break;
4714         case IP_VERSION(3, 1, 2):
4715         case IP_VERSION(3, 1, 3):
4716                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4717                 break;
4718         case IP_VERSION(3, 1, 4):
4719                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4720                 break;
4721         case IP_VERSION(3, 1, 5):
4722                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4723                 break;
4724         case IP_VERSION(3, 1, 6):
4725                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4726                 break;
4727         case IP_VERSION(3, 2, 0):
4728                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4729                 break;
4730         case IP_VERSION(3, 2, 1):
4731                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4732                 break;
4733         case IP_VERSION(3, 5, 0):
4734                 fw_name_dmub = FIRMWARE_DCN_35_DMUB;
4735                 break;
4736         default:
4737                 /* ASIC doesn't support DMUB. */
4738                 return 0;
4739         }
4740         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4741         return r;
4742 }
4743
4744 static int dm_early_init(void *handle)
4745 {
4746         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4747         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4748         struct atom_context *ctx = mode_info->atom_context;
4749         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4750         u16 data_offset;
4751
4752         /* if there is no object header, skip DM */
4753         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4754                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4755                 dev_info(adev->dev, "No object header, skipping DM\n");
4756                 return -ENOENT;
4757         }
4758
4759         switch (adev->asic_type) {
4760 #if defined(CONFIG_DRM_AMD_DC_SI)
4761         case CHIP_TAHITI:
4762         case CHIP_PITCAIRN:
4763         case CHIP_VERDE:
4764                 adev->mode_info.num_crtc = 6;
4765                 adev->mode_info.num_hpd = 6;
4766                 adev->mode_info.num_dig = 6;
4767                 break;
4768         case CHIP_OLAND:
4769                 adev->mode_info.num_crtc = 2;
4770                 adev->mode_info.num_hpd = 2;
4771                 adev->mode_info.num_dig = 2;
4772                 break;
4773 #endif
4774         case CHIP_BONAIRE:
4775         case CHIP_HAWAII:
4776                 adev->mode_info.num_crtc = 6;
4777                 adev->mode_info.num_hpd = 6;
4778                 adev->mode_info.num_dig = 6;
4779                 break;
4780         case CHIP_KAVERI:
4781                 adev->mode_info.num_crtc = 4;
4782                 adev->mode_info.num_hpd = 6;
4783                 adev->mode_info.num_dig = 7;
4784                 break;
4785         case CHIP_KABINI:
4786         case CHIP_MULLINS:
4787                 adev->mode_info.num_crtc = 2;
4788                 adev->mode_info.num_hpd = 6;
4789                 adev->mode_info.num_dig = 6;
4790                 break;
4791         case CHIP_FIJI:
4792         case CHIP_TONGA:
4793                 adev->mode_info.num_crtc = 6;
4794                 adev->mode_info.num_hpd = 6;
4795                 adev->mode_info.num_dig = 7;
4796                 break;
4797         case CHIP_CARRIZO:
4798                 adev->mode_info.num_crtc = 3;
4799                 adev->mode_info.num_hpd = 6;
4800                 adev->mode_info.num_dig = 9;
4801                 break;
4802         case CHIP_STONEY:
4803                 adev->mode_info.num_crtc = 2;
4804                 adev->mode_info.num_hpd = 6;
4805                 adev->mode_info.num_dig = 9;
4806                 break;
4807         case CHIP_POLARIS11:
4808         case CHIP_POLARIS12:
4809                 adev->mode_info.num_crtc = 5;
4810                 adev->mode_info.num_hpd = 5;
4811                 adev->mode_info.num_dig = 5;
4812                 break;
4813         case CHIP_POLARIS10:
4814         case CHIP_VEGAM:
4815                 adev->mode_info.num_crtc = 6;
4816                 adev->mode_info.num_hpd = 6;
4817                 adev->mode_info.num_dig = 6;
4818                 break;
4819         case CHIP_VEGA10:
4820         case CHIP_VEGA12:
4821         case CHIP_VEGA20:
4822                 adev->mode_info.num_crtc = 6;
4823                 adev->mode_info.num_hpd = 6;
4824                 adev->mode_info.num_dig = 6;
4825                 break;
4826         default:
4827
4828                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4829                 case IP_VERSION(2, 0, 2):
4830                 case IP_VERSION(3, 0, 0):
4831                         adev->mode_info.num_crtc = 6;
4832                         adev->mode_info.num_hpd = 6;
4833                         adev->mode_info.num_dig = 6;
4834                         break;
4835                 case IP_VERSION(2, 0, 0):
4836                 case IP_VERSION(3, 0, 2):
4837                         adev->mode_info.num_crtc = 5;
4838                         adev->mode_info.num_hpd = 5;
4839                         adev->mode_info.num_dig = 5;
4840                         break;
4841                 case IP_VERSION(2, 0, 3):
4842                 case IP_VERSION(3, 0, 3):
4843                         adev->mode_info.num_crtc = 2;
4844                         adev->mode_info.num_hpd = 2;
4845                         adev->mode_info.num_dig = 2;
4846                         break;
4847                 case IP_VERSION(1, 0, 0):
4848                 case IP_VERSION(1, 0, 1):
4849                 case IP_VERSION(3, 0, 1):
4850                 case IP_VERSION(2, 1, 0):
4851                 case IP_VERSION(3, 1, 2):
4852                 case IP_VERSION(3, 1, 3):
4853                 case IP_VERSION(3, 1, 4):
4854                 case IP_VERSION(3, 1, 5):
4855                 case IP_VERSION(3, 1, 6):
4856                 case IP_VERSION(3, 2, 0):
4857                 case IP_VERSION(3, 2, 1):
4858                 case IP_VERSION(3, 5, 0):
4859                         adev->mode_info.num_crtc = 4;
4860                         adev->mode_info.num_hpd = 4;
4861                         adev->mode_info.num_dig = 4;
4862                         break;
4863                 default:
4864                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4865                                         amdgpu_ip_version(adev, DCE_HWIP, 0));
4866                         return -EINVAL;
4867                 }
4868                 break;
4869         }
4870
4871         if (adev->mode_info.funcs == NULL)
4872                 adev->mode_info.funcs = &dm_display_funcs;
4873
4874         /*
4875          * Note: Do NOT change adev->audio_endpt_rreg and
4876          * adev->audio_endpt_wreg because they are initialised in
4877          * amdgpu_device_init()
4878          */
4879 #if defined(CONFIG_DEBUG_KERNEL_DC)
4880         device_create_file(
4881                 adev_to_drm(adev)->dev,
4882                 &dev_attr_s3_debug);
4883 #endif
4884         adev->dc_enabled = true;
4885
4886         return dm_init_microcode(adev);
4887 }
4888
4889 static bool modereset_required(struct drm_crtc_state *crtc_state)
4890 {
4891         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4892 }
4893
4894 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4895 {
4896         drm_encoder_cleanup(encoder);
4897         kfree(encoder);
4898 }
4899
4900 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4901         .destroy = amdgpu_dm_encoder_destroy,
4902 };
4903
4904 static int
4905 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4906                             const enum surface_pixel_format format,
4907                             enum dc_color_space *color_space)
4908 {
4909         bool full_range;
4910
4911         *color_space = COLOR_SPACE_SRGB;
4912
4913         /* DRM color properties only affect non-RGB formats. */
4914         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4915                 return 0;
4916
4917         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4918
4919         switch (plane_state->color_encoding) {
4920         case DRM_COLOR_YCBCR_BT601:
4921                 if (full_range)
4922                         *color_space = COLOR_SPACE_YCBCR601;
4923                 else
4924                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4925                 break;
4926
4927         case DRM_COLOR_YCBCR_BT709:
4928                 if (full_range)
4929                         *color_space = COLOR_SPACE_YCBCR709;
4930                 else
4931                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4932                 break;
4933
4934         case DRM_COLOR_YCBCR_BT2020:
4935                 if (full_range)
4936                         *color_space = COLOR_SPACE_2020_YCBCR;
4937                 else
4938                         return -EINVAL;
4939                 break;
4940
4941         default:
4942                 return -EINVAL;
4943         }
4944
4945         return 0;
4946 }
4947
4948 static int
4949 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4950                             const struct drm_plane_state *plane_state,
4951                             const u64 tiling_flags,
4952                             struct dc_plane_info *plane_info,
4953                             struct dc_plane_address *address,
4954                             bool tmz_surface,
4955                             bool force_disable_dcc)
4956 {
4957         const struct drm_framebuffer *fb = plane_state->fb;
4958         const struct amdgpu_framebuffer *afb =
4959                 to_amdgpu_framebuffer(plane_state->fb);
4960         int ret;
4961
4962         memset(plane_info, 0, sizeof(*plane_info));
4963
4964         switch (fb->format->format) {
4965         case DRM_FORMAT_C8:
4966                 plane_info->format =
4967                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4968                 break;
4969         case DRM_FORMAT_RGB565:
4970                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4971                 break;
4972         case DRM_FORMAT_XRGB8888:
4973         case DRM_FORMAT_ARGB8888:
4974                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4975                 break;
4976         case DRM_FORMAT_XRGB2101010:
4977         case DRM_FORMAT_ARGB2101010:
4978                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4979                 break;
4980         case DRM_FORMAT_XBGR2101010:
4981         case DRM_FORMAT_ABGR2101010:
4982                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4983                 break;
4984         case DRM_FORMAT_XBGR8888:
4985         case DRM_FORMAT_ABGR8888:
4986                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4987                 break;
4988         case DRM_FORMAT_NV21:
4989                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4990                 break;
4991         case DRM_FORMAT_NV12:
4992                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4993                 break;
4994         case DRM_FORMAT_P010:
4995                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4996                 break;
4997         case DRM_FORMAT_XRGB16161616F:
4998         case DRM_FORMAT_ARGB16161616F:
4999                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
5000                 break;
5001         case DRM_FORMAT_XBGR16161616F:
5002         case DRM_FORMAT_ABGR16161616F:
5003                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
5004                 break;
5005         case DRM_FORMAT_XRGB16161616:
5006         case DRM_FORMAT_ARGB16161616:
5007                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
5008                 break;
5009         case DRM_FORMAT_XBGR16161616:
5010         case DRM_FORMAT_ABGR16161616:
5011                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
5012                 break;
5013         default:
5014                 DRM_ERROR(
5015                         "Unsupported screen format %p4cc\n",
5016                         &fb->format->format);
5017                 return -EINVAL;
5018         }
5019
5020         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
5021         case DRM_MODE_ROTATE_0:
5022                 plane_info->rotation = ROTATION_ANGLE_0;
5023                 break;
5024         case DRM_MODE_ROTATE_90:
5025                 plane_info->rotation = ROTATION_ANGLE_90;
5026                 break;
5027         case DRM_MODE_ROTATE_180:
5028                 plane_info->rotation = ROTATION_ANGLE_180;
5029                 break;
5030         case DRM_MODE_ROTATE_270:
5031                 plane_info->rotation = ROTATION_ANGLE_270;
5032                 break;
5033         default:
5034                 plane_info->rotation = ROTATION_ANGLE_0;
5035                 break;
5036         }
5037
5038
5039         plane_info->visible = true;
5040         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
5041
5042         plane_info->layer_index = plane_state->normalized_zpos;
5043
5044         ret = fill_plane_color_attributes(plane_state, plane_info->format,
5045                                           &plane_info->color_space);
5046         if (ret)
5047                 return ret;
5048
5049         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
5050                                            plane_info->rotation, tiling_flags,
5051                                            &plane_info->tiling_info,
5052                                            &plane_info->plane_size,
5053                                            &plane_info->dcc, address,
5054                                            tmz_surface, force_disable_dcc);
5055         if (ret)
5056                 return ret;
5057
5058         amdgpu_dm_plane_fill_blending_from_plane_state(
5059                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
5060                 &plane_info->global_alpha, &plane_info->global_alpha_value);
5061
5062         return 0;
5063 }
5064
5065 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5066                                     struct dc_plane_state *dc_plane_state,
5067                                     struct drm_plane_state *plane_state,
5068                                     struct drm_crtc_state *crtc_state)
5069 {
5070         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5071         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5072         struct dc_scaling_info scaling_info;
5073         struct dc_plane_info plane_info;
5074         int ret;
5075         bool force_disable_dcc = false;
5076
5077         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5078         if (ret)
5079                 return ret;
5080
5081         dc_plane_state->src_rect = scaling_info.src_rect;
5082         dc_plane_state->dst_rect = scaling_info.dst_rect;
5083         dc_plane_state->clip_rect = scaling_info.clip_rect;
5084         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5085
5086         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5087         ret = fill_dc_plane_info_and_addr(adev, plane_state,
5088                                           afb->tiling_flags,
5089                                           &plane_info,
5090                                           &dc_plane_state->address,
5091                                           afb->tmz_surface,
5092                                           force_disable_dcc);
5093         if (ret)
5094                 return ret;
5095
5096         dc_plane_state->format = plane_info.format;
5097         dc_plane_state->color_space = plane_info.color_space;
5098         dc_plane_state->format = plane_info.format;
5099         dc_plane_state->plane_size = plane_info.plane_size;
5100         dc_plane_state->rotation = plane_info.rotation;
5101         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5102         dc_plane_state->stereo_format = plane_info.stereo_format;
5103         dc_plane_state->tiling_info = plane_info.tiling_info;
5104         dc_plane_state->visible = plane_info.visible;
5105         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5106         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5107         dc_plane_state->global_alpha = plane_info.global_alpha;
5108         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5109         dc_plane_state->dcc = plane_info.dcc;
5110         dc_plane_state->layer_index = plane_info.layer_index;
5111         dc_plane_state->flip_int_enabled = true;
5112
5113         /*
5114          * Always set input transfer function, since plane state is refreshed
5115          * every time.
5116          */
5117         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5118         if (ret)
5119                 return ret;
5120
5121         return 0;
5122 }
5123
5124 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5125                                       struct rect *dirty_rect, int32_t x,
5126                                       s32 y, s32 width, s32 height,
5127                                       int *i, bool ffu)
5128 {
5129         WARN_ON(*i >= DC_MAX_DIRTY_RECTS);
5130
5131         dirty_rect->x = x;
5132         dirty_rect->y = y;
5133         dirty_rect->width = width;
5134         dirty_rect->height = height;
5135
5136         if (ffu)
5137                 drm_dbg(plane->dev,
5138                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5139                         plane->base.id, width, height);
5140         else
5141                 drm_dbg(plane->dev,
5142                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5143                         plane->base.id, x, y, width, height);
5144
5145         (*i)++;
5146 }
5147
5148 /**
5149  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5150  *
5151  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5152  *         remote fb
5153  * @old_plane_state: Old state of @plane
5154  * @new_plane_state: New state of @plane
5155  * @crtc_state: New state of CRTC connected to the @plane
5156  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5157  * @dirty_regions_changed: dirty regions changed
5158  *
5159  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5160  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5161  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5162  * amdgpu_dm's.
5163  *
5164  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5165  * plane with regions that require flushing to the eDP remote buffer. In
5166  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5167  * implicitly provide damage clips without any client support via the plane
5168  * bounds.
5169  */
5170 static void fill_dc_dirty_rects(struct drm_plane *plane,
5171                                 struct drm_plane_state *old_plane_state,
5172                                 struct drm_plane_state *new_plane_state,
5173                                 struct drm_crtc_state *crtc_state,
5174                                 struct dc_flip_addrs *flip_addrs,
5175                                 bool *dirty_regions_changed)
5176 {
5177         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5178         struct rect *dirty_rects = flip_addrs->dirty_rects;
5179         u32 num_clips;
5180         struct drm_mode_rect *clips;
5181         bool bb_changed;
5182         bool fb_changed;
5183         u32 i = 0;
5184         *dirty_regions_changed = false;
5185
5186         /*
5187          * Cursor plane has it's own dirty rect update interface. See
5188          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5189          */
5190         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5191                 return;
5192
5193         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5194         clips = drm_plane_get_damage_clips(new_plane_state);
5195
5196         if (!dm_crtc_state->mpo_requested) {
5197                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5198                         goto ffu;
5199
5200                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5201                         fill_dc_dirty_rect(new_plane_state->plane,
5202                                            &dirty_rects[flip_addrs->dirty_rect_count],
5203                                            clips->x1, clips->y1,
5204                                            clips->x2 - clips->x1, clips->y2 - clips->y1,
5205                                            &flip_addrs->dirty_rect_count,
5206                                            false);
5207                 return;
5208         }
5209
5210         /*
5211          * MPO is requested. Add entire plane bounding box to dirty rects if
5212          * flipped to or damaged.
5213          *
5214          * If plane is moved or resized, also add old bounding box to dirty
5215          * rects.
5216          */
5217         fb_changed = old_plane_state->fb->base.id !=
5218                      new_plane_state->fb->base.id;
5219         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5220                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5221                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5222                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5223
5224         drm_dbg(plane->dev,
5225                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5226                 new_plane_state->plane->base.id,
5227                 bb_changed, fb_changed, num_clips);
5228
5229         *dirty_regions_changed = bb_changed;
5230
5231         if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS)
5232                 goto ffu;
5233
5234         if (bb_changed) {
5235                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5236                                    new_plane_state->crtc_x,
5237                                    new_plane_state->crtc_y,
5238                                    new_plane_state->crtc_w,
5239                                    new_plane_state->crtc_h, &i, false);
5240
5241                 /* Add old plane bounding-box if plane is moved or resized */
5242                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5243                                    old_plane_state->crtc_x,
5244                                    old_plane_state->crtc_y,
5245                                    old_plane_state->crtc_w,
5246                                    old_plane_state->crtc_h, &i, false);
5247         }
5248
5249         if (num_clips) {
5250                 for (; i < num_clips; clips++)
5251                         fill_dc_dirty_rect(new_plane_state->plane,
5252                                            &dirty_rects[i], clips->x1,
5253                                            clips->y1, clips->x2 - clips->x1,
5254                                            clips->y2 - clips->y1, &i, false);
5255         } else if (fb_changed && !bb_changed) {
5256                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5257                                    new_plane_state->crtc_x,
5258                                    new_plane_state->crtc_y,
5259                                    new_plane_state->crtc_w,
5260                                    new_plane_state->crtc_h, &i, false);
5261         }
5262
5263         flip_addrs->dirty_rect_count = i;
5264         return;
5265
5266 ffu:
5267         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5268                            dm_crtc_state->base.mode.crtc_hdisplay,
5269                            dm_crtc_state->base.mode.crtc_vdisplay,
5270                            &flip_addrs->dirty_rect_count, true);
5271 }
5272
5273 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5274                                            const struct dm_connector_state *dm_state,
5275                                            struct dc_stream_state *stream)
5276 {
5277         enum amdgpu_rmx_type rmx_type;
5278
5279         struct rect src = { 0 }; /* viewport in composition space*/
5280         struct rect dst = { 0 }; /* stream addressable area */
5281
5282         /* no mode. nothing to be done */
5283         if (!mode)
5284                 return;
5285
5286         /* Full screen scaling by default */
5287         src.width = mode->hdisplay;
5288         src.height = mode->vdisplay;
5289         dst.width = stream->timing.h_addressable;
5290         dst.height = stream->timing.v_addressable;
5291
5292         if (dm_state) {
5293                 rmx_type = dm_state->scaling;
5294                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5295                         if (src.width * dst.height <
5296                                         src.height * dst.width) {
5297                                 /* height needs less upscaling/more downscaling */
5298                                 dst.width = src.width *
5299                                                 dst.height / src.height;
5300                         } else {
5301                                 /* width needs less upscaling/more downscaling */
5302                                 dst.height = src.height *
5303                                                 dst.width / src.width;
5304                         }
5305                 } else if (rmx_type == RMX_CENTER) {
5306                         dst = src;
5307                 }
5308
5309                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5310                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5311
5312                 if (dm_state->underscan_enable) {
5313                         dst.x += dm_state->underscan_hborder / 2;
5314                         dst.y += dm_state->underscan_vborder / 2;
5315                         dst.width -= dm_state->underscan_hborder;
5316                         dst.height -= dm_state->underscan_vborder;
5317                 }
5318         }
5319
5320         stream->src = src;
5321         stream->dst = dst;
5322
5323         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5324                       dst.x, dst.y, dst.width, dst.height);
5325
5326 }
5327
5328 static enum dc_color_depth
5329 convert_color_depth_from_display_info(const struct drm_connector *connector,
5330                                       bool is_y420, int requested_bpc)
5331 {
5332         u8 bpc;
5333
5334         if (is_y420) {
5335                 bpc = 8;
5336
5337                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5338                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5339                         bpc = 16;
5340                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5341                         bpc = 12;
5342                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5343                         bpc = 10;
5344         } else {
5345                 bpc = (uint8_t)connector->display_info.bpc;
5346                 /* Assume 8 bpc by default if no bpc is specified. */
5347                 bpc = bpc ? bpc : 8;
5348         }
5349
5350         if (requested_bpc > 0) {
5351                 /*
5352                  * Cap display bpc based on the user requested value.
5353                  *
5354                  * The value for state->max_bpc may not correctly updated
5355                  * depending on when the connector gets added to the state
5356                  * or if this was called outside of atomic check, so it
5357                  * can't be used directly.
5358                  */
5359                 bpc = min_t(u8, bpc, requested_bpc);
5360
5361                 /* Round down to the nearest even number. */
5362                 bpc = bpc - (bpc & 1);
5363         }
5364
5365         switch (bpc) {
5366         case 0:
5367                 /*
5368                  * Temporary Work around, DRM doesn't parse color depth for
5369                  * EDID revision before 1.4
5370                  * TODO: Fix edid parsing
5371                  */
5372                 return COLOR_DEPTH_888;
5373         case 6:
5374                 return COLOR_DEPTH_666;
5375         case 8:
5376                 return COLOR_DEPTH_888;
5377         case 10:
5378                 return COLOR_DEPTH_101010;
5379         case 12:
5380                 return COLOR_DEPTH_121212;
5381         case 14:
5382                 return COLOR_DEPTH_141414;
5383         case 16:
5384                 return COLOR_DEPTH_161616;
5385         default:
5386                 return COLOR_DEPTH_UNDEFINED;
5387         }
5388 }
5389
5390 static enum dc_aspect_ratio
5391 get_aspect_ratio(const struct drm_display_mode *mode_in)
5392 {
5393         /* 1-1 mapping, since both enums follow the HDMI spec. */
5394         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5395 }
5396
5397 static enum dc_color_space
5398 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
5399                        const struct drm_connector_state *connector_state)
5400 {
5401         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5402
5403         switch (connector_state->colorspace) {
5404         case DRM_MODE_COLORIMETRY_BT601_YCC:
5405                 if (dc_crtc_timing->flags.Y_ONLY)
5406                         color_space = COLOR_SPACE_YCBCR601_LIMITED;
5407                 else
5408                         color_space = COLOR_SPACE_YCBCR601;
5409                 break;
5410         case DRM_MODE_COLORIMETRY_BT709_YCC:
5411                 if (dc_crtc_timing->flags.Y_ONLY)
5412                         color_space = COLOR_SPACE_YCBCR709_LIMITED;
5413                 else
5414                         color_space = COLOR_SPACE_YCBCR709;
5415                 break;
5416         case DRM_MODE_COLORIMETRY_OPRGB:
5417                 color_space = COLOR_SPACE_ADOBERGB;
5418                 break;
5419         case DRM_MODE_COLORIMETRY_BT2020_RGB:
5420         case DRM_MODE_COLORIMETRY_BT2020_YCC:
5421                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
5422                         color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
5423                 else
5424                         color_space = COLOR_SPACE_2020_YCBCR;
5425                 break;
5426         case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
5427         default:
5428                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
5429                         color_space = COLOR_SPACE_SRGB;
5430                 /*
5431                  * 27030khz is the separation point between HDTV and SDTV
5432                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5433                  * respectively
5434                  */
5435                 } else if (dc_crtc_timing->pix_clk_100hz > 270300) {
5436                         if (dc_crtc_timing->flags.Y_ONLY)
5437                                 color_space =
5438                                         COLOR_SPACE_YCBCR709_LIMITED;
5439                         else
5440                                 color_space = COLOR_SPACE_YCBCR709;
5441                 } else {
5442                         if (dc_crtc_timing->flags.Y_ONLY)
5443                                 color_space =
5444                                         COLOR_SPACE_YCBCR601_LIMITED;
5445                         else
5446                                 color_space = COLOR_SPACE_YCBCR601;
5447                 }
5448                 break;
5449         }
5450
5451         return color_space;
5452 }
5453
5454 static enum display_content_type
5455 get_output_content_type(const struct drm_connector_state *connector_state)
5456 {
5457         switch (connector_state->content_type) {
5458         default:
5459         case DRM_MODE_CONTENT_TYPE_NO_DATA:
5460                 return DISPLAY_CONTENT_TYPE_NO_DATA;
5461         case DRM_MODE_CONTENT_TYPE_GRAPHICS:
5462                 return DISPLAY_CONTENT_TYPE_GRAPHICS;
5463         case DRM_MODE_CONTENT_TYPE_PHOTO:
5464                 return DISPLAY_CONTENT_TYPE_PHOTO;
5465         case DRM_MODE_CONTENT_TYPE_CINEMA:
5466                 return DISPLAY_CONTENT_TYPE_CINEMA;
5467         case DRM_MODE_CONTENT_TYPE_GAME:
5468                 return DISPLAY_CONTENT_TYPE_GAME;
5469         }
5470 }
5471
5472 static bool adjust_colour_depth_from_display_info(
5473         struct dc_crtc_timing *timing_out,
5474         const struct drm_display_info *info)
5475 {
5476         enum dc_color_depth depth = timing_out->display_color_depth;
5477         int normalized_clk;
5478
5479         do {
5480                 normalized_clk = timing_out->pix_clk_100hz / 10;
5481                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5482                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5483                         normalized_clk /= 2;
5484                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5485                 switch (depth) {
5486                 case COLOR_DEPTH_888:
5487                         break;
5488                 case COLOR_DEPTH_101010:
5489                         normalized_clk = (normalized_clk * 30) / 24;
5490                         break;
5491                 case COLOR_DEPTH_121212:
5492                         normalized_clk = (normalized_clk * 36) / 24;
5493                         break;
5494                 case COLOR_DEPTH_161616:
5495                         normalized_clk = (normalized_clk * 48) / 24;
5496                         break;
5497                 default:
5498                         /* The above depths are the only ones valid for HDMI. */
5499                         return false;
5500                 }
5501                 if (normalized_clk <= info->max_tmds_clock) {
5502                         timing_out->display_color_depth = depth;
5503                         return true;
5504                 }
5505         } while (--depth > COLOR_DEPTH_666);
5506         return false;
5507 }
5508
5509 static void fill_stream_properties_from_drm_display_mode(
5510         struct dc_stream_state *stream,
5511         const struct drm_display_mode *mode_in,
5512         const struct drm_connector *connector,
5513         const struct drm_connector_state *connector_state,
5514         const struct dc_stream_state *old_stream,
5515         int requested_bpc)
5516 {
5517         struct dc_crtc_timing *timing_out = &stream->timing;
5518         const struct drm_display_info *info = &connector->display_info;
5519         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5520         struct hdmi_vendor_infoframe hv_frame;
5521         struct hdmi_avi_infoframe avi_frame;
5522
5523         memset(&hv_frame, 0, sizeof(hv_frame));
5524         memset(&avi_frame, 0, sizeof(avi_frame));
5525
5526         timing_out->h_border_left = 0;
5527         timing_out->h_border_right = 0;
5528         timing_out->v_border_top = 0;
5529         timing_out->v_border_bottom = 0;
5530         /* TODO: un-hardcode */
5531         if (drm_mode_is_420_only(info, mode_in)
5532                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5533                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5534         else if (drm_mode_is_420_also(info, mode_in)
5535                         && aconnector->force_yuv420_output)
5536                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5537         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5538                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5539                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5540         else
5541                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5542
5543         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5544         timing_out->display_color_depth = convert_color_depth_from_display_info(
5545                 connector,
5546                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5547                 requested_bpc);
5548         timing_out->scan_type = SCANNING_TYPE_NODATA;
5549         timing_out->hdmi_vic = 0;
5550
5551         if (old_stream) {
5552                 timing_out->vic = old_stream->timing.vic;
5553                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5554                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5555         } else {
5556                 timing_out->vic = drm_match_cea_mode(mode_in);
5557                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5558                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5559                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5560                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5561         }
5562
5563         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5564                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5565                 timing_out->vic = avi_frame.video_code;
5566                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5567                 timing_out->hdmi_vic = hv_frame.vic;
5568         }
5569
5570         if (is_freesync_video_mode(mode_in, aconnector)) {
5571                 timing_out->h_addressable = mode_in->hdisplay;
5572                 timing_out->h_total = mode_in->htotal;
5573                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5574                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5575                 timing_out->v_total = mode_in->vtotal;
5576                 timing_out->v_addressable = mode_in->vdisplay;
5577                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5578                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5579                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5580         } else {
5581                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5582                 timing_out->h_total = mode_in->crtc_htotal;
5583                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5584                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5585                 timing_out->v_total = mode_in->crtc_vtotal;
5586                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5587                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5588                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5589                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5590         }
5591
5592         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5593
5594         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5595         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5596         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5597                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5598                     drm_mode_is_420_also(info, mode_in) &&
5599                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5600                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5601                         adjust_colour_depth_from_display_info(timing_out, info);
5602                 }
5603         }
5604
5605         stream->output_color_space = get_output_color_space(timing_out, connector_state);
5606         stream->content_type = get_output_content_type(connector_state);
5607 }
5608
5609 static void fill_audio_info(struct audio_info *audio_info,
5610                             const struct drm_connector *drm_connector,
5611                             const struct dc_sink *dc_sink)
5612 {
5613         int i = 0;
5614         int cea_revision = 0;
5615         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5616
5617         audio_info->manufacture_id = edid_caps->manufacturer_id;
5618         audio_info->product_id = edid_caps->product_id;
5619
5620         cea_revision = drm_connector->display_info.cea_rev;
5621
5622         strscpy(audio_info->display_name,
5623                 edid_caps->display_name,
5624                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5625
5626         if (cea_revision >= 3) {
5627                 audio_info->mode_count = edid_caps->audio_mode_count;
5628
5629                 for (i = 0; i < audio_info->mode_count; ++i) {
5630                         audio_info->modes[i].format_code =
5631                                         (enum audio_format_code)
5632                                         (edid_caps->audio_modes[i].format_code);
5633                         audio_info->modes[i].channel_count =
5634                                         edid_caps->audio_modes[i].channel_count;
5635                         audio_info->modes[i].sample_rates.all =
5636                                         edid_caps->audio_modes[i].sample_rate;
5637                         audio_info->modes[i].sample_size =
5638                                         edid_caps->audio_modes[i].sample_size;
5639                 }
5640         }
5641
5642         audio_info->flags.all = edid_caps->speaker_flags;
5643
5644         /* TODO: We only check for the progressive mode, check for interlace mode too */
5645         if (drm_connector->latency_present[0]) {
5646                 audio_info->video_latency = drm_connector->video_latency[0];
5647                 audio_info->audio_latency = drm_connector->audio_latency[0];
5648         }
5649
5650         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5651
5652 }
5653
5654 static void
5655 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5656                                       struct drm_display_mode *dst_mode)
5657 {
5658         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5659         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5660         dst_mode->crtc_clock = src_mode->crtc_clock;
5661         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5662         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5663         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5664         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5665         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5666         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5667         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5668         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5669         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5670         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5671         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5672 }
5673
5674 static void
5675 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5676                                         const struct drm_display_mode *native_mode,
5677                                         bool scale_enabled)
5678 {
5679         if (scale_enabled) {
5680                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5681         } else if (native_mode->clock == drm_mode->clock &&
5682                         native_mode->htotal == drm_mode->htotal &&
5683                         native_mode->vtotal == drm_mode->vtotal) {
5684                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5685         } else {
5686                 /* no scaling nor amdgpu inserted, no need to patch */
5687         }
5688 }
5689
5690 static struct dc_sink *
5691 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5692 {
5693         struct dc_sink_init_data sink_init_data = { 0 };
5694         struct dc_sink *sink = NULL;
5695
5696         sink_init_data.link = aconnector->dc_link;
5697         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5698
5699         sink = dc_sink_create(&sink_init_data);
5700         if (!sink) {
5701                 DRM_ERROR("Failed to create sink!\n");
5702                 return NULL;
5703         }
5704         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5705
5706         return sink;
5707 }
5708
5709 static void set_multisync_trigger_params(
5710                 struct dc_stream_state *stream)
5711 {
5712         struct dc_stream_state *master = NULL;
5713
5714         if (stream->triggered_crtc_reset.enabled) {
5715                 master = stream->triggered_crtc_reset.event_source;
5716                 stream->triggered_crtc_reset.event =
5717                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5718                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5719                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5720         }
5721 }
5722
5723 static void set_master_stream(struct dc_stream_state *stream_set[],
5724                               int stream_count)
5725 {
5726         int j, highest_rfr = 0, master_stream = 0;
5727
5728         for (j = 0;  j < stream_count; j++) {
5729                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5730                         int refresh_rate = 0;
5731
5732                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5733                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5734                         if (refresh_rate > highest_rfr) {
5735                                 highest_rfr = refresh_rate;
5736                                 master_stream = j;
5737                         }
5738                 }
5739         }
5740         for (j = 0;  j < stream_count; j++) {
5741                 if (stream_set[j])
5742                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5743         }
5744 }
5745
5746 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5747 {
5748         int i = 0;
5749         struct dc_stream_state *stream;
5750
5751         if (context->stream_count < 2)
5752                 return;
5753         for (i = 0; i < context->stream_count ; i++) {
5754                 if (!context->streams[i])
5755                         continue;
5756                 /*
5757                  * TODO: add a function to read AMD VSDB bits and set
5758                  * crtc_sync_master.multi_sync_enabled flag
5759                  * For now it's set to false
5760                  */
5761         }
5762
5763         set_master_stream(context->streams, context->stream_count);
5764
5765         for (i = 0; i < context->stream_count ; i++) {
5766                 stream = context->streams[i];
5767
5768                 if (!stream)
5769                         continue;
5770
5771                 set_multisync_trigger_params(stream);
5772         }
5773 }
5774
5775 /**
5776  * DOC: FreeSync Video
5777  *
5778  * When a userspace application wants to play a video, the content follows a
5779  * standard format definition that usually specifies the FPS for that format.
5780  * The below list illustrates some video format and the expected FPS,
5781  * respectively:
5782  *
5783  * - TV/NTSC (23.976 FPS)
5784  * - Cinema (24 FPS)
5785  * - TV/PAL (25 FPS)
5786  * - TV/NTSC (29.97 FPS)
5787  * - TV/NTSC (30 FPS)
5788  * - Cinema HFR (48 FPS)
5789  * - TV/PAL (50 FPS)
5790  * - Commonly used (60 FPS)
5791  * - Multiples of 24 (48,72,96 FPS)
5792  *
5793  * The list of standards video format is not huge and can be added to the
5794  * connector modeset list beforehand. With that, userspace can leverage
5795  * FreeSync to extends the front porch in order to attain the target refresh
5796  * rate. Such a switch will happen seamlessly, without screen blanking or
5797  * reprogramming of the output in any other way. If the userspace requests a
5798  * modesetting change compatible with FreeSync modes that only differ in the
5799  * refresh rate, DC will skip the full update and avoid blink during the
5800  * transition. For example, the video player can change the modesetting from
5801  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5802  * causing any display blink. This same concept can be applied to a mode
5803  * setting change.
5804  */
5805 static struct drm_display_mode *
5806 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5807                 bool use_probed_modes)
5808 {
5809         struct drm_display_mode *m, *m_pref = NULL;
5810         u16 current_refresh, highest_refresh;
5811         struct list_head *list_head = use_probed_modes ?
5812                 &aconnector->base.probed_modes :
5813                 &aconnector->base.modes;
5814
5815         if (aconnector->freesync_vid_base.clock != 0)
5816                 return &aconnector->freesync_vid_base;
5817
5818         /* Find the preferred mode */
5819         list_for_each_entry(m, list_head, head) {
5820                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5821                         m_pref = m;
5822                         break;
5823                 }
5824         }
5825
5826         if (!m_pref) {
5827                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5828                 m_pref = list_first_entry_or_null(
5829                                 &aconnector->base.modes, struct drm_display_mode, head);
5830                 if (!m_pref) {
5831                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5832                         return NULL;
5833                 }
5834         }
5835
5836         highest_refresh = drm_mode_vrefresh(m_pref);
5837
5838         /*
5839          * Find the mode with highest refresh rate with same resolution.
5840          * For some monitors, preferred mode is not the mode with highest
5841          * supported refresh rate.
5842          */
5843         list_for_each_entry(m, list_head, head) {
5844                 current_refresh  = drm_mode_vrefresh(m);
5845
5846                 if (m->hdisplay == m_pref->hdisplay &&
5847                     m->vdisplay == m_pref->vdisplay &&
5848                     highest_refresh < current_refresh) {
5849                         highest_refresh = current_refresh;
5850                         m_pref = m;
5851                 }
5852         }
5853
5854         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5855         return m_pref;
5856 }
5857
5858 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5859                 struct amdgpu_dm_connector *aconnector)
5860 {
5861         struct drm_display_mode *high_mode;
5862         int timing_diff;
5863
5864         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5865         if (!high_mode || !mode)
5866                 return false;
5867
5868         timing_diff = high_mode->vtotal - mode->vtotal;
5869
5870         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5871             high_mode->hdisplay != mode->hdisplay ||
5872             high_mode->vdisplay != mode->vdisplay ||
5873             high_mode->hsync_start != mode->hsync_start ||
5874             high_mode->hsync_end != mode->hsync_end ||
5875             high_mode->htotal != mode->htotal ||
5876             high_mode->hskew != mode->hskew ||
5877             high_mode->vscan != mode->vscan ||
5878             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5879             high_mode->vsync_end - mode->vsync_end != timing_diff)
5880                 return false;
5881         else
5882                 return true;
5883 }
5884
5885 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5886                             struct dc_sink *sink, struct dc_stream_state *stream,
5887                             struct dsc_dec_dpcd_caps *dsc_caps)
5888 {
5889         stream->timing.flags.DSC = 0;
5890         dsc_caps->is_dsc_supported = false;
5891
5892         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5893             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5894                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5895                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5896                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5897                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5898                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5899                                 dsc_caps);
5900         }
5901 }
5902
5903
5904 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5905                                     struct dc_sink *sink, struct dc_stream_state *stream,
5906                                     struct dsc_dec_dpcd_caps *dsc_caps,
5907                                     uint32_t max_dsc_target_bpp_limit_override)
5908 {
5909         const struct dc_link_settings *verified_link_cap = NULL;
5910         u32 link_bw_in_kbps;
5911         u32 edp_min_bpp_x16, edp_max_bpp_x16;
5912         struct dc *dc = sink->ctx->dc;
5913         struct dc_dsc_bw_range bw_range = {0};
5914         struct dc_dsc_config dsc_cfg = {0};
5915         struct dc_dsc_config_options dsc_options = {0};
5916
5917         dc_dsc_get_default_config_option(dc, &dsc_options);
5918         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5919
5920         verified_link_cap = dc_link_get_link_cap(stream->link);
5921         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5922         edp_min_bpp_x16 = 8 * 16;
5923         edp_max_bpp_x16 = 8 * 16;
5924
5925         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5926                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5927
5928         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5929                 edp_min_bpp_x16 = edp_max_bpp_x16;
5930
5931         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5932                                 dc->debug.dsc_min_slice_height_override,
5933                                 edp_min_bpp_x16, edp_max_bpp_x16,
5934                                 dsc_caps,
5935                                 &stream->timing,
5936                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5937                                 &bw_range)) {
5938
5939                 if (bw_range.max_kbps < link_bw_in_kbps) {
5940                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5941                                         dsc_caps,
5942                                         &dsc_options,
5943                                         0,
5944                                         &stream->timing,
5945                                         dc_link_get_highest_encoding_format(aconnector->dc_link),
5946                                         &dsc_cfg)) {
5947                                 stream->timing.dsc_cfg = dsc_cfg;
5948                                 stream->timing.flags.DSC = 1;
5949                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5950                         }
5951                         return;
5952                 }
5953         }
5954
5955         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5956                                 dsc_caps,
5957                                 &dsc_options,
5958                                 link_bw_in_kbps,
5959                                 &stream->timing,
5960                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5961                                 &dsc_cfg)) {
5962                 stream->timing.dsc_cfg = dsc_cfg;
5963                 stream->timing.flags.DSC = 1;
5964         }
5965 }
5966
5967
5968 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5969                                         struct dc_sink *sink, struct dc_stream_state *stream,
5970                                         struct dsc_dec_dpcd_caps *dsc_caps)
5971 {
5972         struct drm_connector *drm_connector = &aconnector->base;
5973         u32 link_bandwidth_kbps;
5974         struct dc *dc = sink->ctx->dc;
5975         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5976         u32 dsc_max_supported_bw_in_kbps;
5977         u32 max_dsc_target_bpp_limit_override =
5978                 drm_connector->display_info.max_dsc_bpp;
5979         struct dc_dsc_config_options dsc_options = {0};
5980
5981         dc_dsc_get_default_config_option(dc, &dsc_options);
5982         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5983
5984         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5985                                                         dc_link_get_link_cap(aconnector->dc_link));
5986
5987         /* Set DSC policy according to dsc_clock_en */
5988         dc_dsc_policy_set_enable_dsc_when_not_needed(
5989                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5990
5991         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5992             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5993             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5994
5995                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5996
5997         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5998                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5999                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
6000                                                 dsc_caps,
6001                                                 &dsc_options,
6002                                                 link_bandwidth_kbps,
6003                                                 &stream->timing,
6004                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
6005                                                 &stream->timing.dsc_cfg)) {
6006                                 stream->timing.flags.DSC = 1;
6007                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
6008                         }
6009                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
6010                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
6011                                         dc_link_get_highest_encoding_format(aconnector->dc_link));
6012                         max_supported_bw_in_kbps = link_bandwidth_kbps;
6013                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
6014
6015                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
6016                                         max_supported_bw_in_kbps > 0 &&
6017                                         dsc_max_supported_bw_in_kbps > 0)
6018                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
6019                                                 dsc_caps,
6020                                                 &dsc_options,
6021                                                 dsc_max_supported_bw_in_kbps,
6022                                                 &stream->timing,
6023                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
6024                                                 &stream->timing.dsc_cfg)) {
6025                                         stream->timing.flags.DSC = 1;
6026                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
6027                                                                          __func__, drm_connector->name);
6028                                 }
6029                 }
6030         }
6031
6032         /* Overwrite the stream flag if DSC is enabled through debugfs */
6033         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
6034                 stream->timing.flags.DSC = 1;
6035
6036         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
6037                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
6038
6039         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
6040                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
6041
6042         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
6043                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
6044 }
6045
6046 static struct dc_stream_state *
6047 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6048                        const struct drm_display_mode *drm_mode,
6049                        const struct dm_connector_state *dm_state,
6050                        const struct dc_stream_state *old_stream,
6051                        int requested_bpc)
6052 {
6053         struct drm_display_mode *preferred_mode = NULL;
6054         struct drm_connector *drm_connector;
6055         const struct drm_connector_state *con_state = &dm_state->base;
6056         struct dc_stream_state *stream = NULL;
6057         struct drm_display_mode mode;
6058         struct drm_display_mode saved_mode;
6059         struct drm_display_mode *freesync_mode = NULL;
6060         bool native_mode_found = false;
6061         bool recalculate_timing = false;
6062         bool scale = dm_state->scaling != RMX_OFF;
6063         int mode_refresh;
6064         int preferred_refresh = 0;
6065         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
6066         struct dsc_dec_dpcd_caps dsc_caps;
6067
6068         struct dc_sink *sink = NULL;
6069
6070         drm_mode_init(&mode, drm_mode);
6071         memset(&saved_mode, 0, sizeof(saved_mode));
6072
6073         if (aconnector == NULL) {
6074                 DRM_ERROR("aconnector is NULL!\n");
6075                 return stream;
6076         }
6077
6078         drm_connector = &aconnector->base;
6079
6080         if (!aconnector->dc_sink) {
6081                 sink = create_fake_sink(aconnector);
6082                 if (!sink)
6083                         return stream;
6084         } else {
6085                 sink = aconnector->dc_sink;
6086                 dc_sink_retain(sink);
6087         }
6088
6089         stream = dc_create_stream_for_sink(sink);
6090
6091         if (stream == NULL) {
6092                 DRM_ERROR("Failed to create stream for sink!\n");
6093                 goto finish;
6094         }
6095
6096         stream->dm_stream_context = aconnector;
6097
6098         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6099                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
6100
6101         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
6102                 /* Search for preferred mode */
6103                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6104                         native_mode_found = true;
6105                         break;
6106                 }
6107         }
6108         if (!native_mode_found)
6109                 preferred_mode = list_first_entry_or_null(
6110                                 &aconnector->base.modes,
6111                                 struct drm_display_mode,
6112                                 head);
6113
6114         mode_refresh = drm_mode_vrefresh(&mode);
6115
6116         if (preferred_mode == NULL) {
6117                 /*
6118                  * This may not be an error, the use case is when we have no
6119                  * usermode calls to reset and set mode upon hotplug. In this
6120                  * case, we call set mode ourselves to restore the previous mode
6121                  * and the modelist may not be filled in time.
6122                  */
6123                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6124         } else {
6125                 recalculate_timing = is_freesync_video_mode(&mode, aconnector);
6126                 if (recalculate_timing) {
6127                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6128                         drm_mode_copy(&saved_mode, &mode);
6129                         drm_mode_copy(&mode, freesync_mode);
6130                 } else {
6131                         decide_crtc_timing_for_drm_display_mode(
6132                                         &mode, preferred_mode, scale);
6133
6134                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6135                 }
6136         }
6137
6138         if (recalculate_timing)
6139                 drm_mode_set_crtcinfo(&saved_mode, 0);
6140
6141         /*
6142          * If scaling is enabled and refresh rate didn't change
6143          * we copy the vic and polarities of the old timings
6144          */
6145         if (!scale || mode_refresh != preferred_refresh)
6146                 fill_stream_properties_from_drm_display_mode(
6147                         stream, &mode, &aconnector->base, con_state, NULL,
6148                         requested_bpc);
6149         else
6150                 fill_stream_properties_from_drm_display_mode(
6151                         stream, &mode, &aconnector->base, con_state, old_stream,
6152                         requested_bpc);
6153
6154         if (aconnector->timing_changed) {
6155                 drm_dbg(aconnector->base.dev,
6156                         "overriding timing for automated test, bpc %d, changing to %d\n",
6157                         stream->timing.display_color_depth,
6158                         aconnector->timing_requested->display_color_depth);
6159                 stream->timing = *aconnector->timing_requested;
6160         }
6161
6162         /* SST DSC determination policy */
6163         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6164         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6165                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6166
6167         update_stream_scaling_settings(&mode, dm_state, stream);
6168
6169         fill_audio_info(
6170                 &stream->audio_info,
6171                 drm_connector,
6172                 sink);
6173
6174         update_stream_signal(stream, sink);
6175
6176         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6177                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6178
6179         if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) {
6180                 //
6181                 // should decide stream support vsc sdp colorimetry capability
6182                 // before building vsc info packet
6183                 //
6184                 stream->use_vsc_sdp_for_colorimetry = false;
6185                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6186                         stream->use_vsc_sdp_for_colorimetry =
6187                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6188                 } else {
6189                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6190                                 stream->use_vsc_sdp_for_colorimetry = true;
6191                 }
6192                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6193                         tf = TRANSFER_FUNC_GAMMA_22;
6194                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6195                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6196
6197         }
6198 finish:
6199         dc_sink_release(sink);
6200
6201         return stream;
6202 }
6203
6204 static enum drm_connector_status
6205 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6206 {
6207         bool connected;
6208         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6209
6210         /*
6211          * Notes:
6212          * 1. This interface is NOT called in context of HPD irq.
6213          * 2. This interface *is called* in context of user-mode ioctl. Which
6214          * makes it a bad place for *any* MST-related activity.
6215          */
6216
6217         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6218             !aconnector->fake_enable)
6219                 connected = (aconnector->dc_sink != NULL);
6220         else
6221                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6222                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6223
6224         update_subconnector_property(aconnector);
6225
6226         return (connected ? connector_status_connected :
6227                         connector_status_disconnected);
6228 }
6229
6230 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6231                                             struct drm_connector_state *connector_state,
6232                                             struct drm_property *property,
6233                                             uint64_t val)
6234 {
6235         struct drm_device *dev = connector->dev;
6236         struct amdgpu_device *adev = drm_to_adev(dev);
6237         struct dm_connector_state *dm_old_state =
6238                 to_dm_connector_state(connector->state);
6239         struct dm_connector_state *dm_new_state =
6240                 to_dm_connector_state(connector_state);
6241
6242         int ret = -EINVAL;
6243
6244         if (property == dev->mode_config.scaling_mode_property) {
6245                 enum amdgpu_rmx_type rmx_type;
6246
6247                 switch (val) {
6248                 case DRM_MODE_SCALE_CENTER:
6249                         rmx_type = RMX_CENTER;
6250                         break;
6251                 case DRM_MODE_SCALE_ASPECT:
6252                         rmx_type = RMX_ASPECT;
6253                         break;
6254                 case DRM_MODE_SCALE_FULLSCREEN:
6255                         rmx_type = RMX_FULL;
6256                         break;
6257                 case DRM_MODE_SCALE_NONE:
6258                 default:
6259                         rmx_type = RMX_OFF;
6260                         break;
6261                 }
6262
6263                 if (dm_old_state->scaling == rmx_type)
6264                         return 0;
6265
6266                 dm_new_state->scaling = rmx_type;
6267                 ret = 0;
6268         } else if (property == adev->mode_info.underscan_hborder_property) {
6269                 dm_new_state->underscan_hborder = val;
6270                 ret = 0;
6271         } else if (property == adev->mode_info.underscan_vborder_property) {
6272                 dm_new_state->underscan_vborder = val;
6273                 ret = 0;
6274         } else if (property == adev->mode_info.underscan_property) {
6275                 dm_new_state->underscan_enable = val;
6276                 ret = 0;
6277         } else if (property == adev->mode_info.abm_level_property) {
6278                 dm_new_state->abm_level = val ?: ABM_LEVEL_IMMEDIATE_DISABLE;
6279                 ret = 0;
6280         }
6281
6282         return ret;
6283 }
6284
6285 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6286                                             const struct drm_connector_state *state,
6287                                             struct drm_property *property,
6288                                             uint64_t *val)
6289 {
6290         struct drm_device *dev = connector->dev;
6291         struct amdgpu_device *adev = drm_to_adev(dev);
6292         struct dm_connector_state *dm_state =
6293                 to_dm_connector_state(state);
6294         int ret = -EINVAL;
6295
6296         if (property == dev->mode_config.scaling_mode_property) {
6297                 switch (dm_state->scaling) {
6298                 case RMX_CENTER:
6299                         *val = DRM_MODE_SCALE_CENTER;
6300                         break;
6301                 case RMX_ASPECT:
6302                         *val = DRM_MODE_SCALE_ASPECT;
6303                         break;
6304                 case RMX_FULL:
6305                         *val = DRM_MODE_SCALE_FULLSCREEN;
6306                         break;
6307                 case RMX_OFF:
6308                 default:
6309                         *val = DRM_MODE_SCALE_NONE;
6310                         break;
6311                 }
6312                 ret = 0;
6313         } else if (property == adev->mode_info.underscan_hborder_property) {
6314                 *val = dm_state->underscan_hborder;
6315                 ret = 0;
6316         } else if (property == adev->mode_info.underscan_vborder_property) {
6317                 *val = dm_state->underscan_vborder;
6318                 ret = 0;
6319         } else if (property == adev->mode_info.underscan_property) {
6320                 *val = dm_state->underscan_enable;
6321                 ret = 0;
6322         } else if (property == adev->mode_info.abm_level_property) {
6323                 *val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ?
6324                         dm_state->abm_level : 0;
6325                 ret = 0;
6326         }
6327
6328         return ret;
6329 }
6330
6331 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6332 {
6333         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6334
6335         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6336 }
6337
6338 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6339 {
6340         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6341         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6342         struct amdgpu_display_manager *dm = &adev->dm;
6343
6344         /*
6345          * Call only if mst_mgr was initialized before since it's not done
6346          * for all connector types.
6347          */
6348         if (aconnector->mst_mgr.dev)
6349                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6350
6351         if (aconnector->bl_idx != -1) {
6352                 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6353                 dm->backlight_dev[aconnector->bl_idx] = NULL;
6354         }
6355
6356         if (aconnector->dc_em_sink)
6357                 dc_sink_release(aconnector->dc_em_sink);
6358         aconnector->dc_em_sink = NULL;
6359         if (aconnector->dc_sink)
6360                 dc_sink_release(aconnector->dc_sink);
6361         aconnector->dc_sink = NULL;
6362
6363         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6364         drm_connector_unregister(connector);
6365         drm_connector_cleanup(connector);
6366         if (aconnector->i2c) {
6367                 i2c_del_adapter(&aconnector->i2c->base);
6368                 kfree(aconnector->i2c);
6369         }
6370         kfree(aconnector->dm_dp_aux.aux.name);
6371
6372         kfree(connector);
6373 }
6374
6375 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6376 {
6377         struct dm_connector_state *state =
6378                 to_dm_connector_state(connector->state);
6379
6380         if (connector->state)
6381                 __drm_atomic_helper_connector_destroy_state(connector->state);
6382
6383         kfree(state);
6384
6385         state = kzalloc(sizeof(*state), GFP_KERNEL);
6386
6387         if (state) {
6388                 state->scaling = RMX_OFF;
6389                 state->underscan_enable = false;
6390                 state->underscan_hborder = 0;
6391                 state->underscan_vborder = 0;
6392                 state->base.max_requested_bpc = 8;
6393                 state->vcpi_slots = 0;
6394                 state->pbn = 0;
6395
6396                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6397                         state->abm_level = amdgpu_dm_abm_level ?:
6398                                 ABM_LEVEL_IMMEDIATE_DISABLE;
6399
6400                 __drm_atomic_helper_connector_reset(connector, &state->base);
6401         }
6402 }
6403
6404 struct drm_connector_state *
6405 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6406 {
6407         struct dm_connector_state *state =
6408                 to_dm_connector_state(connector->state);
6409
6410         struct dm_connector_state *new_state =
6411                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6412
6413         if (!new_state)
6414                 return NULL;
6415
6416         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6417
6418         new_state->freesync_capable = state->freesync_capable;
6419         new_state->abm_level = state->abm_level;
6420         new_state->scaling = state->scaling;
6421         new_state->underscan_enable = state->underscan_enable;
6422         new_state->underscan_hborder = state->underscan_hborder;
6423         new_state->underscan_vborder = state->underscan_vborder;
6424         new_state->vcpi_slots = state->vcpi_slots;
6425         new_state->pbn = state->pbn;
6426         return &new_state->base;
6427 }
6428
6429 static int
6430 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6431 {
6432         struct amdgpu_dm_connector *amdgpu_dm_connector =
6433                 to_amdgpu_dm_connector(connector);
6434         int r;
6435
6436         amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6437
6438         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6439             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6440                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6441                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6442                 if (r)
6443                         return r;
6444         }
6445
6446 #if defined(CONFIG_DEBUG_FS)
6447         connector_debugfs_init(amdgpu_dm_connector);
6448 #endif
6449
6450         return 0;
6451 }
6452
6453 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
6454 {
6455         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6456         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
6457         struct dc_link *dc_link = aconnector->dc_link;
6458         struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
6459         struct edid *edid;
6460
6461         /*
6462          * Note: drm_get_edid gets edid in the following order:
6463          * 1) override EDID if set via edid_override debugfs,
6464          * 2) firmware EDID if set via edid_firmware module parameter
6465          * 3) regular DDC read.
6466          */
6467         edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc);
6468         if (!edid) {
6469                 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6470                 return;
6471         }
6472
6473         aconnector->edid = edid;
6474
6475         /* Update emulated (virtual) sink's EDID */
6476         if (dc_em_sink && dc_link) {
6477                 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
6478                 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);
6479                 dm_helpers_parse_edid_caps(
6480                         dc_link,
6481                         &dc_em_sink->dc_edid,
6482                         &dc_em_sink->edid_caps);
6483         }
6484 }
6485
6486 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6487         .reset = amdgpu_dm_connector_funcs_reset,
6488         .detect = amdgpu_dm_connector_detect,
6489         .fill_modes = drm_helper_probe_single_connector_modes,
6490         .destroy = amdgpu_dm_connector_destroy,
6491         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6492         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6493         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6494         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6495         .late_register = amdgpu_dm_connector_late_register,
6496         .early_unregister = amdgpu_dm_connector_unregister,
6497         .force = amdgpu_dm_connector_funcs_force
6498 };
6499
6500 static int get_modes(struct drm_connector *connector)
6501 {
6502         return amdgpu_dm_connector_get_modes(connector);
6503 }
6504
6505 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6506 {
6507         struct drm_connector *connector = &aconnector->base;
6508         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(&aconnector->base);
6509         struct dc_sink_init_data init_params = {
6510                         .link = aconnector->dc_link,
6511                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6512         };
6513         struct edid *edid;
6514
6515         /*
6516          * Note: drm_get_edid gets edid in the following order:
6517          * 1) override EDID if set via edid_override debugfs,
6518          * 2) firmware EDID if set via edid_firmware module parameter
6519          * 3) regular DDC read.
6520          */
6521         edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc);
6522         if (!edid) {
6523                 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6524                 return;
6525         }
6526
6527         if (drm_detect_hdmi_monitor(edid))
6528                 init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;
6529
6530         aconnector->edid = edid;
6531
6532         aconnector->dc_em_sink = dc_link_add_remote_sink(
6533                 aconnector->dc_link,
6534                 (uint8_t *)edid,
6535                 (edid->extensions + 1) * EDID_LENGTH,
6536                 &init_params);
6537
6538         if (aconnector->base.force == DRM_FORCE_ON) {
6539                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6540                 aconnector->dc_link->local_sink :
6541                 aconnector->dc_em_sink;
6542                 dc_sink_retain(aconnector->dc_sink);
6543         }
6544 }
6545
6546 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6547 {
6548         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6549
6550         /*
6551          * In case of headless boot with force on for DP managed connector
6552          * Those settings have to be != 0 to get initial modeset
6553          */
6554         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6555                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6556                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6557         }
6558
6559         create_eml_sink(aconnector);
6560 }
6561
6562 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6563                                                 struct dc_stream_state *stream)
6564 {
6565         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6566         struct dc_plane_state *dc_plane_state = NULL;
6567         struct dc_state *dc_state = NULL;
6568
6569         if (!stream)
6570                 goto cleanup;
6571
6572         dc_plane_state = dc_create_plane_state(dc);
6573         if (!dc_plane_state)
6574                 goto cleanup;
6575
6576         dc_state = dc_create_state(dc);
6577         if (!dc_state)
6578                 goto cleanup;
6579
6580         /* populate stream to plane */
6581         dc_plane_state->src_rect.height  = stream->src.height;
6582         dc_plane_state->src_rect.width   = stream->src.width;
6583         dc_plane_state->dst_rect.height  = stream->src.height;
6584         dc_plane_state->dst_rect.width   = stream->src.width;
6585         dc_plane_state->clip_rect.height = stream->src.height;
6586         dc_plane_state->clip_rect.width  = stream->src.width;
6587         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6588         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6589         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6590         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6591         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6592         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6593         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6594         dc_plane_state->rotation = ROTATION_ANGLE_0;
6595         dc_plane_state->is_tiling_rotated = false;
6596         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6597
6598         dc_result = dc_validate_stream(dc, stream);
6599         if (dc_result == DC_OK)
6600                 dc_result = dc_validate_plane(dc, dc_plane_state);
6601
6602         if (dc_result == DC_OK)
6603                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6604
6605         if (dc_result == DC_OK && !dc_add_plane_to_context(
6606                                                 dc,
6607                                                 stream,
6608                                                 dc_plane_state,
6609                                                 dc_state))
6610                 dc_result = DC_FAIL_ATTACH_SURFACES;
6611
6612         if (dc_result == DC_OK)
6613                 dc_result = dc_validate_global_state(dc, dc_state, true);
6614
6615 cleanup:
6616         if (dc_state)
6617                 dc_release_state(dc_state);
6618
6619         if (dc_plane_state)
6620                 dc_plane_state_release(dc_plane_state);
6621
6622         return dc_result;
6623 }
6624
6625 struct dc_stream_state *
6626 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6627                                 const struct drm_display_mode *drm_mode,
6628                                 const struct dm_connector_state *dm_state,
6629                                 const struct dc_stream_state *old_stream)
6630 {
6631         struct drm_connector *connector = &aconnector->base;
6632         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6633         struct dc_stream_state *stream;
6634         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6635         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6636         enum dc_status dc_result = DC_OK;
6637
6638         do {
6639                 stream = create_stream_for_sink(aconnector, drm_mode,
6640                                                 dm_state, old_stream,
6641                                                 requested_bpc);
6642                 if (stream == NULL) {
6643                         DRM_ERROR("Failed to create stream for sink!\n");
6644                         break;
6645                 }
6646
6647                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6648                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6649                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6650
6651                 if (dc_result == DC_OK)
6652                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6653
6654                 if (dc_result != DC_OK) {
6655                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6656                                       drm_mode->hdisplay,
6657                                       drm_mode->vdisplay,
6658                                       drm_mode->clock,
6659                                       dc_result,
6660                                       dc_status_to_str(dc_result));
6661
6662                         dc_stream_release(stream);
6663                         stream = NULL;
6664                         requested_bpc -= 2; /* lower bpc to retry validation */
6665                 }
6666
6667         } while (stream == NULL && requested_bpc >= 6);
6668
6669         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6670                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6671
6672                 aconnector->force_yuv420_output = true;
6673                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6674                                                 dm_state, old_stream);
6675                 aconnector->force_yuv420_output = false;
6676         }
6677
6678         return stream;
6679 }
6680
6681 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6682                                    struct drm_display_mode *mode)
6683 {
6684         int result = MODE_ERROR;
6685         struct dc_sink *dc_sink;
6686         /* TODO: Unhardcode stream count */
6687         struct dc_stream_state *stream;
6688         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6689
6690         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6691                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6692                 return result;
6693
6694         /*
6695          * Only run this the first time mode_valid is called to initilialize
6696          * EDID mgmt
6697          */
6698         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6699                 !aconnector->dc_em_sink)
6700                 handle_edid_mgmt(aconnector);
6701
6702         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6703
6704         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6705                                 aconnector->base.force != DRM_FORCE_ON) {
6706                 DRM_ERROR("dc_sink is NULL!\n");
6707                 goto fail;
6708         }
6709
6710         drm_mode_set_crtcinfo(mode, 0);
6711
6712         stream = create_validate_stream_for_sink(aconnector, mode,
6713                                                  to_dm_connector_state(connector->state),
6714                                                  NULL);
6715         if (stream) {
6716                 dc_stream_release(stream);
6717                 result = MODE_OK;
6718         }
6719
6720 fail:
6721         /* TODO: error handling*/
6722         return result;
6723 }
6724
6725 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6726                                 struct dc_info_packet *out)
6727 {
6728         struct hdmi_drm_infoframe frame;
6729         unsigned char buf[30]; /* 26 + 4 */
6730         ssize_t len;
6731         int ret, i;
6732
6733         memset(out, 0, sizeof(*out));
6734
6735         if (!state->hdr_output_metadata)
6736                 return 0;
6737
6738         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6739         if (ret)
6740                 return ret;
6741
6742         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6743         if (len < 0)
6744                 return (int)len;
6745
6746         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6747         if (len != 30)
6748                 return -EINVAL;
6749
6750         /* Prepare the infopacket for DC. */
6751         switch (state->connector->connector_type) {
6752         case DRM_MODE_CONNECTOR_HDMIA:
6753                 out->hb0 = 0x87; /* type */
6754                 out->hb1 = 0x01; /* version */
6755                 out->hb2 = 0x1A; /* length */
6756                 out->sb[0] = buf[3]; /* checksum */
6757                 i = 1;
6758                 break;
6759
6760         case DRM_MODE_CONNECTOR_DisplayPort:
6761         case DRM_MODE_CONNECTOR_eDP:
6762                 out->hb0 = 0x00; /* sdp id, zero */
6763                 out->hb1 = 0x87; /* type */
6764                 out->hb2 = 0x1D; /* payload len - 1 */
6765                 out->hb3 = (0x13 << 2); /* sdp version */
6766                 out->sb[0] = 0x01; /* version */
6767                 out->sb[1] = 0x1A; /* length */
6768                 i = 2;
6769                 break;
6770
6771         default:
6772                 return -EINVAL;
6773         }
6774
6775         memcpy(&out->sb[i], &buf[4], 26);
6776         out->valid = true;
6777
6778         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6779                        sizeof(out->sb), false);
6780
6781         return 0;
6782 }
6783
6784 static int
6785 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6786                                  struct drm_atomic_state *state)
6787 {
6788         struct drm_connector_state *new_con_state =
6789                 drm_atomic_get_new_connector_state(state, conn);
6790         struct drm_connector_state *old_con_state =
6791                 drm_atomic_get_old_connector_state(state, conn);
6792         struct drm_crtc *crtc = new_con_state->crtc;
6793         struct drm_crtc_state *new_crtc_state;
6794         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6795         int ret;
6796
6797         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6798
6799         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6800                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6801                 if (ret < 0)
6802                         return ret;
6803         }
6804
6805         if (!crtc)
6806                 return 0;
6807
6808         if (new_con_state->colorspace != old_con_state->colorspace) {
6809                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6810                 if (IS_ERR(new_crtc_state))
6811                         return PTR_ERR(new_crtc_state);
6812
6813                 new_crtc_state->mode_changed = true;
6814         }
6815
6816         if (new_con_state->content_type != old_con_state->content_type) {
6817                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6818                 if (IS_ERR(new_crtc_state))
6819                         return PTR_ERR(new_crtc_state);
6820
6821                 new_crtc_state->mode_changed = true;
6822         }
6823
6824         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6825                 struct dc_info_packet hdr_infopacket;
6826
6827                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6828                 if (ret)
6829                         return ret;
6830
6831                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6832                 if (IS_ERR(new_crtc_state))
6833                         return PTR_ERR(new_crtc_state);
6834
6835                 /*
6836                  * DC considers the stream backends changed if the
6837                  * static metadata changes. Forcing the modeset also
6838                  * gives a simple way for userspace to switch from
6839                  * 8bpc to 10bpc when setting the metadata to enter
6840                  * or exit HDR.
6841                  *
6842                  * Changing the static metadata after it's been
6843                  * set is permissible, however. So only force a
6844                  * modeset if we're entering or exiting HDR.
6845                  */
6846                 new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
6847                         !old_con_state->hdr_output_metadata ||
6848                         !new_con_state->hdr_output_metadata;
6849         }
6850
6851         return 0;
6852 }
6853
6854 static const struct drm_connector_helper_funcs
6855 amdgpu_dm_connector_helper_funcs = {
6856         /*
6857          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6858          * modes will be filtered by drm_mode_validate_size(), and those modes
6859          * are missing after user start lightdm. So we need to renew modes list.
6860          * in get_modes call back, not just return the modes count
6861          */
6862         .get_modes = get_modes,
6863         .mode_valid = amdgpu_dm_connector_mode_valid,
6864         .atomic_check = amdgpu_dm_connector_atomic_check,
6865 };
6866
6867 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6868 {
6869
6870 }
6871
6872 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6873 {
6874         switch (display_color_depth) {
6875         case COLOR_DEPTH_666:
6876                 return 6;
6877         case COLOR_DEPTH_888:
6878                 return 8;
6879         case COLOR_DEPTH_101010:
6880                 return 10;
6881         case COLOR_DEPTH_121212:
6882                 return 12;
6883         case COLOR_DEPTH_141414:
6884                 return 14;
6885         case COLOR_DEPTH_161616:
6886                 return 16;
6887         default:
6888                 break;
6889         }
6890         return 0;
6891 }
6892
6893 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6894                                           struct drm_crtc_state *crtc_state,
6895                                           struct drm_connector_state *conn_state)
6896 {
6897         struct drm_atomic_state *state = crtc_state->state;
6898         struct drm_connector *connector = conn_state->connector;
6899         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6900         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6901         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6902         struct drm_dp_mst_topology_mgr *mst_mgr;
6903         struct drm_dp_mst_port *mst_port;
6904         struct drm_dp_mst_topology_state *mst_state;
6905         enum dc_color_depth color_depth;
6906         int clock, bpp = 0;
6907         bool is_y420 = false;
6908
6909         if (!aconnector->mst_output_port)
6910                 return 0;
6911
6912         mst_port = aconnector->mst_output_port;
6913         mst_mgr = &aconnector->mst_root->mst_mgr;
6914
6915         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6916                 return 0;
6917
6918         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6919         if (IS_ERR(mst_state))
6920                 return PTR_ERR(mst_state);
6921
6922         if (!mst_state->pbn_div.full)
6923                 mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link));
6924
6925         if (!state->duplicated) {
6926                 int max_bpc = conn_state->max_requested_bpc;
6927
6928                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6929                           aconnector->force_yuv420_output;
6930                 color_depth = convert_color_depth_from_display_info(connector,
6931                                                                     is_y420,
6932                                                                     max_bpc);
6933                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6934                 clock = adjusted_mode->clock;
6935                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);
6936         }
6937
6938         dm_new_connector_state->vcpi_slots =
6939                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6940                                               dm_new_connector_state->pbn);
6941         if (dm_new_connector_state->vcpi_slots < 0) {
6942                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6943                 return dm_new_connector_state->vcpi_slots;
6944         }
6945         return 0;
6946 }
6947
6948 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6949         .disable = dm_encoder_helper_disable,
6950         .atomic_check = dm_encoder_helper_atomic_check
6951 };
6952
6953 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6954                                             struct dc_state *dc_state,
6955                                             struct dsc_mst_fairness_vars *vars)
6956 {
6957         struct dc_stream_state *stream = NULL;
6958         struct drm_connector *connector;
6959         struct drm_connector_state *new_con_state;
6960         struct amdgpu_dm_connector *aconnector;
6961         struct dm_connector_state *dm_conn_state;
6962         int i, j, ret;
6963         int vcpi, pbn_div, pbn, slot_num = 0;
6964
6965         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6966
6967                 aconnector = to_amdgpu_dm_connector(connector);
6968
6969                 if (!aconnector->mst_output_port)
6970                         continue;
6971
6972                 if (!new_con_state || !new_con_state->crtc)
6973                         continue;
6974
6975                 dm_conn_state = to_dm_connector_state(new_con_state);
6976
6977                 for (j = 0; j < dc_state->stream_count; j++) {
6978                         stream = dc_state->streams[j];
6979                         if (!stream)
6980                                 continue;
6981
6982                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6983                                 break;
6984
6985                         stream = NULL;
6986                 }
6987
6988                 if (!stream)
6989                         continue;
6990
6991                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6992                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6993                 for (j = 0; j < dc_state->stream_count; j++) {
6994                         if (vars[j].aconnector == aconnector) {
6995                                 pbn = vars[j].pbn;
6996                                 break;
6997                         }
6998                 }
6999
7000                 if (j == dc_state->stream_count)
7001                         continue;
7002
7003                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
7004
7005                 if (stream->timing.flags.DSC != 1) {
7006                         dm_conn_state->pbn = pbn;
7007                         dm_conn_state->vcpi_slots = slot_num;
7008
7009                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
7010                                                            dm_conn_state->pbn, false);
7011                         if (ret < 0)
7012                                 return ret;
7013
7014                         continue;
7015                 }
7016
7017                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
7018                 if (vcpi < 0)
7019                         return vcpi;
7020
7021                 dm_conn_state->pbn = pbn;
7022                 dm_conn_state->vcpi_slots = vcpi;
7023         }
7024         return 0;
7025 }
7026
7027 static int to_drm_connector_type(enum signal_type st)
7028 {
7029         switch (st) {
7030         case SIGNAL_TYPE_HDMI_TYPE_A:
7031                 return DRM_MODE_CONNECTOR_HDMIA;
7032         case SIGNAL_TYPE_EDP:
7033                 return DRM_MODE_CONNECTOR_eDP;
7034         case SIGNAL_TYPE_LVDS:
7035                 return DRM_MODE_CONNECTOR_LVDS;
7036         case SIGNAL_TYPE_RGB:
7037                 return DRM_MODE_CONNECTOR_VGA;
7038         case SIGNAL_TYPE_DISPLAY_PORT:
7039         case SIGNAL_TYPE_DISPLAY_PORT_MST:
7040                 return DRM_MODE_CONNECTOR_DisplayPort;
7041         case SIGNAL_TYPE_DVI_DUAL_LINK:
7042         case SIGNAL_TYPE_DVI_SINGLE_LINK:
7043                 return DRM_MODE_CONNECTOR_DVID;
7044         case SIGNAL_TYPE_VIRTUAL:
7045                 return DRM_MODE_CONNECTOR_VIRTUAL;
7046
7047         default:
7048                 return DRM_MODE_CONNECTOR_Unknown;
7049         }
7050 }
7051
7052 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
7053 {
7054         struct drm_encoder *encoder;
7055
7056         /* There is only one encoder per connector */
7057         drm_connector_for_each_possible_encoder(connector, encoder)
7058                 return encoder;
7059
7060         return NULL;
7061 }
7062
7063 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
7064 {
7065         struct drm_encoder *encoder;
7066         struct amdgpu_encoder *amdgpu_encoder;
7067
7068         encoder = amdgpu_dm_connector_to_encoder(connector);
7069
7070         if (encoder == NULL)
7071                 return;
7072
7073         amdgpu_encoder = to_amdgpu_encoder(encoder);
7074
7075         amdgpu_encoder->native_mode.clock = 0;
7076
7077         if (!list_empty(&connector->probed_modes)) {
7078                 struct drm_display_mode *preferred_mode = NULL;
7079
7080                 list_for_each_entry(preferred_mode,
7081                                     &connector->probed_modes,
7082                                     head) {
7083                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
7084                                 amdgpu_encoder->native_mode = *preferred_mode;
7085
7086                         break;
7087                 }
7088
7089         }
7090 }
7091
7092 static struct drm_display_mode *
7093 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
7094                              char *name,
7095                              int hdisplay, int vdisplay)
7096 {
7097         struct drm_device *dev = encoder->dev;
7098         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7099         struct drm_display_mode *mode = NULL;
7100         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7101
7102         mode = drm_mode_duplicate(dev, native_mode);
7103
7104         if (mode == NULL)
7105                 return NULL;
7106
7107         mode->hdisplay = hdisplay;
7108         mode->vdisplay = vdisplay;
7109         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7110         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
7111
7112         return mode;
7113
7114 }
7115
7116 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
7117                                                  struct drm_connector *connector)
7118 {
7119         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7120         struct drm_display_mode *mode = NULL;
7121         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7122         struct amdgpu_dm_connector *amdgpu_dm_connector =
7123                                 to_amdgpu_dm_connector(connector);
7124         int i;
7125         int n;
7126         struct mode_size {
7127                 char name[DRM_DISPLAY_MODE_LEN];
7128                 int w;
7129                 int h;
7130         } common_modes[] = {
7131                 {  "640x480",  640,  480},
7132                 {  "800x600",  800,  600},
7133                 { "1024x768", 1024,  768},
7134                 { "1280x720", 1280,  720},
7135                 { "1280x800", 1280,  800},
7136                 {"1280x1024", 1280, 1024},
7137                 { "1440x900", 1440,  900},
7138                 {"1680x1050", 1680, 1050},
7139                 {"1600x1200", 1600, 1200},
7140                 {"1920x1080", 1920, 1080},
7141                 {"1920x1200", 1920, 1200}
7142         };
7143
7144         n = ARRAY_SIZE(common_modes);
7145
7146         for (i = 0; i < n; i++) {
7147                 struct drm_display_mode *curmode = NULL;
7148                 bool mode_existed = false;
7149
7150                 if (common_modes[i].w > native_mode->hdisplay ||
7151                     common_modes[i].h > native_mode->vdisplay ||
7152                    (common_modes[i].w == native_mode->hdisplay &&
7153                     common_modes[i].h == native_mode->vdisplay))
7154                         continue;
7155
7156                 list_for_each_entry(curmode, &connector->probed_modes, head) {
7157                         if (common_modes[i].w == curmode->hdisplay &&
7158                             common_modes[i].h == curmode->vdisplay) {
7159                                 mode_existed = true;
7160                                 break;
7161                         }
7162                 }
7163
7164                 if (mode_existed)
7165                         continue;
7166
7167                 mode = amdgpu_dm_create_common_mode(encoder,
7168                                 common_modes[i].name, common_modes[i].w,
7169                                 common_modes[i].h);
7170                 if (!mode)
7171                         continue;
7172
7173                 drm_mode_probed_add(connector, mode);
7174                 amdgpu_dm_connector->num_modes++;
7175         }
7176 }
7177
7178 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7179 {
7180         struct drm_encoder *encoder;
7181         struct amdgpu_encoder *amdgpu_encoder;
7182         const struct drm_display_mode *native_mode;
7183
7184         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7185             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7186                 return;
7187
7188         mutex_lock(&connector->dev->mode_config.mutex);
7189         amdgpu_dm_connector_get_modes(connector);
7190         mutex_unlock(&connector->dev->mode_config.mutex);
7191
7192         encoder = amdgpu_dm_connector_to_encoder(connector);
7193         if (!encoder)
7194                 return;
7195
7196         amdgpu_encoder = to_amdgpu_encoder(encoder);
7197
7198         native_mode = &amdgpu_encoder->native_mode;
7199         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7200                 return;
7201
7202         drm_connector_set_panel_orientation_with_quirk(connector,
7203                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7204                                                        native_mode->hdisplay,
7205                                                        native_mode->vdisplay);
7206 }
7207
7208 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7209                                               struct edid *edid)
7210 {
7211         struct amdgpu_dm_connector *amdgpu_dm_connector =
7212                         to_amdgpu_dm_connector(connector);
7213
7214         if (edid) {
7215                 /* empty probed_modes */
7216                 INIT_LIST_HEAD(&connector->probed_modes);
7217                 amdgpu_dm_connector->num_modes =
7218                                 drm_add_edid_modes(connector, edid);
7219
7220                 /* sorting the probed modes before calling function
7221                  * amdgpu_dm_get_native_mode() since EDID can have
7222                  * more than one preferred mode. The modes that are
7223                  * later in the probed mode list could be of higher
7224                  * and preferred resolution. For example, 3840x2160
7225                  * resolution in base EDID preferred timing and 4096x2160
7226                  * preferred resolution in DID extension block later.
7227                  */
7228                 drm_mode_sort(&connector->probed_modes);
7229                 amdgpu_dm_get_native_mode(connector);
7230
7231                 /* Freesync capabilities are reset by calling
7232                  * drm_add_edid_modes() and need to be
7233                  * restored here.
7234                  */
7235                 amdgpu_dm_update_freesync_caps(connector, edid);
7236         } else {
7237                 amdgpu_dm_connector->num_modes = 0;
7238         }
7239 }
7240
7241 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7242                               struct drm_display_mode *mode)
7243 {
7244         struct drm_display_mode *m;
7245
7246         list_for_each_entry(m, &aconnector->base.probed_modes, head) {
7247                 if (drm_mode_equal(m, mode))
7248                         return true;
7249         }
7250
7251         return false;
7252 }
7253
7254 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7255 {
7256         const struct drm_display_mode *m;
7257         struct drm_display_mode *new_mode;
7258         uint i;
7259         u32 new_modes_count = 0;
7260
7261         /* Standard FPS values
7262          *
7263          * 23.976       - TV/NTSC
7264          * 24           - Cinema
7265          * 25           - TV/PAL
7266          * 29.97        - TV/NTSC
7267          * 30           - TV/NTSC
7268          * 48           - Cinema HFR
7269          * 50           - TV/PAL
7270          * 60           - Commonly used
7271          * 48,72,96,120 - Multiples of 24
7272          */
7273         static const u32 common_rates[] = {
7274                 23976, 24000, 25000, 29970, 30000,
7275                 48000, 50000, 60000, 72000, 96000, 120000
7276         };
7277
7278         /*
7279          * Find mode with highest refresh rate with the same resolution
7280          * as the preferred mode. Some monitors report a preferred mode
7281          * with lower resolution than the highest refresh rate supported.
7282          */
7283
7284         m = get_highest_refresh_rate_mode(aconnector, true);
7285         if (!m)
7286                 return 0;
7287
7288         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7289                 u64 target_vtotal, target_vtotal_diff;
7290                 u64 num, den;
7291
7292                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7293                         continue;
7294
7295                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7296                     common_rates[i] > aconnector->max_vfreq * 1000)
7297                         continue;
7298
7299                 num = (unsigned long long)m->clock * 1000 * 1000;
7300                 den = common_rates[i] * (unsigned long long)m->htotal;
7301                 target_vtotal = div_u64(num, den);
7302                 target_vtotal_diff = target_vtotal - m->vtotal;
7303
7304                 /* Check for illegal modes */
7305                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7306                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7307                     m->vtotal + target_vtotal_diff < m->vsync_end)
7308                         continue;
7309
7310                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7311                 if (!new_mode)
7312                         goto out;
7313
7314                 new_mode->vtotal += (u16)target_vtotal_diff;
7315                 new_mode->vsync_start += (u16)target_vtotal_diff;
7316                 new_mode->vsync_end += (u16)target_vtotal_diff;
7317                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7318                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7319
7320                 if (!is_duplicate_mode(aconnector, new_mode)) {
7321                         drm_mode_probed_add(&aconnector->base, new_mode);
7322                         new_modes_count += 1;
7323                 } else
7324                         drm_mode_destroy(aconnector->base.dev, new_mode);
7325         }
7326  out:
7327         return new_modes_count;
7328 }
7329
7330 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7331                                                    struct edid *edid)
7332 {
7333         struct amdgpu_dm_connector *amdgpu_dm_connector =
7334                 to_amdgpu_dm_connector(connector);
7335
7336         if (!edid)
7337                 return;
7338
7339         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7340                 amdgpu_dm_connector->num_modes +=
7341                         add_fs_modes(amdgpu_dm_connector);
7342 }
7343
7344 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7345 {
7346         struct amdgpu_dm_connector *amdgpu_dm_connector =
7347                         to_amdgpu_dm_connector(connector);
7348         struct drm_encoder *encoder;
7349         struct edid *edid = amdgpu_dm_connector->edid;
7350         struct dc_link_settings *verified_link_cap =
7351                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7352         const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7353
7354         encoder = amdgpu_dm_connector_to_encoder(connector);
7355
7356         if (!drm_edid_is_valid(edid)) {
7357                 amdgpu_dm_connector->num_modes =
7358                                 drm_add_modes_noedid(connector, 640, 480);
7359                 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7360                         amdgpu_dm_connector->num_modes +=
7361                                 drm_add_modes_noedid(connector, 1920, 1080);
7362         } else {
7363                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7364                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7365                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7366         }
7367         amdgpu_dm_fbc_init(connector);
7368
7369         return amdgpu_dm_connector->num_modes;
7370 }
7371
7372 static const u32 supported_colorspaces =
7373         BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
7374         BIT(DRM_MODE_COLORIMETRY_OPRGB) |
7375         BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
7376         BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
7377
7378 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7379                                      struct amdgpu_dm_connector *aconnector,
7380                                      int connector_type,
7381                                      struct dc_link *link,
7382                                      int link_index)
7383 {
7384         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7385
7386         /*
7387          * Some of the properties below require access to state, like bpc.
7388          * Allocate some default initial connector state with our reset helper.
7389          */
7390         if (aconnector->base.funcs->reset)
7391                 aconnector->base.funcs->reset(&aconnector->base);
7392
7393         aconnector->connector_id = link_index;
7394         aconnector->bl_idx = -1;
7395         aconnector->dc_link = link;
7396         aconnector->base.interlace_allowed = false;
7397         aconnector->base.doublescan_allowed = false;
7398         aconnector->base.stereo_allowed = false;
7399         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7400         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7401         aconnector->audio_inst = -1;
7402         aconnector->pack_sdp_v1_3 = false;
7403         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7404         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7405         mutex_init(&aconnector->hpd_lock);
7406         mutex_init(&aconnector->handle_mst_msg_ready);
7407
7408         /*
7409          * configure support HPD hot plug connector_>polled default value is 0
7410          * which means HPD hot plug not supported
7411          */
7412         switch (connector_type) {
7413         case DRM_MODE_CONNECTOR_HDMIA:
7414                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7415                 aconnector->base.ycbcr_420_allowed =
7416                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7417                 break;
7418         case DRM_MODE_CONNECTOR_DisplayPort:
7419                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7420                 link->link_enc = link_enc_cfg_get_link_enc(link);
7421                 ASSERT(link->link_enc);
7422                 if (link->link_enc)
7423                         aconnector->base.ycbcr_420_allowed =
7424                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7425                 break;
7426         case DRM_MODE_CONNECTOR_DVID:
7427                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7428                 break;
7429         default:
7430                 break;
7431         }
7432
7433         drm_object_attach_property(&aconnector->base.base,
7434                                 dm->ddev->mode_config.scaling_mode_property,
7435                                 DRM_MODE_SCALE_NONE);
7436
7437         drm_object_attach_property(&aconnector->base.base,
7438                                 adev->mode_info.underscan_property,
7439                                 UNDERSCAN_OFF);
7440         drm_object_attach_property(&aconnector->base.base,
7441                                 adev->mode_info.underscan_hborder_property,
7442                                 0);
7443         drm_object_attach_property(&aconnector->base.base,
7444                                 adev->mode_info.underscan_vborder_property,
7445                                 0);
7446
7447         if (!aconnector->mst_root)
7448                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7449
7450         aconnector->base.state->max_bpc = 16;
7451         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7452
7453         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7454             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7455                 drm_object_attach_property(&aconnector->base.base,
7456                                 adev->mode_info.abm_level_property, 0);
7457         }
7458
7459         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7460                 /* Content Type is currently only implemented for HDMI. */
7461                 drm_connector_attach_content_type_property(&aconnector->base);
7462         }
7463
7464         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7465                 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
7466                         drm_connector_attach_colorspace_property(&aconnector->base);
7467         } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) ||
7468                    connector_type == DRM_MODE_CONNECTOR_eDP) {
7469                 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
7470                         drm_connector_attach_colorspace_property(&aconnector->base);
7471         }
7472
7473         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7474             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7475             connector_type == DRM_MODE_CONNECTOR_eDP) {
7476                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7477
7478                 if (!aconnector->mst_root)
7479                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7480
7481                 if (adev->dm.hdcp_workqueue)
7482                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7483         }
7484 }
7485
7486 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7487                               struct i2c_msg *msgs, int num)
7488 {
7489         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7490         struct ddc_service *ddc_service = i2c->ddc_service;
7491         struct i2c_command cmd;
7492         int i;
7493         int result = -EIO;
7494
7495         if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported)
7496                 return result;
7497
7498         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7499
7500         if (!cmd.payloads)
7501                 return result;
7502
7503         cmd.number_of_payloads = num;
7504         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7505         cmd.speed = 100;
7506
7507         for (i = 0; i < num; i++) {
7508                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7509                 cmd.payloads[i].address = msgs[i].addr;
7510                 cmd.payloads[i].length = msgs[i].len;
7511                 cmd.payloads[i].data = msgs[i].buf;
7512         }
7513
7514         if (dc_submit_i2c(
7515                         ddc_service->ctx->dc,
7516                         ddc_service->link->link_index,
7517                         &cmd))
7518                 result = num;
7519
7520         kfree(cmd.payloads);
7521         return result;
7522 }
7523
7524 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7525 {
7526         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7527 }
7528
7529 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7530         .master_xfer = amdgpu_dm_i2c_xfer,
7531         .functionality = amdgpu_dm_i2c_func,
7532 };
7533
7534 static struct amdgpu_i2c_adapter *
7535 create_i2c(struct ddc_service *ddc_service,
7536            int link_index,
7537            int *res)
7538 {
7539         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7540         struct amdgpu_i2c_adapter *i2c;
7541
7542         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7543         if (!i2c)
7544                 return NULL;
7545         i2c->base.owner = THIS_MODULE;
7546         i2c->base.class = I2C_CLASS_DDC;
7547         i2c->base.dev.parent = &adev->pdev->dev;
7548         i2c->base.algo = &amdgpu_dm_i2c_algo;
7549         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7550         i2c_set_adapdata(&i2c->base, i2c);
7551         i2c->ddc_service = ddc_service;
7552
7553         return i2c;
7554 }
7555
7556
7557 /*
7558  * Note: this function assumes that dc_link_detect() was called for the
7559  * dc_link which will be represented by this aconnector.
7560  */
7561 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7562                                     struct amdgpu_dm_connector *aconnector,
7563                                     u32 link_index,
7564                                     struct amdgpu_encoder *aencoder)
7565 {
7566         int res = 0;
7567         int connector_type;
7568         struct dc *dc = dm->dc;
7569         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7570         struct amdgpu_i2c_adapter *i2c;
7571
7572         link->priv = aconnector;
7573
7574
7575         i2c = create_i2c(link->ddc, link->link_index, &res);
7576         if (!i2c) {
7577                 DRM_ERROR("Failed to create i2c adapter data\n");
7578                 return -ENOMEM;
7579         }
7580
7581         aconnector->i2c = i2c;
7582         res = i2c_add_adapter(&i2c->base);
7583
7584         if (res) {
7585                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7586                 goto out_free;
7587         }
7588
7589         connector_type = to_drm_connector_type(link->connector_signal);
7590
7591         res = drm_connector_init_with_ddc(
7592                         dm->ddev,
7593                         &aconnector->base,
7594                         &amdgpu_dm_connector_funcs,
7595                         connector_type,
7596                         &i2c->base);
7597
7598         if (res) {
7599                 DRM_ERROR("connector_init failed\n");
7600                 aconnector->connector_id = -1;
7601                 goto out_free;
7602         }
7603
7604         drm_connector_helper_add(
7605                         &aconnector->base,
7606                         &amdgpu_dm_connector_helper_funcs);
7607
7608         amdgpu_dm_connector_init_helper(
7609                 dm,
7610                 aconnector,
7611                 connector_type,
7612                 link,
7613                 link_index);
7614
7615         drm_connector_attach_encoder(
7616                 &aconnector->base, &aencoder->base);
7617
7618         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7619                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7620                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7621
7622 out_free:
7623         if (res) {
7624                 kfree(i2c);
7625                 aconnector->i2c = NULL;
7626         }
7627         return res;
7628 }
7629
7630 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7631 {
7632         switch (adev->mode_info.num_crtc) {
7633         case 1:
7634                 return 0x1;
7635         case 2:
7636                 return 0x3;
7637         case 3:
7638                 return 0x7;
7639         case 4:
7640                 return 0xf;
7641         case 5:
7642                 return 0x1f;
7643         case 6:
7644         default:
7645                 return 0x3f;
7646         }
7647 }
7648
7649 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7650                                   struct amdgpu_encoder *aencoder,
7651                                   uint32_t link_index)
7652 {
7653         struct amdgpu_device *adev = drm_to_adev(dev);
7654
7655         int res = drm_encoder_init(dev,
7656                                    &aencoder->base,
7657                                    &amdgpu_dm_encoder_funcs,
7658                                    DRM_MODE_ENCODER_TMDS,
7659                                    NULL);
7660
7661         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7662
7663         if (!res)
7664                 aencoder->encoder_id = link_index;
7665         else
7666                 aencoder->encoder_id = -1;
7667
7668         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7669
7670         return res;
7671 }
7672
7673 static void manage_dm_interrupts(struct amdgpu_device *adev,
7674                                  struct amdgpu_crtc *acrtc,
7675                                  bool enable)
7676 {
7677         /*
7678          * We have no guarantee that the frontend index maps to the same
7679          * backend index - some even map to more than one.
7680          *
7681          * TODO: Use a different interrupt or check DC itself for the mapping.
7682          */
7683         int irq_type =
7684                 amdgpu_display_crtc_idx_to_irq_type(
7685                         adev,
7686                         acrtc->crtc_id);
7687
7688         if (enable) {
7689                 drm_crtc_vblank_on(&acrtc->base);
7690                 amdgpu_irq_get(
7691                         adev,
7692                         &adev->pageflip_irq,
7693                         irq_type);
7694 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7695                 amdgpu_irq_get(
7696                         adev,
7697                         &adev->vline0_irq,
7698                         irq_type);
7699 #endif
7700         } else {
7701 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7702                 amdgpu_irq_put(
7703                         adev,
7704                         &adev->vline0_irq,
7705                         irq_type);
7706 #endif
7707                 amdgpu_irq_put(
7708                         adev,
7709                         &adev->pageflip_irq,
7710                         irq_type);
7711                 drm_crtc_vblank_off(&acrtc->base);
7712         }
7713 }
7714
7715 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7716                                       struct amdgpu_crtc *acrtc)
7717 {
7718         int irq_type =
7719                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7720
7721         /**
7722          * This reads the current state for the IRQ and force reapplies
7723          * the setting to hardware.
7724          */
7725         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7726 }
7727
7728 static bool
7729 is_scaling_state_different(const struct dm_connector_state *dm_state,
7730                            const struct dm_connector_state *old_dm_state)
7731 {
7732         if (dm_state->scaling != old_dm_state->scaling)
7733                 return true;
7734         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7735                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7736                         return true;
7737         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7738                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7739                         return true;
7740         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7741                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7742                 return true;
7743         return false;
7744 }
7745
7746 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7747                                             struct drm_crtc_state *old_crtc_state,
7748                                             struct drm_connector_state *new_conn_state,
7749                                             struct drm_connector_state *old_conn_state,
7750                                             const struct drm_connector *connector,
7751                                             struct hdcp_workqueue *hdcp_w)
7752 {
7753         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7754         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7755
7756         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7757                 connector->index, connector->status, connector->dpms);
7758         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7759                 old_conn_state->content_protection, new_conn_state->content_protection);
7760
7761         if (old_crtc_state)
7762                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7763                 old_crtc_state->enable,
7764                 old_crtc_state->active,
7765                 old_crtc_state->mode_changed,
7766                 old_crtc_state->active_changed,
7767                 old_crtc_state->connectors_changed);
7768
7769         if (new_crtc_state)
7770                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7771                 new_crtc_state->enable,
7772                 new_crtc_state->active,
7773                 new_crtc_state->mode_changed,
7774                 new_crtc_state->active_changed,
7775                 new_crtc_state->connectors_changed);
7776
7777         /* hdcp content type change */
7778         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7779             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7780                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7781                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7782                 return true;
7783         }
7784
7785         /* CP is being re enabled, ignore this */
7786         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7787             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7788                 if (new_crtc_state && new_crtc_state->mode_changed) {
7789                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7790                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7791                         return true;
7792                 }
7793                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7794                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7795                 return false;
7796         }
7797
7798         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7799          *
7800          * Handles:     UNDESIRED -> ENABLED
7801          */
7802         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7803             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7804                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7805
7806         /* Stream removed and re-enabled
7807          *
7808          * Can sometimes overlap with the HPD case,
7809          * thus set update_hdcp to false to avoid
7810          * setting HDCP multiple times.
7811          *
7812          * Handles:     DESIRED -> DESIRED (Special case)
7813          */
7814         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7815                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7816                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7817                 dm_con_state->update_hdcp = false;
7818                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7819                         __func__);
7820                 return true;
7821         }
7822
7823         /* Hot-plug, headless s3, dpms
7824          *
7825          * Only start HDCP if the display is connected/enabled.
7826          * update_hdcp flag will be set to false until the next
7827          * HPD comes in.
7828          *
7829          * Handles:     DESIRED -> DESIRED (Special case)
7830          */
7831         if (dm_con_state->update_hdcp &&
7832         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7833         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7834                 dm_con_state->update_hdcp = false;
7835                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7836                         __func__);
7837                 return true;
7838         }
7839
7840         if (old_conn_state->content_protection == new_conn_state->content_protection) {
7841                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7842                         if (new_crtc_state && new_crtc_state->mode_changed) {
7843                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7844                                         __func__);
7845                                 return true;
7846                         }
7847                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7848                                 __func__);
7849                         return false;
7850                 }
7851
7852                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7853                 return false;
7854         }
7855
7856         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7857                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7858                         __func__);
7859                 return true;
7860         }
7861
7862         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7863         return false;
7864 }
7865
7866 static void remove_stream(struct amdgpu_device *adev,
7867                           struct amdgpu_crtc *acrtc,
7868                           struct dc_stream_state *stream)
7869 {
7870         /* this is the update mode case */
7871
7872         acrtc->otg_inst = -1;
7873         acrtc->enabled = false;
7874 }
7875
7876 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7877 {
7878
7879         assert_spin_locked(&acrtc->base.dev->event_lock);
7880         WARN_ON(acrtc->event);
7881
7882         acrtc->event = acrtc->base.state->event;
7883
7884         /* Set the flip status */
7885         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7886
7887         /* Mark this event as consumed */
7888         acrtc->base.state->event = NULL;
7889
7890         drm_dbg_state(acrtc->base.dev,
7891                       "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7892                       acrtc->crtc_id);
7893 }
7894
7895 static void update_freesync_state_on_stream(
7896         struct amdgpu_display_manager *dm,
7897         struct dm_crtc_state *new_crtc_state,
7898         struct dc_stream_state *new_stream,
7899         struct dc_plane_state *surface,
7900         u32 flip_timestamp_in_us)
7901 {
7902         struct mod_vrr_params vrr_params;
7903         struct dc_info_packet vrr_infopacket = {0};
7904         struct amdgpu_device *adev = dm->adev;
7905         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7906         unsigned long flags;
7907         bool pack_sdp_v1_3 = false;
7908         struct amdgpu_dm_connector *aconn;
7909         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7910
7911         if (!new_stream)
7912                 return;
7913
7914         /*
7915          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7916          * For now it's sufficient to just guard against these conditions.
7917          */
7918
7919         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7920                 return;
7921
7922         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7923         vrr_params = acrtc->dm_irq_params.vrr_params;
7924
7925         if (surface) {
7926                 mod_freesync_handle_preflip(
7927                         dm->freesync_module,
7928                         surface,
7929                         new_stream,
7930                         flip_timestamp_in_us,
7931                         &vrr_params);
7932
7933                 if (adev->family < AMDGPU_FAMILY_AI &&
7934                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7935                         mod_freesync_handle_v_update(dm->freesync_module,
7936                                                      new_stream, &vrr_params);
7937
7938                         /* Need to call this before the frame ends. */
7939                         dc_stream_adjust_vmin_vmax(dm->dc,
7940                                                    new_crtc_state->stream,
7941                                                    &vrr_params.adjust);
7942                 }
7943         }
7944
7945         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7946
7947         if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) {
7948                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7949
7950                 if (aconn->vsdb_info.amd_vsdb_version == 1)
7951                         packet_type = PACKET_TYPE_FS_V1;
7952                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7953                         packet_type = PACKET_TYPE_FS_V2;
7954                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7955                         packet_type = PACKET_TYPE_FS_V3;
7956
7957                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7958                                         &new_stream->adaptive_sync_infopacket);
7959         }
7960
7961         mod_freesync_build_vrr_infopacket(
7962                 dm->freesync_module,
7963                 new_stream,
7964                 &vrr_params,
7965                 packet_type,
7966                 TRANSFER_FUNC_UNKNOWN,
7967                 &vrr_infopacket,
7968                 pack_sdp_v1_3);
7969
7970         new_crtc_state->freesync_vrr_info_changed |=
7971                 (memcmp(&new_crtc_state->vrr_infopacket,
7972                         &vrr_infopacket,
7973                         sizeof(vrr_infopacket)) != 0);
7974
7975         acrtc->dm_irq_params.vrr_params = vrr_params;
7976         new_crtc_state->vrr_infopacket = vrr_infopacket;
7977
7978         new_stream->vrr_infopacket = vrr_infopacket;
7979         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7980
7981         if (new_crtc_state->freesync_vrr_info_changed)
7982                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7983                               new_crtc_state->base.crtc->base.id,
7984                               (int)new_crtc_state->base.vrr_enabled,
7985                               (int)vrr_params.state);
7986
7987         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7988 }
7989
7990 static void update_stream_irq_parameters(
7991         struct amdgpu_display_manager *dm,
7992         struct dm_crtc_state *new_crtc_state)
7993 {
7994         struct dc_stream_state *new_stream = new_crtc_state->stream;
7995         struct mod_vrr_params vrr_params;
7996         struct mod_freesync_config config = new_crtc_state->freesync_config;
7997         struct amdgpu_device *adev = dm->adev;
7998         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7999         unsigned long flags;
8000
8001         if (!new_stream)
8002                 return;
8003
8004         /*
8005          * TODO: Determine why min/max totals and vrefresh can be 0 here.
8006          * For now it's sufficient to just guard against these conditions.
8007          */
8008         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
8009                 return;
8010
8011         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8012         vrr_params = acrtc->dm_irq_params.vrr_params;
8013
8014         if (new_crtc_state->vrr_supported &&
8015             config.min_refresh_in_uhz &&
8016             config.max_refresh_in_uhz) {
8017                 /*
8018                  * if freesync compatible mode was set, config.state will be set
8019                  * in atomic check
8020                  */
8021                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
8022                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
8023                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
8024                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
8025                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
8026                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
8027                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
8028                 } else {
8029                         config.state = new_crtc_state->base.vrr_enabled ?
8030                                                      VRR_STATE_ACTIVE_VARIABLE :
8031                                                      VRR_STATE_INACTIVE;
8032                 }
8033         } else {
8034                 config.state = VRR_STATE_UNSUPPORTED;
8035         }
8036
8037         mod_freesync_build_vrr_params(dm->freesync_module,
8038                                       new_stream,
8039                                       &config, &vrr_params);
8040
8041         new_crtc_state->freesync_config = config;
8042         /* Copy state for access from DM IRQ handler */
8043         acrtc->dm_irq_params.freesync_config = config;
8044         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
8045         acrtc->dm_irq_params.vrr_params = vrr_params;
8046         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8047 }
8048
8049 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
8050                                             struct dm_crtc_state *new_state)
8051 {
8052         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
8053         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
8054
8055         if (!old_vrr_active && new_vrr_active) {
8056                 /* Transition VRR inactive -> active:
8057                  * While VRR is active, we must not disable vblank irq, as a
8058                  * reenable after disable would compute bogus vblank/pflip
8059                  * timestamps if it likely happened inside display front-porch.
8060                  *
8061                  * We also need vupdate irq for the actual core vblank handling
8062                  * at end of vblank.
8063                  */
8064                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
8065                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
8066                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
8067                                  __func__, new_state->base.crtc->base.id);
8068         } else if (old_vrr_active && !new_vrr_active) {
8069                 /* Transition VRR active -> inactive:
8070                  * Allow vblank irq disable again for fixed refresh rate.
8071                  */
8072                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
8073                 drm_crtc_vblank_put(new_state->base.crtc);
8074                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
8075                                  __func__, new_state->base.crtc->base.id);
8076         }
8077 }
8078
8079 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
8080 {
8081         struct drm_plane *plane;
8082         struct drm_plane_state *old_plane_state;
8083         int i;
8084
8085         /*
8086          * TODO: Make this per-stream so we don't issue redundant updates for
8087          * commits with multiple streams.
8088          */
8089         for_each_old_plane_in_state(state, plane, old_plane_state, i)
8090                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
8091                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
8092 }
8093
8094 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
8095 {
8096         struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
8097
8098         return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
8099 }
8100
8101 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
8102                                     struct drm_device *dev,
8103                                     struct amdgpu_display_manager *dm,
8104                                     struct drm_crtc *pcrtc,
8105                                     bool wait_for_vblank)
8106 {
8107         u32 i;
8108         u64 timestamp_ns = ktime_get_ns();
8109         struct drm_plane *plane;
8110         struct drm_plane_state *old_plane_state, *new_plane_state;
8111         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
8112         struct drm_crtc_state *new_pcrtc_state =
8113                         drm_atomic_get_new_crtc_state(state, pcrtc);
8114         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
8115         struct dm_crtc_state *dm_old_crtc_state =
8116                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
8117         int planes_count = 0, vpos, hpos;
8118         unsigned long flags;
8119         u32 target_vblank, last_flip_vblank;
8120         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
8121         bool cursor_update = false;
8122         bool pflip_present = false;
8123         bool dirty_rects_changed = false;
8124         struct {
8125                 struct dc_surface_update surface_updates[MAX_SURFACES];
8126                 struct dc_plane_info plane_infos[MAX_SURFACES];
8127                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
8128                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
8129                 struct dc_stream_update stream_update;
8130         } *bundle;
8131
8132         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8133
8134         if (!bundle) {
8135                 drm_err(dev, "Failed to allocate update bundle\n");
8136                 goto cleanup;
8137         }
8138
8139         /*
8140          * Disable the cursor first if we're disabling all the planes.
8141          * It'll remain on the screen after the planes are re-enabled
8142          * if we don't.
8143          */
8144         if (acrtc_state->active_planes == 0)
8145                 amdgpu_dm_commit_cursors(state);
8146
8147         /* update planes when needed */
8148         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8149                 struct drm_crtc *crtc = new_plane_state->crtc;
8150                 struct drm_crtc_state *new_crtc_state;
8151                 struct drm_framebuffer *fb = new_plane_state->fb;
8152                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8153                 bool plane_needs_flip;
8154                 struct dc_plane_state *dc_plane;
8155                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8156
8157                 /* Cursor plane is handled after stream updates */
8158                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
8159                         if ((fb && crtc == pcrtc) ||
8160                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
8161                                 cursor_update = true;
8162
8163                         continue;
8164                 }
8165
8166                 if (!fb || !crtc || pcrtc != crtc)
8167                         continue;
8168
8169                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8170                 if (!new_crtc_state->active)
8171                         continue;
8172
8173                 dc_plane = dm_new_plane_state->dc_state;
8174                 if (!dc_plane)
8175                         continue;
8176
8177                 bundle->surface_updates[planes_count].surface = dc_plane;
8178                 if (new_pcrtc_state->color_mgmt_changed) {
8179                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8180                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8181                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8182                 }
8183
8184                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
8185                                      &bundle->scaling_infos[planes_count]);
8186
8187                 bundle->surface_updates[planes_count].scaling_info =
8188                         &bundle->scaling_infos[planes_count];
8189
8190                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8191
8192                 pflip_present = pflip_present || plane_needs_flip;
8193
8194                 if (!plane_needs_flip) {
8195                         planes_count += 1;
8196                         continue;
8197                 }
8198
8199                 fill_dc_plane_info_and_addr(
8200                         dm->adev, new_plane_state,
8201                         afb->tiling_flags,
8202                         &bundle->plane_infos[planes_count],
8203                         &bundle->flip_addrs[planes_count].address,
8204                         afb->tmz_surface, false);
8205
8206                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8207                                  new_plane_state->plane->index,
8208                                  bundle->plane_infos[planes_count].dcc.enable);
8209
8210                 bundle->surface_updates[planes_count].plane_info =
8211                         &bundle->plane_infos[planes_count];
8212
8213                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled ||
8214                     acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
8215                         fill_dc_dirty_rects(plane, old_plane_state,
8216                                             new_plane_state, new_crtc_state,
8217                                             &bundle->flip_addrs[planes_count],
8218                                             &dirty_rects_changed);
8219
8220                         /*
8221                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8222                          * and enabled it again after dirty regions are stable to avoid video glitch.
8223                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8224                          * during the PSR-SU was disabled.
8225                          */
8226                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8227                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8228 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8229                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8230 #endif
8231                             dirty_rects_changed) {
8232                                 mutex_lock(&dm->dc_lock);
8233                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8234                                 timestamp_ns;
8235                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8236                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8237                                 mutex_unlock(&dm->dc_lock);
8238                         }
8239                 }
8240
8241                 /*
8242                  * Only allow immediate flips for fast updates that don't
8243                  * change memory domain, FB pitch, DCC state, rotation or
8244                  * mirroring.
8245                  *
8246                  * dm_crtc_helper_atomic_check() only accepts async flips with
8247                  * fast updates.
8248                  */
8249                 if (crtc->state->async_flip &&
8250                     (acrtc_state->update_type != UPDATE_TYPE_FAST ||
8251                      get_mem_type(old_plane_state->fb) != get_mem_type(fb)))
8252                         drm_warn_once(state->dev,
8253                                       "[PLANE:%d:%s] async flip with non-fast update\n",
8254                                       plane->base.id, plane->name);
8255
8256                 bundle->flip_addrs[planes_count].flip_immediate =
8257                         crtc->state->async_flip &&
8258                         acrtc_state->update_type == UPDATE_TYPE_FAST &&
8259                         get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8260
8261                 timestamp_ns = ktime_get_ns();
8262                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8263                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8264                 bundle->surface_updates[planes_count].surface = dc_plane;
8265
8266                 if (!bundle->surface_updates[planes_count].surface) {
8267                         DRM_ERROR("No surface for CRTC: id=%d\n",
8268                                         acrtc_attach->crtc_id);
8269                         continue;
8270                 }
8271
8272                 if (plane == pcrtc->primary)
8273                         update_freesync_state_on_stream(
8274                                 dm,
8275                                 acrtc_state,
8276                                 acrtc_state->stream,
8277                                 dc_plane,
8278                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8279
8280                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8281                                  __func__,
8282                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8283                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8284
8285                 planes_count += 1;
8286
8287         }
8288
8289         if (pflip_present) {
8290                 if (!vrr_active) {
8291                         /* Use old throttling in non-vrr fixed refresh rate mode
8292                          * to keep flip scheduling based on target vblank counts
8293                          * working in a backwards compatible way, e.g., for
8294                          * clients using the GLX_OML_sync_control extension or
8295                          * DRI3/Present extension with defined target_msc.
8296                          */
8297                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8298                 } else {
8299                         /* For variable refresh rate mode only:
8300                          * Get vblank of last completed flip to avoid > 1 vrr
8301                          * flips per video frame by use of throttling, but allow
8302                          * flip programming anywhere in the possibly large
8303                          * variable vrr vblank interval for fine-grained flip
8304                          * timing control and more opportunity to avoid stutter
8305                          * on late submission of flips.
8306                          */
8307                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8308                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8309                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8310                 }
8311
8312                 target_vblank = last_flip_vblank + wait_for_vblank;
8313
8314                 /*
8315                  * Wait until we're out of the vertical blank period before the one
8316                  * targeted by the flip
8317                  */
8318                 while ((acrtc_attach->enabled &&
8319                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8320                                                             0, &vpos, &hpos, NULL,
8321                                                             NULL, &pcrtc->hwmode)
8322                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8323                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8324                         (int)(target_vblank -
8325                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8326                         usleep_range(1000, 1100);
8327                 }
8328
8329                 /**
8330                  * Prepare the flip event for the pageflip interrupt to handle.
8331                  *
8332                  * This only works in the case where we've already turned on the
8333                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8334                  * from 0 -> n planes we have to skip a hardware generated event
8335                  * and rely on sending it from software.
8336                  */
8337                 if (acrtc_attach->base.state->event &&
8338                     acrtc_state->active_planes > 0) {
8339                         drm_crtc_vblank_get(pcrtc);
8340
8341                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8342
8343                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8344                         prepare_flip_isr(acrtc_attach);
8345
8346                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8347                 }
8348
8349                 if (acrtc_state->stream) {
8350                         if (acrtc_state->freesync_vrr_info_changed)
8351                                 bundle->stream_update.vrr_infopacket =
8352                                         &acrtc_state->stream->vrr_infopacket;
8353                 }
8354         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8355                    acrtc_attach->base.state->event) {
8356                 drm_crtc_vblank_get(pcrtc);
8357
8358                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8359
8360                 acrtc_attach->event = acrtc_attach->base.state->event;
8361                 acrtc_attach->base.state->event = NULL;
8362
8363                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8364         }
8365
8366         /* Update the planes if changed or disable if we don't have any. */
8367         if ((planes_count || acrtc_state->active_planes == 0) &&
8368                 acrtc_state->stream) {
8369                 /*
8370                  * If PSR or idle optimizations are enabled then flush out
8371                  * any pending work before hardware programming.
8372                  */
8373                 if (dm->vblank_control_workqueue)
8374                         flush_workqueue(dm->vblank_control_workqueue);
8375
8376                 bundle->stream_update.stream = acrtc_state->stream;
8377                 if (new_pcrtc_state->mode_changed) {
8378                         bundle->stream_update.src = acrtc_state->stream->src;
8379                         bundle->stream_update.dst = acrtc_state->stream->dst;
8380                 }
8381
8382                 if (new_pcrtc_state->color_mgmt_changed) {
8383                         /*
8384                          * TODO: This isn't fully correct since we've actually
8385                          * already modified the stream in place.
8386                          */
8387                         bundle->stream_update.gamut_remap =
8388                                 &acrtc_state->stream->gamut_remap_matrix;
8389                         bundle->stream_update.output_csc_transform =
8390                                 &acrtc_state->stream->csc_color_matrix;
8391                         bundle->stream_update.out_transfer_func =
8392                                 acrtc_state->stream->out_transfer_func;
8393                 }
8394
8395                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8396                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8397                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8398
8399                 mutex_lock(&dm->dc_lock);
8400                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8401                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8402                         amdgpu_dm_psr_disable(acrtc_state->stream);
8403                 mutex_unlock(&dm->dc_lock);
8404
8405                 /*
8406                  * If FreeSync state on the stream has changed then we need to
8407                  * re-adjust the min/max bounds now that DC doesn't handle this
8408                  * as part of commit.
8409                  */
8410                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8411                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8412                         dc_stream_adjust_vmin_vmax(
8413                                 dm->dc, acrtc_state->stream,
8414                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8415                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8416                 }
8417                 mutex_lock(&dm->dc_lock);
8418                 update_planes_and_stream_adapter(dm->dc,
8419                                          acrtc_state->update_type,
8420                                          planes_count,
8421                                          acrtc_state->stream,
8422                                          &bundle->stream_update,
8423                                          bundle->surface_updates);
8424
8425                 /**
8426                  * Enable or disable the interrupts on the backend.
8427                  *
8428                  * Most pipes are put into power gating when unused.
8429                  *
8430                  * When power gating is enabled on a pipe we lose the
8431                  * interrupt enablement state when power gating is disabled.
8432                  *
8433                  * So we need to update the IRQ control state in hardware
8434                  * whenever the pipe turns on (since it could be previously
8435                  * power gated) or off (since some pipes can't be power gated
8436                  * on some ASICs).
8437                  */
8438                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8439                         dm_update_pflip_irq_state(drm_to_adev(dev),
8440                                                   acrtc_attach);
8441
8442                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8443                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8444                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8445                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8446
8447                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8448                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8449                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8450                         struct amdgpu_dm_connector *aconn =
8451                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8452
8453                         if (aconn->psr_skip_count > 0)
8454                                 aconn->psr_skip_count--;
8455
8456                         /* Allow PSR when skip count is 0. */
8457                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8458
8459                         /*
8460                          * If sink supports PSR SU, there is no need to rely on
8461                          * a vblank event disable request to enable PSR. PSR SU
8462                          * can be enabled immediately once OS demonstrates an
8463                          * adequate number of fast atomic commits to notify KMD
8464                          * of update events. See `vblank_control_worker()`.
8465                          */
8466                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8467                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8468 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8469                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8470 #endif
8471                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8472                             (timestamp_ns -
8473                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8474                             500000000)
8475                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8476                 } else {
8477                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8478                 }
8479
8480                 mutex_unlock(&dm->dc_lock);
8481         }
8482
8483         /*
8484          * Update cursor state *after* programming all the planes.
8485          * This avoids redundant programming in the case where we're going
8486          * to be disabling a single plane - those pipes are being disabled.
8487          */
8488         if (acrtc_state->active_planes)
8489                 amdgpu_dm_commit_cursors(state);
8490
8491 cleanup:
8492         kfree(bundle);
8493 }
8494
8495 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8496                                    struct drm_atomic_state *state)
8497 {
8498         struct amdgpu_device *adev = drm_to_adev(dev);
8499         struct amdgpu_dm_connector *aconnector;
8500         struct drm_connector *connector;
8501         struct drm_connector_state *old_con_state, *new_con_state;
8502         struct drm_crtc_state *new_crtc_state;
8503         struct dm_crtc_state *new_dm_crtc_state;
8504         const struct dc_stream_status *status;
8505         int i, inst;
8506
8507         /* Notify device removals. */
8508         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8509                 if (old_con_state->crtc != new_con_state->crtc) {
8510                         /* CRTC changes require notification. */
8511                         goto notify;
8512                 }
8513
8514                 if (!new_con_state->crtc)
8515                         continue;
8516
8517                 new_crtc_state = drm_atomic_get_new_crtc_state(
8518                         state, new_con_state->crtc);
8519
8520                 if (!new_crtc_state)
8521                         continue;
8522
8523                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8524                         continue;
8525
8526 notify:
8527                 aconnector = to_amdgpu_dm_connector(connector);
8528
8529                 mutex_lock(&adev->dm.audio_lock);
8530                 inst = aconnector->audio_inst;
8531                 aconnector->audio_inst = -1;
8532                 mutex_unlock(&adev->dm.audio_lock);
8533
8534                 amdgpu_dm_audio_eld_notify(adev, inst);
8535         }
8536
8537         /* Notify audio device additions. */
8538         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8539                 if (!new_con_state->crtc)
8540                         continue;
8541
8542                 new_crtc_state = drm_atomic_get_new_crtc_state(
8543                         state, new_con_state->crtc);
8544
8545                 if (!new_crtc_state)
8546                         continue;
8547
8548                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8549                         continue;
8550
8551                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8552                 if (!new_dm_crtc_state->stream)
8553                         continue;
8554
8555                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8556                 if (!status)
8557                         continue;
8558
8559                 aconnector = to_amdgpu_dm_connector(connector);
8560
8561                 mutex_lock(&adev->dm.audio_lock);
8562                 inst = status->audio_inst;
8563                 aconnector->audio_inst = inst;
8564                 mutex_unlock(&adev->dm.audio_lock);
8565
8566                 amdgpu_dm_audio_eld_notify(adev, inst);
8567         }
8568 }
8569
8570 /*
8571  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8572  * @crtc_state: the DRM CRTC state
8573  * @stream_state: the DC stream state.
8574  *
8575  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8576  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8577  */
8578 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8579                                                 struct dc_stream_state *stream_state)
8580 {
8581         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8582 }
8583
8584 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
8585                                         struct dc_state *dc_state)
8586 {
8587         struct drm_device *dev = state->dev;
8588         struct amdgpu_device *adev = drm_to_adev(dev);
8589         struct amdgpu_display_manager *dm = &adev->dm;
8590         struct drm_crtc *crtc;
8591         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8592         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8593         bool mode_set_reset_required = false;
8594         u32 i;
8595
8596         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8597                                       new_crtc_state, i) {
8598                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8599
8600                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8601
8602                 if (old_crtc_state->active &&
8603                     (!new_crtc_state->active ||
8604                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8605                         manage_dm_interrupts(adev, acrtc, false);
8606                         dc_stream_release(dm_old_crtc_state->stream);
8607                 }
8608         }
8609
8610         drm_atomic_helper_calc_timestamping_constants(state);
8611
8612         /* update changed items */
8613         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8614                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8615
8616                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8617                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8618
8619                 drm_dbg_state(state->dev,
8620                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
8621                         acrtc->crtc_id,
8622                         new_crtc_state->enable,
8623                         new_crtc_state->active,
8624                         new_crtc_state->planes_changed,
8625                         new_crtc_state->mode_changed,
8626                         new_crtc_state->active_changed,
8627                         new_crtc_state->connectors_changed);
8628
8629                 /* Disable cursor if disabling crtc */
8630                 if (old_crtc_state->active && !new_crtc_state->active) {
8631                         struct dc_cursor_position position;
8632
8633                         memset(&position, 0, sizeof(position));
8634                         mutex_lock(&dm->dc_lock);
8635                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8636                         mutex_unlock(&dm->dc_lock);
8637                 }
8638
8639                 /* Copy all transient state flags into dc state */
8640                 if (dm_new_crtc_state->stream) {
8641                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8642                                                             dm_new_crtc_state->stream);
8643                 }
8644
8645                 /* handles headless hotplug case, updating new_state and
8646                  * aconnector as needed
8647                  */
8648
8649                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8650
8651                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8652
8653                         if (!dm_new_crtc_state->stream) {
8654                                 /*
8655                                  * this could happen because of issues with
8656                                  * userspace notifications delivery.
8657                                  * In this case userspace tries to set mode on
8658                                  * display which is disconnected in fact.
8659                                  * dc_sink is NULL in this case on aconnector.
8660                                  * We expect reset mode will come soon.
8661                                  *
8662                                  * This can also happen when unplug is done
8663                                  * during resume sequence ended
8664                                  *
8665                                  * In this case, we want to pretend we still
8666                                  * have a sink to keep the pipe running so that
8667                                  * hw state is consistent with the sw state
8668                                  */
8669                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8670                                                 __func__, acrtc->base.base.id);
8671                                 continue;
8672                         }
8673
8674                         if (dm_old_crtc_state->stream)
8675                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8676
8677                         pm_runtime_get_noresume(dev->dev);
8678
8679                         acrtc->enabled = true;
8680                         acrtc->hw_mode = new_crtc_state->mode;
8681                         crtc->hwmode = new_crtc_state->mode;
8682                         mode_set_reset_required = true;
8683                 } else if (modereset_required(new_crtc_state)) {
8684                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8685                         /* i.e. reset mode */
8686                         if (dm_old_crtc_state->stream)
8687                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8688
8689                         mode_set_reset_required = true;
8690                 }
8691         } /* for_each_crtc_in_state() */
8692
8693         /* if there mode set or reset, disable eDP PSR */
8694         if (mode_set_reset_required) {
8695                 if (dm->vblank_control_workqueue)
8696                         flush_workqueue(dm->vblank_control_workqueue);
8697
8698                 amdgpu_dm_psr_disable_all(dm);
8699         }
8700
8701         dm_enable_per_frame_crtc_master_sync(dc_state);
8702         mutex_lock(&dm->dc_lock);
8703         WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8704
8705         /* Allow idle optimization when vblank count is 0 for display off */
8706         if (dm->active_vblank_irq_count == 0)
8707                 dc_allow_idle_optimizations(dm->dc, true);
8708         mutex_unlock(&dm->dc_lock);
8709
8710         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8711                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8712
8713                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8714
8715                 if (dm_new_crtc_state->stream != NULL) {
8716                         const struct dc_stream_status *status =
8717                                         dc_stream_get_status(dm_new_crtc_state->stream);
8718
8719                         if (!status)
8720                                 status = dc_stream_get_status_from_state(dc_state,
8721                                                                          dm_new_crtc_state->stream);
8722                         if (!status)
8723                                 drm_err(dev,
8724                                         "got no status for stream %p on acrtc%p\n",
8725                                         dm_new_crtc_state->stream, acrtc);
8726                         else
8727                                 acrtc->otg_inst = status->primary_otg_inst;
8728                 }
8729         }
8730 }
8731
8732 /**
8733  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8734  * @state: The atomic state to commit
8735  *
8736  * This will tell DC to commit the constructed DC state from atomic_check,
8737  * programming the hardware. Any failures here implies a hardware failure, since
8738  * atomic check should have filtered anything non-kosher.
8739  */
8740 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8741 {
8742         struct drm_device *dev = state->dev;
8743         struct amdgpu_device *adev = drm_to_adev(dev);
8744         struct amdgpu_display_manager *dm = &adev->dm;
8745         struct dm_atomic_state *dm_state;
8746         struct dc_state *dc_state = NULL;
8747         u32 i, j;
8748         struct drm_crtc *crtc;
8749         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8750         unsigned long flags;
8751         bool wait_for_vblank = true;
8752         struct drm_connector *connector;
8753         struct drm_connector_state *old_con_state, *new_con_state;
8754         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8755         int crtc_disable_count = 0;
8756
8757         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8758
8759         if (dm->dc->caps.ips_support) {
8760                 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8761                         if (new_con_state->crtc &&
8762                                 new_con_state->crtc->state->active &&
8763                                 drm_atomic_crtc_needs_modeset(new_con_state->crtc->state)) {
8764                                 dc_dmub_srv_exit_low_power_state(dm->dc);
8765                                 break;
8766                         }
8767                 }
8768         }
8769
8770         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8771         drm_dp_mst_atomic_wait_for_dependencies(state);
8772
8773         dm_state = dm_atomic_get_new_state(state);
8774         if (dm_state && dm_state->context) {
8775                 dc_state = dm_state->context;
8776                 amdgpu_dm_commit_streams(state, dc_state);
8777         }
8778
8779         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8780                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8781                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8782                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8783
8784                 if (!adev->dm.hdcp_workqueue)
8785                         continue;
8786
8787                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8788
8789                 if (!connector)
8790                         continue;
8791
8792                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8793                         connector->index, connector->status, connector->dpms);
8794                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8795                         old_con_state->content_protection, new_con_state->content_protection);
8796
8797                 if (aconnector->dc_sink) {
8798                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8799                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8800                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8801                                 aconnector->dc_sink->edid_caps.display_name);
8802                         }
8803                 }
8804
8805                 new_crtc_state = NULL;
8806                 old_crtc_state = NULL;
8807
8808                 if (acrtc) {
8809                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8810                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8811                 }
8812
8813                 if (old_crtc_state)
8814                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8815                         old_crtc_state->enable,
8816                         old_crtc_state->active,
8817                         old_crtc_state->mode_changed,
8818                         old_crtc_state->active_changed,
8819                         old_crtc_state->connectors_changed);
8820
8821                 if (new_crtc_state)
8822                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8823                         new_crtc_state->enable,
8824                         new_crtc_state->active,
8825                         new_crtc_state->mode_changed,
8826                         new_crtc_state->active_changed,
8827                         new_crtc_state->connectors_changed);
8828         }
8829
8830         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8831                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8832                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8833                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8834
8835                 if (!adev->dm.hdcp_workqueue)
8836                         continue;
8837
8838                 new_crtc_state = NULL;
8839                 old_crtc_state = NULL;
8840
8841                 if (acrtc) {
8842                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8843                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8844                 }
8845
8846                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8847
8848                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8849                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8850                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8851                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8852                         dm_new_con_state->update_hdcp = true;
8853                         continue;
8854                 }
8855
8856                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8857                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
8858                         /* when display is unplugged from mst hub, connctor will
8859                          * be destroyed within dm_dp_mst_connector_destroy. connector
8860                          * hdcp perperties, like type, undesired, desired, enabled,
8861                          * will be lost. So, save hdcp properties into hdcp_work within
8862                          * amdgpu_dm_atomic_commit_tail. if the same display is
8863                          * plugged back with same display index, its hdcp properties
8864                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8865                          */
8866
8867                         bool enable_encryption = false;
8868
8869                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8870                                 enable_encryption = true;
8871
8872                         if (aconnector->dc_link && aconnector->dc_sink &&
8873                                 aconnector->dc_link->type == dc_connection_mst_branch) {
8874                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8875                                 struct hdcp_workqueue *hdcp_w =
8876                                         &hdcp_work[aconnector->dc_link->link_index];
8877
8878                                 hdcp_w->hdcp_content_type[connector->index] =
8879                                         new_con_state->hdcp_content_type;
8880                                 hdcp_w->content_protection[connector->index] =
8881                                         new_con_state->content_protection;
8882                         }
8883
8884                         if (new_crtc_state && new_crtc_state->mode_changed &&
8885                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8886                                 enable_encryption = true;
8887
8888                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8889
8890                         hdcp_update_display(
8891                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8892                                 new_con_state->hdcp_content_type, enable_encryption);
8893                 }
8894         }
8895
8896         /* Handle connector state changes */
8897         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8898                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8899                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8900                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8901                 struct dc_surface_update *dummy_updates;
8902                 struct dc_stream_update stream_update;
8903                 struct dc_info_packet hdr_packet;
8904                 struct dc_stream_status *status = NULL;
8905                 bool abm_changed, hdr_changed, scaling_changed;
8906
8907                 memset(&stream_update, 0, sizeof(stream_update));
8908
8909                 if (acrtc) {
8910                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8911                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8912                 }
8913
8914                 /* Skip any modesets/resets */
8915                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8916                         continue;
8917
8918                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8919                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8920
8921                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8922                                                              dm_old_con_state);
8923
8924                 abm_changed = dm_new_crtc_state->abm_level !=
8925                               dm_old_crtc_state->abm_level;
8926
8927                 hdr_changed =
8928                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8929
8930                 if (!scaling_changed && !abm_changed && !hdr_changed)
8931                         continue;
8932
8933                 stream_update.stream = dm_new_crtc_state->stream;
8934                 if (scaling_changed) {
8935                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8936                                         dm_new_con_state, dm_new_crtc_state->stream);
8937
8938                         stream_update.src = dm_new_crtc_state->stream->src;
8939                         stream_update.dst = dm_new_crtc_state->stream->dst;
8940                 }
8941
8942                 if (abm_changed) {
8943                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8944
8945                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8946                 }
8947
8948                 if (hdr_changed) {
8949                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8950                         stream_update.hdr_static_metadata = &hdr_packet;
8951                 }
8952
8953                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8954
8955                 if (WARN_ON(!status))
8956                         continue;
8957
8958                 WARN_ON(!status->plane_count);
8959
8960                 /*
8961                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8962                  * Here we create an empty update on each plane.
8963                  * To fix this, DC should permit updating only stream properties.
8964                  */
8965                 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);
8966                 for (j = 0; j < status->plane_count; j++)
8967                         dummy_updates[j].surface = status->plane_states[0];
8968
8969
8970                 mutex_lock(&dm->dc_lock);
8971                 dc_update_planes_and_stream(dm->dc,
8972                                             dummy_updates,
8973                                             status->plane_count,
8974                                             dm_new_crtc_state->stream,
8975                                             &stream_update);
8976                 mutex_unlock(&dm->dc_lock);
8977                 kfree(dummy_updates);
8978         }
8979
8980         /**
8981          * Enable interrupts for CRTCs that are newly enabled or went through
8982          * a modeset. It was intentionally deferred until after the front end
8983          * state was modified to wait until the OTG was on and so the IRQ
8984          * handlers didn't access stale or invalid state.
8985          */
8986         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8987                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8988 #ifdef CONFIG_DEBUG_FS
8989                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8990 #endif
8991                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8992                 if (old_crtc_state->active && !new_crtc_state->active)
8993                         crtc_disable_count++;
8994
8995                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8996                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8997
8998                 /* For freesync config update on crtc state and params for irq */
8999                 update_stream_irq_parameters(dm, dm_new_crtc_state);
9000
9001 #ifdef CONFIG_DEBUG_FS
9002                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9003                 cur_crc_src = acrtc->dm_irq_params.crc_src;
9004                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9005 #endif
9006
9007                 if (new_crtc_state->active &&
9008                     (!old_crtc_state->active ||
9009                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
9010                         dc_stream_retain(dm_new_crtc_state->stream);
9011                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
9012                         manage_dm_interrupts(adev, acrtc, true);
9013                 }
9014                 /* Handle vrr on->off / off->on transitions */
9015                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
9016
9017 #ifdef CONFIG_DEBUG_FS
9018                 if (new_crtc_state->active &&
9019                     (!old_crtc_state->active ||
9020                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
9021                         /**
9022                          * Frontend may have changed so reapply the CRC capture
9023                          * settings for the stream.
9024                          */
9025                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
9026 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
9027                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
9028                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9029                                         acrtc->dm_irq_params.window_param.update_win = true;
9030
9031                                         /**
9032                                          * It takes 2 frames for HW to stably generate CRC when
9033                                          * resuming from suspend, so we set skip_frame_cnt 2.
9034                                          */
9035                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
9036                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9037                                 }
9038 #endif
9039                                 if (amdgpu_dm_crtc_configure_crc_source(
9040                                         crtc, dm_new_crtc_state, cur_crc_src))
9041                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
9042                         }
9043                 }
9044 #endif
9045         }
9046
9047         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
9048                 if (new_crtc_state->async_flip)
9049                         wait_for_vblank = false;
9050
9051         /* update planes when needed per crtc*/
9052         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
9053                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9054
9055                 if (dm_new_crtc_state->stream)
9056                         amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);
9057         }
9058
9059         /* Update audio instances for each connector. */
9060         amdgpu_dm_commit_audio(dev, state);
9061
9062         /* restore the backlight level */
9063         for (i = 0; i < dm->num_of_edps; i++) {
9064                 if (dm->backlight_dev[i] &&
9065                     (dm->actual_brightness[i] != dm->brightness[i]))
9066                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
9067         }
9068
9069         /*
9070          * send vblank event on all events not handled in flip and
9071          * mark consumed event for drm_atomic_helper_commit_hw_done
9072          */
9073         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9074         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9075
9076                 if (new_crtc_state->event)
9077                         drm_send_event_locked(dev, &new_crtc_state->event->base);
9078
9079                 new_crtc_state->event = NULL;
9080         }
9081         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9082
9083         /* Signal HW programming completion */
9084         drm_atomic_helper_commit_hw_done(state);
9085
9086         if (wait_for_vblank)
9087                 drm_atomic_helper_wait_for_flip_done(dev, state);
9088
9089         drm_atomic_helper_cleanup_planes(dev, state);
9090
9091         /* Don't free the memory if we are hitting this as part of suspend.
9092          * This way we don't free any memory during suspend; see
9093          * amdgpu_bo_free_kernel().  The memory will be freed in the first
9094          * non-suspend modeset or when the driver is torn down.
9095          */
9096         if (!adev->in_suspend) {
9097                 /* return the stolen vga memory back to VRAM */
9098                 if (!adev->mman.keep_stolen_vga_memory)
9099                         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
9100                 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
9101         }
9102
9103         /*
9104          * Finally, drop a runtime PM reference for each newly disabled CRTC,
9105          * so we can put the GPU into runtime suspend if we're not driving any
9106          * displays anymore
9107          */
9108         for (i = 0; i < crtc_disable_count; i++)
9109                 pm_runtime_put_autosuspend(dev->dev);
9110         pm_runtime_mark_last_busy(dev->dev);
9111 }
9112
9113 static int dm_force_atomic_commit(struct drm_connector *connector)
9114 {
9115         int ret = 0;
9116         struct drm_device *ddev = connector->dev;
9117         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
9118         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9119         struct drm_plane *plane = disconnected_acrtc->base.primary;
9120         struct drm_connector_state *conn_state;
9121         struct drm_crtc_state *crtc_state;
9122         struct drm_plane_state *plane_state;
9123
9124         if (!state)
9125                 return -ENOMEM;
9126
9127         state->acquire_ctx = ddev->mode_config.acquire_ctx;
9128
9129         /* Construct an atomic state to restore previous display setting */
9130
9131         /*
9132          * Attach connectors to drm_atomic_state
9133          */
9134         conn_state = drm_atomic_get_connector_state(state, connector);
9135
9136         ret = PTR_ERR_OR_ZERO(conn_state);
9137         if (ret)
9138                 goto out;
9139
9140         /* Attach crtc to drm_atomic_state*/
9141         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
9142
9143         ret = PTR_ERR_OR_ZERO(crtc_state);
9144         if (ret)
9145                 goto out;
9146
9147         /* force a restore */
9148         crtc_state->mode_changed = true;
9149
9150         /* Attach plane to drm_atomic_state */
9151         plane_state = drm_atomic_get_plane_state(state, plane);
9152
9153         ret = PTR_ERR_OR_ZERO(plane_state);
9154         if (ret)
9155                 goto out;
9156
9157         /* Call commit internally with the state we just constructed */
9158         ret = drm_atomic_commit(state);
9159
9160 out:
9161         drm_atomic_state_put(state);
9162         if (ret)
9163                 DRM_ERROR("Restoring old state failed with %i\n", ret);
9164
9165         return ret;
9166 }
9167
9168 /*
9169  * This function handles all cases when set mode does not come upon hotplug.
9170  * This includes when a display is unplugged then plugged back into the
9171  * same port and when running without usermode desktop manager supprot
9172  */
9173 void dm_restore_drm_connector_state(struct drm_device *dev,
9174                                     struct drm_connector *connector)
9175 {
9176         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9177         struct amdgpu_crtc *disconnected_acrtc;
9178         struct dm_crtc_state *acrtc_state;
9179
9180         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9181                 return;
9182
9183         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9184         if (!disconnected_acrtc)
9185                 return;
9186
9187         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9188         if (!acrtc_state->stream)
9189                 return;
9190
9191         /*
9192          * If the previous sink is not released and different from the current,
9193          * we deduce we are in a state where we can not rely on usermode call
9194          * to turn on the display, so we do it here
9195          */
9196         if (acrtc_state->stream->sink != aconnector->dc_sink)
9197                 dm_force_atomic_commit(&aconnector->base);
9198 }
9199
9200 /*
9201  * Grabs all modesetting locks to serialize against any blocking commits,
9202  * Waits for completion of all non blocking commits.
9203  */
9204 static int do_aquire_global_lock(struct drm_device *dev,
9205                                  struct drm_atomic_state *state)
9206 {
9207         struct drm_crtc *crtc;
9208         struct drm_crtc_commit *commit;
9209         long ret;
9210
9211         /*
9212          * Adding all modeset locks to aquire_ctx will
9213          * ensure that when the framework release it the
9214          * extra locks we are locking here will get released to
9215          */
9216         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9217         if (ret)
9218                 return ret;
9219
9220         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9221                 spin_lock(&crtc->commit_lock);
9222                 commit = list_first_entry_or_null(&crtc->commit_list,
9223                                 struct drm_crtc_commit, commit_entry);
9224                 if (commit)
9225                         drm_crtc_commit_get(commit);
9226                 spin_unlock(&crtc->commit_lock);
9227
9228                 if (!commit)
9229                         continue;
9230
9231                 /*
9232                  * Make sure all pending HW programming completed and
9233                  * page flips done
9234                  */
9235                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9236
9237                 if (ret > 0)
9238                         ret = wait_for_completion_interruptible_timeout(
9239                                         &commit->flip_done, 10*HZ);
9240
9241                 if (ret == 0)
9242                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",
9243                                   crtc->base.id, crtc->name);
9244
9245                 drm_crtc_commit_put(commit);
9246         }
9247
9248         return ret < 0 ? ret : 0;
9249 }
9250
9251 static void get_freesync_config_for_crtc(
9252         struct dm_crtc_state *new_crtc_state,
9253         struct dm_connector_state *new_con_state)
9254 {
9255         struct mod_freesync_config config = {0};
9256         struct amdgpu_dm_connector *aconnector =
9257                         to_amdgpu_dm_connector(new_con_state->base.connector);
9258         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9259         int vrefresh = drm_mode_vrefresh(mode);
9260         bool fs_vid_mode = false;
9261
9262         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9263                                         vrefresh >= aconnector->min_vfreq &&
9264                                         vrefresh <= aconnector->max_vfreq;
9265
9266         if (new_crtc_state->vrr_supported) {
9267                 new_crtc_state->stream->ignore_msa_timing_param = true;
9268                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9269
9270                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9271                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9272                 config.vsif_supported = true;
9273                 config.btr = true;
9274
9275                 if (fs_vid_mode) {
9276                         config.state = VRR_STATE_ACTIVE_FIXED;
9277                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9278                         goto out;
9279                 } else if (new_crtc_state->base.vrr_enabled) {
9280                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9281                 } else {
9282                         config.state = VRR_STATE_INACTIVE;
9283                 }
9284         }
9285 out:
9286         new_crtc_state->freesync_config = config;
9287 }
9288
9289 static void reset_freesync_config_for_crtc(
9290         struct dm_crtc_state *new_crtc_state)
9291 {
9292         new_crtc_state->vrr_supported = false;
9293
9294         memset(&new_crtc_state->vrr_infopacket, 0,
9295                sizeof(new_crtc_state->vrr_infopacket));
9296 }
9297
9298 static bool
9299 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9300                                  struct drm_crtc_state *new_crtc_state)
9301 {
9302         const struct drm_display_mode *old_mode, *new_mode;
9303
9304         if (!old_crtc_state || !new_crtc_state)
9305                 return false;
9306
9307         old_mode = &old_crtc_state->mode;
9308         new_mode = &new_crtc_state->mode;
9309
9310         if (old_mode->clock       == new_mode->clock &&
9311             old_mode->hdisplay    == new_mode->hdisplay &&
9312             old_mode->vdisplay    == new_mode->vdisplay &&
9313             old_mode->htotal      == new_mode->htotal &&
9314             old_mode->vtotal      != new_mode->vtotal &&
9315             old_mode->hsync_start == new_mode->hsync_start &&
9316             old_mode->vsync_start != new_mode->vsync_start &&
9317             old_mode->hsync_end   == new_mode->hsync_end &&
9318             old_mode->vsync_end   != new_mode->vsync_end &&
9319             old_mode->hskew       == new_mode->hskew &&
9320             old_mode->vscan       == new_mode->vscan &&
9321             (old_mode->vsync_end - old_mode->vsync_start) ==
9322             (new_mode->vsync_end - new_mode->vsync_start))
9323                 return true;
9324
9325         return false;
9326 }
9327
9328 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
9329 {
9330         u64 num, den, res;
9331         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9332
9333         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9334
9335         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9336         den = (unsigned long long)new_crtc_state->mode.htotal *
9337               (unsigned long long)new_crtc_state->mode.vtotal;
9338
9339         res = div_u64(num, den);
9340         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9341 }
9342
9343 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9344                          struct drm_atomic_state *state,
9345                          struct drm_crtc *crtc,
9346                          struct drm_crtc_state *old_crtc_state,
9347                          struct drm_crtc_state *new_crtc_state,
9348                          bool enable,
9349                          bool *lock_and_validation_needed)
9350 {
9351         struct dm_atomic_state *dm_state = NULL;
9352         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9353         struct dc_stream_state *new_stream;
9354         int ret = 0;
9355
9356         /*
9357          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9358          * update changed items
9359          */
9360         struct amdgpu_crtc *acrtc = NULL;
9361         struct amdgpu_dm_connector *aconnector = NULL;
9362         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9363         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9364
9365         new_stream = NULL;
9366
9367         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9368         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9369         acrtc = to_amdgpu_crtc(crtc);
9370         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9371
9372         /* TODO This hack should go away */
9373         if (aconnector && enable) {
9374                 /* Make sure fake sink is created in plug-in scenario */
9375                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9376                                                             &aconnector->base);
9377                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9378                                                             &aconnector->base);
9379
9380                 if (IS_ERR(drm_new_conn_state)) {
9381                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9382                         goto fail;
9383                 }
9384
9385                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9386                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9387
9388                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9389                         goto skip_modeset;
9390
9391                 new_stream = create_validate_stream_for_sink(aconnector,
9392                                                              &new_crtc_state->mode,
9393                                                              dm_new_conn_state,
9394                                                              dm_old_crtc_state->stream);
9395
9396                 /*
9397                  * we can have no stream on ACTION_SET if a display
9398                  * was disconnected during S3, in this case it is not an
9399                  * error, the OS will be updated after detection, and
9400                  * will do the right thing on next atomic commit
9401                  */
9402
9403                 if (!new_stream) {
9404                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9405                                         __func__, acrtc->base.base.id);
9406                         ret = -ENOMEM;
9407                         goto fail;
9408                 }
9409
9410                 /*
9411                  * TODO: Check VSDB bits to decide whether this should
9412                  * be enabled or not.
9413                  */
9414                 new_stream->triggered_crtc_reset.enabled =
9415                         dm->force_timing_sync;
9416
9417                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9418
9419                 ret = fill_hdr_info_packet(drm_new_conn_state,
9420                                            &new_stream->hdr_static_metadata);
9421                 if (ret)
9422                         goto fail;
9423
9424                 /*
9425                  * If we already removed the old stream from the context
9426                  * (and set the new stream to NULL) then we can't reuse
9427                  * the old stream even if the stream and scaling are unchanged.
9428                  * We'll hit the BUG_ON and black screen.
9429                  *
9430                  * TODO: Refactor this function to allow this check to work
9431                  * in all conditions.
9432                  */
9433                 if (dm_new_crtc_state->stream &&
9434                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9435                         goto skip_modeset;
9436
9437                 if (dm_new_crtc_state->stream &&
9438                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9439                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9440                         new_crtc_state->mode_changed = false;
9441                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9442                                          new_crtc_state->mode_changed);
9443                 }
9444         }
9445
9446         /* mode_changed flag may get updated above, need to check again */
9447         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9448                 goto skip_modeset;
9449
9450         drm_dbg_state(state->dev,
9451                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
9452                 acrtc->crtc_id,
9453                 new_crtc_state->enable,
9454                 new_crtc_state->active,
9455                 new_crtc_state->planes_changed,
9456                 new_crtc_state->mode_changed,
9457                 new_crtc_state->active_changed,
9458                 new_crtc_state->connectors_changed);
9459
9460         /* Remove stream for any changed/disabled CRTC */
9461         if (!enable) {
9462
9463                 if (!dm_old_crtc_state->stream)
9464                         goto skip_modeset;
9465
9466                 /* Unset freesync video if it was active before */
9467                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9468                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9469                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9470                 }
9471
9472                 /* Now check if we should set freesync video mode */
9473                 if (dm_new_crtc_state->stream &&
9474                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9475                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
9476                     is_timing_unchanged_for_freesync(new_crtc_state,
9477                                                      old_crtc_state)) {
9478                         new_crtc_state->mode_changed = false;
9479                         DRM_DEBUG_DRIVER(
9480                                 "Mode change not required for front porch change, setting mode_changed to %d",
9481                                 new_crtc_state->mode_changed);
9482
9483                         set_freesync_fixed_config(dm_new_crtc_state);
9484
9485                         goto skip_modeset;
9486                 } else if (aconnector &&
9487                            is_freesync_video_mode(&new_crtc_state->mode,
9488                                                   aconnector)) {
9489                         struct drm_display_mode *high_mode;
9490
9491                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9492                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode))
9493                                 set_freesync_fixed_config(dm_new_crtc_state);
9494                 }
9495
9496                 ret = dm_atomic_get_state(state, &dm_state);
9497                 if (ret)
9498                         goto fail;
9499
9500                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9501                                 crtc->base.id);
9502
9503                 /* i.e. reset mode */
9504                 if (dc_remove_stream_from_ctx(
9505                                 dm->dc,
9506                                 dm_state->context,
9507                                 dm_old_crtc_state->stream) != DC_OK) {
9508                         ret = -EINVAL;
9509                         goto fail;
9510                 }
9511
9512                 dc_stream_release(dm_old_crtc_state->stream);
9513                 dm_new_crtc_state->stream = NULL;
9514
9515                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9516
9517                 *lock_and_validation_needed = true;
9518
9519         } else {/* Add stream for any updated/enabled CRTC */
9520                 /*
9521                  * Quick fix to prevent NULL pointer on new_stream when
9522                  * added MST connectors not found in existing crtc_state in the chained mode
9523                  * TODO: need to dig out the root cause of that
9524                  */
9525                 if (!aconnector)
9526                         goto skip_modeset;
9527
9528                 if (modereset_required(new_crtc_state))
9529                         goto skip_modeset;
9530
9531                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9532                                      dm_old_crtc_state->stream)) {
9533
9534                         WARN_ON(dm_new_crtc_state->stream);
9535
9536                         ret = dm_atomic_get_state(state, &dm_state);
9537                         if (ret)
9538                                 goto fail;
9539
9540                         dm_new_crtc_state->stream = new_stream;
9541
9542                         dc_stream_retain(new_stream);
9543
9544                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9545                                          crtc->base.id);
9546
9547                         if (dc_add_stream_to_ctx(
9548                                         dm->dc,
9549                                         dm_state->context,
9550                                         dm_new_crtc_state->stream) != DC_OK) {
9551                                 ret = -EINVAL;
9552                                 goto fail;
9553                         }
9554
9555                         *lock_and_validation_needed = true;
9556                 }
9557         }
9558
9559 skip_modeset:
9560         /* Release extra reference */
9561         if (new_stream)
9562                 dc_stream_release(new_stream);
9563
9564         /*
9565          * We want to do dc stream updates that do not require a
9566          * full modeset below.
9567          */
9568         if (!(enable && aconnector && new_crtc_state->active))
9569                 return 0;
9570         /*
9571          * Given above conditions, the dc state cannot be NULL because:
9572          * 1. We're in the process of enabling CRTCs (just been added
9573          *    to the dc context, or already is on the context)
9574          * 2. Has a valid connector attached, and
9575          * 3. Is currently active and enabled.
9576          * => The dc stream state currently exists.
9577          */
9578         BUG_ON(dm_new_crtc_state->stream == NULL);
9579
9580         /* Scaling or underscan settings */
9581         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9582                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9583                 update_stream_scaling_settings(
9584                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9585
9586         /* ABM settings */
9587         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9588
9589         /*
9590          * Color management settings. We also update color properties
9591          * when a modeset is needed, to ensure it gets reprogrammed.
9592          */
9593         if (dm_new_crtc_state->base.color_mgmt_changed ||
9594             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9595                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9596                 if (ret)
9597                         goto fail;
9598         }
9599
9600         /* Update Freesync settings. */
9601         get_freesync_config_for_crtc(dm_new_crtc_state,
9602                                      dm_new_conn_state);
9603
9604         return ret;
9605
9606 fail:
9607         if (new_stream)
9608                 dc_stream_release(new_stream);
9609         return ret;
9610 }
9611
9612 static bool should_reset_plane(struct drm_atomic_state *state,
9613                                struct drm_plane *plane,
9614                                struct drm_plane_state *old_plane_state,
9615                                struct drm_plane_state *new_plane_state)
9616 {
9617         struct drm_plane *other;
9618         struct drm_plane_state *old_other_state, *new_other_state;
9619         struct drm_crtc_state *new_crtc_state;
9620         struct amdgpu_device *adev = drm_to_adev(plane->dev);
9621         int i;
9622
9623         /*
9624          * TODO: Remove this hack for all asics once it proves that the
9625          * fast updates works fine on DCN3.2+.
9626          */
9627         if (adev->ip_versions[DCE_HWIP][0] < IP_VERSION(3, 2, 0) && state->allow_modeset)
9628                 return true;
9629
9630         /* Exit early if we know that we're adding or removing the plane. */
9631         if (old_plane_state->crtc != new_plane_state->crtc)
9632                 return true;
9633
9634         /* old crtc == new_crtc == NULL, plane not in context. */
9635         if (!new_plane_state->crtc)
9636                 return false;
9637
9638         new_crtc_state =
9639                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9640
9641         if (!new_crtc_state)
9642                 return true;
9643
9644         /* CRTC Degamma changes currently require us to recreate planes. */
9645         if (new_crtc_state->color_mgmt_changed)
9646                 return true;
9647
9648         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9649                 return true;
9650
9651         /*
9652          * If there are any new primary or overlay planes being added or
9653          * removed then the z-order can potentially change. To ensure
9654          * correct z-order and pipe acquisition the current DC architecture
9655          * requires us to remove and recreate all existing planes.
9656          *
9657          * TODO: Come up with a more elegant solution for this.
9658          */
9659         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9660                 struct amdgpu_framebuffer *old_afb, *new_afb;
9661
9662                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9663                         continue;
9664
9665                 if (old_other_state->crtc != new_plane_state->crtc &&
9666                     new_other_state->crtc != new_plane_state->crtc)
9667                         continue;
9668
9669                 if (old_other_state->crtc != new_other_state->crtc)
9670                         return true;
9671
9672                 /* Src/dst size and scaling updates. */
9673                 if (old_other_state->src_w != new_other_state->src_w ||
9674                     old_other_state->src_h != new_other_state->src_h ||
9675                     old_other_state->crtc_w != new_other_state->crtc_w ||
9676                     old_other_state->crtc_h != new_other_state->crtc_h)
9677                         return true;
9678
9679                 /* Rotation / mirroring updates. */
9680                 if (old_other_state->rotation != new_other_state->rotation)
9681                         return true;
9682
9683                 /* Blending updates. */
9684                 if (old_other_state->pixel_blend_mode !=
9685                     new_other_state->pixel_blend_mode)
9686                         return true;
9687
9688                 /* Alpha updates. */
9689                 if (old_other_state->alpha != new_other_state->alpha)
9690                         return true;
9691
9692                 /* Colorspace changes. */
9693                 if (old_other_state->color_range != new_other_state->color_range ||
9694                     old_other_state->color_encoding != new_other_state->color_encoding)
9695                         return true;
9696
9697                 /* Framebuffer checks fall at the end. */
9698                 if (!old_other_state->fb || !new_other_state->fb)
9699                         continue;
9700
9701                 /* Pixel format changes can require bandwidth updates. */
9702                 if (old_other_state->fb->format != new_other_state->fb->format)
9703                         return true;
9704
9705                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9706                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9707
9708                 /* Tiling and DCC changes also require bandwidth updates. */
9709                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9710                     old_afb->base.modifier != new_afb->base.modifier)
9711                         return true;
9712         }
9713
9714         return false;
9715 }
9716
9717 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9718                               struct drm_plane_state *new_plane_state,
9719                               struct drm_framebuffer *fb)
9720 {
9721         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9722         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9723         unsigned int pitch;
9724         bool linear;
9725
9726         if (fb->width > new_acrtc->max_cursor_width ||
9727             fb->height > new_acrtc->max_cursor_height) {
9728                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9729                                  new_plane_state->fb->width,
9730                                  new_plane_state->fb->height);
9731                 return -EINVAL;
9732         }
9733         if (new_plane_state->src_w != fb->width << 16 ||
9734             new_plane_state->src_h != fb->height << 16) {
9735                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9736                 return -EINVAL;
9737         }
9738
9739         /* Pitch in pixels */
9740         pitch = fb->pitches[0] / fb->format->cpp[0];
9741
9742         if (fb->width != pitch) {
9743                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9744                                  fb->width, pitch);
9745                 return -EINVAL;
9746         }
9747
9748         switch (pitch) {
9749         case 64:
9750         case 128:
9751         case 256:
9752                 /* FB pitch is supported by cursor plane */
9753                 break;
9754         default:
9755                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9756                 return -EINVAL;
9757         }
9758
9759         /* Core DRM takes care of checking FB modifiers, so we only need to
9760          * check tiling flags when the FB doesn't have a modifier.
9761          */
9762         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9763                 if (adev->family < AMDGPU_FAMILY_AI) {
9764                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9765                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9766                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9767                 } else {
9768                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9769                 }
9770                 if (!linear) {
9771                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9772                         return -EINVAL;
9773                 }
9774         }
9775
9776         return 0;
9777 }
9778
9779 static int dm_update_plane_state(struct dc *dc,
9780                                  struct drm_atomic_state *state,
9781                                  struct drm_plane *plane,
9782                                  struct drm_plane_state *old_plane_state,
9783                                  struct drm_plane_state *new_plane_state,
9784                                  bool enable,
9785                                  bool *lock_and_validation_needed,
9786                                  bool *is_top_most_overlay)
9787 {
9788
9789         struct dm_atomic_state *dm_state = NULL;
9790         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9791         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9792         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9793         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9794         struct amdgpu_crtc *new_acrtc;
9795         bool needs_reset;
9796         int ret = 0;
9797
9798
9799         new_plane_crtc = new_plane_state->crtc;
9800         old_plane_crtc = old_plane_state->crtc;
9801         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9802         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9803
9804         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9805                 if (!enable || !new_plane_crtc ||
9806                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9807                         return 0;
9808
9809                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9810
9811                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9812                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9813                         return -EINVAL;
9814                 }
9815
9816                 if (new_plane_state->fb) {
9817                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9818                                                  new_plane_state->fb);
9819                         if (ret)
9820                                 return ret;
9821                 }
9822
9823                 return 0;
9824         }
9825
9826         needs_reset = should_reset_plane(state, plane, old_plane_state,
9827                                          new_plane_state);
9828
9829         /* Remove any changed/removed planes */
9830         if (!enable) {
9831                 if (!needs_reset)
9832                         return 0;
9833
9834                 if (!old_plane_crtc)
9835                         return 0;
9836
9837                 old_crtc_state = drm_atomic_get_old_crtc_state(
9838                                 state, old_plane_crtc);
9839                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9840
9841                 if (!dm_old_crtc_state->stream)
9842                         return 0;
9843
9844                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9845                                 plane->base.id, old_plane_crtc->base.id);
9846
9847                 ret = dm_atomic_get_state(state, &dm_state);
9848                 if (ret)
9849                         return ret;
9850
9851                 if (!dc_remove_plane_from_context(
9852                                 dc,
9853                                 dm_old_crtc_state->stream,
9854                                 dm_old_plane_state->dc_state,
9855                                 dm_state->context)) {
9856
9857                         return -EINVAL;
9858                 }
9859
9860                 if (dm_old_plane_state->dc_state)
9861                         dc_plane_state_release(dm_old_plane_state->dc_state);
9862
9863                 dm_new_plane_state->dc_state = NULL;
9864
9865                 *lock_and_validation_needed = true;
9866
9867         } else { /* Add new planes */
9868                 struct dc_plane_state *dc_new_plane_state;
9869
9870                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9871                         return 0;
9872
9873                 if (!new_plane_crtc)
9874                         return 0;
9875
9876                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9877                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9878
9879                 if (!dm_new_crtc_state->stream)
9880                         return 0;
9881
9882                 if (!needs_reset)
9883                         return 0;
9884
9885                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9886                 if (ret)
9887                         return ret;
9888
9889                 WARN_ON(dm_new_plane_state->dc_state);
9890
9891                 dc_new_plane_state = dc_create_plane_state(dc);
9892                 if (!dc_new_plane_state)
9893                         return -ENOMEM;
9894
9895                 /* Block top most plane from being a video plane */
9896                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9897                         if (amdgpu_dm_plane_is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9898                                 return -EINVAL;
9899
9900                         *is_top_most_overlay = false;
9901                 }
9902
9903                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9904                                  plane->base.id, new_plane_crtc->base.id);
9905
9906                 ret = fill_dc_plane_attributes(
9907                         drm_to_adev(new_plane_crtc->dev),
9908                         dc_new_plane_state,
9909                         new_plane_state,
9910                         new_crtc_state);
9911                 if (ret) {
9912                         dc_plane_state_release(dc_new_plane_state);
9913                         return ret;
9914                 }
9915
9916                 ret = dm_atomic_get_state(state, &dm_state);
9917                 if (ret) {
9918                         dc_plane_state_release(dc_new_plane_state);
9919                         return ret;
9920                 }
9921
9922                 /*
9923                  * Any atomic check errors that occur after this will
9924                  * not need a release. The plane state will be attached
9925                  * to the stream, and therefore part of the atomic
9926                  * state. It'll be released when the atomic state is
9927                  * cleaned.
9928                  */
9929                 if (!dc_add_plane_to_context(
9930                                 dc,
9931                                 dm_new_crtc_state->stream,
9932                                 dc_new_plane_state,
9933                                 dm_state->context)) {
9934
9935                         dc_plane_state_release(dc_new_plane_state);
9936                         return -EINVAL;
9937                 }
9938
9939                 dm_new_plane_state->dc_state = dc_new_plane_state;
9940
9941                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9942
9943                 /* Tell DC to do a full surface update every time there
9944                  * is a plane change. Inefficient, but works for now.
9945                  */
9946                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9947
9948                 *lock_and_validation_needed = true;
9949         }
9950
9951
9952         return ret;
9953 }
9954
9955 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9956                                        int *src_w, int *src_h)
9957 {
9958         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9959         case DRM_MODE_ROTATE_90:
9960         case DRM_MODE_ROTATE_270:
9961                 *src_w = plane_state->src_h >> 16;
9962                 *src_h = plane_state->src_w >> 16;
9963                 break;
9964         case DRM_MODE_ROTATE_0:
9965         case DRM_MODE_ROTATE_180:
9966         default:
9967                 *src_w = plane_state->src_w >> 16;
9968                 *src_h = plane_state->src_h >> 16;
9969                 break;
9970         }
9971 }
9972
9973 static void
9974 dm_get_plane_scale(struct drm_plane_state *plane_state,
9975                    int *out_plane_scale_w, int *out_plane_scale_h)
9976 {
9977         int plane_src_w, plane_src_h;
9978
9979         dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);
9980         *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w;
9981         *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h;
9982 }
9983
9984 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9985                                 struct drm_crtc *crtc,
9986                                 struct drm_crtc_state *new_crtc_state)
9987 {
9988         struct drm_plane *cursor = crtc->cursor, *plane, *underlying;
9989         struct drm_plane_state *old_plane_state, *new_plane_state;
9990         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9991         int i;
9992         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9993         bool any_relevant_change = false;
9994
9995         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9996          * cursor per pipe but it's going to inherit the scaling and
9997          * positioning from the underlying pipe. Check the cursor plane's
9998          * blending properties match the underlying planes'.
9999          */
10000
10001         /* If no plane was enabled or changed scaling, no need to check again */
10002         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10003                 int new_scale_w, new_scale_h, old_scale_w, old_scale_h;
10004
10005                 if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc)
10006                         continue;
10007
10008                 if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) {
10009                         any_relevant_change = true;
10010                         break;
10011                 }
10012
10013                 if (new_plane_state->fb == old_plane_state->fb &&
10014                     new_plane_state->crtc_w == old_plane_state->crtc_w &&
10015                     new_plane_state->crtc_h == old_plane_state->crtc_h)
10016                         continue;
10017
10018                 dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h);
10019                 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h);
10020
10021                 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {
10022                         any_relevant_change = true;
10023                         break;
10024                 }
10025         }
10026
10027         if (!any_relevant_change)
10028                 return 0;
10029
10030         new_cursor_state = drm_atomic_get_plane_state(state, cursor);
10031         if (IS_ERR(new_cursor_state))
10032                 return PTR_ERR(new_cursor_state);
10033
10034         if (!new_cursor_state->fb)
10035                 return 0;
10036
10037         dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h);
10038
10039         /* Need to check all enabled planes, even if this commit doesn't change
10040          * their state
10041          */
10042         i = drm_atomic_add_affected_planes(state, crtc);
10043         if (i)
10044                 return i;
10045
10046         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
10047                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
10048                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
10049                         continue;
10050
10051                 /* Ignore disabled planes */
10052                 if (!new_underlying_state->fb)
10053                         continue;
10054
10055                 dm_get_plane_scale(new_underlying_state,
10056                                    &underlying_scale_w, &underlying_scale_h);
10057
10058                 if (cursor_scale_w != underlying_scale_w ||
10059                     cursor_scale_h != underlying_scale_h) {
10060                         drm_dbg_atomic(crtc->dev,
10061                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
10062                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
10063                         return -EINVAL;
10064                 }
10065
10066                 /* If this plane covers the whole CRTC, no need to check planes underneath */
10067                 if (new_underlying_state->crtc_x <= 0 &&
10068                     new_underlying_state->crtc_y <= 0 &&
10069                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
10070                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
10071                         break;
10072         }
10073
10074         return 0;
10075 }
10076
10077 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
10078 {
10079         struct drm_connector *connector;
10080         struct drm_connector_state *conn_state, *old_conn_state;
10081         struct amdgpu_dm_connector *aconnector = NULL;
10082         int i;
10083
10084         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
10085                 if (!conn_state->crtc)
10086                         conn_state = old_conn_state;
10087
10088                 if (conn_state->crtc != crtc)
10089                         continue;
10090
10091                 aconnector = to_amdgpu_dm_connector(connector);
10092                 if (!aconnector->mst_output_port || !aconnector->mst_root)
10093                         aconnector = NULL;
10094                 else
10095                         break;
10096         }
10097
10098         if (!aconnector)
10099                 return 0;
10100
10101         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
10102 }
10103
10104 /**
10105  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
10106  *
10107  * @dev: The DRM device
10108  * @state: The atomic state to commit
10109  *
10110  * Validate that the given atomic state is programmable by DC into hardware.
10111  * This involves constructing a &struct dc_state reflecting the new hardware
10112  * state we wish to commit, then querying DC to see if it is programmable. It's
10113  * important not to modify the existing DC state. Otherwise, atomic_check
10114  * may unexpectedly commit hardware changes.
10115  *
10116  * When validating the DC state, it's important that the right locks are
10117  * acquired. For full updates case which removes/adds/updates streams on one
10118  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
10119  * that any such full update commit will wait for completion of any outstanding
10120  * flip using DRMs synchronization events.
10121  *
10122  * Note that DM adds the affected connectors for all CRTCs in state, when that
10123  * might not seem necessary. This is because DC stream creation requires the
10124  * DC sink, which is tied to the DRM connector state. Cleaning this up should
10125  * be possible but non-trivial - a possible TODO item.
10126  *
10127  * Return: -Error code if validation failed.
10128  */
10129 static int amdgpu_dm_atomic_check(struct drm_device *dev,
10130                                   struct drm_atomic_state *state)
10131 {
10132         struct amdgpu_device *adev = drm_to_adev(dev);
10133         struct dm_atomic_state *dm_state = NULL;
10134         struct dc *dc = adev->dm.dc;
10135         struct drm_connector *connector;
10136         struct drm_connector_state *old_con_state, *new_con_state;
10137         struct drm_crtc *crtc;
10138         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10139         struct drm_plane *plane;
10140         struct drm_plane_state *old_plane_state, *new_plane_state;
10141         enum dc_status status;
10142         int ret, i;
10143         bool lock_and_validation_needed = false;
10144         bool is_top_most_overlay = true;
10145         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
10146         struct drm_dp_mst_topology_mgr *mgr;
10147         struct drm_dp_mst_topology_state *mst_state;
10148         struct dsc_mst_fairness_vars vars[MAX_PIPES];
10149
10150         trace_amdgpu_dm_atomic_check_begin(state);
10151
10152         ret = drm_atomic_helper_check_modeset(dev, state);
10153         if (ret) {
10154                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
10155                 goto fail;
10156         }
10157
10158         /* Check connector changes */
10159         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10160                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10161                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10162
10163                 /* Skip connectors that are disabled or part of modeset already. */
10164                 if (!new_con_state->crtc)
10165                         continue;
10166
10167                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
10168                 if (IS_ERR(new_crtc_state)) {
10169                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
10170                         ret = PTR_ERR(new_crtc_state);
10171                         goto fail;
10172                 }
10173
10174                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
10175                     dm_old_con_state->scaling != dm_new_con_state->scaling)
10176                         new_crtc_state->connectors_changed = true;
10177         }
10178
10179         if (dc_resource_is_dsc_encoding_supported(dc)) {
10180                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10181                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10182                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
10183                                 if (ret) {
10184                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
10185                                         goto fail;
10186                                 }
10187                         }
10188                 }
10189         }
10190         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10191                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10192
10193                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
10194                     !new_crtc_state->color_mgmt_changed &&
10195                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
10196                         dm_old_crtc_state->dsc_force_changed == false)
10197                         continue;
10198
10199                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
10200                 if (ret) {
10201                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
10202                         goto fail;
10203                 }
10204
10205                 if (!new_crtc_state->enable)
10206                         continue;
10207
10208                 ret = drm_atomic_add_affected_connectors(state, crtc);
10209                 if (ret) {
10210                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
10211                         goto fail;
10212                 }
10213
10214                 ret = drm_atomic_add_affected_planes(state, crtc);
10215                 if (ret) {
10216                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
10217                         goto fail;
10218                 }
10219
10220                 if (dm_old_crtc_state->dsc_force_changed)
10221                         new_crtc_state->mode_changed = true;
10222         }
10223
10224         /*
10225          * Add all primary and overlay planes on the CRTC to the state
10226          * whenever a plane is enabled to maintain correct z-ordering
10227          * and to enable fast surface updates.
10228          */
10229         drm_for_each_crtc(crtc, dev) {
10230                 bool modified = false;
10231
10232                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10233                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10234                                 continue;
10235
10236                         if (new_plane_state->crtc == crtc ||
10237                             old_plane_state->crtc == crtc) {
10238                                 modified = true;
10239                                 break;
10240                         }
10241                 }
10242
10243                 if (!modified)
10244                         continue;
10245
10246                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10247                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10248                                 continue;
10249
10250                         new_plane_state =
10251                                 drm_atomic_get_plane_state(state, plane);
10252
10253                         if (IS_ERR(new_plane_state)) {
10254                                 ret = PTR_ERR(new_plane_state);
10255                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
10256                                 goto fail;
10257                         }
10258                 }
10259         }
10260
10261         /*
10262          * DC consults the zpos (layer_index in DC terminology) to determine the
10263          * hw plane on which to enable the hw cursor (see
10264          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
10265          * atomic state, so call drm helper to normalize zpos.
10266          */
10267         ret = drm_atomic_normalize_zpos(dev, state);
10268         if (ret) {
10269                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10270                 goto fail;
10271         }
10272
10273         /* Remove exiting planes if they are modified */
10274         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10275                 if (old_plane_state->fb && new_plane_state->fb &&
10276                     get_mem_type(old_plane_state->fb) !=
10277                     get_mem_type(new_plane_state->fb))
10278                         lock_and_validation_needed = true;
10279
10280                 ret = dm_update_plane_state(dc, state, plane,
10281                                             old_plane_state,
10282                                             new_plane_state,
10283                                             false,
10284                                             &lock_and_validation_needed,
10285                                             &is_top_most_overlay);
10286                 if (ret) {
10287                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10288                         goto fail;
10289                 }
10290         }
10291
10292         /* Disable all crtcs which require disable */
10293         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10294                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10295                                            old_crtc_state,
10296                                            new_crtc_state,
10297                                            false,
10298                                            &lock_and_validation_needed);
10299                 if (ret) {
10300                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10301                         goto fail;
10302                 }
10303         }
10304
10305         /* Enable all crtcs which require enable */
10306         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10307                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10308                                            old_crtc_state,
10309                                            new_crtc_state,
10310                                            true,
10311                                            &lock_and_validation_needed);
10312                 if (ret) {
10313                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10314                         goto fail;
10315                 }
10316         }
10317
10318         /* Add new/modified planes */
10319         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10320                 ret = dm_update_plane_state(dc, state, plane,
10321                                             old_plane_state,
10322                                             new_plane_state,
10323                                             true,
10324                                             &lock_and_validation_needed,
10325                                             &is_top_most_overlay);
10326                 if (ret) {
10327                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10328                         goto fail;
10329                 }
10330         }
10331
10332         if (dc_resource_is_dsc_encoding_supported(dc)) {
10333                 ret = pre_validate_dsc(state, &dm_state, vars);
10334                 if (ret != 0)
10335                         goto fail;
10336         }
10337
10338         /* Run this here since we want to validate the streams we created */
10339         ret = drm_atomic_helper_check_planes(dev, state);
10340         if (ret) {
10341                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10342                 goto fail;
10343         }
10344
10345         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10346                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10347                 if (dm_new_crtc_state->mpo_requested)
10348                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10349         }
10350
10351         /* Check cursor planes scaling */
10352         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10353                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10354                 if (ret) {
10355                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10356                         goto fail;
10357                 }
10358         }
10359
10360         if (state->legacy_cursor_update) {
10361                 /*
10362                  * This is a fast cursor update coming from the plane update
10363                  * helper, check if it can be done asynchronously for better
10364                  * performance.
10365                  */
10366                 state->async_update =
10367                         !drm_atomic_helper_async_check(dev, state);
10368
10369                 /*
10370                  * Skip the remaining global validation if this is an async
10371                  * update. Cursor updates can be done without affecting
10372                  * state or bandwidth calcs and this avoids the performance
10373                  * penalty of locking the private state object and
10374                  * allocating a new dc_state.
10375                  */
10376                 if (state->async_update)
10377                         return 0;
10378         }
10379
10380         /* Check scaling and underscan changes*/
10381         /* TODO Removed scaling changes validation due to inability to commit
10382          * new stream into context w\o causing full reset. Need to
10383          * decide how to handle.
10384          */
10385         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10386                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10387                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10388                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10389
10390                 /* Skip any modesets/resets */
10391                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10392                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10393                         continue;
10394
10395                 /* Skip any thing not scale or underscan changes */
10396                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10397                         continue;
10398
10399                 lock_and_validation_needed = true;
10400         }
10401
10402         /* set the slot info for each mst_state based on the link encoding format */
10403         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10404                 struct amdgpu_dm_connector *aconnector;
10405                 struct drm_connector *connector;
10406                 struct drm_connector_list_iter iter;
10407                 u8 link_coding_cap;
10408
10409                 drm_connector_list_iter_begin(dev, &iter);
10410                 drm_for_each_connector_iter(connector, &iter) {
10411                         if (connector->index == mst_state->mgr->conn_base_id) {
10412                                 aconnector = to_amdgpu_dm_connector(connector);
10413                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10414                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10415
10416                                 break;
10417                         }
10418                 }
10419                 drm_connector_list_iter_end(&iter);
10420         }
10421
10422         /**
10423          * Streams and planes are reset when there are changes that affect
10424          * bandwidth. Anything that affects bandwidth needs to go through
10425          * DC global validation to ensure that the configuration can be applied
10426          * to hardware.
10427          *
10428          * We have to currently stall out here in atomic_check for outstanding
10429          * commits to finish in this case because our IRQ handlers reference
10430          * DRM state directly - we can end up disabling interrupts too early
10431          * if we don't.
10432          *
10433          * TODO: Remove this stall and drop DM state private objects.
10434          */
10435         if (lock_and_validation_needed) {
10436                 ret = dm_atomic_get_state(state, &dm_state);
10437                 if (ret) {
10438                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10439                         goto fail;
10440                 }
10441
10442                 ret = do_aquire_global_lock(dev, state);
10443                 if (ret) {
10444                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10445                         goto fail;
10446                 }
10447
10448                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10449                 if (ret) {
10450                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10451                         ret = -EINVAL;
10452                         goto fail;
10453                 }
10454
10455                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10456                 if (ret) {
10457                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10458                         goto fail;
10459                 }
10460
10461                 /*
10462                  * Perform validation of MST topology in the state:
10463                  * We need to perform MST atomic check before calling
10464                  * dc_validate_global_state(), or there is a chance
10465                  * to get stuck in an infinite loop and hang eventually.
10466                  */
10467                 ret = drm_dp_mst_atomic_check(state);
10468                 if (ret) {
10469                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10470                         goto fail;
10471                 }
10472                 status = dc_validate_global_state(dc, dm_state->context, true);
10473                 if (status != DC_OK) {
10474                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10475                                        dc_status_to_str(status), status);
10476                         ret = -EINVAL;
10477                         goto fail;
10478                 }
10479         } else {
10480                 /*
10481                  * The commit is a fast update. Fast updates shouldn't change
10482                  * the DC context, affect global validation, and can have their
10483                  * commit work done in parallel with other commits not touching
10484                  * the same resource. If we have a new DC context as part of
10485                  * the DM atomic state from validation we need to free it and
10486                  * retain the existing one instead.
10487                  *
10488                  * Furthermore, since the DM atomic state only contains the DC
10489                  * context and can safely be annulled, we can free the state
10490                  * and clear the associated private object now to free
10491                  * some memory and avoid a possible use-after-free later.
10492                  */
10493
10494                 for (i = 0; i < state->num_private_objs; i++) {
10495                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10496
10497                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10498                                 int j = state->num_private_objs-1;
10499
10500                                 dm_atomic_destroy_state(obj,
10501                                                 state->private_objs[i].state);
10502
10503                                 /* If i is not at the end of the array then the
10504                                  * last element needs to be moved to where i was
10505                                  * before the array can safely be truncated.
10506                                  */
10507                                 if (i != j)
10508                                         state->private_objs[i] =
10509                                                 state->private_objs[j];
10510
10511                                 state->private_objs[j].ptr = NULL;
10512                                 state->private_objs[j].state = NULL;
10513                                 state->private_objs[j].old_state = NULL;
10514                                 state->private_objs[j].new_state = NULL;
10515
10516                                 state->num_private_objs = j;
10517                                 break;
10518                         }
10519                 }
10520         }
10521
10522         /* Store the overall update type for use later in atomic check. */
10523         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10524                 struct dm_crtc_state *dm_new_crtc_state =
10525                         to_dm_crtc_state(new_crtc_state);
10526
10527                 /*
10528                  * Only allow async flips for fast updates that don't change
10529                  * the FB pitch, the DCC state, rotation, etc.
10530                  */
10531                 if (new_crtc_state->async_flip && lock_and_validation_needed) {
10532                         drm_dbg_atomic(crtc->dev,
10533                                        "[CRTC:%d:%s] async flips are only supported for fast updates\n",
10534                                        crtc->base.id, crtc->name);
10535                         ret = -EINVAL;
10536                         goto fail;
10537                 }
10538
10539                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10540                         UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;
10541         }
10542
10543         /* Must be success */
10544         WARN_ON(ret);
10545
10546         trace_amdgpu_dm_atomic_check_finish(state, ret);
10547
10548         return ret;
10549
10550 fail:
10551         if (ret == -EDEADLK)
10552                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10553         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10554                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10555         else
10556                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret);
10557
10558         trace_amdgpu_dm_atomic_check_finish(state, ret);
10559
10560         return ret;
10561 }
10562
10563 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10564                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10565 {
10566         u8 dpcd_data;
10567         bool capable = false;
10568
10569         if (amdgpu_dm_connector->dc_link &&
10570                 dm_helpers_dp_read_dpcd(
10571                                 NULL,
10572                                 amdgpu_dm_connector->dc_link,
10573                                 DP_DOWN_STREAM_PORT_COUNT,
10574                                 &dpcd_data,
10575                                 sizeof(dpcd_data))) {
10576                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10577         }
10578
10579         return capable;
10580 }
10581
10582 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10583                 unsigned int offset,
10584                 unsigned int total_length,
10585                 u8 *data,
10586                 unsigned int length,
10587                 struct amdgpu_hdmi_vsdb_info *vsdb)
10588 {
10589         bool res;
10590         union dmub_rb_cmd cmd;
10591         struct dmub_cmd_send_edid_cea *input;
10592         struct dmub_cmd_edid_cea_output *output;
10593
10594         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10595                 return false;
10596
10597         memset(&cmd, 0, sizeof(cmd));
10598
10599         input = &cmd.edid_cea.data.input;
10600
10601         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10602         cmd.edid_cea.header.sub_type = 0;
10603         cmd.edid_cea.header.payload_bytes =
10604                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10605         input->offset = offset;
10606         input->length = length;
10607         input->cea_total_length = total_length;
10608         memcpy(input->payload, data, length);
10609
10610         res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
10611         if (!res) {
10612                 DRM_ERROR("EDID CEA parser failed\n");
10613                 return false;
10614         }
10615
10616         output = &cmd.edid_cea.data.output;
10617
10618         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10619                 if (!output->ack.success) {
10620                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
10621                                         output->ack.offset);
10622                 }
10623         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10624                 if (!output->amd_vsdb.vsdb_found)
10625                         return false;
10626
10627                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10628                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10629                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10630                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10631         } else {
10632                 DRM_WARN("Unknown EDID CEA parser results\n");
10633                 return false;
10634         }
10635
10636         return true;
10637 }
10638
10639 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10640                 u8 *edid_ext, int len,
10641                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10642 {
10643         int i;
10644
10645         /* send extension block to DMCU for parsing */
10646         for (i = 0; i < len; i += 8) {
10647                 bool res;
10648                 int offset;
10649
10650                 /* send 8 bytes a time */
10651                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10652                         return false;
10653
10654                 if (i+8 == len) {
10655                         /* EDID block sent completed, expect result */
10656                         int version, min_rate, max_rate;
10657
10658                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10659                         if (res) {
10660                                 /* amd vsdb found */
10661                                 vsdb_info->freesync_supported = 1;
10662                                 vsdb_info->amd_vsdb_version = version;
10663                                 vsdb_info->min_refresh_rate_hz = min_rate;
10664                                 vsdb_info->max_refresh_rate_hz = max_rate;
10665                                 return true;
10666                         }
10667                         /* not amd vsdb */
10668                         return false;
10669                 }
10670
10671                 /* check for ack*/
10672                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10673                 if (!res)
10674                         return false;
10675         }
10676
10677         return false;
10678 }
10679
10680 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10681                 u8 *edid_ext, int len,
10682                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10683 {
10684         int i;
10685
10686         /* send extension block to DMCU for parsing */
10687         for (i = 0; i < len; i += 8) {
10688                 /* send 8 bytes a time */
10689                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10690                         return false;
10691         }
10692
10693         return vsdb_info->freesync_supported;
10694 }
10695
10696 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10697                 u8 *edid_ext, int len,
10698                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10699 {
10700         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10701         bool ret;
10702
10703         mutex_lock(&adev->dm.dc_lock);
10704         if (adev->dm.dmub_srv)
10705                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10706         else
10707                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10708         mutex_unlock(&adev->dm.dc_lock);
10709         return ret;
10710 }
10711
10712 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10713                           struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10714 {
10715         u8 *edid_ext = NULL;
10716         int i;
10717         int j = 0;
10718
10719         if (edid == NULL || edid->extensions == 0)
10720                 return -ENODEV;
10721
10722         /* Find DisplayID extension */
10723         for (i = 0; i < edid->extensions; i++) {
10724                 edid_ext = (void *)(edid + (i + 1));
10725                 if (edid_ext[0] == DISPLAYID_EXT)
10726                         break;
10727         }
10728
10729         while (j < EDID_LENGTH) {
10730                 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
10731                 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
10732
10733                 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID &&
10734                                 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) {
10735                         vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;
10736                         vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3;
10737                         DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode);
10738
10739                         return true;
10740                 }
10741                 j++;
10742         }
10743
10744         return false;
10745 }
10746
10747 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10748                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10749 {
10750         u8 *edid_ext = NULL;
10751         int i;
10752         bool valid_vsdb_found = false;
10753
10754         /*----- drm_find_cea_extension() -----*/
10755         /* No EDID or EDID extensions */
10756         if (edid == NULL || edid->extensions == 0)
10757                 return -ENODEV;
10758
10759         /* Find CEA extension */
10760         for (i = 0; i < edid->extensions; i++) {
10761                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10762                 if (edid_ext[0] == CEA_EXT)
10763                         break;
10764         }
10765
10766         if (i == edid->extensions)
10767                 return -ENODEV;
10768
10769         /*----- cea_db_offsets() -----*/
10770         if (edid_ext[0] != CEA_EXT)
10771                 return -ENODEV;
10772
10773         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10774
10775         return valid_vsdb_found ? i : -ENODEV;
10776 }
10777
10778 /**
10779  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10780  *
10781  * @connector: Connector to query.
10782  * @edid: EDID from monitor
10783  *
10784  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10785  * track of some of the display information in the internal data struct used by
10786  * amdgpu_dm. This function checks which type of connector we need to set the
10787  * FreeSync parameters.
10788  */
10789 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10790                                     struct edid *edid)
10791 {
10792         int i = 0;
10793         struct detailed_timing *timing;
10794         struct detailed_non_pixel *data;
10795         struct detailed_data_monitor_range *range;
10796         struct amdgpu_dm_connector *amdgpu_dm_connector =
10797                         to_amdgpu_dm_connector(connector);
10798         struct dm_connector_state *dm_con_state = NULL;
10799         struct dc_sink *sink;
10800
10801         struct amdgpu_device *adev = drm_to_adev(connector->dev);
10802         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10803         bool freesync_capable = false;
10804         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10805
10806         if (!connector->state) {
10807                 DRM_ERROR("%s - Connector has no state", __func__);
10808                 goto update;
10809         }
10810
10811         sink = amdgpu_dm_connector->dc_sink ?
10812                 amdgpu_dm_connector->dc_sink :
10813                 amdgpu_dm_connector->dc_em_sink;
10814
10815         if (!edid || !sink) {
10816                 dm_con_state = to_dm_connector_state(connector->state);
10817
10818                 amdgpu_dm_connector->min_vfreq = 0;
10819                 amdgpu_dm_connector->max_vfreq = 0;
10820                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10821                 connector->display_info.monitor_range.min_vfreq = 0;
10822                 connector->display_info.monitor_range.max_vfreq = 0;
10823                 freesync_capable = false;
10824
10825                 goto update;
10826         }
10827
10828         dm_con_state = to_dm_connector_state(connector->state);
10829
10830         if (!adev->dm.freesync_module)
10831                 goto update;
10832
10833         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10834                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10835                 bool edid_check_required = false;
10836
10837                 if (edid) {
10838                         edid_check_required = is_dp_capable_without_timing_msa(
10839                                                 adev->dm.dc,
10840                                                 amdgpu_dm_connector);
10841                 }
10842
10843                 if (edid_check_required == true && (edid->version > 1 ||
10844                    (edid->version == 1 && edid->revision > 1))) {
10845                         for (i = 0; i < 4; i++) {
10846
10847                                 timing  = &edid->detailed_timings[i];
10848                                 data    = &timing->data.other_data;
10849                                 range   = &data->data.range;
10850                                 /*
10851                                  * Check if monitor has continuous frequency mode
10852                                  */
10853                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10854                                         continue;
10855                                 /*
10856                                  * Check for flag range limits only. If flag == 1 then
10857                                  * no additional timing information provided.
10858                                  * Default GTF, GTF Secondary curve and CVT are not
10859                                  * supported
10860                                  */
10861                                 if (range->flags != 1)
10862                                         continue;
10863
10864                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10865                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10866                                 amdgpu_dm_connector->pixel_clock_mhz =
10867                                         range->pixel_clock_mhz * 10;
10868
10869                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10870                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10871
10872                                 break;
10873                         }
10874
10875                         if (amdgpu_dm_connector->max_vfreq -
10876                             amdgpu_dm_connector->min_vfreq > 10) {
10877
10878                                 freesync_capable = true;
10879                         }
10880                 }
10881                 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10882
10883                 if (vsdb_info.replay_mode) {
10884                         amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;
10885                         amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;
10886                         amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
10887                 }
10888
10889         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10890                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10891                 if (i >= 0 && vsdb_info.freesync_supported) {
10892                         timing  = &edid->detailed_timings[i];
10893                         data    = &timing->data.other_data;
10894
10895                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10896                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10897                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10898                                 freesync_capable = true;
10899
10900                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10901                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10902                 }
10903         }
10904
10905         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10906
10907         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10908                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10909                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10910
10911                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
10912                         amdgpu_dm_connector->as_type = as_type;
10913                         amdgpu_dm_connector->vsdb_info = vsdb_info;
10914
10915                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10916                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10917                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10918                                 freesync_capable = true;
10919
10920                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10921                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10922                 }
10923         }
10924
10925 update:
10926         if (dm_con_state)
10927                 dm_con_state->freesync_capable = freesync_capable;
10928
10929         if (connector->vrr_capable_property)
10930                 drm_connector_set_vrr_capable_property(connector,
10931                                                        freesync_capable);
10932 }
10933
10934 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10935 {
10936         struct amdgpu_device *adev = drm_to_adev(dev);
10937         struct dc *dc = adev->dm.dc;
10938         int i;
10939
10940         mutex_lock(&adev->dm.dc_lock);
10941         if (dc->current_state) {
10942                 for (i = 0; i < dc->current_state->stream_count; ++i)
10943                         dc->current_state->streams[i]
10944                                 ->triggered_crtc_reset.enabled =
10945                                 adev->dm.force_timing_sync;
10946
10947                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10948                 dc_trigger_sync(dc, dc->current_state);
10949         }
10950         mutex_unlock(&adev->dm.dc_lock);
10951 }
10952
10953 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10954                        u32 value, const char *func_name)
10955 {
10956 #ifdef DM_CHECK_ADDR_0
10957         if (address == 0) {
10958                 drm_err(adev_to_drm(ctx->driver_context),
10959                         "invalid register write. address = 0");
10960                 return;
10961         }
10962 #endif
10963         cgs_write_register(ctx->cgs_device, address, value);
10964         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10965 }
10966
10967 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10968                           const char *func_name)
10969 {
10970         u32 value;
10971 #ifdef DM_CHECK_ADDR_0
10972         if (address == 0) {
10973                 drm_err(adev_to_drm(ctx->driver_context),
10974                         "invalid register read; address = 0\n");
10975                 return 0;
10976         }
10977 #endif
10978
10979         if (ctx->dmub_srv &&
10980             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10981             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10982                 ASSERT(false);
10983                 return 0;
10984         }
10985
10986         value = cgs_read_register(ctx->cgs_device, address);
10987
10988         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10989
10990         return value;
10991 }
10992
10993 int amdgpu_dm_process_dmub_aux_transfer_sync(
10994                 struct dc_context *ctx,
10995                 unsigned int link_index,
10996                 struct aux_payload *payload,
10997                 enum aux_return_code_type *operation_result)
10998 {
10999         struct amdgpu_device *adev = ctx->driver_context;
11000         struct dmub_notification *p_notify = adev->dm.dmub_notify;
11001         int ret = -1;
11002
11003         mutex_lock(&adev->dm.dpia_aux_lock);
11004         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
11005                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
11006                 goto out;
11007         }
11008
11009         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
11010                 DRM_ERROR("wait_for_completion_timeout timeout!");
11011                 *operation_result = AUX_RET_ERROR_TIMEOUT;
11012                 goto out;
11013         }
11014
11015         if (p_notify->result != AUX_RET_SUCCESS) {
11016                 /*
11017                  * Transient states before tunneling is enabled could
11018                  * lead to this error. We can ignore this for now.
11019                  */
11020                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
11021                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
11022                                         payload->address, payload->length,
11023                                         p_notify->result);
11024                 }
11025                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11026                 goto out;
11027         }
11028
11029
11030         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
11031         if (!payload->write && p_notify->aux_reply.length &&
11032                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
11033
11034                 if (payload->length != p_notify->aux_reply.length) {
11035                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
11036                                 p_notify->aux_reply.length,
11037                                         payload->address, payload->length);
11038                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11039                         goto out;
11040                 }
11041
11042                 memcpy(payload->data, p_notify->aux_reply.data,
11043                                 p_notify->aux_reply.length);
11044         }
11045
11046         /* success */
11047         ret = p_notify->aux_reply.length;
11048         *operation_result = p_notify->result;
11049 out:
11050         reinit_completion(&adev->dm.dmub_aux_transfer_done);
11051         mutex_unlock(&adev->dm.dpia_aux_lock);
11052         return ret;
11053 }
11054
11055 int amdgpu_dm_process_dmub_set_config_sync(
11056                 struct dc_context *ctx,
11057                 unsigned int link_index,
11058                 struct set_config_cmd_payload *payload,
11059                 enum set_config_status *operation_result)
11060 {
11061         struct amdgpu_device *adev = ctx->driver_context;
11062         bool is_cmd_complete;
11063         int ret;
11064
11065         mutex_lock(&adev->dm.dpia_aux_lock);
11066         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
11067                         link_index, payload, adev->dm.dmub_notify);
11068
11069         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
11070                 ret = 0;
11071                 *operation_result = adev->dm.dmub_notify->sc_status;
11072         } else {
11073                 DRM_ERROR("wait_for_completion_timeout timeout!");
11074                 ret = -1;
11075                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
11076         }
11077
11078         if (!is_cmd_complete)
11079                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
11080         mutex_unlock(&adev->dm.dpia_aux_lock);
11081         return ret;
11082 }
11083
11084 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11085 {
11086         return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
11087 }
11088
11089 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11090 {
11091         return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);
11092 }