drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <[email protected]>,
   7  *          Sebastian Andrzej Siewior <[email protected]>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 149                 int status)
 150 {
 151         struct dwc3                     *dwc = dep->dwc;
 152         int                             i;
 153
 154         if (req->started) {
 155                 i = 0;
 156                 do {
 157                         dep->busy_slot++;
 158                         /*
 159                          * Skip LINK TRB. We can't use req->trb and check for
 160                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 161                          * just completed (not the LINK TRB).
 162                          */
 163                         if (((dep->busy_slot & DWC3_TRB_MASK) ==
 164                                 DWC3_TRB_NUM- 1) &&
 165                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
 166                                 dep->busy_slot++;
 167                 } while(++i < req->request.num_mapped_sgs);
 168                 req->started = false;
 169         }
 170         list_del(&req->list);
 171         req->trb = NULL;
 172
 173         if (req->request.status == -EINPROGRESS)
 174                 req->request.status = status;
 175
 176         if (dwc->ep0_bounced && dep->number == 0)
 177                 dwc->ep0_bounced = false;
 178         else
 179                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 180                                 req->direction);
 181
 182         trace_dwc3_gadget_giveback(req);
 183
 184         spin_unlock(&dwc->lock);
 185         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 186         spin_lock(&dwc->lock);
 187 }
 188
 189 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 190 {
 191         u32             timeout = 500;
 192         u32             reg;
 193
 194         trace_dwc3_gadget_generic_cmd(cmd, param);
 195
 196         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 197         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 198
 199         do {
 200                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 201                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 202                         dwc3_trace(trace_dwc3_gadget,
 203                                         "Command Complete --> %d",
 204                                         DWC3_DGCMD_STATUS(reg));
 205                         if (DWC3_DGCMD_STATUS(reg))
 206                                 return -EINVAL;
 207                         return 0;
 208                 }
 209
 210                 /*
 211                  * We can't sleep here, because it's also called from
 212                  * interrupt context.
 213                  */
 214                 timeout--;
 215                 if (!timeout) {
 216                         dwc3_trace(trace_dwc3_gadget,
 217                                         "Command Timed Out");
 218                         return -ETIMEDOUT;
 219                 }
 220                 udelay(1);
 221         } while (1);
 222 }
 223
 224 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 225                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 226 {
 227         struct dwc3_ep          *dep = dwc->eps[ep];
 228         u32                     timeout = 500;
 229         u32                     reg;
 230
 231         trace_dwc3_gadget_ep_cmd(dep, cmd, params);
 232
 233         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 234         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 235         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 236
 237         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 238         do {
 239                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 240                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 241                         dwc3_trace(trace_dwc3_gadget,
 242                                         "Command Complete --> %d",
 243                                         DWC3_DEPCMD_STATUS(reg));
 244                         if (DWC3_DEPCMD_STATUS(reg))
 245                                 return -EINVAL;
 246                         return 0;
 247                 }
 248
 249                 /*
 250                  * We can't sleep here, because it is also called from
 251                  * interrupt context.
 252                  */
 253                 timeout--;
 254                 if (!timeout) {
 255                         dwc3_trace(trace_dwc3_gadget,
 256                                         "Command Timed Out");
 257                         return -ETIMEDOUT;
 258                 }
 259
 260                 udelay(1);
 261         } while (1);
 262 }
 263
 264 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 265                 struct dwc3_trb *trb)
 266 {
 267         u32             offset = (char *) trb - (char *) dep->trb_pool;
 268
 269         return dep->trb_pool_dma + offset;
 270 }
 271
 272 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 273 {
 274         struct dwc3             *dwc = dep->dwc;
 275
 276         if (dep->trb_pool)
 277                 return 0;
 278
 279         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 280                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 281                         &dep->trb_pool_dma, GFP_KERNEL);
 282         if (!dep->trb_pool) {
 283                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 284                                 dep->name);
 285                 return -ENOMEM;
 286         }
 287
 288         return 0;
 289 }
 290
 291 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 292 {
 293         struct dwc3             *dwc = dep->dwc;
 294
 295         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 296                         dep->trb_pool, dep->trb_pool_dma);
 297
 298         dep->trb_pool = NULL;
 299         dep->trb_pool_dma = 0;
 300 }
 301
 302 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 303
 304 /**
 305  * dwc3_gadget_start_config - Configure EP resources
 306  * @dwc: pointer to our controller context structure
 307  * @dep: endpoint that is being enabled
 308  *
 309  * The assignment of transfer resources cannot perfectly follow the
 310  * data book due to the fact that the controller driver does not have
 311  * all knowledge of the configuration in advance. It is given this
 312  * information piecemeal by the composite gadget framework after every
 313  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 314  * programming model in this scenario can cause errors. For two
 315  * reasons:
 316  *
 317  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 318  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 319  * multiple interfaces.
 320  *
 321  * 2) The databook does not mention doing more DEPXFERCFG for new
 322  * endpoint on alt setting (8.1.6).
 323  *
 324  * The following simplified method is used instead:
 325  *
 326  * All hardware endpoints can be assigned a transfer resource and this
 327  * setting will stay persistent until either a core reset or
 328  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 329  * do DEPXFERCFG for every hardware endpoint as well. We are
 330  * guaranteed that there are as many transfer resources as endpoints.
 331  *
 332  * This function is called for each endpoint when it is being enabled
 333  * but is triggered only when called for EP0-out, which always happens
 334  * first, and which should only happen in one of the above conditions.
 335  */
 336 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 337 {
 338         struct dwc3_gadget_ep_cmd_params params;
 339         u32                     cmd;
 340         int                     i;
 341         int                     ret;
 342
 343         if (dep->number)
 344                 return 0;
 345
 346         memset(&params, 0x00, sizeof(params));
 347         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 348
 349         ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 350         if (ret)
 351                 return ret;
 352
 353         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 354                 struct dwc3_ep *dep = dwc->eps[i];
 355
 356                 if (!dep)
 357                         continue;
 358
 359                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 360                 if (ret)
 361                         return ret;
 362         }
 363
 364         return 0;
 365 }
 366
 367 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 368                 const struct usb_endpoint_descriptor *desc,
 369                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 370                 bool ignore, bool restore)
 371 {
 372         struct dwc3_gadget_ep_cmd_params params;
 373
 374         memset(&params, 0x00, sizeof(params));
 375
 376         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 377                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 378
 379         /* Burst size is only needed in SuperSpeed mode */
 380         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
 381                 u32 burst = dep->endpoint.maxburst - 1;
 382
 383                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 384         }
 385
 386         if (ignore)
 387                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 388
 389         if (restore) {
 390                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 391                 params.param2 |= dep->saved_state;
 392         }
 393
 394         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 395                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 396
 397         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 398                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 399                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 400                 dep->stream_capable = true;
 401         }
 402
 403         if (!usb_endpoint_xfer_control(desc))
 404                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 405
 406         /*
 407          * We are doing 1:1 mapping for endpoints, meaning
 408          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 409          * so on. We consider the direction bit as part of the physical
 410          * endpoint number. So USB endpoint 0x81 is 0x03.
 411          */
 412         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 413
 414         /*
 415          * We must use the lower 16 TX FIFOs even though
 416          * HW might have more
 417          */
 418         if (dep->direction)
 419                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 420
 421         if (desc->bInterval) {
 422                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 423                 dep->interval = 1 << (desc->bInterval - 1);
 424         }
 425
 426         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 427                         DWC3_DEPCMD_SETEPCONFIG, &params);
 428 }
 429
 430 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 431 {
 432         struct dwc3_gadget_ep_cmd_params params;
 433
 434         memset(&params, 0x00, sizeof(params));
 435
 436         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 437
 438         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 439                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 440 }
 441
 442 /**
 443  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 444  * @dep: endpoint to be initialized
 445  * @desc: USB Endpoint Descriptor
 446  *
 447  * Caller should take care of locking
 448  */
 449 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 450                 const struct usb_endpoint_descriptor *desc,
 451                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 452                 bool ignore, bool restore)
 453 {
 454         struct dwc3             *dwc = dep->dwc;
 455         u32                     reg;
 456         int                     ret;
 457
 458         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 459
 460         if (!(dep->flags & DWC3_EP_ENABLED)) {
 461                 ret = dwc3_gadget_start_config(dwc, dep);
 462                 if (ret)
 463                         return ret;
 464         }
 465
 466         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 467                         restore);
 468         if (ret)
 469                 return ret;
 470
 471         if (!(dep->flags & DWC3_EP_ENABLED)) {
 472                 struct dwc3_trb *trb_st_hw;
 473                 struct dwc3_trb *trb_link;
 474
 475                 dep->endpoint.desc = desc;
 476                 dep->comp_desc = comp_desc;
 477                 dep->type = usb_endpoint_type(desc);
 478                 dep->flags |= DWC3_EP_ENABLED;
 479
 480                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 481                 reg |= DWC3_DALEPENA_EP(dep->number);
 482                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 483
 484                 if (!usb_endpoint_xfer_isoc(desc))
 485                         goto out;
 486
 487                 /* Link TRB for ISOC. The HWO bit is never reset */
 488                 trb_st_hw = &dep->trb_pool[0];
 489
 490                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 491                 memset(trb_link, 0, sizeof(*trb_link));
 492
 493                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 494                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 495                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 496                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 497         }
 498
 499 out:
 500         switch (usb_endpoint_type(desc)) {
 501         case USB_ENDPOINT_XFER_CONTROL:
 502                 /* don't change name */
 503                 break;
 504         case USB_ENDPOINT_XFER_ISOC:
 505                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 506                 break;
 507         case USB_ENDPOINT_XFER_BULK:
 508                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 509                 break;
 510         case USB_ENDPOINT_XFER_INT:
 511                 strlcat(dep->name, "-int", sizeof(dep->name));
 512                 break;
 513         default:
 514                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 515         }
 516
 517         return 0;
 518 }
 519
 520 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 521 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 522 {
 523         struct dwc3_request             *req;
 524
 525         if (!list_empty(&dep->started_list)) {
 526                 dwc3_stop_active_transfer(dwc, dep->number, true);
 527
 528                 /* - giveback all requests to gadget driver */
 529                 while (!list_empty(&dep->started_list)) {
 530                         req = next_request(&dep->started_list);
 531
 532                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 533                 }
 534         }
 535
 536         while (!list_empty(&dep->pending_list)) {
 537                 req = next_request(&dep->pending_list);
 538
 539                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 540         }
 541 }
 542
 543 /**
 544  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 545  * @dep: the endpoint to disable
 546  *
 547  * This function also removes requests which are currently processed ny the
 548  * hardware and those which are not yet scheduled.
 549  * Caller should take care of locking.
 550  */
 551 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 552 {
 553         struct dwc3             *dwc = dep->dwc;
 554         u32                     reg;
 555
 556         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 557
 558         dwc3_remove_requests(dwc, dep);
 559
 560         /* make sure HW endpoint isn't stalled */
 561         if (dep->flags & DWC3_EP_STALL)
 562                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 563
 564         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 565         reg &= ~DWC3_DALEPENA_EP(dep->number);
 566         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 567
 568         dep->stream_capable = false;
 569         dep->endpoint.desc = NULL;
 570         dep->comp_desc = NULL;
 571         dep->type = 0;
 572         dep->flags = 0;
 573
 574         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 575                         dep->number >> 1,
 576                         (dep->number & 1) ? "in" : "out");
 577
 578         return 0;
 579 }
 580
 581 /* -------------------------------------------------------------------------- */
 582
 583 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 584                 const struct usb_endpoint_descriptor *desc)
 585 {
 586         return -EINVAL;
 587 }
 588
 589 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 590 {
 591         return -EINVAL;
 592 }
 593
 594 /* -------------------------------------------------------------------------- */
 595
 596 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 597                 const struct usb_endpoint_descriptor *desc)
 598 {
 599         struct dwc3_ep                  *dep;
 600         struct dwc3                     *dwc;
 601         unsigned long                   flags;
 602         int                             ret;
 603
 604         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 605                 pr_debug("dwc3: invalid parameters\n");
 606                 return -EINVAL;
 607         }
 608
 609         if (!desc->wMaxPacketSize) {
 610                 pr_debug("dwc3: missing wMaxPacketSize\n");
 611                 return -EINVAL;
 612         }
 613
 614         dep = to_dwc3_ep(ep);
 615         dwc = dep->dwc;
 616
 617         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 618                                         "%s is already enabled\n",
 619                                         dep->name))
 620                 return 0;
 621
 622         spin_lock_irqsave(&dwc->lock, flags);
 623         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 624         spin_unlock_irqrestore(&dwc->lock, flags);
 625
 626         return ret;
 627 }
 628
 629 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 630 {
 631         struct dwc3_ep                  *dep;
 632         struct dwc3                     *dwc;
 633         unsigned long                   flags;
 634         int                             ret;
 635
 636         if (!ep) {
 637                 pr_debug("dwc3: invalid parameters\n");
 638                 return -EINVAL;
 639         }
 640
 641         dep = to_dwc3_ep(ep);
 642         dwc = dep->dwc;
 643
 644         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 645                                         "%s is already disabled\n",
 646                                         dep->name))
 647                 return 0;
 648
 649         spin_lock_irqsave(&dwc->lock, flags);
 650         ret = __dwc3_gadget_ep_disable(dep);
 651         spin_unlock_irqrestore(&dwc->lock, flags);
 652
 653         return ret;
 654 }
 655
 656 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 657         gfp_t gfp_flags)
 658 {
 659         struct dwc3_request             *req;
 660         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 661
 662         req = kzalloc(sizeof(*req), gfp_flags);
 663         if (!req)
 664                 return NULL;
 665
 666         req->epnum      = dep->number;
 667         req->dep        = dep;
 668
 669         trace_dwc3_alloc_request(req);
 670
 671         return &req->request;
 672 }
 673
 674 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 675                 struct usb_request *request)
 676 {
 677         struct dwc3_request             *req = to_dwc3_request(request);
 678
 679         trace_dwc3_free_request(req);
 680         kfree(req);
 681 }
 682
 683 /**
 684  * dwc3_prepare_one_trb - setup one TRB from one request
 685  * @dep: endpoint for which this request is prepared
 686  * @req: dwc3_request pointer
 687  */
 688 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 689                 struct dwc3_request *req, dma_addr_t dma,
 690                 unsigned length, unsigned last, unsigned chain, unsigned node)
 691 {
 692         struct dwc3_trb         *trb;
 693
 694         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 695                         dep->name, req, (unsigned long long) dma,
 696                         length, last ? " last" : "",
 697                         chain ? " chain" : "");
 698
 699
 700         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 701
 702         if (!req->trb) {
 703                 dwc3_gadget_move_started_request(req);
 704                 req->trb = trb;
 705                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 706                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 707         }
 708
 709         dep->free_slot++;
 710         /* Skip the LINK-TRB on ISOC */
 711         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 712                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 713                 dep->free_slot++;
 714
 715         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 716         trb->bpl = lower_32_bits(dma);
 717         trb->bph = upper_32_bits(dma);
 718
 719         switch (usb_endpoint_type(dep->endpoint.desc)) {
 720         case USB_ENDPOINT_XFER_CONTROL:
 721                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 722                 break;
 723
 724         case USB_ENDPOINT_XFER_ISOC:
 725                 if (!node)
 726                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 727                 else
 728                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 729
 730                 /* always enable Interrupt on Missed ISOC */
 731                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 732                 break;
 733
 734         case USB_ENDPOINT_XFER_BULK:
 735         case USB_ENDPOINT_XFER_INT:
 736                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 737                 break;
 738         default:
 739                 /*
 740                  * This is only possible with faulty memory because we
 741                  * checked it already :)
 742                  */
 743                 BUG();
 744         }
 745
 746         /* always enable Continue on Short Packet */
 747         trb->ctrl |= DWC3_TRB_CTRL_CSP;
 748
 749         if (!req->request.no_interrupt)
 750                 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
 751
 752         if (last)
 753                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 754
 755         if (chain)
 756                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 757
 758         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 759                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 760
 761         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 762
 763         trace_dwc3_prepare_trb(dep, trb);
 764 }
 765
 766 /*
 767  * dwc3_prepare_trbs - setup TRBs from requests
 768  * @dep: endpoint for which requests are being prepared
 769  * @starting: true if the endpoint is idle and no requests are queued.
 770  *
 771  * The function goes through the requests list and sets up TRBs for the
 772  * transfers. The function returns once there are no more TRBs available or
 773  * it runs out of requests.
 774  */
 775 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 776 {
 777         struct dwc3_request     *req, *n;
 778         u32                     trbs_left;
 779         u32                     max;
 780         unsigned int            last_one = 0;
 781
 782         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 783
 784         /* the first request must not be queued */
 785         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 786
 787         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 788         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 789                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 790                 if (trbs_left > max)
 791                         trbs_left = max;
 792         }
 793
 794         /*
 795          * If busy & slot are equal than it is either full or empty. If we are
 796          * starting to process requests then we are empty. Otherwise we are
 797          * full and don't do anything
 798          */
 799         if (!trbs_left) {
 800                 if (!starting)
 801                         return;
 802                 trbs_left = DWC3_TRB_NUM;
 803                 /*
 804                  * In case we start from scratch, we queue the ISOC requests
 805                  * starting from slot 1. This is done because we use ring
 806                  * buffer and have no LST bit to stop us. Instead, we place
 807                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 808                  * after the first request so we start at slot 1 and have
 809                  * 7 requests proceed before we hit the first IOC.
 810                  * Other transfer types don't use the ring buffer and are
 811                  * processed from the first TRB until the last one. Since we
 812                  * don't wrap around we have to start at the beginning.
 813                  */
 814                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 815                         dep->busy_slot = 1;
 816                         dep->free_slot = 1;
 817                 } else {
 818                         dep->busy_slot = 0;
 819                         dep->free_slot = 0;
 820                 }
 821         }
 822
 823         /* The last TRB is a link TRB, not used for xfer */
 824         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 825                 return;
 826
 827         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
 828                 unsigned        length;
 829                 dma_addr_t      dma;
 830                 last_one = false;
 831
 832                 if (req->request.num_mapped_sgs > 0) {
 833                         struct usb_request *request = &req->request;
 834                         struct scatterlist *sg = request->sg;
 835                         struct scatterlist *s;
 836                         int             i;
 837
 838                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 839                                 unsigned chain = true;
 840
 841                                 length = sg_dma_len(s);
 842                                 dma = sg_dma_address(s);
 843
 844                                 if (i == (request->num_mapped_sgs - 1) ||
 845                                                 sg_is_last(s)) {
 846                                         if (list_empty(&dep->pending_list))
 847                                                 last_one = true;
 848                                         chain = false;
 849                                 }
 850
 851                                 trbs_left--;
 852                                 if (!trbs_left)
 853                                         last_one = true;
 854
 855                                 if (last_one)
 856                                         chain = false;
 857
 858                                 dwc3_prepare_one_trb(dep, req, dma, length,
 859                                                 last_one, chain, i);
 860
 861                                 if (last_one)
 862                                         break;
 863                         }
 864
 865                         if (last_one)
 866                                 break;
 867                 } else {
 868                         dma = req->request.dma;
 869                         length = req->request.length;
 870                         trbs_left--;
 871
 872                         if (!trbs_left)
 873                                 last_one = 1;
 874
 875                         /* Is this the last request? */
 876                         if (list_is_last(&req->list, &dep->pending_list))
 877                                 last_one = 1;
 878
 879                         dwc3_prepare_one_trb(dep, req, dma, length,
 880                                         last_one, false, 0);
 881
 882                         if (last_one)
 883                                 break;
 884                 }
 885         }
 886 }
 887
 888 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 889                 int start_new)
 890 {
 891         struct dwc3_gadget_ep_cmd_params params;
 892         struct dwc3_request             *req;
 893         struct dwc3                     *dwc = dep->dwc;
 894         int                             ret;
 895         u32                             cmd;
 896
 897         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 898                 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
 899                 return -EBUSY;
 900         }
 901
 902         /*
 903          * If we are getting here after a short-out-packet we don't enqueue any
 904          * new requests as we try to set the IOC bit only on the last request.
 905          */
 906         if (start_new) {
 907                 if (list_empty(&dep->started_list))
 908                         dwc3_prepare_trbs(dep, start_new);
 909
 910                 /* req points to the first request which will be sent */
 911                 req = next_request(&dep->started_list);
 912         } else {
 913                 dwc3_prepare_trbs(dep, start_new);
 914
 915                 /*
 916                  * req points to the first request where HWO changed from 0 to 1
 917                  */
 918                 req = next_request(&dep->started_list);
 919         }
 920         if (!req) {
 921                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 922                 return 0;
 923         }
 924
 925         memset(&params, 0, sizeof(params));
 926
 927         if (start_new) {
 928                 params.param0 = upper_32_bits(req->trb_dma);
 929                 params.param1 = lower_32_bits(req->trb_dma);
 930                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 931         } else {
 932                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 933         }
 934
 935         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 936         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 937         if (ret < 0) {
 938                 /*
 939                  * FIXME we need to iterate over the list of requests
 940                  * here and stop, unmap, free and del each of the linked
 941                  * requests instead of what we do now.
 942                  */
 943                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 944                                 req->direction);
 945                 list_del(&req->list);
 946                 return ret;
 947         }
 948
 949         dep->flags |= DWC3_EP_BUSY;
 950
 951         if (start_new) {
 952                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 953                                 dep->number);
 954                 WARN_ON_ONCE(!dep->resource_index);
 955         }
 956
 957         return 0;
 958 }
 959
 960 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
 961                 struct dwc3_ep *dep, u32 cur_uf)
 962 {
 963         u32 uf;
 964
 965         if (list_empty(&dep->pending_list)) {
 966                 dwc3_trace(trace_dwc3_gadget,
 967                                 "ISOC ep %s run out for requests",
 968                                 dep->name);
 969                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 970                 return;
 971         }
 972
 973         /* 4 micro frames in the future */
 974         uf = cur_uf + dep->interval * 4;
 975
 976         __dwc3_gadget_kick_transfer(dep, uf, 1);
 977 }
 978
 979 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
 980                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
 981 {
 982         u32 cur_uf, mask;
 983
 984         mask = ~(dep->interval - 1);
 985         cur_uf = event->parameters & mask;
 986
 987         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
 988 }
 989
 990 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
 991 {
 992         struct dwc3             *dwc = dep->dwc;
 993         int                     ret;
 994
 995         if (!dep->endpoint.desc) {
 996                 dwc3_trace(trace_dwc3_gadget,
 997                                 "trying to queue request %p to disabled %s\n",
 998                                 &req->request, dep->endpoint.name);
 999                 return -ESHUTDOWN;
1000         }
1001
1002         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1003                                 &req->request, req->dep->name)) {
1004                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1005                                 &req->request, req->dep->name);
1006                 return -EINVAL;
1007         }
1008
1009         req->request.actual     = 0;
1010         req->request.status     = -EINPROGRESS;
1011         req->direction          = dep->direction;
1012         req->epnum              = dep->number;
1013
1014         trace_dwc3_ep_queue(req);
1015
1016         /*
1017          * We only add to our list of requests now and
1018          * start consuming the list once we get XferNotReady
1019          * IRQ.
1020          *
1021          * That way, we avoid doing anything that we don't need
1022          * to do now and defer it until the point we receive a
1023          * particular token from the Host side.
1024          *
1025          * This will also avoid Host cancelling URBs due to too
1026          * many NAKs.
1027          */
1028         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1029                         dep->direction);
1030         if (ret)
1031                 return ret;
1032
1033         list_add_tail(&req->list, &dep->pending_list);
1034
1035         /*
1036          * If there are no pending requests and the endpoint isn't already
1037          * busy, we will just start the request straight away.
1038          *
1039          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1040          * little bit faster.
1041          */
1042         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1043                         !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1044                         !(dep->flags & DWC3_EP_BUSY)) {
1045                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1046                 goto out;
1047         }
1048
1049         /*
1050          * There are a few special cases:
1051          *
1052          * 1. XferNotReady with empty list of requests. We need to kick the
1053          *    transfer here in that situation, otherwise we will be NAKing
1054          *    forever. If we get XferNotReady before gadget driver has a
1055          *    chance to queue a request, we will ACK the IRQ but won't be
1056          *    able to receive the data until the next request is queued.
1057          *    The following code is handling exactly that.
1058          *
1059          */
1060         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1061                 /*
1062                  * If xfernotready is already elapsed and it is a case
1063                  * of isoc transfer, then issue END TRANSFER, so that
1064                  * you can receive xfernotready again and can have
1065                  * notion of current microframe.
1066                  */
1067                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1068                         if (list_empty(&dep->started_list)) {
1069                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1070                                 dep->flags = DWC3_EP_ENABLED;
1071                         }
1072                         return 0;
1073                 }
1074
1075                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1076                 if (!ret)
1077                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1078
1079                 goto out;
1080         }
1081
1082         /*
1083          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1084          *    kick the transfer here after queuing a request, otherwise the
1085          *    core may not see the modified TRB(s).
1086          */
1087         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1088                         (dep->flags & DWC3_EP_BUSY) &&
1089                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1090                 WARN_ON_ONCE(!dep->resource_index);
1091                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1092                                 false);
1093                 goto out;
1094         }
1095
1096         /*
1097          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1098          * right away, otherwise host will not know we have streams to be
1099          * handled.
1100          */
1101         if (dep->stream_capable)
1102                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1103
1104 out:
1105         if (ret && ret != -EBUSY)
1106                 dwc3_trace(trace_dwc3_gadget,
1107                                 "%s: failed to kick transfers\n",
1108                                 dep->name);
1109         if (ret == -EBUSY)
1110                 ret = 0;
1111
1112         return ret;
1113 }
1114
1115 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1116                 struct usb_request *request)
1117 {
1118         dwc3_gadget_ep_free_request(ep, request);
1119 }
1120
1121 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1122 {
1123         struct dwc3_request             *req;
1124         struct usb_request              *request;
1125         struct usb_ep                   *ep = &dep->endpoint;
1126
1127         dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1128         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1129         if (!request)
1130                 return -ENOMEM;
1131
1132         request->length = 0;
1133         request->buf = dwc->zlp_buf;
1134         request->complete = __dwc3_gadget_ep_zlp_complete;
1135
1136         req = to_dwc3_request(request);
1137
1138         return __dwc3_gadget_ep_queue(dep, req);
1139 }
1140
1141 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1142         gfp_t gfp_flags)
1143 {
1144         struct dwc3_request             *req = to_dwc3_request(request);
1145         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1146         struct dwc3                     *dwc = dep->dwc;
1147
1148         unsigned long                   flags;
1149
1150         int                             ret;
1151
1152         spin_lock_irqsave(&dwc->lock, flags);
1153         ret = __dwc3_gadget_ep_queue(dep, req);
1154
1155         /*
1156          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1157          * setting request->zero, instead of doing magic, we will just queue an
1158          * extra usb_request ourselves so that it gets handled the same way as
1159          * any other request.
1160          */
1161         if (ret == 0 && request->zero && request->length &&
1162             (request->length % ep->maxpacket == 0))
1163                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1164
1165         spin_unlock_irqrestore(&dwc->lock, flags);
1166
1167         return ret;
1168 }
1169
1170 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1171                 struct usb_request *request)
1172 {
1173         struct dwc3_request             *req = to_dwc3_request(request);
1174         struct dwc3_request             *r = NULL;
1175
1176         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1177         struct dwc3                     *dwc = dep->dwc;
1178
1179         unsigned long                   flags;
1180         int                             ret = 0;
1181
1182         trace_dwc3_ep_dequeue(req);
1183
1184         spin_lock_irqsave(&dwc->lock, flags);
1185
1186         list_for_each_entry(r, &dep->pending_list, list) {
1187                 if (r == req)
1188                         break;
1189         }
1190
1191         if (r != req) {
1192                 list_for_each_entry(r, &dep->started_list, list) {
1193                         if (r == req)
1194                                 break;
1195                 }
1196                 if (r == req) {
1197                         /* wait until it is processed */
1198                         dwc3_stop_active_transfer(dwc, dep->number, true);
1199                         goto out1;
1200                 }
1201                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1202                                 request, ep->name);
1203                 ret = -EINVAL;
1204                 goto out0;
1205         }
1206
1207 out1:
1208         /* giveback the request */
1209         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1210
1211 out0:
1212         spin_unlock_irqrestore(&dwc->lock, flags);
1213
1214         return ret;
1215 }
1216
1217 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1218 {
1219         struct dwc3_gadget_ep_cmd_params        params;
1220         struct dwc3                             *dwc = dep->dwc;
1221         int                                     ret;
1222
1223         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1224                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1225                 return -EINVAL;
1226         }
1227
1228         memset(&params, 0x00, sizeof(params));
1229
1230         if (value) {
1231                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1232                                 (!list_empty(&dep->started_list) ||
1233                                  !list_empty(&dep->pending_list)))) {
1234                         dwc3_trace(trace_dwc3_gadget,
1235                                         "%s: pending request, cannot halt\n",
1236                                         dep->name);
1237                         return -EAGAIN;
1238                 }
1239
1240                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1241                         DWC3_DEPCMD_SETSTALL, &params);
1242                 if (ret)
1243                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1244                                         dep->name);
1245                 else
1246                         dep->flags |= DWC3_EP_STALL;
1247         } else {
1248                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1249                         DWC3_DEPCMD_CLEARSTALL, &params);
1250                 if (ret)
1251                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1252                                         dep->name);
1253                 else
1254                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1255         }
1256
1257         return ret;
1258 }
1259
1260 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1261 {
1262         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1263         struct dwc3                     *dwc = dep->dwc;
1264
1265         unsigned long                   flags;
1266
1267         int                             ret;
1268
1269         spin_lock_irqsave(&dwc->lock, flags);
1270         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1271         spin_unlock_irqrestore(&dwc->lock, flags);
1272
1273         return ret;
1274 }
1275
1276 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1277 {
1278         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1279         struct dwc3                     *dwc = dep->dwc;
1280         unsigned long                   flags;
1281         int                             ret;
1282
1283         spin_lock_irqsave(&dwc->lock, flags);
1284         dep->flags |= DWC3_EP_WEDGE;
1285
1286         if (dep->number == 0 || dep->number == 1)
1287                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1288         else
1289                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1290         spin_unlock_irqrestore(&dwc->lock, flags);
1291
1292         return ret;
1293 }
1294
1295 /* -------------------------------------------------------------------------- */
1296
1297 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1298         .bLength        = USB_DT_ENDPOINT_SIZE,
1299         .bDescriptorType = USB_DT_ENDPOINT,
1300         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1301 };
1302
1303 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1304         .enable         = dwc3_gadget_ep0_enable,
1305         .disable        = dwc3_gadget_ep0_disable,
1306         .alloc_request  = dwc3_gadget_ep_alloc_request,
1307         .free_request   = dwc3_gadget_ep_free_request,
1308         .queue          = dwc3_gadget_ep0_queue,
1309         .dequeue        = dwc3_gadget_ep_dequeue,
1310         .set_halt       = dwc3_gadget_ep0_set_halt,
1311         .set_wedge      = dwc3_gadget_ep_set_wedge,
1312 };
1313
1314 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1315         .enable         = dwc3_gadget_ep_enable,
1316         .disable        = dwc3_gadget_ep_disable,
1317         .alloc_request  = dwc3_gadget_ep_alloc_request,
1318         .free_request   = dwc3_gadget_ep_free_request,
1319         .queue          = dwc3_gadget_ep_queue,
1320         .dequeue        = dwc3_gadget_ep_dequeue,
1321         .set_halt       = dwc3_gadget_ep_set_halt,
1322         .set_wedge      = dwc3_gadget_ep_set_wedge,
1323 };
1324
1325 /* -------------------------------------------------------------------------- */
1326
1327 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1328 {
1329         struct dwc3             *dwc = gadget_to_dwc(g);
1330         u32                     reg;
1331
1332         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1333         return DWC3_DSTS_SOFFN(reg);
1334 }
1335
1336 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1337 {
1338         struct dwc3             *dwc = gadget_to_dwc(g);
1339
1340         unsigned long           timeout;
1341         unsigned long           flags;
1342
1343         u32                     reg;
1344
1345         int                     ret = 0;
1346
1347         u8                      link_state;
1348         u8                      speed;
1349
1350         spin_lock_irqsave(&dwc->lock, flags);
1351
1352         /*
1353          * According to the Databook Remote wakeup request should
1354          * be issued only when the device is in early suspend state.
1355          *
1356          * We can check that via USB Link State bits in DSTS register.
1357          */
1358         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1359
1360         speed = reg & DWC3_DSTS_CONNECTSPD;
1361         if ((speed == DWC3_DSTS_SUPERSPEED) ||
1362             (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
1363                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1364                 ret = -EINVAL;
1365                 goto out;
1366         }
1367
1368         link_state = DWC3_DSTS_USBLNKST(reg);
1369
1370         switch (link_state) {
1371         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1372         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1373                 break;
1374         default:
1375                 dwc3_trace(trace_dwc3_gadget,
1376                                 "can't wakeup from '%s'\n",
1377                                 dwc3_gadget_link_string(link_state));
1378                 ret = -EINVAL;
1379                 goto out;
1380         }
1381
1382         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1383         if (ret < 0) {
1384                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1385                 goto out;
1386         }
1387
1388         /* Recent versions do this automatically */
1389         if (dwc->revision < DWC3_REVISION_194A) {
1390                 /* write zeroes to Link Change Request */
1391                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1392                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1393                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1394         }
1395
1396         /* poll until Link State changes to ON */
1397         timeout = jiffies + msecs_to_jiffies(100);
1398
1399         while (!time_after(jiffies, timeout)) {
1400                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1401
1402                 /* in HS, means ON */
1403                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1404                         break;
1405         }
1406
1407         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1408                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1409                 ret = -EINVAL;
1410         }
1411
1412 out:
1413         spin_unlock_irqrestore(&dwc->lock, flags);
1414
1415         return ret;
1416 }
1417
1418 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1419                 int is_selfpowered)
1420 {
1421         struct dwc3             *dwc = gadget_to_dwc(g);
1422         unsigned long           flags;
1423
1424         spin_lock_irqsave(&dwc->lock, flags);
1425         g->is_selfpowered = !!is_selfpowered;
1426         spin_unlock_irqrestore(&dwc->lock, flags);
1427
1428         return 0;
1429 }
1430
1431 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1432 {
1433         u32                     reg;
1434         u32                     timeout = 500;
1435
1436         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1437         if (is_on) {
1438                 if (dwc->revision <= DWC3_REVISION_187A) {
1439                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1440                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1441                 }
1442
1443                 if (dwc->revision >= DWC3_REVISION_194A)
1444                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1445                 reg |= DWC3_DCTL_RUN_STOP;
1446
1447                 if (dwc->has_hibernation)
1448                         reg |= DWC3_DCTL_KEEP_CONNECT;
1449
1450                 dwc->pullups_connected = true;
1451         } else {
1452                 reg &= ~DWC3_DCTL_RUN_STOP;
1453
1454                 if (dwc->has_hibernation && !suspend)
1455                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1456
1457                 dwc->pullups_connected = false;
1458         }
1459
1460         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1461
1462         do {
1463                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1464                 if (is_on) {
1465                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1466                                 break;
1467                 } else {
1468                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1469                                 break;
1470                 }
1471                 timeout--;
1472                 if (!timeout)
1473                         return -ETIMEDOUT;
1474                 udelay(1);
1475         } while (1);
1476
1477         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1478                         dwc->gadget_driver
1479                         ? dwc->gadget_driver->function : "no-function",
1480                         is_on ? "connect" : "disconnect");
1481
1482         return 0;
1483 }
1484
1485 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1486 {
1487         struct dwc3             *dwc = gadget_to_dwc(g);
1488         unsigned long           flags;
1489         int                     ret;
1490
1491         is_on = !!is_on;
1492
1493         spin_lock_irqsave(&dwc->lock, flags);
1494         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1495         spin_unlock_irqrestore(&dwc->lock, flags);
1496
1497         return ret;
1498 }
1499
1500 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1501 {
1502         u32                     reg;
1503
1504         /* Enable all but Start and End of Frame IRQs */
1505         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1506                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1507                         DWC3_DEVTEN_CMDCMPLTEN |
1508                         DWC3_DEVTEN_ERRTICERREN |
1509                         DWC3_DEVTEN_WKUPEVTEN |
1510                         DWC3_DEVTEN_ULSTCNGEN |
1511                         DWC3_DEVTEN_CONNECTDONEEN |
1512                         DWC3_DEVTEN_USBRSTEN |
1513                         DWC3_DEVTEN_DISCONNEVTEN);
1514
1515         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1516 }
1517
1518 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1519 {
1520         /* mask all interrupts */
1521         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1522 }
1523
1524 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1525 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1526
1527 static int dwc3_gadget_start(struct usb_gadget *g,
1528                 struct usb_gadget_driver *driver)
1529 {
1530         struct dwc3             *dwc = gadget_to_dwc(g);
1531         struct dwc3_ep          *dep;
1532         unsigned long           flags;
1533         int                     ret = 0;
1534         int                     irq;
1535         u32                     reg;
1536
1537         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1538         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1539                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1540         if (ret) {
1541                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1542                                 irq, ret);
1543                 goto err0;
1544         }
1545
1546         spin_lock_irqsave(&dwc->lock, flags);
1547
1548         if (dwc->gadget_driver) {
1549                 dev_err(dwc->dev, "%s is already bound to %s\n",
1550                                 dwc->gadget.name,
1551                                 dwc->gadget_driver->driver.name);
1552                 ret = -EBUSY;
1553                 goto err1;
1554         }
1555
1556         dwc->gadget_driver      = driver;
1557
1558         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1559         reg &= ~(DWC3_DCFG_SPEED_MASK);
1560
1561         /**
1562          * WORKAROUND: DWC3 revision < 2.20a have an issue
1563          * which would cause metastability state on Run/Stop
1564          * bit if we try to force the IP to USB2-only mode.
1565          *
1566          * Because of that, we cannot configure the IP to any
1567          * speed other than the SuperSpeed
1568          *
1569          * Refers to:
1570          *
1571          * STAR#9000525659: Clock Domain Crossing on DCTL in
1572          * USB 2.0 Mode
1573          */
1574         if (dwc->revision < DWC3_REVISION_220A) {
1575                 reg |= DWC3_DCFG_SUPERSPEED;
1576         } else {
1577                 switch (dwc->maximum_speed) {
1578                 case USB_SPEED_LOW:
1579                         reg |= DWC3_DSTS_LOWSPEED;
1580                         break;
1581                 case USB_SPEED_FULL:
1582                         reg |= DWC3_DSTS_FULLSPEED1;
1583                         break;
1584                 case USB_SPEED_HIGH:
1585                         reg |= DWC3_DSTS_HIGHSPEED;
1586                         break;
1587                 case USB_SPEED_SUPER_PLUS:
1588                         reg |= DWC3_DSTS_SUPERSPEED_PLUS;
1589                         break;
1590                 default:
1591                         dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1592                                 dwc->maximum_speed);
1593                         /* fall through */
1594                 case USB_SPEED_SUPER:
1595                         reg |= DWC3_DCFG_SUPERSPEED;
1596                         break;
1597                 }
1598         }
1599         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1600
1601         /* Start with SuperSpeed Default */
1602         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1603
1604         dep = dwc->eps[0];
1605         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1606                         false);
1607         if (ret) {
1608                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1609                 goto err2;
1610         }
1611
1612         dep = dwc->eps[1];
1613         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1614                         false);
1615         if (ret) {
1616                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1617                 goto err3;
1618         }
1619
1620         /* begin to receive SETUP packets */
1621         dwc->ep0state = EP0_SETUP_PHASE;
1622         dwc3_ep0_out_start(dwc);
1623
1624         dwc3_gadget_enable_irq(dwc);
1625
1626         spin_unlock_irqrestore(&dwc->lock, flags);
1627
1628         return 0;
1629
1630 err3:
1631         __dwc3_gadget_ep_disable(dwc->eps[0]);
1632
1633 err2:
1634         dwc->gadget_driver = NULL;
1635
1636 err1:
1637         spin_unlock_irqrestore(&dwc->lock, flags);
1638
1639         free_irq(irq, dwc->ev_buf);
1640
1641 err0:
1642         return ret;
1643 }
1644
1645 static int dwc3_gadget_stop(struct usb_gadget *g)
1646 {
1647         struct dwc3             *dwc = gadget_to_dwc(g);
1648         unsigned long           flags;
1649         int                     irq;
1650
1651         spin_lock_irqsave(&dwc->lock, flags);
1652
1653         dwc3_gadget_disable_irq(dwc);
1654         __dwc3_gadget_ep_disable(dwc->eps[0]);
1655         __dwc3_gadget_ep_disable(dwc->eps[1]);
1656
1657         dwc->gadget_driver      = NULL;
1658
1659         spin_unlock_irqrestore(&dwc->lock, flags);
1660
1661         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1662         free_irq(irq, dwc->ev_buf);
1663
1664         return 0;
1665 }
1666
1667 static const struct usb_gadget_ops dwc3_gadget_ops = {
1668         .get_frame              = dwc3_gadget_get_frame,
1669         .wakeup                 = dwc3_gadget_wakeup,
1670         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1671         .pullup                 = dwc3_gadget_pullup,
1672         .udc_start              = dwc3_gadget_start,
1673         .udc_stop               = dwc3_gadget_stop,
1674 };
1675
1676 /* -------------------------------------------------------------------------- */
1677
1678 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1679                 u8 num, u32 direction)
1680 {
1681         struct dwc3_ep                  *dep;
1682         u8                              i;
1683
1684         for (i = 0; i < num; i++) {
1685                 u8 epnum = (i << 1) | (!!direction);
1686
1687                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1688                 if (!dep)
1689                         return -ENOMEM;
1690
1691                 dep->dwc = dwc;
1692                 dep->number = epnum;
1693                 dep->direction = !!direction;
1694                 dwc->eps[epnum] = dep;
1695
1696                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1697                                 (epnum & 1) ? "in" : "out");
1698
1699                 dep->endpoint.name = dep->name;
1700
1701                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1702
1703                 if (epnum == 0 || epnum == 1) {
1704                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1705                         dep->endpoint.maxburst = 1;
1706                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1707                         if (!epnum)
1708                                 dwc->gadget.ep0 = &dep->endpoint;
1709                 } else {
1710                         int             ret;
1711
1712                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1713                         dep->endpoint.max_streams = 15;
1714                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1715                         list_add_tail(&dep->endpoint.ep_list,
1716                                         &dwc->gadget.ep_list);
1717
1718                         ret = dwc3_alloc_trb_pool(dep);
1719                         if (ret)
1720                                 return ret;
1721                 }
1722
1723                 if (epnum == 0 || epnum == 1) {
1724                         dep->endpoint.caps.type_control = true;
1725                 } else {
1726                         dep->endpoint.caps.type_iso = true;
1727                         dep->endpoint.caps.type_bulk = true;
1728                         dep->endpoint.caps.type_int = true;
1729                 }
1730
1731                 dep->endpoint.caps.dir_in = !!direction;
1732                 dep->endpoint.caps.dir_out = !direction;
1733
1734                 INIT_LIST_HEAD(&dep->pending_list);
1735                 INIT_LIST_HEAD(&dep->started_list);
1736         }
1737
1738         return 0;
1739 }
1740
1741 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1742 {
1743         int                             ret;
1744
1745         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1746
1747         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1748         if (ret < 0) {
1749                 dwc3_trace(trace_dwc3_gadget,
1750                                 "failed to allocate OUT endpoints");
1751                 return ret;
1752         }
1753
1754         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1755         if (ret < 0) {
1756                 dwc3_trace(trace_dwc3_gadget,
1757                                 "failed to allocate IN endpoints");
1758                 return ret;
1759         }
1760
1761         return 0;
1762 }
1763
1764 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1765 {
1766         struct dwc3_ep                  *dep;
1767         u8                              epnum;
1768
1769         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1770                 dep = dwc->eps[epnum];
1771                 if (!dep)
1772                         continue;
1773                 /*
1774                  * Physical endpoints 0 and 1 are special; they form the
1775                  * bi-directional USB endpoint 0.
1776                  *
1777                  * For those two physical endpoints, we don't allocate a TRB
1778                  * pool nor do we add them the endpoints list. Due to that, we
1779                  * shouldn't do these two operations otherwise we would end up
1780                  * with all sorts of bugs when removing dwc3.ko.
1781                  */
1782                 if (epnum != 0 && epnum != 1) {
1783                         dwc3_free_trb_pool(dep);
1784                         list_del(&dep->endpoint.ep_list);
1785                 }
1786
1787                 kfree(dep);
1788         }
1789 }
1790
1791 /* -------------------------------------------------------------------------- */
1792
1793 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1794                 struct dwc3_request *req, struct dwc3_trb *trb,
1795                 const struct dwc3_event_depevt *event, int status)
1796 {
1797         unsigned int            count;
1798         unsigned int            s_pkt = 0;
1799         unsigned int            trb_status;
1800
1801         trace_dwc3_complete_trb(dep, trb);
1802
1803         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1804                 /*
1805                  * We continue despite the error. There is not much we
1806                  * can do. If we don't clean it up we loop forever. If
1807                  * we skip the TRB then it gets overwritten after a
1808                  * while since we use them in a ring buffer. A BUG()
1809                  * would help. Lets hope that if this occurs, someone
1810                  * fixes the root cause instead of looking away :)
1811                  */
1812                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1813                                 dep->name, trb);
1814         count = trb->size & DWC3_TRB_SIZE_MASK;
1815
1816         if (dep->direction) {
1817                 if (count) {
1818                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1819                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1820                                 dwc3_trace(trace_dwc3_gadget,
1821                                                 "%s: incomplete IN transfer\n",
1822                                                 dep->name);
1823                                 /*
1824                                  * If missed isoc occurred and there is
1825                                  * no request queued then issue END
1826                                  * TRANSFER, so that core generates
1827                                  * next xfernotready and we will issue
1828                                  * a fresh START TRANSFER.
1829                                  * If there are still queued request
1830                                  * then wait, do not issue either END
1831                                  * or UPDATE TRANSFER, just attach next
1832                                  * request in pending_list during
1833                                  * giveback.If any future queued request
1834                                  * is successfully transferred then we
1835                                  * will issue UPDATE TRANSFER for all
1836                                  * request in the pending_list.
1837                                  */
1838                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1839                         } else {
1840                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1841                                                 dep->name);
1842                                 status = -ECONNRESET;
1843                         }
1844                 } else {
1845                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1846                 }
1847         } else {
1848                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1849                         s_pkt = 1;
1850         }
1851
1852         /*
1853          * We assume here we will always receive the entire data block
1854          * which we should receive. Meaning, if we program RX to
1855          * receive 4K but we receive only 2K, we assume that's all we
1856          * should receive and we simply bounce the request back to the
1857          * gadget driver for further processing.
1858          */
1859         req->request.actual += req->request.length - count;
1860         if (s_pkt)
1861                 return 1;
1862         if ((event->status & DEPEVT_STATUS_LST) &&
1863                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1864                                 DWC3_TRB_CTRL_HWO)))
1865                 return 1;
1866         if ((event->status & DEPEVT_STATUS_IOC) &&
1867                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1868                 return 1;
1869         return 0;
1870 }
1871
1872 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1873                 const struct dwc3_event_depevt *event, int status)
1874 {
1875         struct dwc3_request     *req;
1876         struct dwc3_trb         *trb;
1877         unsigned int            slot;
1878         unsigned int            i;
1879         int                     ret;
1880
1881         do {
1882                 req = next_request(&dep->started_list);
1883                 if (WARN_ON_ONCE(!req))
1884                         return 1;
1885
1886                 i = 0;
1887                 do {
1888                         slot = req->start_slot + i;
1889                         if ((slot == DWC3_TRB_NUM - 1) &&
1890                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1891                                 slot++;
1892                         slot %= DWC3_TRB_NUM;
1893                         trb = &dep->trb_pool[slot];
1894
1895                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1896                                         event, status);
1897                         if (ret)
1898                                 break;
1899                 } while (++i < req->request.num_mapped_sgs);
1900
1901                 dwc3_gadget_giveback(dep, req, status);
1902
1903                 if (ret)
1904                         break;
1905         } while (1);
1906
1907         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1908                         list_empty(&dep->started_list)) {
1909                 if (list_empty(&dep->pending_list)) {
1910                         /*
1911                          * If there is no entry in request list then do
1912                          * not issue END TRANSFER now. Just set PENDING
1913                          * flag, so that END TRANSFER is issued when an
1914                          * entry is added into request list.
1915                          */
1916                         dep->flags = DWC3_EP_PENDING_REQUEST;
1917                 } else {
1918                         dwc3_stop_active_transfer(dwc, dep->number, true);
1919                         dep->flags = DWC3_EP_ENABLED;
1920                 }
1921                 return 1;
1922         }
1923
1924         return 1;
1925 }
1926
1927 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1928                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1929 {
1930         unsigned                status = 0;
1931         int                     clean_busy;
1932         u32                     is_xfer_complete;
1933
1934         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
1935
1936         if (event->status & DEPEVT_STATUS_BUSERR)
1937                 status = -ECONNRESET;
1938
1939         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1940         if (clean_busy && (is_xfer_complete ||
1941                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
1942                 dep->flags &= ~DWC3_EP_BUSY;
1943
1944         /*
1945          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1946          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1947          */
1948         if (dwc->revision < DWC3_REVISION_183A) {
1949                 u32             reg;
1950                 int             i;
1951
1952                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1953                         dep = dwc->eps[i];
1954
1955                         if (!(dep->flags & DWC3_EP_ENABLED))
1956                                 continue;
1957
1958                         if (!list_empty(&dep->started_list))
1959                                 return;
1960                 }
1961
1962                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1963                 reg |= dwc->u1u2;
1964                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1965
1966                 dwc->u1u2 = 0;
1967         }
1968
1969         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1970                 int ret;
1971
1972                 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
1973                 if (!ret || ret == -EBUSY)
1974                         return;
1975         }
1976 }
1977
1978 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1979                 const struct dwc3_event_depevt *event)
1980 {
1981         struct dwc3_ep          *dep;
1982         u8                      epnum = event->endpoint_number;
1983
1984         dep = dwc->eps[epnum];
1985
1986         if (!(dep->flags & DWC3_EP_ENABLED))
1987                 return;
1988
1989         if (epnum == 0 || epnum == 1) {
1990                 dwc3_ep0_interrupt(dwc, event);
1991                 return;
1992         }
1993
1994         switch (event->endpoint_event) {
1995         case DWC3_DEPEVT_XFERCOMPLETE:
1996                 dep->resource_index = 0;
1997
1998                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1999                         dwc3_trace(trace_dwc3_gadget,
2000                                         "%s is an Isochronous endpoint\n",
2001                                         dep->name);
2002                         return;
2003                 }
2004
2005                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2006                 break;
2007         case DWC3_DEPEVT_XFERINPROGRESS:
2008                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2009                 break;
2010         case DWC3_DEPEVT_XFERNOTREADY:
2011                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2012                         dwc3_gadget_start_isoc(dwc, dep, event);
2013                 } else {
2014                         int active;
2015                         int ret;
2016
2017                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2018
2019                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2020                                         dep->name, active ? "Transfer Active"
2021                                         : "Transfer Not Active");
2022
2023                         ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
2024                         if (!ret || ret == -EBUSY)
2025                                 return;
2026
2027                         dwc3_trace(trace_dwc3_gadget,
2028                                         "%s: failed to kick transfers\n",
2029                                         dep->name);
2030                 }
2031
2032                 break;
2033         case DWC3_DEPEVT_STREAMEVT:
2034                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2035                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2036                                         dep->name);
2037                         return;
2038                 }
2039
2040                 switch (event->status) {
2041                 case DEPEVT_STREAMEVT_FOUND:
2042                         dwc3_trace(trace_dwc3_gadget,
2043                                         "Stream %d found and started",
2044                                         event->parameters);
2045
2046                         break;
2047                 case DEPEVT_STREAMEVT_NOTFOUND:
2048                         /* FALLTHROUGH */
2049                 default:
2050                         dwc3_trace(trace_dwc3_gadget,
2051                                         "unable to find suitable stream\n");
2052                 }
2053                 break;
2054         case DWC3_DEPEVT_RXTXFIFOEVT:
2055                 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2056                 break;
2057         case DWC3_DEPEVT_EPCMDCMPLT:
2058                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2059                 break;
2060         }
2061 }
2062
2063 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2064 {
2065         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2066                 spin_unlock(&dwc->lock);
2067                 dwc->gadget_driver->disconnect(&dwc->gadget);
2068                 spin_lock(&dwc->lock);
2069         }
2070 }
2071
2072 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2073 {
2074         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2075                 spin_unlock(&dwc->lock);
2076                 dwc->gadget_driver->suspend(&dwc->gadget);
2077                 spin_lock(&dwc->lock);
2078         }
2079 }
2080
2081 static void dwc3_resume_gadget(struct dwc3 *dwc)
2082 {
2083         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2084                 spin_unlock(&dwc->lock);
2085                 dwc->gadget_driver->resume(&dwc->gadget);
2086                 spin_lock(&dwc->lock);
2087         }
2088 }
2089
2090 static void dwc3_reset_gadget(struct dwc3 *dwc)
2091 {
2092         if (!dwc->gadget_driver)
2093                 return;
2094
2095         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2096                 spin_unlock(&dwc->lock);
2097                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2098                 spin_lock(&dwc->lock);
2099         }
2100 }
2101
2102 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2103 {
2104         struct dwc3_ep *dep;
2105         struct dwc3_gadget_ep_cmd_params params;
2106         u32 cmd;
2107         int ret;
2108
2109         dep = dwc->eps[epnum];
2110
2111         if (!dep->resource_index)
2112                 return;
2113
2114         /*
2115          * NOTICE: We are violating what the Databook says about the
2116          * EndTransfer command. Ideally we would _always_ wait for the
2117          * EndTransfer Command Completion IRQ, but that's causing too
2118          * much trouble synchronizing between us and gadget driver.
2119          *
2120          * We have discussed this with the IP Provider and it was
2121          * suggested to giveback all requests here, but give HW some
2122          * extra time to synchronize with the interconnect. We're using
2123          * an arbitrary 100us delay for that.
2124          *
2125          * Note also that a similar handling was tested by Synopsys
2126          * (thanks a lot Paul) and nothing bad has come out of it.
2127          * In short, what we're doing is:
2128          *
2129          * - Issue EndTransfer WITH CMDIOC bit set
2130          * - Wait 100us
2131          */
2132
2133         cmd = DWC3_DEPCMD_ENDTRANSFER;
2134         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2135         cmd |= DWC3_DEPCMD_CMDIOC;
2136         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2137         memset(&params, 0, sizeof(params));
2138         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2139         WARN_ON_ONCE(ret);
2140         dep->resource_index = 0;
2141         dep->flags &= ~DWC3_EP_BUSY;
2142         udelay(100);
2143 }
2144
2145 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2146 {
2147         u32 epnum;
2148
2149         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2150                 struct dwc3_ep *dep;
2151
2152                 dep = dwc->eps[epnum];
2153                 if (!dep)
2154                         continue;
2155
2156                 if (!(dep->flags & DWC3_EP_ENABLED))
2157                         continue;
2158
2159                 dwc3_remove_requests(dwc, dep);
2160         }
2161 }
2162
2163 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2164 {
2165         u32 epnum;
2166
2167         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2168                 struct dwc3_ep *dep;
2169                 struct dwc3_gadget_ep_cmd_params params;
2170                 int ret;
2171
2172                 dep = dwc->eps[epnum];
2173                 if (!dep)
2174                         continue;
2175
2176                 if (!(dep->flags & DWC3_EP_STALL))
2177                         continue;
2178
2179                 dep->flags &= ~DWC3_EP_STALL;
2180
2181                 memset(&params, 0, sizeof(params));
2182                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2183                                 DWC3_DEPCMD_CLEARSTALL, &params);
2184                 WARN_ON_ONCE(ret);
2185         }
2186 }
2187
2188 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2189 {
2190         int                     reg;
2191
2192         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2193         reg &= ~DWC3_DCTL_INITU1ENA;
2194         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2195
2196         reg &= ~DWC3_DCTL_INITU2ENA;
2197         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2198
2199         dwc3_disconnect_gadget(dwc);
2200
2201         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2202         dwc->setup_packet_pending = false;
2203         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2204 }
2205
2206 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2207 {
2208         u32                     reg;
2209
2210         /*
2211          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2212          * would cause a missing Disconnect Event if there's a
2213          * pending Setup Packet in the FIFO.
2214          *
2215          * There's no suggested workaround on the official Bug
2216          * report, which states that "unless the driver/application
2217          * is doing any special handling of a disconnect event,
2218          * there is no functional issue".
2219          *
2220          * Unfortunately, it turns out that we _do_ some special
2221          * handling of a disconnect event, namely complete all
2222          * pending transfers, notify gadget driver of the
2223          * disconnection, and so on.
2224          *
2225          * Our suggested workaround is to follow the Disconnect
2226          * Event steps here, instead, based on a setup_packet_pending
2227          * flag. Such flag gets set whenever we have a SETUP_PENDING
2228          * status for EP0 TRBs and gets cleared on XferComplete for the
2229          * same endpoint.
2230          *
2231          * Refers to:
2232          *
2233          * STAR#9000466709: RTL: Device : Disconnect event not
2234          * generated if setup packet pending in FIFO
2235          */
2236         if (dwc->revision < DWC3_REVISION_188A) {
2237                 if (dwc->setup_packet_pending)
2238                         dwc3_gadget_disconnect_interrupt(dwc);
2239         }
2240
2241         dwc3_reset_gadget(dwc);
2242
2243         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2244         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2245         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2246         dwc->test_mode = false;
2247
2248         dwc3_stop_active_transfers(dwc);
2249         dwc3_clear_stall_all_ep(dwc);
2250
2251         /* Reset device address to zero */
2252         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2253         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2254         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2255 }
2256
2257 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2258 {
2259         u32 reg;
2260         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2261
2262         /*
2263          * We change the clock only at SS but I dunno why I would want to do
2264          * this. Maybe it becomes part of the power saving plan.
2265          */
2266
2267         if ((speed != DWC3_DSTS_SUPERSPEED) &&
2268             (speed != DWC3_DSTS_SUPERSPEED_PLUS))
2269                 return;
2270
2271         /*
2272          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2273          * each time on Connect Done.
2274          */
2275         if (!usb30_clock)
2276                 return;
2277
2278         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2279         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2280         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2281 }
2282
2283 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2284 {
2285         struct dwc3_ep          *dep;
2286         int                     ret;
2287         u32                     reg;
2288         u8                      speed;
2289
2290         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2291         speed = reg & DWC3_DSTS_CONNECTSPD;
2292         dwc->speed = speed;
2293
2294         dwc3_update_ram_clk_sel(dwc, speed);
2295
2296         switch (speed) {
2297         case DWC3_DCFG_SUPERSPEED_PLUS:
2298                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2299                 dwc->gadget.ep0->maxpacket = 512;
2300                 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2301                 break;
2302         case DWC3_DCFG_SUPERSPEED:
2303                 /*
2304                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2305                  * would cause a missing USB3 Reset event.
2306                  *
2307                  * In such situations, we should force a USB3 Reset
2308                  * event by calling our dwc3_gadget_reset_interrupt()
2309                  * routine.
2310                  *
2311                  * Refers to:
2312                  *
2313                  * STAR#9000483510: RTL: SS : USB3 reset event may
2314                  * not be generated always when the link enters poll
2315                  */
2316                 if (dwc->revision < DWC3_REVISION_190A)
2317                         dwc3_gadget_reset_interrupt(dwc);
2318
2319                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2320                 dwc->gadget.ep0->maxpacket = 512;
2321                 dwc->gadget.speed = USB_SPEED_SUPER;
2322                 break;
2323         case DWC3_DCFG_HIGHSPEED:
2324                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2325                 dwc->gadget.ep0->maxpacket = 64;
2326                 dwc->gadget.speed = USB_SPEED_HIGH;
2327                 break;
2328         case DWC3_DCFG_FULLSPEED2:
2329         case DWC3_DCFG_FULLSPEED1:
2330                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2331                 dwc->gadget.ep0->maxpacket = 64;
2332                 dwc->gadget.speed = USB_SPEED_FULL;
2333                 break;
2334         case DWC3_DCFG_LOWSPEED:
2335                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2336                 dwc->gadget.ep0->maxpacket = 8;
2337                 dwc->gadget.speed = USB_SPEED_LOW;
2338                 break;
2339         }
2340
2341         /* Enable USB2 LPM Capability */
2342
2343         if ((dwc->revision > DWC3_REVISION_194A) &&
2344             (speed != DWC3_DCFG_SUPERSPEED) &&
2345             (speed != DWC3_DCFG_SUPERSPEED_PLUS)) {
2346                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2347                 reg |= DWC3_DCFG_LPM_CAP;
2348                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2349
2350                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2351                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2352
2353                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2354
2355                 /*
2356                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2357                  * DCFG.LPMCap is set, core responses with an ACK and the
2358                  * BESL value in the LPM token is less than or equal to LPM
2359                  * NYET threshold.
2360                  */
2361                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2362                                 && dwc->has_lpm_erratum,
2363                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2364
2365                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2366                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2367
2368                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2369         } else {
2370                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2371                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2372                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2373         }
2374
2375         dep = dwc->eps[0];
2376         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2377                         false);
2378         if (ret) {
2379                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2380                 return;
2381         }
2382
2383         dep = dwc->eps[1];
2384         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2385                         false);
2386         if (ret) {
2387                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2388                 return;
2389         }
2390
2391         /*
2392          * Configure PHY via GUSB3PIPECTLn if required.
2393          *
2394          * Update GTXFIFOSIZn
2395          *
2396          * In both cases reset values should be sufficient.
2397          */
2398 }
2399
2400 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2401 {
2402         /*
2403          * TODO take core out of low power mode when that's
2404          * implemented.
2405          */
2406
2407         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2408                 spin_unlock(&dwc->lock);
2409                 dwc->gadget_driver->resume(&dwc->gadget);
2410                 spin_lock(&dwc->lock);
2411         }
2412 }
2413
2414 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2415                 unsigned int evtinfo)
2416 {
2417         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2418         unsigned int            pwropt;
2419
2420         /*
2421          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2422          * Hibernation mode enabled which would show up when device detects
2423          * host-initiated U3 exit.
2424          *
2425          * In that case, device will generate a Link State Change Interrupt
2426          * from U3 to RESUME which is only necessary if Hibernation is
2427          * configured in.
2428          *
2429          * There are no functional changes due to such spurious event and we
2430          * just need to ignore it.
2431          *
2432          * Refers to:
2433          *
2434          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2435          * operational mode
2436          */
2437         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2438         if ((dwc->revision < DWC3_REVISION_250A) &&
2439                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2440                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2441                                 (next == DWC3_LINK_STATE_RESUME)) {
2442                         dwc3_trace(trace_dwc3_gadget,
2443                                         "ignoring transition U3 -> Resume");
2444                         return;
2445                 }
2446         }
2447
2448         /*
2449          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2450          * on the link partner, the USB session might do multiple entry/exit
2451          * of low power states before a transfer takes place.
2452          *
2453          * Due to this problem, we might experience lower throughput. The
2454          * suggested workaround is to disable DCTL[12:9] bits if we're
2455          * transitioning from U1/U2 to U0 and enable those bits again
2456          * after a transfer completes and there are no pending transfers
2457          * on any of the enabled endpoints.
2458          *
2459          * This is the first half of that workaround.
2460          *
2461          * Refers to:
2462          *
2463          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2464          * core send LGO_Ux entering U0
2465          */
2466         if (dwc->revision < DWC3_REVISION_183A) {
2467                 if (next == DWC3_LINK_STATE_U0) {
2468                         u32     u1u2;
2469                         u32     reg;
2470
2471                         switch (dwc->link_state) {
2472                         case DWC3_LINK_STATE_U1:
2473                         case DWC3_LINK_STATE_U2:
2474                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2475                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2476                                                 | DWC3_DCTL_ACCEPTU2ENA
2477                                                 | DWC3_DCTL_INITU1ENA
2478                                                 | DWC3_DCTL_ACCEPTU1ENA);
2479
2480                                 if (!dwc->u1u2)
2481                                         dwc->u1u2 = reg & u1u2;
2482
2483                                 reg &= ~u1u2;
2484
2485                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2486                                 break;
2487                         default:
2488                                 /* do nothing */
2489                                 break;
2490                         }
2491                 }
2492         }
2493
2494         switch (next) {
2495         case DWC3_LINK_STATE_U1:
2496                 if (dwc->speed == USB_SPEED_SUPER)
2497                         dwc3_suspend_gadget(dwc);
2498                 break;
2499         case DWC3_LINK_STATE_U2:
2500         case DWC3_LINK_STATE_U3:
2501                 dwc3_suspend_gadget(dwc);
2502                 break;
2503         case DWC3_LINK_STATE_RESUME:
2504                 dwc3_resume_gadget(dwc);
2505                 break;
2506         default:
2507                 /* do nothing */
2508                 break;
2509         }
2510
2511         dwc->link_state = next;
2512 }
2513
2514 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2515                 unsigned int evtinfo)
2516 {
2517         unsigned int is_ss = evtinfo & BIT(4);
2518
2519         /**
2520          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2521          * have a known issue which can cause USB CV TD.9.23 to fail
2522          * randomly.
2523          *
2524          * Because of this issue, core could generate bogus hibernation
2525          * events which SW needs to ignore.
2526          *
2527          * Refers to:
2528          *
2529          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2530          * Device Fallback from SuperSpeed
2531          */
2532         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2533                 return;
2534
2535         /* enter hibernation here */
2536 }
2537
2538 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2539                 const struct dwc3_event_devt *event)
2540 {
2541         switch (event->type) {
2542         case DWC3_DEVICE_EVENT_DISCONNECT:
2543                 dwc3_gadget_disconnect_interrupt(dwc);
2544                 break;
2545         case DWC3_DEVICE_EVENT_RESET:
2546                 dwc3_gadget_reset_interrupt(dwc);
2547                 break;
2548         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2549                 dwc3_gadget_conndone_interrupt(dwc);
2550                 break;
2551         case DWC3_DEVICE_EVENT_WAKEUP:
2552                 dwc3_gadget_wakeup_interrupt(dwc);
2553                 break;
2554         case DWC3_DEVICE_EVENT_HIBER_REQ:
2555                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2556                                         "unexpected hibernation event\n"))
2557                         break;
2558
2559                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2560                 break;
2561         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2562                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2563                 break;
2564         case DWC3_DEVICE_EVENT_EOPF:
2565                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2566                 break;
2567         case DWC3_DEVICE_EVENT_SOF:
2568                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2569                 break;
2570         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2571                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2572                 break;
2573         case DWC3_DEVICE_EVENT_CMD_CMPL:
2574                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2575                 break;
2576         case DWC3_DEVICE_EVENT_OVERFLOW:
2577                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2578                 break;
2579         default:
2580                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2581         }
2582 }
2583
2584 static void dwc3_process_event_entry(struct dwc3 *dwc,
2585                 const union dwc3_event *event)
2586 {
2587         trace_dwc3_event(event->raw);
2588
2589         /* Endpoint IRQ, handle it and return early */
2590         if (event->type.is_devspec == 0) {
2591                 /* depevt */
2592                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2593         }
2594
2595         switch (event->type.type) {
2596         case DWC3_EVENT_TYPE_DEV:
2597                 dwc3_gadget_interrupt(dwc, &event->devt);
2598                 break;
2599         /* REVISIT what to do with Carkit and I2C events ? */
2600         default:
2601                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2602         }
2603 }
2604
2605 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2606 {
2607         struct dwc3 *dwc = evt->dwc;
2608         irqreturn_t ret = IRQ_NONE;
2609         int left;
2610         u32 reg;
2611
2612         left = evt->count;
2613
2614         if (!(evt->flags & DWC3_EVENT_PENDING))
2615                 return IRQ_NONE;
2616
2617         while (left > 0) {
2618                 union dwc3_event event;
2619
2620                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2621
2622                 dwc3_process_event_entry(dwc, &event);
2623
2624                 /*
2625                  * FIXME we wrap around correctly to the next entry as
2626                  * almost all entries are 4 bytes in size. There is one
2627                  * entry which has 12 bytes which is a regular entry
2628                  * followed by 8 bytes data. ATM I don't know how
2629                  * things are organized if we get next to the a
2630                  * boundary so I worry about that once we try to handle
2631                  * that.
2632                  */
2633                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2634                 left -= 4;
2635
2636                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2637         }
2638
2639         evt->count = 0;
2640         evt->flags &= ~DWC3_EVENT_PENDING;
2641         ret = IRQ_HANDLED;
2642
2643         /* Unmask interrupt */
2644         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2645         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2646         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2647
2648         return ret;
2649 }
2650
2651 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2652 {
2653         struct dwc3_event_buffer *evt = _evt;
2654         struct dwc3 *dwc = evt->dwc;
2655         unsigned long flags;
2656         irqreturn_t ret = IRQ_NONE;
2657
2658         spin_lock_irqsave(&dwc->lock, flags);
2659         ret = dwc3_process_event_buf(evt);
2660         spin_unlock_irqrestore(&dwc->lock, flags);
2661
2662         return ret;
2663 }
2664
2665 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2666 {
2667         struct dwc3 *dwc = evt->dwc;
2668         u32 count;
2669         u32 reg;
2670
2671         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2672         count &= DWC3_GEVNTCOUNT_MASK;
2673         if (!count)
2674                 return IRQ_NONE;
2675
2676         evt->count = count;
2677         evt->flags |= DWC3_EVENT_PENDING;
2678
2679         /* Mask interrupt */
2680         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2681         reg |= DWC3_GEVNTSIZ_INTMASK;
2682         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2683
2684         return IRQ_WAKE_THREAD;
2685 }
2686
2687 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2688 {
2689         struct dwc3_event_buffer        *evt = _evt;
2690
2691         return dwc3_check_event_buf(evt);
2692 }
2693
2694 /**
2695  * dwc3_gadget_init - Initializes gadget related registers
2696  * @dwc: pointer to our controller context structure
2697  *
2698  * Returns 0 on success otherwise negative errno.
2699  */
2700 int dwc3_gadget_init(struct dwc3 *dwc)
2701 {
2702         int                                     ret;
2703
2704         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2705                         &dwc->ctrl_req_addr, GFP_KERNEL);
2706         if (!dwc->ctrl_req) {
2707                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2708                 ret = -ENOMEM;
2709                 goto err0;
2710         }
2711
2712         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2713                         &dwc->ep0_trb_addr, GFP_KERNEL);
2714         if (!dwc->ep0_trb) {
2715                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2716                 ret = -ENOMEM;
2717                 goto err1;
2718         }
2719
2720         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2721         if (!dwc->setup_buf) {
2722                 ret = -ENOMEM;
2723                 goto err2;
2724         }
2725
2726         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2727                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2728                         GFP_KERNEL);
2729         if (!dwc->ep0_bounce) {
2730                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2731                 ret = -ENOMEM;
2732                 goto err3;
2733         }
2734
2735         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2736         if (!dwc->zlp_buf) {
2737                 ret = -ENOMEM;
2738                 goto err4;
2739         }
2740
2741         dwc->gadget.ops                 = &dwc3_gadget_ops;
2742         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2743         dwc->gadget.sg_supported        = true;
2744         dwc->gadget.name                = "dwc3-gadget";
2745         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
2746
2747         /*
2748          * FIXME We might be setting max_speed to <SUPER, however versions
2749          * <2.20a of dwc3 have an issue with metastability (documented
2750          * elsewhere in this driver) which tells us we can't set max speed to
2751          * anything lower than SUPER.
2752          *
2753          * Because gadget.max_speed is only used by composite.c and function
2754          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2755          * to happen so we avoid sending SuperSpeed Capability descriptor
2756          * together with our BOS descriptor as that could confuse host into
2757          * thinking we can handle super speed.
2758          *
2759          * Note that, in fact, we won't even support GetBOS requests when speed
2760          * is less than super speed because we don't have means, yet, to tell
2761          * composite.c that we are USB 2.0 + LPM ECN.
2762          */
2763         if (dwc->revision < DWC3_REVISION_220A)
2764                 dwc3_trace(trace_dwc3_gadget,
2765                                 "Changing max_speed on rev %08x\n",
2766                                 dwc->revision);
2767
2768         dwc->gadget.max_speed           = dwc->maximum_speed;
2769
2770         /*
2771          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2772          * on ep out.
2773          */
2774         dwc->gadget.quirk_ep_out_aligned_size = true;
2775
2776         /*
2777          * REVISIT: Here we should clear all pending IRQs to be
2778          * sure we're starting from a well known location.
2779          */
2780
2781         ret = dwc3_gadget_init_endpoints(dwc);
2782         if (ret)
2783                 goto err5;
2784
2785         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2786         if (ret) {
2787                 dev_err(dwc->dev, "failed to register udc\n");
2788                 goto err5;
2789         }
2790
2791         return 0;
2792
2793 err5:
2794         kfree(dwc->zlp_buf);
2795
2796 err4:
2797         dwc3_gadget_free_endpoints(dwc);
2798         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2799                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2800
2801 err3:
2802         kfree(dwc->setup_buf);
2803
2804 err2:
2805         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2806                         dwc->ep0_trb, dwc->ep0_trb_addr);
2807
2808 err1:
2809         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2810                         dwc->ctrl_req, dwc->ctrl_req_addr);
2811
2812 err0:
2813         return ret;
2814 }
2815
2816 /* -------------------------------------------------------------------------- */
2817
2818 void dwc3_gadget_exit(struct dwc3 *dwc)
2819 {
2820         usb_del_gadget_udc(&dwc->gadget);
2821
2822         dwc3_gadget_free_endpoints(dwc);
2823
2824         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2825                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2826
2827         kfree(dwc->setup_buf);
2828         kfree(dwc->zlp_buf);
2829
2830         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2831                         dwc->ep0_trb, dwc->ep0_trb_addr);
2832
2833         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2834                         dwc->ctrl_req, dwc->ctrl_req_addr);
2835 }
2836
2837 int dwc3_gadget_suspend(struct dwc3 *dwc)
2838 {
2839         if (dwc->pullups_connected) {
2840                 dwc3_gadget_disable_irq(dwc);
2841                 dwc3_gadget_run_stop(dwc, true, true);
2842         }
2843
2844         __dwc3_gadget_ep_disable(dwc->eps[0]);
2845         __dwc3_gadget_ep_disable(dwc->eps[1]);
2846
2847         dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2848
2849         return 0;
2850 }
2851
2852 int dwc3_gadget_resume(struct dwc3 *dwc)
2853 {
2854         struct dwc3_ep          *dep;
2855         int                     ret;
2856
2857         /* Start with SuperSpeed Default */
2858         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2859
2860         dep = dwc->eps[0];
2861         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2862                         false);
2863         if (ret)
2864                 goto err0;
2865
2866         dep = dwc->eps[1];
2867         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2868                         false);
2869         if (ret)
2870                 goto err1;
2871
2872         /* begin to receive SETUP packets */
2873         dwc->ep0state = EP0_SETUP_PHASE;
2874         dwc3_ep0_out_start(dwc);
2875
2876         dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2877
2878         if (dwc->pullups_connected) {
2879                 dwc3_gadget_enable_irq(dwc);
2880                 dwc3_gadget_run_stop(dwc, true, false);
2881         }
2882
2883         return 0;
2884
2885 err1:
2886         __dwc3_gadget_ep_disable(dwc->eps[0]);
2887
2888 err0:
2889         return ret;
2890 }