drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dc.h"
  27 #include "dc_dmub_srv.h"
  28 #include "../dmub/dmub_srv.h"
  29 #include "dm_helpers.h"
  30 #include "dc_hw_types.h"
  31 #include "core_types.h"
  32 #include "../basics/conversion.h"
  33 #include "cursor_reg_cache.h"
  34 #include "resource.h"
  35 #include "clk_mgr.h"
  36 #include "dc_state_priv.h"
  37
  38 #define CTX dc_dmub_srv->ctx
  39 #define DC_LOGGER CTX->logger
  40
  41 static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc,
  42                                   struct dmub_srv *dmub)
  43 {
  44         dc_srv->dmub = dmub;
  45         dc_srv->ctx = dc->ctx;
  46 }
  47
  48 struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub)
  49 {
  50         struct dc_dmub_srv *dc_srv =
  51                 kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL);
  52
  53         if (dc_srv == NULL) {
  54                 BREAK_TO_DEBUGGER();
  55                 return NULL;
  56         }
  57
  58         dc_dmub_srv_construct(dc_srv, dc, dmub);
  59
  60         return dc_srv;
  61 }
  62
  63 void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv)
  64 {
  65         if (*dmub_srv) {
  66                 kfree(*dmub_srv);
  67                 *dmub_srv = NULL;
  68         }
  69 }
  70
  71 void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
  72 {
  73         struct dmub_srv *dmub = dc_dmub_srv->dmub;
  74         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
  75         enum dmub_status status;
  76
  77         status = dmub_srv_wait_for_idle(dmub, 100000);
  78         if (status != DMUB_STATUS_OK) {
  79                 DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
  80                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
  81         }
  82 }
  83
  84 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv)
  85 {
  86         struct dmub_srv *dmub = dc_dmub_srv->dmub;
  87         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
  88         enum dmub_status status = DMUB_STATUS_OK;
  89
  90         status = dmub_srv_clear_inbox0_ack(dmub);
  91         if (status != DMUB_STATUS_OK) {
  92                 DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status);
  93                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
  94         }
  95 }
  96
  97 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv)
  98 {
  99         struct dmub_srv *dmub = dc_dmub_srv->dmub;
 100         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
 101         enum dmub_status status = DMUB_STATUS_OK;
 102
 103         status = dmub_srv_wait_for_inbox0_ack(dmub, 100000);
 104         if (status != DMUB_STATUS_OK) {
 105                 DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n");
 106                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 107         }
 108 }
 109
 110 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dc_dmub_srv,
 111                                  union dmub_inbox0_data_register data)
 112 {
 113         struct dmub_srv *dmub = dc_dmub_srv->dmub;
 114         struct dc_context *dc_ctx = dc_dmub_srv->ctx;
 115         enum dmub_status status = DMUB_STATUS_OK;
 116
 117         status = dmub_srv_send_inbox0_cmd(dmub, data);
 118         if (status != DMUB_STATUS_OK) {
 119                 DC_ERROR("Error sending INBOX0 cmd\n");
 120                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 121         }
 122 }
 123
 124 bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,
 125                 unsigned int count,
 126                 union dmub_rb_cmd *cmd_list)
 127 {
 128         struct dc_context *dc_ctx;
 129         struct dmub_srv *dmub;
 130         enum dmub_status status;
 131         int i;
 132
 133         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 134                 return false;
 135
 136         dc_ctx = dc_dmub_srv->ctx;
 137         dmub = dc_dmub_srv->dmub;
 138
 139         for (i = 0 ; i < count; i++) {
 140                 // Queue command
 141                 status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
 142
 143                 if (status == DMUB_STATUS_QUEUE_FULL) {
 144                         /* Execute and wait for queue to become empty again. */
 145                         status = dmub_srv_cmd_execute(dmub);
 146                         if (status == DMUB_STATUS_POWER_STATE_D3)
 147                                 return false;
 148
 149                         dmub_srv_wait_for_idle(dmub, 100000);
 150
 151                         /* Requeue the command. */
 152                         status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
 153                 }
 154
 155                 if (status != DMUB_STATUS_OK) {
 156                         if (status != DMUB_STATUS_POWER_STATE_D3) {
 157                                 DC_ERROR("Error queueing DMUB command: status=%d\n", status);
 158                                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 159                         }
 160                         return false;
 161                 }
 162         }
 163
 164         status = dmub_srv_cmd_execute(dmub);
 165         if (status != DMUB_STATUS_OK) {
 166                 if (status != DMUB_STATUS_POWER_STATE_D3) {
 167                         DC_ERROR("Error starting DMUB execution: status=%d\n", status);
 168                         dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 169                 }
 170                 return false;
 171         }
 172
 173         return true;
 174 }
 175
 176 bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv,
 177                 enum dm_dmub_wait_type wait_type,
 178                 union dmub_rb_cmd *cmd_list)
 179 {
 180         struct dmub_srv *dmub;
 181         enum dmub_status status;
 182
 183         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 184                 return false;
 185
 186         dmub = dc_dmub_srv->dmub;
 187
 188         // Wait for DMUB to process command
 189         if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) {
 190                 status = dmub_srv_wait_for_idle(dmub, 100000);
 191
 192                 if (status != DMUB_STATUS_OK) {
 193                         DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status);
 194                         dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 195                         return false;
 196                 }
 197
 198                 // Copy data back from ring buffer into command
 199                 if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)
 200                         dmub_rb_get_return_data(&dmub->inbox1_rb, cmd_list);
 201         }
 202
 203         return true;
 204 }
 205
 206 bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
 207 {
 208         return dc_dmub_srv_cmd_run_list(dc_dmub_srv, 1, cmd, wait_type);
 209 }
 210
 211 bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type)
 212 {
 213         struct dc_context *dc_ctx;
 214         struct dmub_srv *dmub;
 215         enum dmub_status status;
 216         int i;
 217
 218         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 219                 return false;
 220
 221         dc_ctx = dc_dmub_srv->ctx;
 222         dmub = dc_dmub_srv->dmub;
 223
 224         for (i = 0 ; i < count; i++) {
 225                 // Queue command
 226                 status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
 227
 228                 if (status == DMUB_STATUS_QUEUE_FULL) {
 229                         /* Execute and wait for queue to become empty again. */
 230                         status = dmub_srv_cmd_execute(dmub);
 231                         if (status == DMUB_STATUS_POWER_STATE_D3)
 232                                 return false;
 233
 234                         dmub_srv_wait_for_idle(dmub, 100000);
 235
 236                         /* Requeue the command. */
 237                         status = dmub_srv_cmd_queue(dmub, &cmd_list[i]);
 238                 }
 239
 240                 if (status != DMUB_STATUS_OK) {
 241                         if (status != DMUB_STATUS_POWER_STATE_D3) {
 242                                 DC_ERROR("Error queueing DMUB command: status=%d\n", status);
 243                                 dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 244                         }
 245                         return false;
 246                 }
 247         }
 248
 249         status = dmub_srv_cmd_execute(dmub);
 250         if (status != DMUB_STATUS_OK) {
 251                 if (status != DMUB_STATUS_POWER_STATE_D3) {
 252                         DC_ERROR("Error starting DMUB execution: status=%d\n", status);
 253                         dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 254                 }
 255                 return false;
 256         }
 257
 258         // Wait for DMUB to process command
 259         if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) {
 260                 if (dc_dmub_srv->ctx->dc->debug.disable_timeout) {
 261                         do {
 262                                 status = dmub_srv_wait_for_idle(dmub, 100000);
 263                         } while (status != DMUB_STATUS_OK);
 264                 } else
 265                         status = dmub_srv_wait_for_idle(dmub, 100000);
 266
 267                 if (status != DMUB_STATUS_OK) {
 268                         DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status);
 269                         dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
 270                         return false;
 271                 }
 272
 273                 // Copy data back from ring buffer into command
 274                 if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)
 275                         dmub_rb_get_return_data(&dmub->inbox1_rb, cmd_list);
 276         }
 277
 278         return true;
 279 }
 280
 281 bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv)
 282 {
 283         struct dmub_srv *dmub;
 284         struct dc_context *dc_ctx;
 285         union dmub_fw_boot_status boot_status;
 286         enum dmub_status status;
 287
 288         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 289                 return false;
 290
 291         dmub = dc_dmub_srv->dmub;
 292         dc_ctx = dc_dmub_srv->ctx;
 293
 294         status = dmub_srv_get_fw_boot_status(dmub, &boot_status);
 295         if (status != DMUB_STATUS_OK) {
 296                 DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
 297                 return false;
 298         }
 299
 300         return boot_status.bits.optimized_init_done;
 301 }
 302
 303 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
 304                                     unsigned int stream_mask)
 305 {
 306         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 307                 return false;
 308
 309         return dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,
 310                                          stream_mask, NULL, DM_DMUB_WAIT_TYPE_WAIT);
 311 }
 312
 313 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)
 314 {
 315         struct dmub_srv *dmub;
 316         struct dc_context *dc_ctx;
 317         union dmub_fw_boot_status boot_status;
 318         enum dmub_status status;
 319
 320         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 321                 return false;
 322
 323         dmub = dc_dmub_srv->dmub;
 324         dc_ctx = dc_dmub_srv->ctx;
 325
 326         status = dmub_srv_get_fw_boot_status(dmub, &boot_status);
 327         if (status != DMUB_STATUS_OK) {
 328                 DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
 329                 return false;
 330         }
 331
 332         return boot_status.bits.restore_required;
 333 }
 334
 335 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)
 336 {
 337         struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;
 338         return dmub_srv_get_outbox0_msg(dmub, entry);
 339 }
 340
 341 void dc_dmub_trace_event_control(struct dc *dc, bool enable)
 342 {
 343         dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable);
 344 }
 345
 346 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max)
 347 {
 348         union dmub_rb_cmd cmd = { 0 };
 349
 350         cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
 351         cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE;
 352         cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max;
 353         cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min;
 354         cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
 355
 356         cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
 357
 358         // Send the command to the DMCUB.
 359         dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 360 }
 361
 362 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)
 363 {
 364         union dmub_rb_cmd cmd = { 0 };
 365
 366         cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
 367         cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER;
 368         cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
 369
 370         cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
 371
 372         // Send the command to the DMCUB.
 373         dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 374 }
 375
 376 static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream)
 377 {
 378         uint8_t pipes = 0;
 379         int i = 0;
 380
 381         for (i = 0; i < MAX_PIPES; i++) {
 382                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 383
 384                 if (pipe->stream == stream && pipe->stream_res.tg)
 385                         pipes = i;
 386         }
 387         return pipes;
 388 }
 389
 390 static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context,
 391                 struct pipe_ctx *head_pipe,
 392                 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data *fams_pipe_data)
 393 {
 394         int j;
 395         int pipe_idx = 0;
 396
 397         fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst;
 398         for (j = 0; j < dc->res_pool->pipe_count; j++) {
 399                 struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j];
 400
 401                 if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) {
 402                         fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst;
 403                 }
 404         }
 405         fams_pipe_data->pipe_count = pipe_idx;
 406 }
 407
 408 bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context)
 409 {
 410         union dmub_rb_cmd cmd = { 0 };
 411         struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data;
 412         int i = 0, k = 0;
 413         int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it.
 414         uint8_t visual_confirm_enabled;
 415         int pipe_idx = 0;
 416
 417         if (dc == NULL)
 418                 return false;
 419
 420         visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS;
 421
 422         // Format command.
 423         cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
 424         cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL;
 425         cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate;
 426         cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled;
 427
 428         if (should_manage_pstate) {
 429                 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 430                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 431
 432                         if (!pipe->stream)
 433                                 continue;
 434
 435                         /* If FAMS is being used to support P-State and there is a stream
 436                          * that does not use FAMS, we are in an FPO + VActive scenario.
 437                          * Assign vactive stretch margin in this case.
 438                          */
 439                         if (!pipe->stream->fpo_in_use) {
 440                                 cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us;
 441                                 break;
 442                         }
 443                         pipe_idx++;
 444                 }
 445         }
 446
 447         for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) {
 448                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 449
 450                 if (resource_is_pipe_type(pipe, OTG_MASTER) && pipe->stream->fpo_in_use) {
 451                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 452                         uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000;
 453
 454                         config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz;
 455                         config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz;
 456                         config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps;
 457                         config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream);
 458                         dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]);
 459                         k++;
 460                 }
 461         }
 462         cmd.fw_assisted_mclk_switch.header.payload_bytes =
 463                 sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header);
 464
 465         // Send the command to the DMCUB.
 466         dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 467
 468         return true;
 469 }
 470
 471 void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv)
 472 {
 473         union dmub_rb_cmd cmd = { 0 };
 474
 475         if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)
 476                 return;
 477
 478         memset(&cmd, 0, sizeof(cmd));
 479
 480         /* Prepare fw command */
 481         cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS;
 482         cmd.query_feature_caps.header.sub_type = 0;
 483         cmd.query_feature_caps.header.ret_status = 1;
 484         cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data);
 485
 486         /* If command was processed, copy feature caps to dmub srv */
 487         if (dc_wake_and_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
 488             cmd.query_feature_caps.header.ret_status == 0) {
 489                 memcpy(&dc_dmub_srv->dmub->feature_caps,
 490                        &cmd.query_feature_caps.query_feature_caps_data,
 491                        sizeof(struct dmub_feature_caps));
 492         }
 493 }
 494
 495 void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx)
 496 {
 497         union dmub_rb_cmd cmd = { 0 };
 498         unsigned int panel_inst = 0;
 499
 500         dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst);
 501
 502         memset(&cmd, 0, sizeof(cmd));
 503
 504         // Prepare fw command
 505         cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR;
 506         cmd.visual_confirm_color.header.sub_type = 0;
 507         cmd.visual_confirm_color.header.ret_status = 1;
 508         cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data);
 509         cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst;
 510
 511         // If command was processed, copy feature caps to dmub srv
 512         if (dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
 513                 cmd.visual_confirm_color.header.ret_status == 0) {
 514                 memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,
 515                         &cmd.visual_confirm_color.visual_confirm_color_data,
 516                         sizeof(struct dmub_visual_confirm_color));
 517         }
 518 }
 519
 520 /**
 521  * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command
 522  *
 523  * @dc: [in] pointer to dc object
 524  * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
 525  * @vblank_pipe: [in] pipe_ctx for the DRR pipe
 526  * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info
 527  * @context: [in] DC state for access to phantom stream
 528  *
 529  * Populate the DMCUB SubVP command with DRR pipe info. All the information
 530  * required for calculating the SubVP + DRR microschedule is populated here.
 531  *
 532  * High level algorithm:
 533  * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
 534  * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule
 535  * 3. Populate the drr_info with the min and max supported vtotal values
 536  */
 537 static void populate_subvp_cmd_drr_info(struct dc *dc,
 538                 struct dc_state *context,
 539                 struct pipe_ctx *subvp_pipe,
 540                 struct pipe_ctx *vblank_pipe,
 541                 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data)
 542 {
 543         struct dc_stream_state *phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe->stream);
 544         struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
 545         struct dc_crtc_timing *phantom_timing = &phantom_stream->timing;
 546         struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing;
 547         uint16_t drr_frame_us = 0;
 548         uint16_t min_drr_supported_us = 0;
 549         uint16_t max_drr_supported_us = 0;
 550         uint16_t max_drr_vblank_us = 0;
 551         uint16_t max_drr_mallregion_us = 0;
 552         uint16_t mall_region_us = 0;
 553         uint16_t prefetch_us = 0;
 554         uint16_t subvp_active_us = 0;
 555         uint16_t drr_active_us = 0;
 556         uint16_t min_vtotal_supported = 0;
 557         uint16_t max_vtotal_supported = 0;
 558
 559         pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true;
 560         pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping
 561         pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now
 562
 563         drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000),
 564                         (((uint64_t)drr_timing->pix_clk_100hz * 100)));
 565         // P-State allow width and FW delays already included phantom_timing->v_addressable
 566         mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000),
 567                         (((uint64_t)phantom_timing->pix_clk_100hz * 100)));
 568         min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
 569         min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us),
 570                         (((uint64_t)drr_timing->h_total * 1000000)));
 571
 572         prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000),
 573                         (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
 574         subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000),
 575                         (((uint64_t)main_timing->pix_clk_100hz * 100)));
 576         drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000),
 577                         (((uint64_t)drr_timing->pix_clk_100hz * 100)));
 578         max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us -
 579                         dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us;
 580         max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us;
 581         max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us;
 582         max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us),
 583                         (((uint64_t)drr_timing->h_total * 1000000)));
 584
 585         /* When calculating the max vtotal supported for SubVP + DRR cases, add
 586          * margin due to possible rounding errors (being off by 1 line in the
 587          * FW calculation can incorrectly push the P-State switch to wait 1 frame
 588          * longer).
 589          */
 590         max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us;
 591
 592         pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;
 593         pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;
 594         pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us;
 595 }
 596
 597 /**
 598  * populate_subvp_cmd_vblank_pipe_info - Helper to populate VBLANK pipe info for the DMUB subvp command
 599  *
 600  * @dc: [in] current dc state
 601  * @context: [in] new dc state
 602  * @cmd: [in] DMUB cmd to be populated with SubVP info
 603  * @vblank_pipe: [in] pipe_ctx for the VBLANK pipe
 604  * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
 605  *
 606  * Populate the DMCUB SubVP command with VBLANK pipe info. All the information
 607  * required to calculate the microschedule for SubVP + VBLANK case is stored in
 608  * the pipe_data (subvp_data and vblank_data).  Also check if the VBLANK pipe
 609  * is a DRR display -- if it is make a call to populate drr_info.
 610  */
 611 static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc,
 612                 struct dc_state *context,
 613                 union dmub_rb_cmd *cmd,
 614                 struct pipe_ctx *vblank_pipe,
 615                 uint8_t cmd_pipe_index)
 616 {
 617         uint32_t i;
 618         struct pipe_ctx *pipe = NULL;
 619         struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
 620                         &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
 621
 622         // Find the SubVP pipe
 623         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 624                 pipe = &context->res_ctx.pipe_ctx[i];
 625
 626                 // We check for master pipe, but it shouldn't matter since we only need
 627                 // the pipe for timing info (stream should be same for any pipe splits)
 628                 if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
 629                                 !resource_is_pipe_type(pipe, DPP_PIPE))
 630                         continue;
 631
 632                 // Find the SubVP pipe
 633                 if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)
 634                         break;
 635         }
 636
 637         pipe_data->mode = VBLANK;
 638         pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz;
 639         pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total -
 640                                                         vblank_pipe->stream->timing.v_front_porch;
 641         pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total;
 642         pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total;
 643         pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx;
 644         pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start;
 645         pipe_data->pipe_config.vblank_data.vblank_end =
 646                         vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable;
 647
 648         if (vblank_pipe->stream->ignore_msa_timing_param &&
 649                 (vblank_pipe->stream->allow_freesync || vblank_pipe->stream->vrr_active_variable || vblank_pipe->stream->vrr_active_fixed))
 650                 populate_subvp_cmd_drr_info(dc, context, pipe, vblank_pipe, pipe_data);
 651 }
 652
 653 /**
 654  * update_subvp_prefetch_end_to_mall_start - Helper for SubVP + SubVP case
 655  *
 656  * @dc: [in] current dc state
 657  * @context: [in] new dc state
 658  * @cmd: [in] DMUB cmd to be populated with SubVP info
 659  * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2)
 660  *
 661  * For SubVP + SubVP, we use a single vertical interrupt to start the
 662  * microschedule for both SubVP pipes. In order for this to work correctly, the
 663  * MALL REGION of both SubVP pipes must start at the same time. This function
 664  * lengthens the prefetch end to mall start delay of the SubVP pipe that has
 665  * the shorter prefetch so that both MALL REGION's will start at the same time.
 666  */
 667 static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
 668                 struct dc_state *context,
 669                 union dmub_rb_cmd *cmd,
 670                 struct pipe_ctx *subvp_pipes[])
 671 {
 672         uint32_t subvp0_prefetch_us = 0;
 673         uint32_t subvp1_prefetch_us = 0;
 674         uint32_t prefetch_delta_us = 0;
 675         struct dc_stream_state *phantom_stream0 = NULL;
 676         struct dc_stream_state *phantom_stream1 = NULL;
 677         struct dc_crtc_timing *phantom_timing0 = NULL;
 678         struct dc_crtc_timing *phantom_timing1 = NULL;
 679         struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL;
 680
 681         phantom_stream0 = dc_state_get_paired_subvp_stream(context, subvp_pipes[0]->stream);
 682         phantom_stream1 = dc_state_get_paired_subvp_stream(context, subvp_pipes[1]->stream);
 683         phantom_timing0 = &phantom_stream0->timing;
 684         phantom_timing1 = &phantom_stream1->timing;
 685
 686         subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) *
 687                         (uint64_t)phantom_timing0->h_total * 1000000),
 688                         (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
 689         subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) *
 690                         (uint64_t)phantom_timing1->h_total * 1000000),
 691                         (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
 692
 693         // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time)
 694         // should increase it's prefetch time to match the other
 695         if (subvp0_prefetch_us > subvp1_prefetch_us) {
 696                 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1];
 697                 prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us;
 698                 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
 699                                 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
 700                                         ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)),
 701                                         ((uint64_t)phantom_timing1->h_total * 1000000));
 702
 703         } else if (subvp1_prefetch_us >  subvp0_prefetch_us) {
 704                 pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0];
 705                 prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us;
 706                 pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
 707                                 div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
 708                                         ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)),
 709                                         ((uint64_t)phantom_timing0->h_total * 1000000));
 710         }
 711 }
 712
 713 /**
 714  * populate_subvp_cmd_pipe_info - Helper to populate the SubVP pipe info for the DMUB subvp command
 715  *
 716  * @dc: [in] current dc state
 717  * @context: [in] new dc state
 718  * @cmd: [in] DMUB cmd to be populated with SubVP info
 719  * @subvp_pipe: [in] pipe_ctx for the SubVP pipe
 720  * @cmd_pipe_index: [in] index for the pipe array in DMCUB SubVP cmd
 721  *
 722  * Populate the DMCUB SubVP command with SubVP pipe info. All the information
 723  * required to calculate the microschedule for the SubVP pipe is stored in the
 724  * pipe_data of the DMCUB SubVP command.
 725  */
 726 static void populate_subvp_cmd_pipe_info(struct dc *dc,
 727                 struct dc_state *context,
 728                 union dmub_rb_cmd *cmd,
 729                 struct pipe_ctx *subvp_pipe,
 730                 uint8_t cmd_pipe_index)
 731 {
 732         uint32_t j;
 733         struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =
 734                         &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
 735         struct dc_stream_state *phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe->stream);
 736         struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
 737         struct dc_crtc_timing *phantom_timing = &phantom_stream->timing;
 738         uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den;
 739
 740         pipe_data->mode = SUBVP;
 741         pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz;
 742         pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total;
 743         pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total;
 744         pipe_data->pipe_config.subvp_data.main_vblank_start =
 745                         main_timing->v_total - main_timing->v_front_porch;
 746         pipe_data->pipe_config.subvp_data.main_vblank_end =
 747                         main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable;
 748         pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable;
 749         pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst;
 750         pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param &&
 751                 (subvp_pipe->stream->allow_freesync || subvp_pipe->stream->vrr_active_variable || subvp_pipe->stream->vrr_active_fixed);
 752
 753         /* Calculate the scaling factor from the src and dst height.
 754          * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2.
 755          * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor"
 756          *
 757          * Make sure to combine stream and plane scaling together.
 758          */
 759         reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height,
 760                         &out_num_stream, &out_den_stream);
 761         reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height,
 762                         &out_num_plane, &out_den_plane);
 763         reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den);
 764         pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num;
 765         pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den;
 766
 767         // Prefetch lines is equal to VACTIVE + BP + VSYNC
 768         pipe_data->pipe_config.subvp_data.prefetch_lines =
 769                         phantom_timing->v_total - phantom_timing->v_front_porch;
 770
 771         // Round up
 772         pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
 773                         div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
 774                                         ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
 775         pipe_data->pipe_config.subvp_data.processing_delay_lines =
 776                         div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
 777                                         ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
 778
 779         if (subvp_pipe->bottom_pipe) {
 780                 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx;
 781         } else if (subvp_pipe->next_odm_pipe) {
 782                 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx;
 783         } else {
 784                 pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0;
 785         }
 786
 787         // Find phantom pipe index based on phantom stream
 788         for (j = 0; j < dc->res_pool->pipe_count; j++) {
 789                 struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j];
 790
 791                 if (phantom_pipe->stream == dc_state_get_paired_subvp_stream(context, subvp_pipe->stream)) {
 792                         pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst;
 793                         if (phantom_pipe->bottom_pipe) {
 794                                 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst;
 795                         } else if (phantom_pipe->next_odm_pipe) {
 796                                 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst;
 797                         } else {
 798                                 pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0;
 799                         }
 800                         break;
 801                 }
 802         }
 803 }
 804
 805 /**
 806  * dc_dmub_setup_subvp_dmub_command - Populate the DMCUB SubVP command
 807  *
 808  * @dc: [in] current dc state
 809  * @context: [in] new dc state
 810  * @enable: [in] if true enables the pipes population
 811  *
 812  * This function loops through each pipe and populates the DMUB SubVP CMD info
 813  * based on the pipe (e.g. SubVP, VBLANK).
 814  */
 815 void dc_dmub_setup_subvp_dmub_command(struct dc *dc,
 816                 struct dc_state *context,
 817                 bool enable)
 818 {
 819         uint8_t cmd_pipe_index = 0;
 820         uint32_t i, pipe_idx;
 821         uint8_t subvp_count = 0;
 822         union dmub_rb_cmd cmd;
 823         struct pipe_ctx *subvp_pipes[2];
 824         uint32_t wm_val_refclk = 0;
 825         enum mall_stream_type pipe_mall_type;
 826
 827         memset(&cmd, 0, sizeof(cmd));
 828         // FW command for SUBVP
 829         cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
 830         cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD;
 831         cmd.fw_assisted_mclk_switch_v2.header.payload_bytes =
 832                         sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header);
 833
 834         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 835                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 836
 837                 /* For SubVP pipe count, only count the top most (ODM / MPC) pipe
 838                  */
 839                 if (resource_is_pipe_type(pipe, OTG_MASTER) &&
 840                                 resource_is_pipe_type(pipe, DPP_PIPE) &&
 841                                 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)
 842                         subvp_pipes[subvp_count++] = pipe;
 843         }
 844
 845         if (enable) {
 846                 // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd
 847                 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 848                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 849                         pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);
 850
 851                         if (!pipe->stream)
 852                                 continue;
 853
 854                         /* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe.
 855                          * Any ODM or MPC splits being used in SubVP will be handled internally in
 856                          * populate_subvp_cmd_pipe_info
 857                          */
 858                         if (resource_is_pipe_type(pipe, OTG_MASTER) &&
 859                                         resource_is_pipe_type(pipe, DPP_PIPE) &&
 860                                         pipe_mall_type == SUBVP_MAIN) {
 861                                 populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);
 862                         } else if (resource_is_pipe_type(pipe, OTG_MASTER) &&
 863                                         resource_is_pipe_type(pipe, DPP_PIPE) &&
 864                                         pipe_mall_type == SUBVP_NONE) {
 865                                 // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where
 866                                 // we run through DML without calculating "natural" P-state support
 867                                 populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);
 868
 869                         }
 870                         pipe_idx++;
 871                 }
 872                 if (subvp_count == 2) {
 873                         update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes);
 874                 }
 875                 cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
 876                 cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us;
 877
 878                 // Store the original watermark value for this SubVP config so we can lower it when the
 879                 // MCLK switch starts
 880                 wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns *
 881                                 (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000;
 882
 883                 cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF;
 884         }
 885
 886         dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 887 }
 888
 889 bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data)
 890 {
 891         if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data)
 892                 return false;
 893         return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data);
 894 }
 895
 896 void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)
 897 {
 898         struct dmub_diagnostic_data diag_data = {0};
 899
 900         if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
 901                 DC_LOG_ERROR("%s: invalid parameters.", __func__);
 902                 return;
 903         }
 904
 905         if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) {
 906                 DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__);
 907                 return;
 908         }
 909
 910         DC_LOG_DEBUG("DMCUB STATE:");
 911         DC_LOG_DEBUG("    dmcub_version      : %08x", diag_data.dmcub_version);
 912         DC_LOG_DEBUG("    scratch  [0]       : %08x", diag_data.scratch[0]);
 913         DC_LOG_DEBUG("    scratch  [1]       : %08x", diag_data.scratch[1]);
 914         DC_LOG_DEBUG("    scratch  [2]       : %08x", diag_data.scratch[2]);
 915         DC_LOG_DEBUG("    scratch  [3]       : %08x", diag_data.scratch[3]);
 916         DC_LOG_DEBUG("    scratch  [4]       : %08x", diag_data.scratch[4]);
 917         DC_LOG_DEBUG("    scratch  [5]       : %08x", diag_data.scratch[5]);
 918         DC_LOG_DEBUG("    scratch  [6]       : %08x", diag_data.scratch[6]);
 919         DC_LOG_DEBUG("    scratch  [7]       : %08x", diag_data.scratch[7]);
 920         DC_LOG_DEBUG("    scratch  [8]       : %08x", diag_data.scratch[8]);
 921         DC_LOG_DEBUG("    scratch  [9]       : %08x", diag_data.scratch[9]);
 922         DC_LOG_DEBUG("    scratch [10]       : %08x", diag_data.scratch[10]);
 923         DC_LOG_DEBUG("    scratch [11]       : %08x", diag_data.scratch[11]);
 924         DC_LOG_DEBUG("    scratch [12]       : %08x", diag_data.scratch[12]);
 925         DC_LOG_DEBUG("    scratch [13]       : %08x", diag_data.scratch[13]);
 926         DC_LOG_DEBUG("    scratch [14]       : %08x", diag_data.scratch[14]);
 927         DC_LOG_DEBUG("    scratch [15]       : %08x", diag_data.scratch[15]);
 928         DC_LOG_DEBUG("    pc                 : %08x", diag_data.pc);
 929         DC_LOG_DEBUG("    unk_fault_addr     : %08x", diag_data.undefined_address_fault_addr);
 930         DC_LOG_DEBUG("    inst_fault_addr    : %08x", diag_data.inst_fetch_fault_addr);
 931         DC_LOG_DEBUG("    data_fault_addr    : %08x", diag_data.data_write_fault_addr);
 932         DC_LOG_DEBUG("    inbox1_rptr        : %08x", diag_data.inbox1_rptr);
 933         DC_LOG_DEBUG("    inbox1_wptr        : %08x", diag_data.inbox1_wptr);
 934         DC_LOG_DEBUG("    inbox1_size        : %08x", diag_data.inbox1_size);
 935         DC_LOG_DEBUG("    inbox0_rptr        : %08x", diag_data.inbox0_rptr);
 936         DC_LOG_DEBUG("    inbox0_wptr        : %08x", diag_data.inbox0_wptr);
 937         DC_LOG_DEBUG("    inbox0_size        : %08x", diag_data.inbox0_size);
 938         DC_LOG_DEBUG("    is_enabled         : %d", diag_data.is_dmcub_enabled);
 939         DC_LOG_DEBUG("    is_soft_reset      : %d", diag_data.is_dmcub_soft_reset);
 940         DC_LOG_DEBUG("    is_secure_reset    : %d", diag_data.is_dmcub_secure_reset);
 941         DC_LOG_DEBUG("    is_traceport_en    : %d", diag_data.is_traceport_en);
 942         DC_LOG_DEBUG("    is_cw0_en          : %d", diag_data.is_cw0_enabled);
 943         DC_LOG_DEBUG("    is_cw6_en          : %d", diag_data.is_cw6_enabled);
 944 }
 945
 946 static bool dc_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
 947 {
 948         struct pipe_ctx *test_pipe, *split_pipe;
 949         const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data;
 950         struct rect r1 = scl_data->recout, r2, r2_half;
 951         int r1_r = r1.x + r1.width, r1_b = r1.y + r1.height, r2_r, r2_b;
 952         int cur_layer = pipe_ctx->plane_state->layer_index;
 953
 954         /**
 955          * Disable the cursor if there's another pipe above this with a
 956          * plane that contains this pipe's viewport to prevent double cursor
 957          * and incorrect scaling artifacts.
 958          */
 959         for (test_pipe = pipe_ctx->top_pipe; test_pipe;
 960              test_pipe = test_pipe->top_pipe) {
 961                 // Skip invisible layer and pipe-split plane on same layer
 962                 if (!test_pipe->plane_state->visible || test_pipe->plane_state->layer_index == cur_layer)
 963                         continue;
 964
 965                 r2 = test_pipe->plane_res.scl_data.recout;
 966                 r2_r = r2.x + r2.width;
 967                 r2_b = r2.y + r2.height;
 968                 split_pipe = test_pipe;
 969
 970                 /**
 971                  * There is another half plane on same layer because of
 972                  * pipe-split, merge together per same height.
 973                  */
 974                 for (split_pipe = pipe_ctx->top_pipe; split_pipe;
 975                      split_pipe = split_pipe->top_pipe)
 976                         if (split_pipe->plane_state->layer_index == test_pipe->plane_state->layer_index) {
 977                                 r2_half = split_pipe->plane_res.scl_data.recout;
 978                                 r2.x = (r2_half.x < r2.x) ? r2_half.x : r2.x;
 979                                 r2.width = r2.width + r2_half.width;
 980                                 r2_r = r2.x + r2.width;
 981                                 break;
 982                         }
 983
 984                 if (r1.x >= r2.x && r1.y >= r2.y && r1_r <= r2_r && r1_b <= r2_b)
 985                         return true;
 986         }
 987
 988         return false;
 989 }
 990
 991 static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx)
 992 {
 993         if (pipe_ctx->plane_state != NULL) {
 994                 if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
 995                         return false;
 996
 997                 if (dc_can_pipe_disable_cursor(pipe_ctx))
 998                         return false;
 999         }
1000
1001         if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 ||
1002                 pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) &&
1003                 pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1)
1004                 return true;
1005
1006         if (pipe_ctx->stream->link->replay_settings.config.replay_supported)
1007                 return true;
1008
1009         return false;
1010 }
1011
1012 static void dc_build_cursor_update_payload0(
1013                 struct pipe_ctx *pipe_ctx, uint8_t p_idx,
1014                 struct dmub_cmd_update_cursor_payload0 *payload)
1015 {
1016         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1017         unsigned int panel_inst = 0;
1018
1019         if (!dc_get_edp_link_panel_inst(hubp->ctx->dc,
1020                 pipe_ctx->stream->link, &panel_inst))
1021                 return;
1022
1023         /* Payload: Cursor Rect is built from position & attribute
1024          * x & y are obtained from postion
1025          */
1026         payload->cursor_rect.x = hubp->cur_rect.x;
1027         payload->cursor_rect.y = hubp->cur_rect.y;
1028         /* w & h are obtained from attribute */
1029         payload->cursor_rect.width  = hubp->cur_rect.w;
1030         payload->cursor_rect.height = hubp->cur_rect.h;
1031
1032         payload->enable      = hubp->pos.cur_ctl.bits.cur_enable;
1033         payload->pipe_idx    = p_idx;
1034         payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
1035         payload->panel_inst  = panel_inst;
1036 }
1037
1038 static void dc_build_cursor_position_update_payload0(
1039                 struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx,
1040                 const struct hubp *hubp, const struct dpp *dpp)
1041 {
1042         /* Hubp */
1043         pl->position_cfg.pHubp.cur_ctl.raw  = hubp->pos.cur_ctl.raw;
1044         pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw;
1045         pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw;
1046         pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw;
1047
1048         /* dpp */
1049         pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw;
1050         pl->position_cfg.pipe_idx = p_idx;
1051 }
1052
1053 static void dc_build_cursor_attribute_update_payload1(
1054                 struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx,
1055                 const struct hubp *hubp, const struct dpp *dpp)
1056 {
1057         /* Hubp */
1058         pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH;
1059         pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR;
1060         pl_A->aHubp.cur_ctl.raw  = hubp->att.cur_ctl.raw;
1061         pl_A->aHubp.size.raw     = hubp->att.size.raw;
1062         pl_A->aHubp.settings.raw = hubp->att.settings.raw;
1063
1064         /* dpp */
1065         pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw;
1066 }
1067
1068 /**
1069  * dc_send_update_cursor_info_to_dmu - Populate the DMCUB Cursor update info command
1070  *
1071  * @pCtx: [in] pipe context
1072  * @pipe_idx: [in] pipe index
1073  *
1074  * This function would store the cursor related information and pass it into
1075  * dmub
1076  */
1077 void dc_send_update_cursor_info_to_dmu(
1078                 struct pipe_ctx *pCtx, uint8_t pipe_idx)
1079 {
1080         union dmub_rb_cmd cmd[2];
1081         union dmub_cmd_update_cursor_info_data *update_cursor_info_0 =
1082                                         &cmd[0].update_cursor_info.update_cursor_info_data;
1083
1084         memset(cmd, 0, sizeof(cmd));
1085
1086         if (!dc_dmub_should_update_cursor_data(pCtx))
1087                 return;
1088         /*
1089          * Since we use multi_cmd_pending for dmub command, the 2nd command is
1090          * only assigned to store cursor attributes info.
1091          * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other
1092          * is to store cursor position info.
1093          *
1094          * Command heaer type must be the same type if using  multi_cmd_pending.
1095          * Besides, while process 2nd command in DMU, the sub type is useless.
1096          * So it's meanless to pass the sub type header with different type.
1097          */
1098
1099         {
1100                 /* Build Payload#0 Header */
1101                 cmd[0].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
1102                 cmd[0].update_cursor_info.header.payload_bytes =
1103                                 sizeof(cmd[0].update_cursor_info.update_cursor_info_data);
1104                 cmd[0].update_cursor_info.header.multi_cmd_pending = 1; //To combine multi dmu cmd, 1st cmd
1105
1106                 /* Prepare Payload */
1107                 dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info_0->payload0);
1108
1109                 dc_build_cursor_position_update_payload0(&update_cursor_info_0->payload0, pipe_idx,
1110                                 pCtx->plane_res.hubp, pCtx->plane_res.dpp);
1111                 }
1112         {
1113                 /* Build Payload#1 Header */
1114                 cmd[1].update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
1115                 cmd[1].update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg);
1116                 cmd[1].update_cursor_info.header.multi_cmd_pending = 0; //Indicate it's the last command.
1117
1118                 dc_build_cursor_attribute_update_payload1(
1119                                 &cmd[1].update_cursor_info.update_cursor_info_data.payload1.attribute_cfg,
1120                                 pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp);
1121
1122                 /* Combine 2nd cmds update_curosr_info to DMU */
1123                 dc_wake_and_execute_dmub_cmd_list(pCtx->stream->ctx, 2, cmd, DM_DMUB_WAIT_TYPE_WAIT);
1124         }
1125 }
1126
1127 bool dc_dmub_check_min_version(struct dmub_srv *srv)
1128 {
1129         if (!srv->hw_funcs.is_psrsu_supported)
1130                 return true;
1131         return srv->hw_funcs.is_psrsu_supported(srv);
1132 }
1133
1134 void dc_dmub_srv_enable_dpia_trace(const struct dc *dc)
1135 {
1136         struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;
1137
1138         if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
1139                 DC_LOG_ERROR("%s: invalid parameters.", __func__);
1140                 return;
1141         }
1142
1143         if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1,
1144                                        0x0010, NULL, DM_DMUB_WAIT_TYPE_WAIT)) {
1145                 DC_LOG_ERROR("timeout updating trace buffer mask word\n");
1146                 return;
1147         }
1148
1149         if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK,
1150                                        0x0000, NULL, DM_DMUB_WAIT_TYPE_WAIT)) {
1151                 DC_LOG_ERROR("timeout updating trace buffer mask word\n");
1152                 return;
1153         }
1154
1155         DC_LOG_DEBUG("Enabled DPIA trace\n");
1156 }
1157
1158 void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, const struct dc_plane_address *addr, uint8_t subvp_index)
1159 {
1160         dmub_srv_subvp_save_surf_addr(dc_dmub_srv->dmub, addr, subvp_index);
1161 }
1162
1163 bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait)
1164 {
1165         struct dc_context *dc_ctx;
1166         enum dmub_status status;
1167
1168         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
1169                 return true;
1170
1171         if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)
1172                 return true;
1173
1174         dc_ctx = dc_dmub_srv->ctx;
1175
1176         if (wait) {
1177                 if (dc_dmub_srv->ctx->dc->debug.disable_timeout) {
1178                         do {
1179                                 status = dmub_srv_wait_for_hw_pwr_up(dc_dmub_srv->dmub, 500000);
1180                         } while (status != DMUB_STATUS_OK);
1181                 } else {
1182                         status = dmub_srv_wait_for_hw_pwr_up(dc_dmub_srv->dmub, 500000);
1183                         if (status != DMUB_STATUS_OK) {
1184                                 DC_ERROR("Error querying DMUB hw power up status: error=%d\n", status);
1185                                 return false;
1186                         }
1187                 }
1188         } else
1189                 return dmub_srv_is_hw_pwr_up(dc_dmub_srv->dmub);
1190
1191         return true;
1192 }
1193
1194 static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)
1195 {
1196         union dmub_rb_cmd cmd = {0};
1197
1198         if (dc->debug.dmcub_emulation)
1199                 return;
1200
1201         memset(&cmd, 0, sizeof(cmd));
1202         cmd.idle_opt_notify_idle.header.type = DMUB_CMD__IDLE_OPT;
1203         cmd.idle_opt_notify_idle.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE;
1204         cmd.idle_opt_notify_idle.header.payload_bytes =
1205                 sizeof(cmd.idle_opt_notify_idle) -
1206                 sizeof(cmd.idle_opt_notify_idle.header);
1207
1208         cmd.idle_opt_notify_idle.cntl_data.driver_idle = allow_idle;
1209
1210         if (allow_idle) {
1211                 if (dc->hwss.set_idle_state)
1212                         dc->hwss.set_idle_state(dc, true);
1213         }
1214
1215         /* NOTE: This does not use the "wake" interface since this is part of the wake path. */
1216         /* We also do not perform a wait since DMCUB could enter idle after the notification. */
1217         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
1218 }
1219
1220 static void dc_dmub_srv_exit_low_power_state(const struct dc *dc)
1221 {
1222         uint32_t allow_state = 0;
1223         uint32_t commit_state = 0;
1224
1225         if (dc->debug.dmcub_emulation)
1226                 return;
1227
1228         if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub)
1229                 return;
1230
1231         if (dc->hwss.get_idle_state &&
1232                 dc->hwss.set_idle_state &&
1233                 dc->clk_mgr->funcs->exit_low_power_state) {
1234
1235                 allow_state = dc->hwss.get_idle_state(dc);
1236                 dc->hwss.set_idle_state(dc, false);
1237
1238                 if (!(allow_state & DMUB_IPS2_ALLOW_MASK)) {
1239                         // Wait for evaluation time
1240                         for (;;) {
1241                                 udelay(dc->debug.ips2_eval_delay_us);
1242                                 commit_state = dc->hwss.get_idle_state(dc);
1243                                 if (commit_state & DMUB_IPS2_ALLOW_MASK)
1244                                         break;
1245
1246                                 /* allow was still set, retry eval delay */
1247                                 dc->hwss.set_idle_state(dc, false);
1248                         }
1249
1250                         if (!(commit_state & DMUB_IPS2_COMMIT_MASK)) {
1251                                 // Tell PMFW to exit low power state
1252                                 dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
1253
1254                                 // Wait for IPS2 entry upper bound
1255                                 udelay(dc->debug.ips2_entry_delay_us);
1256                                 dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
1257
1258                                 for (;;) {
1259                                         commit_state = dc->hwss.get_idle_state(dc);
1260                                         if (commit_state & DMUB_IPS2_COMMIT_MASK)
1261                                                 break;
1262
1263                                         udelay(1);
1264                                 }
1265
1266                                 if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))
1267                                         ASSERT(0);
1268
1269                                 /* TODO: See if we can return early here - IPS2 should go
1270                                  * back directly to IPS0 and clear the flags, but it will
1271                                  * be safer to directly notify DMCUB of this.
1272                                  */
1273                                 allow_state = dc->hwss.get_idle_state(dc);
1274                         }
1275                 }
1276
1277                 dc_dmub_srv_notify_idle(dc, false);
1278                 if (!(allow_state & DMUB_IPS1_ALLOW_MASK)) {
1279                         for (;;) {
1280                                 commit_state = dc->hwss.get_idle_state(dc);
1281                                 if (commit_state & DMUB_IPS1_COMMIT_MASK)
1282                                         break;
1283
1284                                 udelay(1);
1285                         }
1286                 }
1287         }
1288
1289         if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))
1290                 ASSERT(0);
1291 }
1292
1293 void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state powerState)
1294 {
1295         struct dmub_srv *dmub;
1296
1297         if (!dc_dmub_srv)
1298                 return;
1299
1300         dmub = dc_dmub_srv->dmub;
1301
1302         if (powerState == DC_ACPI_CM_POWER_STATE_D0)
1303                 dmub_srv_set_power_state(dmub, DMUB_POWER_STATE_D0);
1304         else
1305                 dmub_srv_set_power_state(dmub, DMUB_POWER_STATE_D3);
1306 }
1307
1308 void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle)
1309 {
1310         struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;
1311
1312         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
1313                 return;
1314
1315         if (dc_dmub_srv->idle_allowed == allow_idle)
1316                 return;
1317
1318         /*
1319          * Entering a low power state requires a driver notification.
1320          * Powering up the hardware requires notifying PMFW and DMCUB.
1321          * Clearing the driver idle allow requires a DMCUB command.
1322          * DMCUB commands requires the DMCUB to be powered up and restored.
1323          *
1324          * Exit out early to prevent an infinite loop of DMCUB commands
1325          * triggering exit low power - use software state to track this.
1326          */
1327         dc_dmub_srv->idle_allowed = allow_idle;
1328
1329         if (!allow_idle)
1330                 dc_dmub_srv_exit_low_power_state(dc);
1331         else
1332                 dc_dmub_srv_notify_idle(dc, allow_idle);
1333 }
1334
1335 bool dc_wake_and_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd,
1336                                   enum dm_dmub_wait_type wait_type)
1337 {
1338         return dc_wake_and_execute_dmub_cmd_list(ctx, 1, cmd, wait_type);
1339 }
1340
1341 bool dc_wake_and_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count,
1342                                        union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
1343 {
1344         struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;
1345         bool result = false, reallow_idle = false;
1346
1347         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
1348                 return false;
1349
1350         if (count == 0)
1351                 return true;
1352
1353         if (dc_dmub_srv->idle_allowed) {
1354                 dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, false);
1355                 reallow_idle = true;
1356         }
1357
1358         /*
1359          * These may have different implementations in DM, so ensure
1360          * that we guide it to the expected helper.
1361          */
1362         if (count > 1)
1363                 result = dm_execute_dmub_cmd_list(ctx, count, cmd, wait_type);
1364         else
1365                 result = dm_execute_dmub_cmd(ctx, cmd, wait_type);
1366
1367         if (result && reallow_idle)
1368                 dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true);
1369
1370         return result;
1371 }
1372
1373 static bool dc_dmub_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code,
1374                                   uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type)
1375 {
1376         struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;
1377         const uint32_t wait_us = wait_type == DM_DMUB_WAIT_TYPE_NO_WAIT ? 0 : 30;
1378         enum dmub_status status;
1379
1380         if (response)
1381                 *response = 0;
1382
1383         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
1384                 return false;
1385
1386         status = dmub_srv_send_gpint_command(dc_dmub_srv->dmub, command_code, param, wait_us);
1387         if (status != DMUB_STATUS_OK) {
1388                 if (status == DMUB_STATUS_TIMEOUT && wait_type == DM_DMUB_WAIT_TYPE_NO_WAIT)
1389                         return true;
1390
1391                 return false;
1392         }
1393
1394         if (response && wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)
1395                 dmub_srv_get_gpint_response(dc_dmub_srv->dmub, response);
1396
1397         return true;
1398 }
1399
1400 bool dc_wake_and_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code,
1401                                uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type)
1402 {
1403         struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;
1404         bool result = false, reallow_idle = false;
1405
1406         if (!dc_dmub_srv || !dc_dmub_srv->dmub)
1407                 return false;
1408
1409         if (dc_dmub_srv->idle_allowed) {
1410                 dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, false);
1411                 reallow_idle = true;
1412         }
1413
1414         result = dc_dmub_execute_gpint(ctx, command_code, param, response, wait_type);
1415
1416         if (result && reallow_idle)
1417                 dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true);
1418
1419         return result;
1420 }