drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/power_supply.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34
  35
  36 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  37
  38 static const struct cg_flag_name clocks[] = {
  39         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  40         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  41         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  42         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  43         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  46         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  49         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  50         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  51         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  52         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  55         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  56         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  58         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  61         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  63         {0, NULL},
  64 };
  65
  66 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  67 {
  68         if (adev->pm.dpm_enabled) {
  69                 mutex_lock(&adev->pm.mutex);
  70                 if (power_supply_is_system_supplied() > 0)
  71                         adev->pm.ac_power = true;
  72                 else
  73                         adev->pm.ac_power = false;
  74                 if (adev->powerplay.pp_funcs->enable_bapm)
  75                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  76                 mutex_unlock(&adev->pm.mutex);
  77         }
  78 }
  79
  80 /**
  81  * DOC: power_dpm_state
  82  *
  83  * The power_dpm_state file is a legacy interface and is only provided for
  84  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
  85  * certain power related parameters.  The file power_dpm_state is used for this.
  86  * It accepts the following arguments:
  87  *
  88  * - battery
  89  *
  90  * - balanced
  91  *
  92  * - performance
  93  *
  94  * battery
  95  *
  96  * On older GPUs, the vbios provided a special power state for battery
  97  * operation.  Selecting battery switched to this state.  This is no
  98  * longer provided on newer GPUs so the option does nothing in that case.
  99  *
 100  * balanced
 101  *
 102  * On older GPUs, the vbios provided a special power state for balanced
 103  * operation.  Selecting balanced switched to this state.  This is no
 104  * longer provided on newer GPUs so the option does nothing in that case.
 105  *
 106  * performance
 107  *
 108  * On older GPUs, the vbios provided a special power state for performance
 109  * operation.  Selecting performance switched to this state.  This is no
 110  * longer provided on newer GPUs so the option does nothing in that case.
 111  *
 112  */
 113
 114 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 115                                     struct device_attribute *attr,
 116                                     char *buf)
 117 {
 118         struct drm_device *ddev = dev_get_drvdata(dev);
 119         struct amdgpu_device *adev = ddev->dev_private;
 120         enum amd_pm_state_type pm;
 121
 122         if (adev->powerplay.pp_funcs->get_current_power_state)
 123                 pm = amdgpu_dpm_get_current_power_state(adev);
 124         else
 125                 pm = adev->pm.dpm.user_state;
 126
 127         return snprintf(buf, PAGE_SIZE, "%s\n",
 128                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 129                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 130 }
 131
 132 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 133                                     struct device_attribute *attr,
 134                                     const char *buf,
 135                                     size_t count)
 136 {
 137         struct drm_device *ddev = dev_get_drvdata(dev);
 138         struct amdgpu_device *adev = ddev->dev_private;
 139         enum amd_pm_state_type  state;
 140
 141         if (strncmp("battery", buf, strlen("battery")) == 0)
 142                 state = POWER_STATE_TYPE_BATTERY;
 143         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 144                 state = POWER_STATE_TYPE_BALANCED;
 145         else if (strncmp("performance", buf, strlen("performance")) == 0)
 146                 state = POWER_STATE_TYPE_PERFORMANCE;
 147         else {
 148                 count = -EINVAL;
 149                 goto fail;
 150         }
 151
 152         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 153                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 154         } else {
 155                 mutex_lock(&adev->pm.mutex);
 156                 adev->pm.dpm.user_state = state;
 157                 mutex_unlock(&adev->pm.mutex);
 158
 159                 /* Can't set dpm state when the card is off */
 160                 if (!(adev->flags & AMD_IS_PX) ||
 161                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 162                         amdgpu_pm_compute_clocks(adev);
 163         }
 164 fail:
 165         return count;
 166 }
 167
 168
 169 /**
 170  * DOC: power_dpm_force_performance_level
 171  *
 172  * The amdgpu driver provides a sysfs API for adjusting certain power
 173  * related parameters.  The file power_dpm_force_performance_level is
 174  * used for this.  It accepts the following arguments:
 175  *
 176  * - auto
 177  *
 178  * - low
 179  *
 180  * - high
 181  *
 182  * - manual
 183  *
 184  * - profile_standard
 185  *
 186  * - profile_min_sclk
 187  *
 188  * - profile_min_mclk
 189  *
 190  * - profile_peak
 191  *
 192  * auto
 193  *
 194  * When auto is selected, the driver will attempt to dynamically select
 195  * the optimal power profile for current conditions in the driver.
 196  *
 197  * low
 198  *
 199  * When low is selected, the clocks are forced to the lowest power state.
 200  *
 201  * high
 202  *
 203  * When high is selected, the clocks are forced to the highest power state.
 204  *
 205  * manual
 206  *
 207  * When manual is selected, the user can manually adjust which power states
 208  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 209  * and pp_dpm_pcie files and adjust the power state transition heuristics
 210  * via the pp_power_profile_mode sysfs file.
 211  *
 212  * profile_standard
 213  * profile_min_sclk
 214  * profile_min_mclk
 215  * profile_peak
 216  *
 217  * When the profiling modes are selected, clock and power gating are
 218  * disabled and the clocks are set for different profiling cases. This
 219  * mode is recommended for profiling specific work loads where you do
 220  * not want clock or power gating for clock fluctuation to interfere
 221  * with your results. profile_standard sets the clocks to a fixed clock
 222  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 223  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 224  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 225  *
 226  */
 227
 228 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 229                                                 struct device_attribute *attr,
 230                                                                 char *buf)
 231 {
 232         struct drm_device *ddev = dev_get_drvdata(dev);
 233         struct amdgpu_device *adev = ddev->dev_private;
 234         enum amd_dpm_forced_level level = 0xff;
 235
 236         if  ((adev->flags & AMD_IS_PX) &&
 237              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 238                 return snprintf(buf, PAGE_SIZE, "off\n");
 239
 240         if (adev->powerplay.pp_funcs->get_performance_level)
 241                 level = amdgpu_dpm_get_performance_level(adev);
 242         else
 243                 level = adev->pm.dpm.forced_level;
 244
 245         return snprintf(buf, PAGE_SIZE, "%s\n",
 246                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 247                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 248                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 249                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 250                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 251                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 252                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 253                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 254                         "unknown");
 255 }
 256
 257 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 258                                                        struct device_attribute *attr,
 259                                                        const char *buf,
 260                                                        size_t count)
 261 {
 262         struct drm_device *ddev = dev_get_drvdata(dev);
 263         struct amdgpu_device *adev = ddev->dev_private;
 264         enum amd_dpm_forced_level level;
 265         enum amd_dpm_forced_level current_level = 0xff;
 266         int ret = 0;
 267
 268         /* Can't force performance level when the card is off */
 269         if  ((adev->flags & AMD_IS_PX) &&
 270              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 271                 return -EINVAL;
 272
 273         if (adev->powerplay.pp_funcs->get_performance_level)
 274                 current_level = amdgpu_dpm_get_performance_level(adev);
 275
 276         if (strncmp("low", buf, strlen("low")) == 0) {
 277                 level = AMD_DPM_FORCED_LEVEL_LOW;
 278         } else if (strncmp("high", buf, strlen("high")) == 0) {
 279                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 280         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 281                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 282         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 283                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 284         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 285                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 286         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 287                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 288         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 289                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 290         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 291                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 292         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 293                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 294         }  else {
 295                 count = -EINVAL;
 296                 goto fail;
 297         }
 298
 299         if (current_level == level)
 300                 return count;
 301
 302         if (adev->powerplay.pp_funcs->force_performance_level) {
 303                 mutex_lock(&adev->pm.mutex);
 304                 if (adev->pm.dpm.thermal_active) {
 305                         count = -EINVAL;
 306                         mutex_unlock(&adev->pm.mutex);
 307                         goto fail;
 308                 }
 309                 ret = amdgpu_dpm_force_performance_level(adev, level);
 310                 if (ret)
 311                         count = -EINVAL;
 312                 else
 313                         adev->pm.dpm.forced_level = level;
 314                 mutex_unlock(&adev->pm.mutex);
 315         }
 316
 317 fail:
 318         return count;
 319 }
 320
 321 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 322                 struct device_attribute *attr,
 323                 char *buf)
 324 {
 325         struct drm_device *ddev = dev_get_drvdata(dev);
 326         struct amdgpu_device *adev = ddev->dev_private;
 327         struct pp_states_info data;
 328         int i, buf_len;
 329
 330         if (adev->powerplay.pp_funcs->get_pp_num_states)
 331                 amdgpu_dpm_get_pp_num_states(adev, &data);
 332
 333         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 334         for (i = 0; i < data.nums; i++)
 335                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 336                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 337                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 338                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 339                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 340
 341         return buf_len;
 342 }
 343
 344 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 345                 struct device_attribute *attr,
 346                 char *buf)
 347 {
 348         struct drm_device *ddev = dev_get_drvdata(dev);
 349         struct amdgpu_device *adev = ddev->dev_private;
 350         struct pp_states_info data;
 351         enum amd_pm_state_type pm = 0;
 352         int i = 0;
 353
 354         if (adev->powerplay.pp_funcs->get_current_power_state
 355                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 356                 pm = amdgpu_dpm_get_current_power_state(adev);
 357                 amdgpu_dpm_get_pp_num_states(adev, &data);
 358
 359                 for (i = 0; i < data.nums; i++) {
 360                         if (pm == data.states[i])
 361                                 break;
 362                 }
 363
 364                 if (i == data.nums)
 365                         i = -EINVAL;
 366         }
 367
 368         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 369 }
 370
 371 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 372                 struct device_attribute *attr,
 373                 char *buf)
 374 {
 375         struct drm_device *ddev = dev_get_drvdata(dev);
 376         struct amdgpu_device *adev = ddev->dev_private;
 377
 378         if (adev->pp_force_state_enabled)
 379                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 380         else
 381                 return snprintf(buf, PAGE_SIZE, "\n");
 382 }
 383
 384 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 385                 struct device_attribute *attr,
 386                 const char *buf,
 387                 size_t count)
 388 {
 389         struct drm_device *ddev = dev_get_drvdata(dev);
 390         struct amdgpu_device *adev = ddev->dev_private;
 391         enum amd_pm_state_type state = 0;
 392         unsigned long idx;
 393         int ret;
 394
 395         if (strlen(buf) == 1)
 396                 adev->pp_force_state_enabled = false;
 397         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 398                         adev->powerplay.pp_funcs->get_pp_num_states) {
 399                 struct pp_states_info data;
 400
 401                 ret = kstrtoul(buf, 0, &idx);
 402                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 403                         count = -EINVAL;
 404                         goto fail;
 405                 }
 406
 407                 amdgpu_dpm_get_pp_num_states(adev, &data);
 408                 state = data.states[idx];
 409                 /* only set user selected power states */
 410                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 411                     state != POWER_STATE_TYPE_DEFAULT) {
 412                         amdgpu_dpm_dispatch_task(adev,
 413                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 414                         adev->pp_force_state_enabled = true;
 415                 }
 416         }
 417 fail:
 418         return count;
 419 }
 420
 421 /**
 422  * DOC: pp_table
 423  *
 424  * The amdgpu driver provides a sysfs API for uploading new powerplay
 425  * tables.  The file pp_table is used for this.  Reading the file
 426  * will dump the current power play table.  Writing to the file
 427  * will attempt to upload a new powerplay table and re-initialize
 428  * powerplay using that new table.
 429  *
 430  */
 431
 432 static ssize_t amdgpu_get_pp_table(struct device *dev,
 433                 struct device_attribute *attr,
 434                 char *buf)
 435 {
 436         struct drm_device *ddev = dev_get_drvdata(dev);
 437         struct amdgpu_device *adev = ddev->dev_private;
 438         char *table = NULL;
 439         int size;
 440
 441         if (adev->powerplay.pp_funcs->get_pp_table)
 442                 size = amdgpu_dpm_get_pp_table(adev, &table);
 443         else
 444                 return 0;
 445
 446         if (size >= PAGE_SIZE)
 447                 size = PAGE_SIZE - 1;
 448
 449         memcpy(buf, table, size);
 450
 451         return size;
 452 }
 453
 454 static ssize_t amdgpu_set_pp_table(struct device *dev,
 455                 struct device_attribute *attr,
 456                 const char *buf,
 457                 size_t count)
 458 {
 459         struct drm_device *ddev = dev_get_drvdata(dev);
 460         struct amdgpu_device *adev = ddev->dev_private;
 461
 462         if (adev->powerplay.pp_funcs->set_pp_table)
 463                 amdgpu_dpm_set_pp_table(adev, buf, count);
 464
 465         return count;
 466 }
 467
 468 /**
 469  * DOC: pp_od_clk_voltage
 470  *
 471  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 472  * in each power level within a power state.  The pp_od_clk_voltage is used for
 473  * this.
 474  *
 475  * Reading the file will display:
 476  *
 477  * - a list of engine clock levels and voltages labeled OD_SCLK
 478  *
 479  * - a list of memory clock levels and voltages labeled OD_MCLK
 480  *
 481  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 482  *
 483  * To manually adjust these settings, first select manual using
 484  * power_dpm_force_performance_level. Enter a new value for each
 485  * level by writing a string that contains "s/m level clock voltage" to
 486  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 487  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 488  * 810 mV.  When you have edited all of the states as needed, write
 489  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 490  * default power levels, write "r" (reset) to the file to reset them.
 491  *
 492  */
 493
 494 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 495                 struct device_attribute *attr,
 496                 const char *buf,
 497                 size_t count)
 498 {
 499         struct drm_device *ddev = dev_get_drvdata(dev);
 500         struct amdgpu_device *adev = ddev->dev_private;
 501         int ret;
 502         uint32_t parameter_size = 0;
 503         long parameter[64];
 504         char buf_cpy[128];
 505         char *tmp_str;
 506         char *sub_str;
 507         const char delimiter[3] = {' ', '\n', '\0'};
 508         uint32_t type;
 509
 510         if (count > 127)
 511                 return -EINVAL;
 512
 513         if (*buf == 's')
 514                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 515         else if (*buf == 'm')
 516                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 517         else if(*buf == 'r')
 518                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 519         else if (*buf == 'c')
 520                 type = PP_OD_COMMIT_DPM_TABLE;
 521         else
 522                 return -EINVAL;
 523
 524         memcpy(buf_cpy, buf, count+1);
 525
 526         tmp_str = buf_cpy;
 527
 528         while (isspace(*++tmp_str));
 529
 530         while (tmp_str[0]) {
 531                 sub_str = strsep(&tmp_str, delimiter);
 532                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 533                 if (ret)
 534                         return -EINVAL;
 535                 parameter_size++;
 536
 537                 while (isspace(*tmp_str))
 538                         tmp_str++;
 539         }
 540
 541         if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 542                 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 543                                                 parameter, parameter_size);
 544
 545         if (ret)
 546                 return -EINVAL;
 547
 548         if (type == PP_OD_COMMIT_DPM_TABLE) {
 549                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
 550                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 551                         return count;
 552                 } else {
 553                         return -EINVAL;
 554                 }
 555         }
 556
 557         return count;
 558 }
 559
 560 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 561                 struct device_attribute *attr,
 562                 char *buf)
 563 {
 564         struct drm_device *ddev = dev_get_drvdata(dev);
 565         struct amdgpu_device *adev = ddev->dev_private;
 566         uint32_t size = 0;
 567
 568         if (adev->powerplay.pp_funcs->print_clock_levels) {
 569                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 570                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 571                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 572                 return size;
 573         } else {
 574                 return snprintf(buf, PAGE_SIZE, "\n");
 575         }
 576
 577 }
 578
 579 /**
 580  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
 581  *
 582  * The amdgpu driver provides a sysfs API for adjusting what power levels
 583  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 584  * and pp_dpm_pcie are used for this.
 585  *
 586  * Reading back the files will show you the available power levels within
 587  * the power state and the clock information for those levels.
 588  *
 589  * To manually adjust these states, first select manual using
 590  * power_dpm_force_performance_level.
 591  * Secondly,Enter a new value for each level by inputing a string that
 592  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 593  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
 594  */
 595
 596 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 597                 struct device_attribute *attr,
 598                 char *buf)
 599 {
 600         struct drm_device *ddev = dev_get_drvdata(dev);
 601         struct amdgpu_device *adev = ddev->dev_private;
 602
 603         if (adev->powerplay.pp_funcs->print_clock_levels)
 604                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 605         else
 606                 return snprintf(buf, PAGE_SIZE, "\n");
 607 }
 608
 609 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 610                 struct device_attribute *attr,
 611                 const char *buf,
 612                 size_t count)
 613 {
 614         struct drm_device *ddev = dev_get_drvdata(dev);
 615         struct amdgpu_device *adev = ddev->dev_private;
 616         int ret;
 617         long level;
 618         uint32_t mask = 0;
 619         char *sub_str = NULL;
 620         char *tmp;
 621         char buf_cpy[count];
 622         const char delimiter[3] = {' ', '\n', '\0'};
 623
 624         memcpy(buf_cpy, buf, count+1);
 625         tmp = buf_cpy;
 626         while (tmp[0]) {
 627                 sub_str =  strsep(&tmp, delimiter);
 628                 if (strlen(sub_str)) {
 629                         ret = kstrtol(sub_str, 0, &level);
 630
 631                         if (ret) {
 632                                 count = -EINVAL;
 633                                 goto fail;
 634                         }
 635                         mask |= 1 << level;
 636                 } else
 637                         break;
 638         }
 639         if (adev->powerplay.pp_funcs->force_clock_level)
 640                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 641
 642 fail:
 643         return count;
 644 }
 645
 646 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 647                 struct device_attribute *attr,
 648                 char *buf)
 649 {
 650         struct drm_device *ddev = dev_get_drvdata(dev);
 651         struct amdgpu_device *adev = ddev->dev_private;
 652
 653         if (adev->powerplay.pp_funcs->print_clock_levels)
 654                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 655         else
 656                 return snprintf(buf, PAGE_SIZE, "\n");
 657 }
 658
 659 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 660                 struct device_attribute *attr,
 661                 const char *buf,
 662                 size_t count)
 663 {
 664         struct drm_device *ddev = dev_get_drvdata(dev);
 665         struct amdgpu_device *adev = ddev->dev_private;
 666         int ret;
 667         long level;
 668         uint32_t mask = 0;
 669         char *sub_str = NULL;
 670         char *tmp;
 671         char buf_cpy[count];
 672         const char delimiter[3] = {' ', '\n', '\0'};
 673
 674         memcpy(buf_cpy, buf, count+1);
 675         tmp = buf_cpy;
 676         while (tmp[0]) {
 677                 sub_str =  strsep(&tmp, delimiter);
 678                 if (strlen(sub_str)) {
 679                         ret = kstrtol(sub_str, 0, &level);
 680
 681                         if (ret) {
 682                                 count = -EINVAL;
 683                                 goto fail;
 684                         }
 685                         mask |= 1 << level;
 686                 } else
 687                         break;
 688         }
 689         if (adev->powerplay.pp_funcs->force_clock_level)
 690                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 691
 692 fail:
 693         return count;
 694 }
 695
 696 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 697                 struct device_attribute *attr,
 698                 char *buf)
 699 {
 700         struct drm_device *ddev = dev_get_drvdata(dev);
 701         struct amdgpu_device *adev = ddev->dev_private;
 702
 703         if (adev->powerplay.pp_funcs->print_clock_levels)
 704                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 705         else
 706                 return snprintf(buf, PAGE_SIZE, "\n");
 707 }
 708
 709 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 710                 struct device_attribute *attr,
 711                 const char *buf,
 712                 size_t count)
 713 {
 714         struct drm_device *ddev = dev_get_drvdata(dev);
 715         struct amdgpu_device *adev = ddev->dev_private;
 716         int ret;
 717         long level;
 718         uint32_t mask = 0;
 719         char *sub_str = NULL;
 720         char *tmp;
 721         char buf_cpy[count];
 722         const char delimiter[3] = {' ', '\n', '\0'};
 723
 724         memcpy(buf_cpy, buf, count+1);
 725         tmp = buf_cpy;
 726
 727         while (tmp[0]) {
 728                 sub_str =  strsep(&tmp, delimiter);
 729                 if (strlen(sub_str)) {
 730                         ret = kstrtol(sub_str, 0, &level);
 731
 732                         if (ret) {
 733                                 count = -EINVAL;
 734                                 goto fail;
 735                         }
 736                         mask |= 1 << level;
 737                 } else
 738                         break;
 739         }
 740         if (adev->powerplay.pp_funcs->force_clock_level)
 741                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 742
 743 fail:
 744         return count;
 745 }
 746
 747 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 748                 struct device_attribute *attr,
 749                 char *buf)
 750 {
 751         struct drm_device *ddev = dev_get_drvdata(dev);
 752         struct amdgpu_device *adev = ddev->dev_private;
 753         uint32_t value = 0;
 754
 755         if (adev->powerplay.pp_funcs->get_sclk_od)
 756                 value = amdgpu_dpm_get_sclk_od(adev);
 757
 758         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 759 }
 760
 761 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
 762                 struct device_attribute *attr,
 763                 const char *buf,
 764                 size_t count)
 765 {
 766         struct drm_device *ddev = dev_get_drvdata(dev);
 767         struct amdgpu_device *adev = ddev->dev_private;
 768         int ret;
 769         long int value;
 770
 771         ret = kstrtol(buf, 0, &value);
 772
 773         if (ret) {
 774                 count = -EINVAL;
 775                 goto fail;
 776         }
 777         if (adev->powerplay.pp_funcs->set_sclk_od)
 778                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
 779
 780         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 781                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 782         } else {
 783                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 784                 amdgpu_pm_compute_clocks(adev);
 785         }
 786
 787 fail:
 788         return count;
 789 }
 790
 791 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
 792                 struct device_attribute *attr,
 793                 char *buf)
 794 {
 795         struct drm_device *ddev = dev_get_drvdata(dev);
 796         struct amdgpu_device *adev = ddev->dev_private;
 797         uint32_t value = 0;
 798
 799         if (adev->powerplay.pp_funcs->get_mclk_od)
 800                 value = amdgpu_dpm_get_mclk_od(adev);
 801
 802         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 803 }
 804
 805 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
 806                 struct device_attribute *attr,
 807                 const char *buf,
 808                 size_t count)
 809 {
 810         struct drm_device *ddev = dev_get_drvdata(dev);
 811         struct amdgpu_device *adev = ddev->dev_private;
 812         int ret;
 813         long int value;
 814
 815         ret = kstrtol(buf, 0, &value);
 816
 817         if (ret) {
 818                 count = -EINVAL;
 819                 goto fail;
 820         }
 821         if (adev->powerplay.pp_funcs->set_mclk_od)
 822                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
 823
 824         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 825                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 826         } else {
 827                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 828                 amdgpu_pm_compute_clocks(adev);
 829         }
 830
 831 fail:
 832         return count;
 833 }
 834
 835 /**
 836  * DOC: pp_power_profile_mode
 837  *
 838  * The amdgpu driver provides a sysfs API for adjusting the heuristics
 839  * related to switching between power levels in a power state.  The file
 840  * pp_power_profile_mode is used for this.
 841  *
 842  * Reading this file outputs a list of all of the predefined power profiles
 843  * and the relevant heuristics settings for that profile.
 844  *
 845  * To select a profile or create a custom profile, first select manual using
 846  * power_dpm_force_performance_level.  Writing the number of a predefined
 847  * profile to pp_power_profile_mode will enable those heuristics.  To
 848  * create a custom set of heuristics, write a string of numbers to the file
 849  * starting with the number of the custom profile along with a setting
 850  * for each heuristic parameter.  Due to differences across asic families
 851  * the heuristic parameters vary from family to family.
 852  *
 853  */
 854
 855 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
 856                 struct device_attribute *attr,
 857                 char *buf)
 858 {
 859         struct drm_device *ddev = dev_get_drvdata(dev);
 860         struct amdgpu_device *adev = ddev->dev_private;
 861
 862         if (adev->powerplay.pp_funcs->get_power_profile_mode)
 863                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
 864
 865         return snprintf(buf, PAGE_SIZE, "\n");
 866 }
 867
 868
 869 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
 870                 struct device_attribute *attr,
 871                 const char *buf,
 872                 size_t count)
 873 {
 874         int ret = 0xff;
 875         struct drm_device *ddev = dev_get_drvdata(dev);
 876         struct amdgpu_device *adev = ddev->dev_private;
 877         uint32_t parameter_size = 0;
 878         long parameter[64];
 879         char *sub_str, buf_cpy[128];
 880         char *tmp_str;
 881         uint32_t i = 0;
 882         char tmp[2];
 883         long int profile_mode = 0;
 884         const char delimiter[3] = {' ', '\n', '\0'};
 885
 886         tmp[0] = *(buf);
 887         tmp[1] = '\0';
 888         ret = kstrtol(tmp, 0, &profile_mode);
 889         if (ret)
 890                 goto fail;
 891
 892         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
 893                 if (count < 2 || count > 127)
 894                         return -EINVAL;
 895                 while (isspace(*++buf))
 896                         i++;
 897                 memcpy(buf_cpy, buf, count-i);
 898                 tmp_str = buf_cpy;
 899                 while (tmp_str[0]) {
 900                         sub_str = strsep(&tmp_str, delimiter);
 901                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 902                         if (ret) {
 903                                 count = -EINVAL;
 904                                 goto fail;
 905                         }
 906                         parameter_size++;
 907                         while (isspace(*tmp_str))
 908                                 tmp_str++;
 909                 }
 910         }
 911         parameter[parameter_size] = profile_mode;
 912         if (adev->powerplay.pp_funcs->set_power_profile_mode)
 913                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
 914
 915         if (!ret)
 916                 return count;
 917 fail:
 918         return -EINVAL;
 919 }
 920
 921 /**
 922  * DOC: busy_percent
 923  *
 924  * The amdgpu driver provides a sysfs API for reading how busy the GPU
 925  * is as a percentage.  The file gpu_busy_percent is used for this.
 926  * The SMU firmware computes a percentage of load based on the
 927  * aggregate activity level in the IP cores.
 928  */
 929 static ssize_t amdgpu_get_busy_percent(struct device *dev,
 930                 struct device_attribute *attr,
 931                 char *buf)
 932 {
 933         struct drm_device *ddev = dev_get_drvdata(dev);
 934         struct amdgpu_device *adev = ddev->dev_private;
 935         int r, value, size = sizeof(value);
 936
 937         /* sanity check PP is enabled */
 938         if (!(adev->powerplay.pp_funcs &&
 939               adev->powerplay.pp_funcs->read_sensor))
 940                 return -EINVAL;
 941
 942         /* read the IP busy sensor */
 943         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
 944                                    (void *)&value, &size);
 945         if (r)
 946                 return r;
 947
 948         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 949 }
 950
 951 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 952 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 953                    amdgpu_get_dpm_forced_performance_level,
 954                    amdgpu_set_dpm_forced_performance_level);
 955 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 956 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 957 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 958                 amdgpu_get_pp_force_state,
 959                 amdgpu_set_pp_force_state);
 960 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 961                 amdgpu_get_pp_table,
 962                 amdgpu_set_pp_table);
 963 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 964                 amdgpu_get_pp_dpm_sclk,
 965                 amdgpu_set_pp_dpm_sclk);
 966 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 967                 amdgpu_get_pp_dpm_mclk,
 968                 amdgpu_set_pp_dpm_mclk);
 969 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 970                 amdgpu_get_pp_dpm_pcie,
 971                 amdgpu_set_pp_dpm_pcie);
 972 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
 973                 amdgpu_get_pp_sclk_od,
 974                 amdgpu_set_pp_sclk_od);
 975 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
 976                 amdgpu_get_pp_mclk_od,
 977                 amdgpu_set_pp_mclk_od);
 978 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
 979                 amdgpu_get_pp_power_profile_mode,
 980                 amdgpu_set_pp_power_profile_mode);
 981 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
 982                 amdgpu_get_pp_od_clk_voltage,
 983                 amdgpu_set_pp_od_clk_voltage);
 984 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
 985                 amdgpu_get_busy_percent, NULL);
 986
 987 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 988                                       struct device_attribute *attr,
 989                                       char *buf)
 990 {
 991         struct amdgpu_device *adev = dev_get_drvdata(dev);
 992         struct drm_device *ddev = adev->ddev;
 993         int r, temp, size = sizeof(temp);
 994
 995         /* Can't get temperature when the card is off */
 996         if  ((adev->flags & AMD_IS_PX) &&
 997              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 998                 return -EINVAL;
 999
1000         /* sanity check PP is enabled */
1001         if (!(adev->powerplay.pp_funcs &&
1002               adev->powerplay.pp_funcs->read_sensor))
1003                 return -EINVAL;
1004
1005         /* get the temperature */
1006         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1007                                    (void *)&temp, &size);
1008         if (r)
1009                 return r;
1010
1011         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1012 }
1013
1014 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
1015                                              struct device_attribute *attr,
1016                                              char *buf)
1017 {
1018         struct amdgpu_device *adev = dev_get_drvdata(dev);
1019         int hyst = to_sensor_dev_attr(attr)->index;
1020         int temp;
1021
1022         if (hyst)
1023                 temp = adev->pm.dpm.thermal.min_temp;
1024         else
1025                 temp = adev->pm.dpm.thermal.max_temp;
1026
1027         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1028 }
1029
1030 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
1031                                             struct device_attribute *attr,
1032                                             char *buf)
1033 {
1034         struct amdgpu_device *adev = dev_get_drvdata(dev);
1035         u32 pwm_mode = 0;
1036
1037         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1038                 return -EINVAL;
1039
1040         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1041
1042         return sprintf(buf, "%i\n", pwm_mode);
1043 }
1044
1045 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
1046                                             struct device_attribute *attr,
1047                                             const char *buf,
1048                                             size_t count)
1049 {
1050         struct amdgpu_device *adev = dev_get_drvdata(dev);
1051         int err;
1052         int value;
1053
1054         /* Can't adjust fan when the card is off */
1055         if  ((adev->flags & AMD_IS_PX) &&
1056              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1057                 return -EINVAL;
1058
1059         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1060                 return -EINVAL;
1061
1062         err = kstrtoint(buf, 10, &value);
1063         if (err)
1064                 return err;
1065
1066         amdgpu_dpm_set_fan_control_mode(adev, value);
1067
1068         return count;
1069 }
1070
1071 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1072                                          struct device_attribute *attr,
1073                                          char *buf)
1074 {
1075         return sprintf(buf, "%i\n", 0);
1076 }
1077
1078 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1079                                          struct device_attribute *attr,
1080                                          char *buf)
1081 {
1082         return sprintf(buf, "%i\n", 255);
1083 }
1084
1085 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1086                                      struct device_attribute *attr,
1087                                      const char *buf, size_t count)
1088 {
1089         struct amdgpu_device *adev = dev_get_drvdata(dev);
1090         int err;
1091         u32 value;
1092
1093         /* Can't adjust fan when the card is off */
1094         if  ((adev->flags & AMD_IS_PX) &&
1095              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1096                 return -EINVAL;
1097
1098         err = kstrtou32(buf, 10, &value);
1099         if (err)
1100                 return err;
1101
1102         value = (value * 100) / 255;
1103
1104         if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1105                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1106                 if (err)
1107                         return err;
1108         }
1109
1110         return count;
1111 }
1112
1113 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1114                                      struct device_attribute *attr,
1115                                      char *buf)
1116 {
1117         struct amdgpu_device *adev = dev_get_drvdata(dev);
1118         int err;
1119         u32 speed = 0;
1120
1121         /* Can't adjust fan when the card is off */
1122         if  ((adev->flags & AMD_IS_PX) &&
1123              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1124                 return -EINVAL;
1125
1126         if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1127                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1128                 if (err)
1129                         return err;
1130         }
1131
1132         speed = (speed * 255) / 100;
1133
1134         return sprintf(buf, "%i\n", speed);
1135 }
1136
1137 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1138                                            struct device_attribute *attr,
1139                                            char *buf)
1140 {
1141         struct amdgpu_device *adev = dev_get_drvdata(dev);
1142         int err;
1143         u32 speed = 0;
1144
1145         /* Can't adjust fan when the card is off */
1146         if  ((adev->flags & AMD_IS_PX) &&
1147              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1148                 return -EINVAL;
1149
1150         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1151                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1152                 if (err)
1153                         return err;
1154         }
1155
1156         return sprintf(buf, "%i\n", speed);
1157 }
1158
1159 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1160                                         struct device_attribute *attr,
1161                                         char *buf)
1162 {
1163         struct amdgpu_device *adev = dev_get_drvdata(dev);
1164         struct drm_device *ddev = adev->ddev;
1165         u32 vddgfx;
1166         int r, size = sizeof(vddgfx);
1167
1168         /* Can't get voltage when the card is off */
1169         if  ((adev->flags & AMD_IS_PX) &&
1170              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1171                 return -EINVAL;
1172
1173         /* sanity check PP is enabled */
1174         if (!(adev->powerplay.pp_funcs &&
1175               adev->powerplay.pp_funcs->read_sensor))
1176               return -EINVAL;
1177
1178         /* get the voltage */
1179         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1180                                    (void *)&vddgfx, &size);
1181         if (r)
1182                 return r;
1183
1184         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1185 }
1186
1187 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1188                                               struct device_attribute *attr,
1189                                               char *buf)
1190 {
1191         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1192 }
1193
1194 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1195                                        struct device_attribute *attr,
1196                                        char *buf)
1197 {
1198         struct amdgpu_device *adev = dev_get_drvdata(dev);
1199         struct drm_device *ddev = adev->ddev;
1200         u32 vddnb;
1201         int r, size = sizeof(vddnb);
1202
1203         /* only APUs have vddnb */
1204         if  (adev->flags & AMD_IS_APU)
1205                 return -EINVAL;
1206
1207         /* Can't get voltage when the card is off */
1208         if  ((adev->flags & AMD_IS_PX) &&
1209              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1210                 return -EINVAL;
1211
1212         /* sanity check PP is enabled */
1213         if (!(adev->powerplay.pp_funcs &&
1214               adev->powerplay.pp_funcs->read_sensor))
1215               return -EINVAL;
1216
1217         /* get the voltage */
1218         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1219                                    (void *)&vddnb, &size);
1220         if (r)
1221                 return r;
1222
1223         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1224 }
1225
1226 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1227                                               struct device_attribute *attr,
1228                                               char *buf)
1229 {
1230         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1231 }
1232
1233 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1234                                            struct device_attribute *attr,
1235                                            char *buf)
1236 {
1237         struct amdgpu_device *adev = dev_get_drvdata(dev);
1238         struct drm_device *ddev = adev->ddev;
1239         u32 query = 0;
1240         int r, size = sizeof(u32);
1241         unsigned uw;
1242
1243         /* Can't get power when the card is off */
1244         if  ((adev->flags & AMD_IS_PX) &&
1245              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1246                 return -EINVAL;
1247
1248         /* sanity check PP is enabled */
1249         if (!(adev->powerplay.pp_funcs &&
1250               adev->powerplay.pp_funcs->read_sensor))
1251               return -EINVAL;
1252
1253         /* get the voltage */
1254         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1255                                    (void *)&query, &size);
1256         if (r)
1257                 return r;
1258
1259         /* convert to microwatts */
1260         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1261
1262         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1263 }
1264
1265 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1266                                          struct device_attribute *attr,
1267                                          char *buf)
1268 {
1269         return sprintf(buf, "%i\n", 0);
1270 }
1271
1272 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1273                                          struct device_attribute *attr,
1274                                          char *buf)
1275 {
1276         struct amdgpu_device *adev = dev_get_drvdata(dev);
1277         uint32_t limit = 0;
1278
1279         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1280                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1281                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1282         } else {
1283                 return snprintf(buf, PAGE_SIZE, "\n");
1284         }
1285 }
1286
1287 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1288                                          struct device_attribute *attr,
1289                                          char *buf)
1290 {
1291         struct amdgpu_device *adev = dev_get_drvdata(dev);
1292         uint32_t limit = 0;
1293
1294         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1295                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1296                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1297         } else {
1298                 return snprintf(buf, PAGE_SIZE, "\n");
1299         }
1300 }
1301
1302
1303 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
1304                 struct device_attribute *attr,
1305                 const char *buf,
1306                 size_t count)
1307 {
1308         struct amdgpu_device *adev = dev_get_drvdata(dev);
1309         int err;
1310         u32 value;
1311
1312         err = kstrtou32(buf, 10, &value);
1313         if (err)
1314                 return err;
1315
1316         value = value / 1000000; /* convert to Watt */
1317         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
1318                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
1319                 if (err)
1320                         return err;
1321         } else {
1322                 return -EINVAL;
1323         }
1324
1325         return count;
1326 }
1327
1328
1329 /**
1330  * DOC: hwmon
1331  *
1332  * The amdgpu driver exposes the following sensor interfaces:
1333  *
1334  * - GPU temperature (via the on-die sensor)
1335  *
1336  * - GPU voltage
1337  *
1338  * - Northbridge voltage (APUs only)
1339  *
1340  * - GPU power
1341  *
1342  * - GPU fan
1343  *
1344  * hwmon interfaces for GPU temperature:
1345  *
1346  * - temp1_input: the on die GPU temperature in millidegrees Celsius
1347  *
1348  * - temp1_crit: temperature critical max value in millidegrees Celsius
1349  *
1350  * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1351  *
1352  * hwmon interfaces for GPU voltage:
1353  *
1354  * - in0_input: the voltage on the GPU in millivolts
1355  *
1356  * - in1_input: the voltage on the Northbridge in millivolts
1357  *
1358  * hwmon interfaces for GPU power:
1359  *
1360  * - power1_average: average power used by the GPU in microWatts
1361  *
1362  * - power1_cap_min: minimum cap supported in microWatts
1363  *
1364  * - power1_cap_max: maximum cap supported in microWatts
1365  *
1366  * - power1_cap: selected power cap in microWatts
1367  *
1368  * hwmon interfaces for GPU fan:
1369  *
1370  * - pwm1: pulse width modulation fan level (0-255)
1371  *
1372  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
1373  *
1374  * - pwm1_min: pulse width modulation fan control minimum level (0)
1375  *
1376  * - pwm1_max: pulse width modulation fan control maximum level (255)
1377  *
1378  * - fan1_input: fan speed in RPM
1379  *
1380  * You can use hwmon tools like sensors to view this information on your system.
1381  *
1382  */
1383
1384 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
1385 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
1386 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
1387 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
1388 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
1389 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
1390 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
1391 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
1392 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
1393 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
1394 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
1395 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
1396 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
1397 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
1398 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
1399 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
1400
1401 static struct attribute *hwmon_attributes[] = {
1402         &sensor_dev_attr_temp1_input.dev_attr.attr,
1403         &sensor_dev_attr_temp1_crit.dev_attr.attr,
1404         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
1405         &sensor_dev_attr_pwm1.dev_attr.attr,
1406         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1407         &sensor_dev_attr_pwm1_min.dev_attr.attr,
1408         &sensor_dev_attr_pwm1_max.dev_attr.attr,
1409         &sensor_dev_attr_fan1_input.dev_attr.attr,
1410         &sensor_dev_attr_in0_input.dev_attr.attr,
1411         &sensor_dev_attr_in0_label.dev_attr.attr,
1412         &sensor_dev_attr_in1_input.dev_attr.attr,
1413         &sensor_dev_attr_in1_label.dev_attr.attr,
1414         &sensor_dev_attr_power1_average.dev_attr.attr,
1415         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
1416         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
1417         &sensor_dev_attr_power1_cap.dev_attr.attr,
1418         NULL
1419 };
1420
1421 static umode_t hwmon_attributes_visible(struct kobject *kobj,
1422                                         struct attribute *attr, int index)
1423 {
1424         struct device *dev = kobj_to_dev(kobj);
1425         struct amdgpu_device *adev = dev_get_drvdata(dev);
1426         umode_t effective_mode = attr->mode;
1427
1428
1429         /* Skip fan attributes if fan is not present */
1430         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1431             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1432             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1433             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
1434             attr == &sensor_dev_attr_fan1_input.dev_attr.attr))
1435                 return 0;
1436
1437         /* Skip limit attributes if DPM is not enabled */
1438         if (!adev->pm.dpm_enabled &&
1439             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
1440              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
1441              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1442              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1443              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1444              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1445                 return 0;
1446
1447         /* mask fan attributes if we have no bindings for this asic to expose */
1448         if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
1449              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
1450             (!adev->powerplay.pp_funcs->get_fan_control_mode &&
1451              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
1452                 effective_mode &= ~S_IRUGO;
1453
1454         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1455              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
1456             (!adev->powerplay.pp_funcs->set_fan_control_mode &&
1457              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
1458                 effective_mode &= ~S_IWUSR;
1459
1460         if ((adev->flags & AMD_IS_APU) &&
1461             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
1462              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
1463              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
1464                 return 0;
1465
1466         /* hide max/min values if we can't both query and manage the fan */
1467         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1468              !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
1469             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1470              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1471                 return 0;
1472
1473         /* only APUs have vddnb */
1474         if (!(adev->flags & AMD_IS_APU) &&
1475             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
1476              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
1477                 return 0;
1478
1479         return effective_mode;
1480 }
1481
1482 static const struct attribute_group hwmon_attrgroup = {
1483         .attrs = hwmon_attributes,
1484         .is_visible = hwmon_attributes_visible,
1485 };
1486
1487 static const struct attribute_group *hwmon_groups[] = {
1488         &hwmon_attrgroup,
1489         NULL
1490 };
1491
1492 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
1493 {
1494         struct amdgpu_device *adev =
1495                 container_of(work, struct amdgpu_device,
1496                              pm.dpm.thermal.work);
1497         /* switch to the thermal state */
1498         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
1499         int temp, size = sizeof(temp);
1500
1501         if (!adev->pm.dpm_enabled)
1502                 return;
1503
1504         if (adev->powerplay.pp_funcs &&
1505             adev->powerplay.pp_funcs->read_sensor &&
1506             !amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1507                                     (void *)&temp, &size)) {
1508                 if (temp < adev->pm.dpm.thermal.min_temp)
1509                         /* switch back the user state */
1510                         dpm_state = adev->pm.dpm.user_state;
1511         } else {
1512                 if (adev->pm.dpm.thermal.high_to_low)
1513                         /* switch back the user state */
1514                         dpm_state = adev->pm.dpm.user_state;
1515         }
1516         mutex_lock(&adev->pm.mutex);
1517         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
1518                 adev->pm.dpm.thermal_active = true;
1519         else
1520                 adev->pm.dpm.thermal_active = false;
1521         adev->pm.dpm.state = dpm_state;
1522         mutex_unlock(&adev->pm.mutex);
1523
1524         amdgpu_pm_compute_clocks(adev);
1525 }
1526
1527 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
1528                                                      enum amd_pm_state_type dpm_state)
1529 {
1530         int i;
1531         struct amdgpu_ps *ps;
1532         u32 ui_class;
1533         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
1534                 true : false;
1535
1536         /* check if the vblank period is too short to adjust the mclk */
1537         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
1538                 if (amdgpu_dpm_vblank_too_short(adev))
1539                         single_display = false;
1540         }
1541
1542         /* certain older asics have a separare 3D performance state,
1543          * so try that first if the user selected performance
1544          */
1545         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
1546                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
1547         /* balanced states don't exist at the moment */
1548         if (dpm_state == POWER_STATE_TYPE_BALANCED)
1549                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1550
1551 restart_search:
1552         /* Pick the best power state based on current conditions */
1553         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
1554                 ps = &adev->pm.dpm.ps[i];
1555                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
1556                 switch (dpm_state) {
1557                 /* user states */
1558                 case POWER_STATE_TYPE_BATTERY:
1559                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
1560                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1561                                         if (single_display)
1562                                                 return ps;
1563                                 } else
1564                                         return ps;
1565                         }
1566                         break;
1567                 case POWER_STATE_TYPE_BALANCED:
1568                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
1569                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1570                                         if (single_display)
1571                                                 return ps;
1572                                 } else
1573                                         return ps;
1574                         }
1575                         break;
1576                 case POWER_STATE_TYPE_PERFORMANCE:
1577                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
1578                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1579                                         if (single_display)
1580                                                 return ps;
1581                                 } else
1582                                         return ps;
1583                         }
1584                         break;
1585                 /* internal states */
1586                 case POWER_STATE_TYPE_INTERNAL_UVD:
1587                         if (adev->pm.dpm.uvd_ps)
1588                                 return adev->pm.dpm.uvd_ps;
1589                         else
1590                                 break;
1591                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1592                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1593                                 return ps;
1594                         break;
1595                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1596                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1597                                 return ps;
1598                         break;
1599                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1600                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1601                                 return ps;
1602                         break;
1603                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1604                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1605                                 return ps;
1606                         break;
1607                 case POWER_STATE_TYPE_INTERNAL_BOOT:
1608                         return adev->pm.dpm.boot_ps;
1609                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1610                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1611                                 return ps;
1612                         break;
1613                 case POWER_STATE_TYPE_INTERNAL_ACPI:
1614                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1615                                 return ps;
1616                         break;
1617                 case POWER_STATE_TYPE_INTERNAL_ULV:
1618                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1619                                 return ps;
1620                         break;
1621                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1622                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1623                                 return ps;
1624                         break;
1625                 default:
1626                         break;
1627                 }
1628         }
1629         /* use a fallback state if we didn't match */
1630         switch (dpm_state) {
1631         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1632                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1633                 goto restart_search;
1634         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1635         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1636         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1637                 if (adev->pm.dpm.uvd_ps) {
1638                         return adev->pm.dpm.uvd_ps;
1639                 } else {
1640                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1641                         goto restart_search;
1642                 }
1643         case POWER_STATE_TYPE_INTERNAL_THERMAL:
1644                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1645                 goto restart_search;
1646         case POWER_STATE_TYPE_INTERNAL_ACPI:
1647                 dpm_state = POWER_STATE_TYPE_BATTERY;
1648                 goto restart_search;
1649         case POWER_STATE_TYPE_BATTERY:
1650         case POWER_STATE_TYPE_BALANCED:
1651         case POWER_STATE_TYPE_INTERNAL_3DPERF:
1652                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1653                 goto restart_search;
1654         default:
1655                 break;
1656         }
1657
1658         return NULL;
1659 }
1660
1661 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1662 {
1663         struct amdgpu_ps *ps;
1664         enum amd_pm_state_type dpm_state;
1665         int ret;
1666         bool equal = false;
1667
1668         /* if dpm init failed */
1669         if (!adev->pm.dpm_enabled)
1670                 return;
1671
1672         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1673                 /* add other state override checks here */
1674                 if ((!adev->pm.dpm.thermal_active) &&
1675                     (!adev->pm.dpm.uvd_active))
1676                         adev->pm.dpm.state = adev->pm.dpm.user_state;
1677         }
1678         dpm_state = adev->pm.dpm.state;
1679
1680         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1681         if (ps)
1682                 adev->pm.dpm.requested_ps = ps;
1683         else
1684                 return;
1685
1686         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
1687                 printk("switching from power state:\n");
1688                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1689                 printk("switching to power state:\n");
1690                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1691         }
1692
1693         /* update whether vce is active */
1694         ps->vce_active = adev->pm.dpm.vce_active;
1695         if (adev->powerplay.pp_funcs->display_configuration_changed)
1696                 amdgpu_dpm_display_configuration_changed(adev);
1697
1698         ret = amdgpu_dpm_pre_set_power_state(adev);
1699         if (ret)
1700                 return;
1701
1702         if (adev->powerplay.pp_funcs->check_state_equal) {
1703                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
1704                         equal = false;
1705         }
1706
1707         if (equal)
1708                 return;
1709
1710         amdgpu_dpm_set_power_state(adev);
1711         amdgpu_dpm_post_set_power_state(adev);
1712
1713         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1714         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1715
1716         if (adev->powerplay.pp_funcs->force_performance_level) {
1717                 if (adev->pm.dpm.thermal_active) {
1718                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1719                         /* force low perf level for thermal */
1720                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1721                         /* save the user's level */
1722                         adev->pm.dpm.forced_level = level;
1723                 } else {
1724                         /* otherwise, user selected level */
1725                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1726                 }
1727         }
1728 }
1729
1730 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1731 {
1732         if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
1733                 /* enable/disable UVD */
1734                 mutex_lock(&adev->pm.mutex);
1735                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
1736                 mutex_unlock(&adev->pm.mutex);
1737         } else {
1738                 if (enable) {
1739                         mutex_lock(&adev->pm.mutex);
1740                         adev->pm.dpm.uvd_active = true;
1741                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1742                         mutex_unlock(&adev->pm.mutex);
1743                 } else {
1744                         mutex_lock(&adev->pm.mutex);
1745                         adev->pm.dpm.uvd_active = false;
1746                         mutex_unlock(&adev->pm.mutex);
1747                 }
1748                 amdgpu_pm_compute_clocks(adev);
1749         }
1750 }
1751
1752 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1753 {
1754         if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
1755                 /* enable/disable VCE */
1756                 mutex_lock(&adev->pm.mutex);
1757                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
1758                 mutex_unlock(&adev->pm.mutex);
1759         } else {
1760                 if (enable) {
1761                         mutex_lock(&adev->pm.mutex);
1762                         adev->pm.dpm.vce_active = true;
1763                         /* XXX select vce level based on ring/task */
1764                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1765                         mutex_unlock(&adev->pm.mutex);
1766                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1767                                                                AMD_CG_STATE_UNGATE);
1768                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1769                                                                AMD_PG_STATE_UNGATE);
1770                         amdgpu_pm_compute_clocks(adev);
1771                 } else {
1772                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1773                                                                AMD_PG_STATE_GATE);
1774                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1775                                                                AMD_CG_STATE_GATE);
1776                         mutex_lock(&adev->pm.mutex);
1777                         adev->pm.dpm.vce_active = false;
1778                         mutex_unlock(&adev->pm.mutex);
1779                         amdgpu_pm_compute_clocks(adev);
1780                 }
1781
1782         }
1783 }
1784
1785 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1786 {
1787         int i;
1788
1789         if (adev->powerplay.pp_funcs->print_power_state == NULL)
1790                 return;
1791
1792         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1793                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1794
1795 }
1796
1797 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1798 {
1799         int ret;
1800
1801         if (adev->pm.sysfs_initialized)
1802                 return 0;
1803
1804         if (adev->pm.dpm_enabled == 0)
1805                 return 0;
1806
1807         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1808                                                                    DRIVER_NAME, adev,
1809                                                                    hwmon_groups);
1810         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1811                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1812                 dev_err(adev->dev,
1813                         "Unable to register hwmon device: %d\n", ret);
1814                 return ret;
1815         }
1816
1817         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1818         if (ret) {
1819                 DRM_ERROR("failed to create device file for dpm state\n");
1820                 return ret;
1821         }
1822         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1823         if (ret) {
1824                 DRM_ERROR("failed to create device file for dpm state\n");
1825                 return ret;
1826         }
1827
1828
1829         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1830         if (ret) {
1831                 DRM_ERROR("failed to create device file pp_num_states\n");
1832                 return ret;
1833         }
1834         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1835         if (ret) {
1836                 DRM_ERROR("failed to create device file pp_cur_state\n");
1837                 return ret;
1838         }
1839         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1840         if (ret) {
1841                 DRM_ERROR("failed to create device file pp_force_state\n");
1842                 return ret;
1843         }
1844         ret = device_create_file(adev->dev, &dev_attr_pp_table);
1845         if (ret) {
1846                 DRM_ERROR("failed to create device file pp_table\n");
1847                 return ret;
1848         }
1849
1850         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1851         if (ret) {
1852                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1853                 return ret;
1854         }
1855         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1856         if (ret) {
1857                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1858                 return ret;
1859         }
1860         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1861         if (ret) {
1862                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1863                 return ret;
1864         }
1865         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1866         if (ret) {
1867                 DRM_ERROR("failed to create device file pp_sclk_od\n");
1868                 return ret;
1869         }
1870         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1871         if (ret) {
1872                 DRM_ERROR("failed to create device file pp_mclk_od\n");
1873                 return ret;
1874         }
1875         ret = device_create_file(adev->dev,
1876                         &dev_attr_pp_power_profile_mode);
1877         if (ret) {
1878                 DRM_ERROR("failed to create device file "
1879                                 "pp_power_profile_mode\n");
1880                 return ret;
1881         }
1882         ret = device_create_file(adev->dev,
1883                         &dev_attr_pp_od_clk_voltage);
1884         if (ret) {
1885                 DRM_ERROR("failed to create device file "
1886                                 "pp_od_clk_voltage\n");
1887                 return ret;
1888         }
1889         ret = device_create_file(adev->dev,
1890                         &dev_attr_gpu_busy_percent);
1891         if (ret) {
1892                 DRM_ERROR("failed to create device file "
1893                                 "gpu_busy_level\n");
1894                 return ret;
1895         }
1896         ret = amdgpu_debugfs_pm_init(adev);
1897         if (ret) {
1898                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1899                 return ret;
1900         }
1901
1902         adev->pm.sysfs_initialized = true;
1903
1904         return 0;
1905 }
1906
1907 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1908 {
1909         if (adev->pm.dpm_enabled == 0)
1910                 return;
1911
1912         if (adev->pm.int_hwmon_dev)
1913                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1914         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1915         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1916
1917         device_remove_file(adev->dev, &dev_attr_pp_num_states);
1918         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1919         device_remove_file(adev->dev, &dev_attr_pp_force_state);
1920         device_remove_file(adev->dev, &dev_attr_pp_table);
1921
1922         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1923         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1924         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1925         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1926         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1927         device_remove_file(adev->dev,
1928                         &dev_attr_pp_power_profile_mode);
1929         device_remove_file(adev->dev,
1930                         &dev_attr_pp_od_clk_voltage);
1931         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
1932 }
1933
1934 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1935 {
1936         int i = 0;
1937
1938         if (!adev->pm.dpm_enabled)
1939                 return;
1940
1941         if (adev->mode_info.num_crtc)
1942                 amdgpu_display_bandwidth_update(adev);
1943
1944         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1945                 struct amdgpu_ring *ring = adev->rings[i];
1946                 if (ring && ring->ready)
1947                         amdgpu_fence_wait_empty(ring);
1948         }
1949
1950         mutex_lock(&adev->pm.mutex);
1951         /* update battery/ac status */
1952         if (power_supply_is_system_supplied() > 0)
1953                 adev->pm.ac_power = true;
1954         else
1955                 adev->pm.ac_power = false;
1956         mutex_unlock(&adev->pm.mutex);
1957
1958         if (adev->powerplay.pp_funcs->dispatch_tasks) {
1959                 if (!amdgpu_device_has_dc_support(adev)) {
1960                         mutex_lock(&adev->pm.mutex);
1961                         amdgpu_dpm_get_active_displays(adev);
1962                         adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
1963                         adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
1964                         adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
1965                         /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
1966                         if (adev->pm.pm_display_cfg.vrefresh > 120)
1967                                 adev->pm.pm_display_cfg.min_vblank_time = 0;
1968                         if (adev->powerplay.pp_funcs->display_configuration_change)
1969                                 adev->powerplay.pp_funcs->display_configuration_change(
1970                                                                 adev->powerplay.pp_handle,
1971                                                                 &adev->pm.pm_display_cfg);
1972                         mutex_unlock(&adev->pm.mutex);
1973                 }
1974                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
1975         } else {
1976                 mutex_lock(&adev->pm.mutex);
1977                 amdgpu_dpm_get_active_displays(adev);
1978                 amdgpu_dpm_change_power_state_locked(adev);
1979                 mutex_unlock(&adev->pm.mutex);
1980         }
1981 }
1982
1983 /*
1984  * Debugfs info
1985  */
1986 #if defined(CONFIG_DEBUG_FS)
1987
1988 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1989 {
1990         uint32_t value;
1991         uint32_t query = 0;
1992         int size;
1993
1994         /* sanity check PP is enabled */
1995         if (!(adev->powerplay.pp_funcs &&
1996               adev->powerplay.pp_funcs->read_sensor))
1997               return -EINVAL;
1998
1999         /* GPU Clocks */
2000         size = sizeof(value);
2001         seq_printf(m, "GFX Clocks and Power:\n");
2002         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
2003                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
2004         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
2005                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
2006         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
2007                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
2008         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
2009                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
2010         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
2011                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
2012         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
2013                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
2014         size = sizeof(uint32_t);
2015         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
2016                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
2017         size = sizeof(value);
2018         seq_printf(m, "\n");
2019
2020         /* GPU Temp */
2021         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
2022                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
2023
2024         /* GPU Load */
2025         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
2026                 seq_printf(m, "GPU Load: %u %%\n", value);
2027         seq_printf(m, "\n");
2028
2029         /* UVD clocks */
2030         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
2031                 if (!value) {
2032                         seq_printf(m, "UVD: Disabled\n");
2033                 } else {
2034                         seq_printf(m, "UVD: Enabled\n");
2035                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
2036                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
2037                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
2038                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
2039                 }
2040         }
2041         seq_printf(m, "\n");
2042
2043         /* VCE clocks */
2044         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
2045                 if (!value) {
2046                         seq_printf(m, "VCE: Disabled\n");
2047                 } else {
2048                         seq_printf(m, "VCE: Enabled\n");
2049                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
2050                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
2051                 }
2052         }
2053
2054         return 0;
2055 }
2056
2057 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
2058 {
2059         int i;
2060
2061         for (i = 0; clocks[i].flag; i++)
2062                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
2063                            (flags & clocks[i].flag) ? "On" : "Off");
2064 }
2065
2066 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
2067 {
2068         struct drm_info_node *node = (struct drm_info_node *) m->private;
2069         struct drm_device *dev = node->minor->dev;
2070         struct amdgpu_device *adev = dev->dev_private;
2071         struct drm_device *ddev = adev->ddev;
2072         u32 flags = 0;
2073
2074         amdgpu_device_ip_get_clockgating_state(adev, &flags);
2075         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
2076         amdgpu_parse_cg_state(m, flags);
2077         seq_printf(m, "\n");
2078
2079         if (!adev->pm.dpm_enabled) {
2080                 seq_printf(m, "dpm not enabled\n");
2081                 return 0;
2082         }
2083         if  ((adev->flags & AMD_IS_PX) &&
2084              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
2085                 seq_printf(m, "PX asic powered off\n");
2086         } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
2087                 mutex_lock(&adev->pm.mutex);
2088                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
2089                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
2090                 else
2091                         seq_printf(m, "Debugfs support not implemented for this asic\n");
2092                 mutex_unlock(&adev->pm.mutex);
2093         } else {
2094                 return amdgpu_debugfs_pm_info_pp(m, adev);
2095         }
2096
2097         return 0;
2098 }
2099
2100 static const struct drm_info_list amdgpu_pm_info_list[] = {
2101         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
2102 };
2103 #endif
2104
2105 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
2106 {
2107 #if defined(CONFIG_DEBUG_FS)
2108         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
2109 #else
2110         return 0;
2111 #endif
2112 }