drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "mmhub_v2_0.h"
  26
  27 #include "mmhub/mmhub_2_0_0_offset.h"
  28 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  29 #include "mmhub/mmhub_2_0_0_default.h"
  30 #include "navi10_enum.h"
  31
  32 #include "soc15_common.h"
  33
  34 static void mmhub_v2_0_init_gart_pt_regs(struct amdgpu_device *adev)
  35 {
  36         uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
  37
  38         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  39                      lower_32_bits(value));
  40
  41         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  42                      upper_32_bits(value));
  43 }
  44
  45 static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
  46 {
  47         mmhub_v2_0_init_gart_pt_regs(adev);
  48
  49         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  50                      (u32)(adev->gmc.gart_start >> 12));
  51         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  52                      (u32)(adev->gmc.gart_start >> 44));
  53
  54         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  55                      (u32)(adev->gmc.gart_end >> 12));
  56         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  57                      (u32)(adev->gmc.gart_end >> 44));
  58 }
  59
  60 static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
  61 {
  62         uint64_t value;
  63         uint32_t tmp;
  64
  65         /* Disable AGP. */
  66         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
  67         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0);
  68         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF);
  69
  70         /* Program the system aperture low logical page number. */
  71         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
  72                      adev->gmc.vram_start >> 18);
  73         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  74                      adev->gmc.vram_end >> 18);
  75
  76         /* Set default page address. */
  77         value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
  78                 adev->vm_manager.vram_base_offset;
  79         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
  80                      (u32)(value >> 12));
  81         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
  82                      (u32)(value >> 44));
  83
  84         /* Program "protection fault". */
  85         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
  86                      (u32)(adev->dummy_page_addr >> 12));
  87         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
  88                      (u32)((u64)adev->dummy_page_addr >> 44));
  89
  90         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
  91         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
  92                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
  93         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
  94 }
  95
  96 static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev)
  97 {
  98         uint32_t tmp;
  99
 100         /* Setup TLB control */
 101         tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
 102
 103         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 104         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 105         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 106                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 107         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 108                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 109         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 110         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 111                             MTYPE, MTYPE_UC); /* UC, uncached */
 112
 113         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
 114 }
 115
 116 static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
 117 {
 118         uint32_t tmp;
 119
 120         /* Setup L2 cache */
 121         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
 122         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
 123         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
 124         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
 125                             ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 126         /* XXX for emulation, Refer to closed source code.*/
 127         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 128                             0);
 129         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
 130         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 131         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 132         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
 133
 134         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
 135         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 136         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 137         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
 138
 139         tmp = mmMMVM_L2_CNTL3_DEFAULT;
 140         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
 141
 142         tmp = mmMMVM_L2_CNTL4_DEFAULT;
 143         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 144         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 145         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
 146 }
 147
 148 static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
 149 {
 150         uint32_t tmp;
 151
 152         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
 153         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 154         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 155         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
 156 }
 157
 158 static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
 159 {
 160         WREG32_SOC15(MMHUB, 0,
 161                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 162                      0xFFFFFFFF);
 163         WREG32_SOC15(MMHUB, 0,
 164                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 165                      0x0000000F);
 166
 167         WREG32_SOC15(MMHUB, 0,
 168                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
 169         WREG32_SOC15(MMHUB, 0,
 170                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
 171
 172         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 173                      0);
 174         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 175                      0);
 176 }
 177
 178 static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
 179 {
 180         int i;
 181         uint32_t tmp;
 182
 183         for (i = 0; i <= 14; i++) {
 184                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
 185                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 186                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 187                                     adev->vm_manager.num_level);
 188                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 189                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 190                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 191                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 192                                     1);
 193                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 194                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 195                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 196                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 197                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 198                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 199                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 200                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 201                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 202                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 203                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 204                                     PAGE_TABLE_BLOCK_SIZE,
 205                                     adev->vm_manager.block_size - 9);
 206                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 207                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 208                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 209                                     !amdgpu_noretry);
 210                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i, tmp);
 211                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
 212                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
 213                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
 214                         lower_32_bits(adev->vm_manager.max_pfn - 1));
 215                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
 216                         upper_32_bits(adev->vm_manager.max_pfn - 1));
 217         }
 218 }
 219
 220 static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev)
 221 {
 222         unsigned i;
 223
 224         for (i = 0; i < 18; ++i) {
 225                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 226                                     2 * i, 0xffffffff);
 227                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 228                                     2 * i, 0x1f);
 229         }
 230 }
 231
 232 int mmhub_v2_0_gart_enable(struct amdgpu_device *adev)
 233 {
 234         if (amdgpu_sriov_vf(adev)) {
 235                 /*
 236                  * MMMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 237                  * VF copy registers so vbios post doesn't program them, for
 238                  * SRIOV driver need to program them
 239                  */
 240                 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_BASE,
 241                              adev->gmc.vram_start >> 24);
 242                 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_TOP,
 243                              adev->gmc.vram_end >> 24);
 244         }
 245
 246         /* GART Enable. */
 247         mmhub_v2_0_init_gart_aperture_regs(adev);
 248         mmhub_v2_0_init_system_aperture_regs(adev);
 249         mmhub_v2_0_init_tlb_regs(adev);
 250         mmhub_v2_0_init_cache_regs(adev);
 251
 252         mmhub_v2_0_enable_system_domain(adev);
 253         mmhub_v2_0_disable_identity_aperture(adev);
 254         mmhub_v2_0_setup_vmid_config(adev);
 255         mmhub_v2_0_program_invalidation(adev);
 256
 257         return 0;
 258 }
 259
 260 void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
 261 {
 262         u32 tmp;
 263         u32 i;
 264
 265         /* Disable all tables */
 266         for (i = 0; i < 16; i++)
 267                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, i, 0);
 268
 269         /* Setup TLB control */
 270         tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
 271         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 272         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 273                             ENABLE_ADVANCED_DRIVER_MODEL, 0);
 274         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
 275
 276         /* Setup L2 cache */
 277         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
 278         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
 279         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
 280         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0);
 281 }
 282
 283 /**
 284  * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling
 285  *
 286  * @adev: amdgpu_device pointer
 287  * @value: true redirects VM faults to the default page
 288  */
 289 void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 290 {
 291         u32 tmp;
 292         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
 293         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 294                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 295         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 296                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 297         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 298                             PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 299         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 300                             PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 301         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 302                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 303                             value);
 304         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 305                             NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 306         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 307                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 308         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 309                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 310         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 311                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 312         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 313                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 314         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 315                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 316         if (!value) {
 317                 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 318                                 CRASH_ON_NO_RETRY_FAULT, 1);
 319                 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 320                                 CRASH_ON_RETRY_FAULT, 1);
 321         }
 322         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
 323 }
 324
 325 void mmhub_v2_0_init(struct amdgpu_device *adev)
 326 {
 327         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB];
 328
 329         hub->ctx0_ptb_addr_lo32 =
 330                 SOC15_REG_OFFSET(MMHUB, 0,
 331                                  mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 332         hub->ctx0_ptb_addr_hi32 =
 333                 SOC15_REG_OFFSET(MMHUB, 0,
 334                                  mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 335         hub->vm_inv_eng0_req =
 336                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
 337         hub->vm_inv_eng0_ack =
 338                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
 339         hub->vm_context0_cntl =
 340                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
 341         hub->vm_l2_pro_fault_status =
 342                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
 343         hub->vm_l2_pro_fault_cntl =
 344                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
 345
 346 }
 347
 348 static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 349                                                         bool enable)
 350 {
 351         uint32_t def, data, def1, data1;
 352
 353         def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
 354
 355         def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
 356
 357         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
 358                 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
 359
 360                 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 361                            DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 362                            DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 363                            DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 364                            DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 365                            DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 366
 367         } else {
 368                 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
 369
 370                 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 371                           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 372                           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 373                           DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 374                           DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 375                           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 376         }
 377
 378         if (def != data)
 379                 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
 380
 381         if (def1 != data1)
 382                 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
 383 }
 384
 385 static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 386                                                        bool enable)
 387 {
 388         uint32_t def, data;
 389
 390         def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
 391
 392         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 393                 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 394         else
 395                 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 396
 397         if (def != data)
 398                 WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
 399 }
 400
 401 int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
 402                                enum amd_clockgating_state state)
 403 {
 404         if (amdgpu_sriov_vf(adev))
 405                 return 0;
 406
 407         switch (adev->asic_type) {
 408         case CHIP_NAVI10:
 409                 mmhub_v2_0_update_medium_grain_clock_gating(adev,
 410                                 state == AMD_CG_STATE_GATE ? true : false);
 411                 mmhub_v2_0_update_medium_grain_light_sleep(adev,
 412                                 state == AMD_CG_STATE_GATE ? true : false);
 413                 break;
 414         default:
 415                 break;
 416         }
 417
 418         return 0;
 419 }
 420
 421 void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 422 {
 423         int data, data1;
 424
 425         if (amdgpu_sriov_vf(adev))
 426                 *flags = 0;
 427
 428         data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
 429
 430         data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
 431
 432         /* AMD_CG_SUPPORT_MC_MGCG */
 433         if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) &&
 434             !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 435                        DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 436                        DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 437                        DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 438                        DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 439                        DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
 440                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
 441
 442         /* AMD_CG_SUPPORT_MC_LS */
 443         if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
 444                 *flags |= AMD_CG_SUPPORT_MC_LS;
 445 }