drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "smuio/smuio_11_0_0_offset.h"
  39 #include "smuio/smuio_11_0_0_sh_mask.h"
  40 #include "navi10_enum.h"
  41 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  42
  43 #include "soc15.h"
  44 #include "soc15d.h"
  45 #include "soc15_common.h"
  46 #include "clearstate_gfx10.h"
  47 #include "v10_structs.h"
  48 #include "gfx_v10_0.h"
  49 #include "nbio_v2_3.h"
  50
  51 /**
  52  * Navi10 has two graphic rings to share each graphic pipe.
  53  * 1. Primary ring
  54  * 2. Async ring
  55  */
  56 #define GFX10_NUM_GFX_RINGS_NV1X        1
  57 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  58 #define GFX10_MEC_HPD_SIZE      2048
  59
  60 #define F32_CE_PROGRAM_RAM_SIZE         65536
  61 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  62
  63 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  65 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  66 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  67 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  68 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  69
  70 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  71 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  72
  73 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  74 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  75 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  76 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  77 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  79 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  81 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  83 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  85 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  87 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  89 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  91 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  93 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  95 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
  96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
  97 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
  98 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
  99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 100
 101 #define mmCGTS_TCC_DISABLE_Vangogh                0x5006
 102 #define mmCGTS_TCC_DISABLE_Vangogh_BASE_IDX       1
 103 #define mmCGTS_USER_TCC_DISABLE_Vangogh                0x5007
 104 #define mmCGTS_USER_TCC_DISABLE_Vangogh_BASE_IDX       1
 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 109 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 110 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 111 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 112 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 113 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 114 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 115 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 116 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 117 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 118 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 119 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 120 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 121 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 122 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 123 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 124 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 125 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 126 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 127 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 128
 129 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 130 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 131 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 132 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 133 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 134 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 135 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 136 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 137 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 138 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 139 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 140 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 141
 142 #define mmCPG_PSP_DEBUG                         0x5c10
 143 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 144 #define mmCPC_PSP_DEBUG                         0x5c11
 145 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 146 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 147 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 148
 149 //CC_GC_SA_UNIT_DISABLE
 150 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 151 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 152 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 153 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 154 //GC_USER_SA_UNIT_DISABLE
 155 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 156 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 157 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 158 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 159 //PA_SC_ENHANCE_3
 160 #define mmPA_SC_ENHANCE_3                       0x1085
 161 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 162 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 163 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 164
 165 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 166 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 167
 168 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 169 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 170 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 171 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 172
 173 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 174 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 175
 176 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 177 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 178 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 179 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 180 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 181 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 182
 183 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 184 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 185 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 186 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 187 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 188 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 189 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 190 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 191 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 192 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 193 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 194
 195 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 196 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 197 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 198 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 199 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 200 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 201
 202 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 203 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 204 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 205 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 206 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 207 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 208
 209 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 210 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 211 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 212 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 213 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 214 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 215
 216 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 217 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 218 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 219 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 220 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 221 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 222
 223 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 224 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 225 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 226 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 227 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 228 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 229
 230 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 231 {
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 272 };
 273
 274 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 275 {
 276         /* Pending on emulation bring up */
 277 };
 278
 279 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 280 {
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1333 };
1334
1335 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1336 {
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1375 };
1376
1377 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1378 {
1379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1419 };
1420
1421 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1422 {
1423         static void *scratch_reg0;
1424         static void *scratch_reg1;
1425         static void *spare_int;
1426         uint32_t i = 0;
1427         uint32_t retries = 50000;
1428
1429         scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1430         scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1431         spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1432
1433         if (amdgpu_sriov_runtime(adev)) {
1434                 pr_err("shouldn't call rlcg write register during runtime\n");
1435                 return;
1436         }
1437
1438         writel(v, scratch_reg0);
1439         writel(offset | 0x80000000, scratch_reg1);
1440         writel(1, spare_int);
1441         for (i = 0; i < retries; i++) {
1442                 u32 tmp;
1443
1444                 tmp = readl(scratch_reg1);
1445                 if (!(tmp & 0x80000000))
1446                         break;
1447
1448                 udelay(10);
1449         }
1450
1451         if (i >= retries)
1452                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1453 }
1454
1455 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1456 {
1457         /* Pending on emulation bring up */
1458 };
1459
1460 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1461 {
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2082 };
2083
2084 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2085 {
2086         /* Pending on emulation bring up */
2087 };
2088
2089 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2090 {
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3143 };
3144
3145 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3146 {
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3189 };
3190
3191 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3192 {
3193         /* Pending on emulation bring up */
3194 };
3195
3196 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3197 {
3198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3239
3240         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3242 };
3243
3244 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3245 {
3246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3269
3270         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3272 };
3273
3274 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3275 {
3276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500),
3283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3311 };
3312
3313 #define DEFAULT_SH_MEM_CONFIG \
3314         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3315          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3316          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3317          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3318
3319
3320 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3321 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3322 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3323 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3324 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3325                                  struct amdgpu_cu_info *cu_info);
3326 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3327 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3328                                    u32 sh_num, u32 instance);
3329 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3330
3331 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3332 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3333 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3334 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3335 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3336 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3337 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3338 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3339 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3340 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3341
3342 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3343 {
3344         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3345         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3346                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3347         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3348         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3349         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3350         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3351         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3352         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3353 }
3354
3355 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3356                                  struct amdgpu_ring *ring)
3357 {
3358         struct amdgpu_device *adev = kiq_ring->adev;
3359         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3360         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3361         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3362
3363         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3364         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3365         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3366                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3367                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3368                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3369                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3370                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3371                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3372                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3373                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3374                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3375         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3376         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3377         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3378         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3379         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3380 }
3381
3382 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3383                                    struct amdgpu_ring *ring,
3384                                    enum amdgpu_unmap_queues_action action,
3385                                    u64 gpu_addr, u64 seq)
3386 {
3387         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3388
3389         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3390         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3391                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3392                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3393                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3394                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3395         amdgpu_ring_write(kiq_ring,
3396                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3397
3398         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3399                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3400                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3401                 amdgpu_ring_write(kiq_ring, seq);
3402         } else {
3403                 amdgpu_ring_write(kiq_ring, 0);
3404                 amdgpu_ring_write(kiq_ring, 0);
3405                 amdgpu_ring_write(kiq_ring, 0);
3406         }
3407 }
3408
3409 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3410                                    struct amdgpu_ring *ring,
3411                                    u64 addr,
3412                                    u64 seq)
3413 {
3414         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3415
3416         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3417         amdgpu_ring_write(kiq_ring,
3418                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3419                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3420                           PACKET3_QUERY_STATUS_COMMAND(2));
3421         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3422                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3423                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3424         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3425         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3426         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3427         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3428 }
3429
3430 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3431                                 uint16_t pasid, uint32_t flush_type,
3432                                 bool all_hub)
3433 {
3434         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3435         amdgpu_ring_write(kiq_ring,
3436                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3437                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3438                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3439                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3440 }
3441
3442 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3443         .kiq_set_resources = gfx10_kiq_set_resources,
3444         .kiq_map_queues = gfx10_kiq_map_queues,
3445         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3446         .kiq_query_status = gfx10_kiq_query_status,
3447         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3448         .set_resources_size = 8,
3449         .map_queues_size = 7,
3450         .unmap_queues_size = 6,
3451         .query_status_size = 7,
3452         .invalidate_tlbs_size = 2,
3453 };
3454
3455 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3456 {
3457         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3458 }
3459
3460 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3461 {
3462         switch (adev->asic_type) {
3463         case CHIP_NAVI10:
3464                 soc15_program_register_sequence(adev,
3465                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3466                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3467                 break;
3468         case CHIP_NAVI14:
3469                 soc15_program_register_sequence(adev,
3470                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3471                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3472                 break;
3473         case CHIP_NAVI12:
3474                 soc15_program_register_sequence(adev,
3475                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3476                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3477                 break;
3478         default:
3479                 break;
3480         }
3481 }
3482
3483 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3484 {
3485         switch (adev->asic_type) {
3486         case CHIP_NAVI10:
3487                 soc15_program_register_sequence(adev,
3488                                                 golden_settings_gc_10_1,
3489                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3490                 soc15_program_register_sequence(adev,
3491                                                 golden_settings_gc_10_0_nv10,
3492                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3493                 break;
3494         case CHIP_NAVI14:
3495                 soc15_program_register_sequence(adev,
3496                                                 golden_settings_gc_10_1_1,
3497                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3498                 soc15_program_register_sequence(adev,
3499                                                 golden_settings_gc_10_1_nv14,
3500                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3501                 break;
3502         case CHIP_NAVI12:
3503                 soc15_program_register_sequence(adev,
3504                                                 golden_settings_gc_10_1_2,
3505                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3506                 soc15_program_register_sequence(adev,
3507                                                 golden_settings_gc_10_1_2_nv12,
3508                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3509                 break;
3510         case CHIP_SIENNA_CICHLID:
3511                 soc15_program_register_sequence(adev,
3512                                                 golden_settings_gc_10_3,
3513                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3514                 soc15_program_register_sequence(adev,
3515                                                 golden_settings_gc_10_3_sienna_cichlid,
3516                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3517                 break;
3518         case CHIP_NAVY_FLOUNDER:
3519                 soc15_program_register_sequence(adev,
3520                                                 golden_settings_gc_10_3_2,
3521                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3522                 break;
3523         case CHIP_VANGOGH:
3524                 soc15_program_register_sequence(adev,
3525                                                 golden_settings_gc_10_3_vangogh,
3526                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3527                 break;
3528         case CHIP_DIMGREY_CAVEFISH:
3529                 soc15_program_register_sequence(adev,
3530                                                 golden_settings_gc_10_3_4,
3531                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3532                 break;
3533         default:
3534                 break;
3535         }
3536         gfx_v10_0_init_spm_golden_registers(adev);
3537 }
3538
3539 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3540 {
3541         adev->gfx.scratch.num_reg = 8;
3542         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3543         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3544 }
3545
3546 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3547                                        bool wc, uint32_t reg, uint32_t val)
3548 {
3549         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3550         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3551                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3552         amdgpu_ring_write(ring, reg);
3553         amdgpu_ring_write(ring, 0);
3554         amdgpu_ring_write(ring, val);
3555 }
3556
3557 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3558                                   int mem_space, int opt, uint32_t addr0,
3559                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3560                                   uint32_t inv)
3561 {
3562         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3563         amdgpu_ring_write(ring,
3564                           /* memory (1) or register (0) */
3565                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3566                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3567                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3568                            WAIT_REG_MEM_ENGINE(eng_sel)));
3569
3570         if (mem_space)
3571                 BUG_ON(addr0 & 0x3); /* Dword align */
3572         amdgpu_ring_write(ring, addr0);
3573         amdgpu_ring_write(ring, addr1);
3574         amdgpu_ring_write(ring, ref);
3575         amdgpu_ring_write(ring, mask);
3576         amdgpu_ring_write(ring, inv); /* poll interval */
3577 }
3578
3579 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3580 {
3581         struct amdgpu_device *adev = ring->adev;
3582         uint32_t scratch;
3583         uint32_t tmp = 0;
3584         unsigned i;
3585         int r;
3586
3587         r = amdgpu_gfx_scratch_get(adev, &scratch);
3588         if (r) {
3589                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3590                 return r;
3591         }
3592
3593         WREG32(scratch, 0xCAFEDEAD);
3594
3595         r = amdgpu_ring_alloc(ring, 3);
3596         if (r) {
3597                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3598                           ring->idx, r);
3599                 amdgpu_gfx_scratch_free(adev, scratch);
3600                 return r;
3601         }
3602
3603         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3604         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3605         amdgpu_ring_write(ring, 0xDEADBEEF);
3606         amdgpu_ring_commit(ring);
3607
3608         for (i = 0; i < adev->usec_timeout; i++) {
3609                 tmp = RREG32(scratch);
3610                 if (tmp == 0xDEADBEEF)
3611                         break;
3612                 if (amdgpu_emu_mode == 1)
3613                         msleep(1);
3614                 else
3615                         udelay(1);
3616         }
3617
3618         if (i >= adev->usec_timeout)
3619                 r = -ETIMEDOUT;
3620
3621         amdgpu_gfx_scratch_free(adev, scratch);
3622
3623         return r;
3624 }
3625
3626 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3627 {
3628         struct amdgpu_device *adev = ring->adev;
3629         struct amdgpu_ib ib;
3630         struct dma_fence *f = NULL;
3631         unsigned index;
3632         uint64_t gpu_addr;
3633         uint32_t tmp;
3634         long r;
3635
3636         r = amdgpu_device_wb_get(adev, &index);
3637         if (r)
3638                 return r;
3639
3640         gpu_addr = adev->wb.gpu_addr + (index * 4);
3641         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3642         memset(&ib, 0, sizeof(ib));
3643         r = amdgpu_ib_get(adev, NULL, 16,
3644                                         AMDGPU_IB_POOL_DIRECT, &ib);
3645         if (r)
3646                 goto err1;
3647
3648         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3649         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3650         ib.ptr[2] = lower_32_bits(gpu_addr);
3651         ib.ptr[3] = upper_32_bits(gpu_addr);
3652         ib.ptr[4] = 0xDEADBEEF;
3653         ib.length_dw = 5;
3654
3655         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3656         if (r)
3657                 goto err2;
3658
3659         r = dma_fence_wait_timeout(f, false, timeout);
3660         if (r == 0) {
3661                 r = -ETIMEDOUT;
3662                 goto err2;
3663         } else if (r < 0) {
3664                 goto err2;
3665         }
3666
3667         tmp = adev->wb.wb[index];
3668         if (tmp == 0xDEADBEEF)
3669                 r = 0;
3670         else
3671                 r = -EINVAL;
3672 err2:
3673         amdgpu_ib_free(adev, &ib, NULL);
3674         dma_fence_put(f);
3675 err1:
3676         amdgpu_device_wb_free(adev, index);
3677         return r;
3678 }
3679
3680 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3681 {
3682         release_firmware(adev->gfx.pfp_fw);
3683         adev->gfx.pfp_fw = NULL;
3684         release_firmware(adev->gfx.me_fw);
3685         adev->gfx.me_fw = NULL;
3686         release_firmware(adev->gfx.ce_fw);
3687         adev->gfx.ce_fw = NULL;
3688         release_firmware(adev->gfx.rlc_fw);
3689         adev->gfx.rlc_fw = NULL;
3690         release_firmware(adev->gfx.mec_fw);
3691         adev->gfx.mec_fw = NULL;
3692         release_firmware(adev->gfx.mec2_fw);
3693         adev->gfx.mec2_fw = NULL;
3694
3695         kfree(adev->gfx.rlc.register_list_format);
3696 }
3697
3698 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3699 {
3700         adev->gfx.cp_fw_write_wait = false;
3701
3702         switch (adev->asic_type) {
3703         case CHIP_NAVI10:
3704         case CHIP_NAVI12:
3705         case CHIP_NAVI14:
3706                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3707                     (adev->gfx.me_feature_version >= 27) &&
3708                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3709                     (adev->gfx.pfp_feature_version >= 27) &&
3710                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3711                     (adev->gfx.mec_feature_version >= 27))
3712                         adev->gfx.cp_fw_write_wait = true;
3713                 break;
3714         case CHIP_SIENNA_CICHLID:
3715         case CHIP_NAVY_FLOUNDER:
3716         case CHIP_VANGOGH:
3717         case CHIP_DIMGREY_CAVEFISH:
3718                 adev->gfx.cp_fw_write_wait = true;
3719                 break;
3720         default:
3721                 break;
3722         }
3723
3724         if (!adev->gfx.cp_fw_write_wait)
3725                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3726 }
3727
3728
3729 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3730 {
3731         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3732
3733         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3734         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3735         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3736         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3737         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3738         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3739         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3740         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3741         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3742         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3743         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3744         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3745         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3746         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3747                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3748 }
3749
3750 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3751 {
3752         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3753
3754         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3755         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3756         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3757         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3758         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3759 }
3760
3761 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3762 {
3763         bool ret = false;
3764
3765         switch (adev->pdev->revision) {
3766         case 0xc2:
3767         case 0xc3:
3768                 ret = true;
3769                 break;
3770         default:
3771                 ret = false;
3772                 break;
3773         }
3774
3775         return ret ;
3776 }
3777
3778 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3779 {
3780         switch (adev->asic_type) {
3781         case CHIP_NAVI10:
3782                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3783                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3784                 break;
3785         default:
3786                 break;
3787         }
3788 }
3789
3790 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3791 {
3792         const char *chip_name;
3793         char fw_name[40];
3794         char wks[10];
3795         int err;
3796         struct amdgpu_firmware_info *info = NULL;
3797         const struct common_firmware_header *header = NULL;
3798         const struct gfx_firmware_header_v1_0 *cp_hdr;
3799         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3800         unsigned int *tmp = NULL;
3801         unsigned int i = 0;
3802         uint16_t version_major;
3803         uint16_t version_minor;
3804
3805         DRM_DEBUG("\n");
3806
3807         memset(wks, 0, sizeof(wks));
3808         switch (adev->asic_type) {
3809         case CHIP_NAVI10:
3810                 chip_name = "navi10";
3811                 break;
3812         case CHIP_NAVI14:
3813                 chip_name = "navi14";
3814                 if (!(adev->pdev->device == 0x7340 &&
3815                       adev->pdev->revision != 0x00))
3816                         snprintf(wks, sizeof(wks), "_wks");
3817                 break;
3818         case CHIP_NAVI12:
3819                 chip_name = "navi12";
3820                 break;
3821         case CHIP_SIENNA_CICHLID:
3822                 chip_name = "sienna_cichlid";
3823                 break;
3824         case CHIP_NAVY_FLOUNDER:
3825                 chip_name = "navy_flounder";
3826                 break;
3827         case CHIP_VANGOGH:
3828                 chip_name = "vangogh";
3829                 break;
3830         case CHIP_DIMGREY_CAVEFISH:
3831                 chip_name = "dimgrey_cavefish";
3832                 break;
3833         default:
3834                 BUG();
3835         }
3836
3837         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3838         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3839         if (err)
3840                 goto out;
3841         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3842         if (err)
3843                 goto out;
3844         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3845         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3846         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3847
3848         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3849         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3850         if (err)
3851                 goto out;
3852         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3853         if (err)
3854                 goto out;
3855         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3856         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3857         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3858
3859         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3860         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3861         if (err)
3862                 goto out;
3863         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3864         if (err)
3865                 goto out;
3866         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3867         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3868         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3869
3870         if (!amdgpu_sriov_vf(adev)) {
3871                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3872                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3873                 if (err)
3874                         goto out;
3875                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3876                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3877                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3878                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3879
3880                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3881                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3882                 adev->gfx.rlc.save_and_restore_offset =
3883                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3884                 adev->gfx.rlc.clear_state_descriptor_offset =
3885                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3886                 adev->gfx.rlc.avail_scratch_ram_locations =
3887                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3888                 adev->gfx.rlc.reg_restore_list_size =
3889                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3890                 adev->gfx.rlc.reg_list_format_start =
3891                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3892                 adev->gfx.rlc.reg_list_format_separate_start =
3893                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3894                 adev->gfx.rlc.starting_offsets_start =
3895                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3896                 adev->gfx.rlc.reg_list_format_size_bytes =
3897                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3898                 adev->gfx.rlc.reg_list_size_bytes =
3899                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3900                 adev->gfx.rlc.register_list_format =
3901                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3902                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3903                 if (!adev->gfx.rlc.register_list_format) {
3904                         err = -ENOMEM;
3905                         goto out;
3906                 }
3907
3908                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3909                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3910                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3911                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
3912
3913                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3914
3915                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3916                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3917                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3918                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3919
3920                 if (version_major == 2) {
3921                         if (version_minor >= 1)
3922                                 gfx_v10_0_init_rlc_ext_microcode(adev);
3923                         if (version_minor == 2)
3924                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
3925                 }
3926         }
3927
3928         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3929         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3930         if (err)
3931                 goto out;
3932         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3933         if (err)
3934                 goto out;
3935         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3936         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3937         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3938
3939         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3940         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3941         if (!err) {
3942                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3943                 if (err)
3944                         goto out;
3945                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3946                 adev->gfx.mec2_fw->data;
3947                 adev->gfx.mec2_fw_version =
3948                 le32_to_cpu(cp_hdr->header.ucode_version);
3949                 adev->gfx.mec2_feature_version =
3950                 le32_to_cpu(cp_hdr->ucode_feature_version);
3951         } else {
3952                 err = 0;
3953                 adev->gfx.mec2_fw = NULL;
3954         }
3955
3956         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3957                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3958                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3959                 info->fw = adev->gfx.pfp_fw;
3960                 header = (const struct common_firmware_header *)info->fw->data;
3961                 adev->firmware.fw_size +=
3962                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3963
3964                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3965                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3966                 info->fw = adev->gfx.me_fw;
3967                 header = (const struct common_firmware_header *)info->fw->data;
3968                 adev->firmware.fw_size +=
3969                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3970
3971                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3972                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3973                 info->fw = adev->gfx.ce_fw;
3974                 header = (const struct common_firmware_header *)info->fw->data;
3975                 adev->firmware.fw_size +=
3976                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3977
3978                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3979                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3980                 info->fw = adev->gfx.rlc_fw;
3981                 if (info->fw) {
3982                         header = (const struct common_firmware_header *)info->fw->data;
3983                         adev->firmware.fw_size +=
3984                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3985                 }
3986                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3987                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3988                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3989                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3990                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3991                         info->fw = adev->gfx.rlc_fw;
3992                         adev->firmware.fw_size +=
3993                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3994
3995                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3996                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3997                         info->fw = adev->gfx.rlc_fw;
3998                         adev->firmware.fw_size +=
3999                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4000
4001                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4002                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4003                         info->fw = adev->gfx.rlc_fw;
4004                         adev->firmware.fw_size +=
4005                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4006
4007                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4008                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4009                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4010                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4011                                 info->fw = adev->gfx.rlc_fw;
4012                                 adev->firmware.fw_size +=
4013                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4014
4015                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4016                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4017                                 info->fw = adev->gfx.rlc_fw;
4018                                 adev->firmware.fw_size +=
4019                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4020                         }
4021                 }
4022
4023                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4024                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4025                 info->fw = adev->gfx.mec_fw;
4026                 header = (const struct common_firmware_header *)info->fw->data;
4027                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4028                 adev->firmware.fw_size +=
4029                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4030                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4031
4032                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4033                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4034                 info->fw = adev->gfx.mec_fw;
4035                 adev->firmware.fw_size +=
4036                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4037
4038                 if (adev->gfx.mec2_fw) {
4039                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4040                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4041                         info->fw = adev->gfx.mec2_fw;
4042                         header = (const struct common_firmware_header *)info->fw->data;
4043                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4044                         adev->firmware.fw_size +=
4045                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4046                                       le32_to_cpu(cp_hdr->jt_size) * 4,
4047                                       PAGE_SIZE);
4048                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4049                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4050                         info->fw = adev->gfx.mec2_fw;
4051                         adev->firmware.fw_size +=
4052                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4053                                       PAGE_SIZE);
4054                 }
4055         }
4056
4057         gfx_v10_0_check_fw_write_wait(adev);
4058 out:
4059         if (err) {
4060                 dev_err(adev->dev,
4061                         "gfx10: Failed to load firmware \"%s\"\n",
4062                         fw_name);
4063                 release_firmware(adev->gfx.pfp_fw);
4064                 adev->gfx.pfp_fw = NULL;
4065                 release_firmware(adev->gfx.me_fw);
4066                 adev->gfx.me_fw = NULL;
4067                 release_firmware(adev->gfx.ce_fw);
4068                 adev->gfx.ce_fw = NULL;
4069                 release_firmware(adev->gfx.rlc_fw);
4070                 adev->gfx.rlc_fw = NULL;
4071                 release_firmware(adev->gfx.mec_fw);
4072                 adev->gfx.mec_fw = NULL;
4073                 release_firmware(adev->gfx.mec2_fw);
4074                 adev->gfx.mec2_fw = NULL;
4075         }
4076
4077         gfx_v10_0_check_gfxoff_flag(adev);
4078
4079         return err;
4080 }
4081
4082 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4083 {
4084         u32 count = 0;
4085         const struct cs_section_def *sect = NULL;
4086         const struct cs_extent_def *ext = NULL;
4087
4088         /* begin clear state */
4089         count += 2;
4090         /* context control state */
4091         count += 3;
4092
4093         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4094                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4095                         if (sect->id == SECT_CONTEXT)
4096                                 count += 2 + ext->reg_count;
4097                         else
4098                                 return 0;
4099                 }
4100         }
4101
4102         /* set PA_SC_TILE_STEERING_OVERRIDE */
4103         count += 3;
4104         /* end clear state */
4105         count += 2;
4106         /* clear state */
4107         count += 2;
4108
4109         return count;
4110 }
4111
4112 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4113                                     volatile u32 *buffer)
4114 {
4115         u32 count = 0, i;
4116         const struct cs_section_def *sect = NULL;
4117         const struct cs_extent_def *ext = NULL;
4118         int ctx_reg_offset;
4119
4120         if (adev->gfx.rlc.cs_data == NULL)
4121                 return;
4122         if (buffer == NULL)
4123                 return;
4124
4125         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4126         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4127
4128         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4129         buffer[count++] = cpu_to_le32(0x80000000);
4130         buffer[count++] = cpu_to_le32(0x80000000);
4131
4132         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4133                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4134                         if (sect->id == SECT_CONTEXT) {
4135                                 buffer[count++] =
4136                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4137                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4138                                                 PACKET3_SET_CONTEXT_REG_START);
4139                                 for (i = 0; i < ext->reg_count; i++)
4140                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4141                         } else {
4142                                 return;
4143                         }
4144                 }
4145         }
4146
4147         ctx_reg_offset =
4148                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4149         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4150         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4151         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4152
4153         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4154         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4155
4156         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4157         buffer[count++] = cpu_to_le32(0);
4158 }
4159
4160 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4161 {
4162         /* clear state block */
4163         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4164                         &adev->gfx.rlc.clear_state_gpu_addr,
4165                         (void **)&adev->gfx.rlc.cs_ptr);
4166
4167         /* jump table block */
4168         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4169                         &adev->gfx.rlc.cp_table_gpu_addr,
4170                         (void **)&adev->gfx.rlc.cp_table_ptr);
4171 }
4172
4173 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4174 {
4175         const struct cs_section_def *cs_data;
4176         int r;
4177
4178         adev->gfx.rlc.cs_data = gfx10_cs_data;
4179
4180         cs_data = adev->gfx.rlc.cs_data;
4181
4182         if (cs_data) {
4183                 /* init clear state block */
4184                 r = amdgpu_gfx_rlc_init_csb(adev);
4185                 if (r)
4186                         return r;
4187         }
4188
4189         /* init spm vmid with 0xf */
4190         if (adev->gfx.rlc.funcs->update_spm_vmid)
4191                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4192
4193         return 0;
4194 }
4195
4196 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4197 {
4198         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4199         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4200 }
4201
4202 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4203 {
4204         int r;
4205
4206         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4207
4208         amdgpu_gfx_graphics_queue_acquire(adev);
4209
4210         r = gfx_v10_0_init_microcode(adev);
4211         if (r)
4212                 DRM_ERROR("Failed to load gfx firmware!\n");
4213
4214         return r;
4215 }
4216
4217 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4218 {
4219         int r;
4220         u32 *hpd;
4221         const __le32 *fw_data = NULL;
4222         unsigned fw_size;
4223         u32 *fw = NULL;
4224         size_t mec_hpd_size;
4225
4226         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4227
4228         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4229
4230         /* take ownership of the relevant compute queues */
4231         amdgpu_gfx_compute_queue_acquire(adev);
4232         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4233
4234         if (mec_hpd_size) {
4235                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4236                                               AMDGPU_GEM_DOMAIN_GTT,
4237                                               &adev->gfx.mec.hpd_eop_obj,
4238                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4239                                               (void **)&hpd);
4240                 if (r) {
4241                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4242                         gfx_v10_0_mec_fini(adev);
4243                         return r;
4244                 }
4245
4246                 memset(hpd, 0, mec_hpd_size);
4247
4248                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4249                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4250         }
4251
4252         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4253                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4254
4255                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4256                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4257                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4258
4259                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4260                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4261                                               &adev->gfx.mec.mec_fw_obj,
4262                                               &adev->gfx.mec.mec_fw_gpu_addr,
4263                                               (void **)&fw);
4264                 if (r) {
4265                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4266                         gfx_v10_0_mec_fini(adev);
4267                         return r;
4268                 }
4269
4270                 memcpy(fw, fw_data, fw_size);
4271
4272                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4273                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4274         }
4275
4276         return 0;
4277 }
4278
4279 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4280 {
4281         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4282                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4283                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4284         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4285 }
4286
4287 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4288                            uint32_t thread, uint32_t regno,
4289                            uint32_t num, uint32_t *out)
4290 {
4291         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4292                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4293                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4294                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4295                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4296         while (num--)
4297                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4298 }
4299
4300 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4301 {
4302         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4303          * field when performing a select_se_sh so it should be
4304          * zero here */
4305         WARN_ON(simd != 0);
4306
4307         /* type 2 wave data */
4308         dst[(*no_fields)++] = 2;
4309         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4310         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4311         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4312         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4313         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4314         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4315         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4316         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4317         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4318         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4319         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4320         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4321         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4322         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4323         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4324 }
4325
4326 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4327                                      uint32_t wave, uint32_t start,
4328                                      uint32_t size, uint32_t *dst)
4329 {
4330         WARN_ON(simd != 0);
4331
4332         wave_read_regs(
4333                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4334                 dst);
4335 }
4336
4337 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4338                                       uint32_t wave, uint32_t thread,
4339                                       uint32_t start, uint32_t size,
4340                                       uint32_t *dst)
4341 {
4342         wave_read_regs(
4343                 adev, wave, thread,
4344                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4345 }
4346
4347 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4348                                        u32 me, u32 pipe, u32 q, u32 vm)
4349 {
4350         nv_grbm_select(adev, me, pipe, q, vm);
4351 }
4352
4353 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4354                                           bool enable)
4355 {
4356         uint32_t data, def;
4357
4358         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4359
4360         if (enable)
4361                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4362         else
4363                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4364
4365         if (data != def)
4366                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4367 }
4368
4369 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4370         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4371         .select_se_sh = &gfx_v10_0_select_se_sh,
4372         .read_wave_data = &gfx_v10_0_read_wave_data,
4373         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4374         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4375         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4376         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4377         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4378 };
4379
4380 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4381 {
4382         u32 gb_addr_config;
4383
4384         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4385
4386         switch (adev->asic_type) {
4387         case CHIP_NAVI10:
4388         case CHIP_NAVI14:
4389         case CHIP_NAVI12:
4390                 adev->gfx.config.max_hw_contexts = 8;
4391                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4392                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4393                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4394                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4395                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4396                 break;
4397         case CHIP_SIENNA_CICHLID:
4398         case CHIP_NAVY_FLOUNDER:
4399         case CHIP_VANGOGH:
4400         case CHIP_DIMGREY_CAVEFISH:
4401                 adev->gfx.config.max_hw_contexts = 8;
4402                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4403                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4404                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4405                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4406                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4407                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4408                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4409                 break;
4410         default:
4411                 BUG();
4412                 break;
4413         }
4414
4415         adev->gfx.config.gb_addr_config = gb_addr_config;
4416
4417         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4418                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4419                                       GB_ADDR_CONFIG, NUM_PIPES);
4420
4421         adev->gfx.config.max_tile_pipes =
4422                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4423
4424         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4425                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4426                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4427         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4428                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4429                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4430         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4431                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4432                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4433         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4434                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4435                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4436 }
4437
4438 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4439                                    int me, int pipe, int queue)
4440 {
4441         int r;
4442         struct amdgpu_ring *ring;
4443         unsigned int irq_type;
4444
4445         ring = &adev->gfx.gfx_ring[ring_id];
4446
4447         ring->me = me;
4448         ring->pipe = pipe;
4449         ring->queue = queue;
4450
4451         ring->ring_obj = NULL;
4452         ring->use_doorbell = true;
4453
4454         if (!ring_id)
4455                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4456         else
4457                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4458         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4459
4460         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4461         r = amdgpu_ring_init(adev, ring, 1024,
4462                              &adev->gfx.eop_irq, irq_type,
4463                              AMDGPU_RING_PRIO_DEFAULT);
4464         if (r)
4465                 return r;
4466         return 0;
4467 }
4468
4469 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4470                                        int mec, int pipe, int queue)
4471 {
4472         int r;
4473         unsigned irq_type;
4474         struct amdgpu_ring *ring;
4475         unsigned int hw_prio;
4476
4477         ring = &adev->gfx.compute_ring[ring_id];
4478
4479         /* mec0 is me1 */
4480         ring->me = mec + 1;
4481         ring->pipe = pipe;
4482         ring->queue = queue;
4483
4484         ring->ring_obj = NULL;
4485         ring->use_doorbell = true;
4486         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4487         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4488                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4489         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4490
4491         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4492                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4493                 + ring->pipe;
4494         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
4495                                                             ring->queue) ?
4496                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4497         /* type-2 packets are deprecated on MEC, use type-3 instead */
4498         r = amdgpu_ring_init(adev, ring, 1024,
4499                              &adev->gfx.eop_irq, irq_type, hw_prio);
4500         if (r)
4501                 return r;
4502
4503         return 0;
4504 }
4505
4506 static int gfx_v10_0_sw_init(void *handle)
4507 {
4508         int i, j, k, r, ring_id = 0;
4509         struct amdgpu_kiq *kiq;
4510         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4511
4512         switch (adev->asic_type) {
4513         case CHIP_NAVI10:
4514         case CHIP_NAVI14:
4515         case CHIP_NAVI12:
4516                 adev->gfx.me.num_me = 1;
4517                 adev->gfx.me.num_pipe_per_me = 1;
4518                 adev->gfx.me.num_queue_per_pipe = 1;
4519                 adev->gfx.mec.num_mec = 2;
4520                 adev->gfx.mec.num_pipe_per_mec = 4;
4521                 adev->gfx.mec.num_queue_per_pipe = 8;
4522                 break;
4523         case CHIP_SIENNA_CICHLID:
4524         case CHIP_NAVY_FLOUNDER:
4525         case CHIP_VANGOGH:
4526         case CHIP_DIMGREY_CAVEFISH:
4527                 adev->gfx.me.num_me = 1;
4528                 adev->gfx.me.num_pipe_per_me = 1;
4529                 adev->gfx.me.num_queue_per_pipe = 1;
4530                 adev->gfx.mec.num_mec = 2;
4531                 adev->gfx.mec.num_pipe_per_mec = 4;
4532                 adev->gfx.mec.num_queue_per_pipe = 4;
4533                 break;
4534         default:
4535                 adev->gfx.me.num_me = 1;
4536                 adev->gfx.me.num_pipe_per_me = 1;
4537                 adev->gfx.me.num_queue_per_pipe = 1;
4538                 adev->gfx.mec.num_mec = 1;
4539                 adev->gfx.mec.num_pipe_per_mec = 4;
4540                 adev->gfx.mec.num_queue_per_pipe = 8;
4541                 break;
4542         }
4543
4544         /* KIQ event */
4545         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4546                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4547                               &adev->gfx.kiq.irq);
4548         if (r)
4549                 return r;
4550
4551         /* EOP Event */
4552         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4553                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4554                               &adev->gfx.eop_irq);
4555         if (r)
4556                 return r;
4557
4558         /* Privileged reg */
4559         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4560                               &adev->gfx.priv_reg_irq);
4561         if (r)
4562                 return r;
4563
4564         /* Privileged inst */
4565         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4566                               &adev->gfx.priv_inst_irq);
4567         if (r)
4568                 return r;
4569
4570         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4571
4572         gfx_v10_0_scratch_init(adev);
4573
4574         r = gfx_v10_0_me_init(adev);
4575         if (r)
4576                 return r;
4577
4578         r = gfx_v10_0_rlc_init(adev);
4579         if (r) {
4580                 DRM_ERROR("Failed to init rlc BOs!\n");
4581                 return r;
4582         }
4583
4584         r = gfx_v10_0_mec_init(adev);
4585         if (r) {
4586                 DRM_ERROR("Failed to init MEC BOs!\n");
4587                 return r;
4588         }
4589
4590         /* set up the gfx ring */
4591         for (i = 0; i < adev->gfx.me.num_me; i++) {
4592                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4593                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4594                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4595                                         continue;
4596
4597                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4598                                                             i, k, j);
4599                                 if (r)
4600                                         return r;
4601                                 ring_id++;
4602                         }
4603                 }
4604         }
4605
4606         ring_id = 0;
4607         /* set up the compute queues - allocate horizontally across pipes */
4608         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4609                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4610                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4611                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4612                                                                      j))
4613                                         continue;
4614
4615                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4616                                                                 i, k, j);
4617                                 if (r)
4618                                         return r;
4619
4620                                 ring_id++;
4621                         }
4622                 }
4623         }
4624
4625         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4626         if (r) {
4627                 DRM_ERROR("Failed to init KIQ BOs!\n");
4628                 return r;
4629         }
4630
4631         kiq = &adev->gfx.kiq;
4632         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4633         if (r)
4634                 return r;
4635
4636         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4637         if (r)
4638                 return r;
4639
4640         /* allocate visible FB for rlc auto-loading fw */
4641         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4642                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4643                 if (r)
4644                         return r;
4645         }
4646
4647         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4648
4649         gfx_v10_0_gpu_early_init(adev);
4650
4651         return 0;
4652 }
4653
4654 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4655 {
4656         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4657                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4658                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4659 }
4660
4661 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4662 {
4663         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4664                               &adev->gfx.ce.ce_fw_gpu_addr,
4665                               (void **)&adev->gfx.ce.ce_fw_ptr);
4666 }
4667
4668 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4669 {
4670         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4671                               &adev->gfx.me.me_fw_gpu_addr,
4672                               (void **)&adev->gfx.me.me_fw_ptr);
4673 }
4674
4675 static int gfx_v10_0_sw_fini(void *handle)
4676 {
4677         int i;
4678         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4679
4680         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4681                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4682         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4683                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4684
4685         amdgpu_gfx_mqd_sw_fini(adev);
4686         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4687         amdgpu_gfx_kiq_fini(adev);
4688
4689         gfx_v10_0_pfp_fini(adev);
4690         gfx_v10_0_ce_fini(adev);
4691         gfx_v10_0_me_fini(adev);
4692         gfx_v10_0_rlc_fini(adev);
4693         gfx_v10_0_mec_fini(adev);
4694
4695         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4696                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4697
4698         gfx_v10_0_free_microcode(adev);
4699
4700         return 0;
4701 }
4702
4703 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4704                                    u32 sh_num, u32 instance)
4705 {
4706         u32 data;
4707
4708         if (instance == 0xffffffff)
4709                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4710                                      INSTANCE_BROADCAST_WRITES, 1);
4711         else
4712                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4713                                      instance);
4714
4715         if (se_num == 0xffffffff)
4716                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4717                                      1);
4718         else
4719                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4720
4721         if (sh_num == 0xffffffff)
4722                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4723                                      1);
4724         else
4725                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4726
4727         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4728 }
4729
4730 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4731 {
4732         u32 data, mask;
4733
4734         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4735         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4736
4737         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4738         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4739
4740         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4741                                          adev->gfx.config.max_sh_per_se);
4742
4743         return (~data) & mask;
4744 }
4745
4746 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4747 {
4748         int i, j;
4749         u32 data;
4750         u32 active_rbs = 0;
4751         u32 bitmap;
4752         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4753                                         adev->gfx.config.max_sh_per_se;
4754
4755         mutex_lock(&adev->grbm_idx_mutex);
4756         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4757                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4758                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4759                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
4760                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4761                                 continue;
4762                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4763                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4764                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4765                                                rb_bitmap_width_per_sh);
4766                 }
4767         }
4768         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4769         mutex_unlock(&adev->grbm_idx_mutex);
4770
4771         adev->gfx.config.backend_enable_mask = active_rbs;
4772         adev->gfx.config.num_rbs = hweight32(active_rbs);
4773 }
4774
4775 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4776 {
4777         uint32_t num_sc;
4778         uint32_t enabled_rb_per_sh;
4779         uint32_t active_rb_bitmap;
4780         uint32_t num_rb_per_sc;
4781         uint32_t num_packer_per_sc;
4782         uint32_t pa_sc_tile_steering_override;
4783
4784         /* for ASICs that integrates GFX v10.3
4785          * pa_sc_tile_steering_override should be set to 0 */
4786         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
4787                 return 0;
4788
4789         /* init num_sc */
4790         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4791                         adev->gfx.config.num_sc_per_sh;
4792         /* init num_rb_per_sc */
4793         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4794         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4795         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4796         /* init num_packer_per_sc */
4797         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4798
4799         pa_sc_tile_steering_override = 0;
4800         pa_sc_tile_steering_override |=
4801                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4802                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4803         pa_sc_tile_steering_override |=
4804                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4805                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4806         pa_sc_tile_steering_override |=
4807                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4808                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4809
4810         return pa_sc_tile_steering_override;
4811 }
4812
4813 #define DEFAULT_SH_MEM_BASES    (0x6000)
4814
4815 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4816 {
4817         int i;
4818         uint32_t sh_mem_bases;
4819
4820         /*
4821          * Configure apertures:
4822          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4823          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4824          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4825          */
4826         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4827
4828         mutex_lock(&adev->srbm_mutex);
4829         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4830                 nv_grbm_select(adev, 0, 0, 0, i);
4831                 /* CP and shaders */
4832                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4833                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4834         }
4835         nv_grbm_select(adev, 0, 0, 0, 0);
4836         mutex_unlock(&adev->srbm_mutex);
4837
4838         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4839            acccess. These should be enabled by FW for target VMIDs. */
4840         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4841                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4842                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4843                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4844                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4845         }
4846 }
4847
4848 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4849 {
4850         int vmid;
4851
4852         /*
4853          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4854          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4855          * the driver can enable them for graphics. VMID0 should maintain
4856          * access so that HWS firmware can save/restore entries.
4857          */
4858         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
4859                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4860                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4861                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4862                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4863         }
4864 }
4865
4866
4867 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4868 {
4869         int i, j, k;
4870         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4871         u32 tmp, wgp_active_bitmap = 0;
4872         u32 gcrd_targets_disable_tcp = 0;
4873         u32 utcl_invreq_disable = 0;
4874         /*
4875          * GCRD_TARGETS_DISABLE field contains
4876          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4877          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4878          */
4879         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4880                 2 * max_wgp_per_sh + /* TCP */
4881                 max_wgp_per_sh + /* SQC */
4882                 4); /* GL1C */
4883         /*
4884          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4885          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4886          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4887          */
4888         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4889                 2 * max_wgp_per_sh + /* TCP */
4890                 2 * max_wgp_per_sh + /* SQC */
4891                 4 + /* RMI */
4892                 1); /* SQG */
4893
4894         if (adev->asic_type == CHIP_NAVI10 ||
4895             adev->asic_type == CHIP_NAVI14 ||
4896             adev->asic_type == CHIP_NAVI12) {
4897                 mutex_lock(&adev->grbm_idx_mutex);
4898                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4899                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4900                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4901                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4902                                 /*
4903                                  * Set corresponding TCP bits for the inactive WGPs in
4904                                  * GCRD_SA_TARGETS_DISABLE
4905                                  */
4906                                 gcrd_targets_disable_tcp = 0;
4907                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4908                                 utcl_invreq_disable = 0;
4909
4910                                 for (k = 0; k < max_wgp_per_sh; k++) {
4911                                         if (!(wgp_active_bitmap & (1 << k))) {
4912                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
4913                                                 utcl_invreq_disable |= (3 << (2 * k)) |
4914                                                         (3 << (2 * (max_wgp_per_sh + k)));
4915                                         }
4916                                 }
4917
4918                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4919                                 /* only override TCP & SQC bits */
4920                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4921                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4922                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4923
4924                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4925                                 /* only override TCP bits */
4926                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4927                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4928                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4929                         }
4930                 }
4931
4932                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4933                 mutex_unlock(&adev->grbm_idx_mutex);
4934         }
4935 }
4936
4937 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4938 {
4939         /* TCCs are global (not instanced). */
4940         uint32_t tcc_disable;
4941
4942         switch (adev->asic_type) {
4943         case CHIP_VANGOGH:
4944                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_Vangogh) |
4945                                 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_Vangogh);
4946                 break;
4947         default:
4948                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4949                                 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4950                 break;
4951         }
4952
4953         adev->gfx.config.tcc_disabled_mask =
4954                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4955                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4956 }
4957
4958 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4959 {
4960         u32 tmp;
4961         int i;
4962
4963         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4964
4965         gfx_v10_0_setup_rb(adev);
4966         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4967         gfx_v10_0_get_tcc_info(adev);
4968         adev->gfx.config.pa_sc_tile_steering_override =
4969                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4970
4971         /* XXX SH_MEM regs */
4972         /* where to put LDS, scratch, GPUVM in FSA64 space */
4973         mutex_lock(&adev->srbm_mutex);
4974         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4975                 nv_grbm_select(adev, 0, 0, 0, i);
4976                 /* CP and shaders */
4977                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4978                 if (i != 0) {
4979                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4980                                 (adev->gmc.private_aperture_start >> 48));
4981                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4982                                 (adev->gmc.shared_aperture_start >> 48));
4983                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4984                 }
4985         }
4986         nv_grbm_select(adev, 0, 0, 0, 0);
4987
4988         mutex_unlock(&adev->srbm_mutex);
4989
4990         gfx_v10_0_init_compute_vmid(adev);
4991         gfx_v10_0_init_gds_vmid(adev);
4992
4993 }
4994
4995 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4996                                                bool enable)
4997 {
4998         u32 tmp;
4999
5000         if (amdgpu_sriov_vf(adev))
5001                 return;
5002
5003         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5004
5005         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5006                             enable ? 1 : 0);
5007         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5008                             enable ? 1 : 0);
5009         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5010                             enable ? 1 : 0);
5011         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5012                             enable ? 1 : 0);
5013
5014         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5015 }
5016
5017 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5018 {
5019         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5020
5021         /* csib */
5022         if (adev->asic_type == CHIP_NAVI12) {
5023                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5024                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5025                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5026                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5027                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5028         } else {
5029                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5030                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5031                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5032                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5033                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5034         }
5035         return 0;
5036 }
5037
5038 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5039 {
5040         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5041
5042         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5043         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5044 }
5045
5046 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5047 {
5048         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5049         udelay(50);
5050         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5051         udelay(50);
5052 }
5053
5054 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5055                                              bool enable)
5056 {
5057         uint32_t rlc_pg_cntl;
5058
5059         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5060
5061         if (!enable) {
5062                 /* RLC_PG_CNTL[23] = 0 (default)
5063                  * RLC will wait for handshake acks with SMU
5064                  * GFXOFF will be enabled
5065                  * RLC_PG_CNTL[23] = 1
5066                  * RLC will not issue any message to SMU
5067                  * hence no handshake between SMU & RLC
5068                  * GFXOFF will be disabled
5069                  */
5070                 rlc_pg_cntl |= 0x800000;
5071         } else
5072                 rlc_pg_cntl &= ~0x800000;
5073         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5074 }
5075
5076 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5077 {
5078         /* TODO: enable rlc & smu handshake until smu
5079          * and gfxoff feature works as expected */
5080         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5081                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5082
5083         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5084         udelay(50);
5085 }
5086
5087 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5088 {
5089         uint32_t tmp;
5090
5091         /* enable Save Restore Machine */
5092         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
5093         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5094         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5095         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
5096 }
5097
5098 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5099 {
5100         const struct rlc_firmware_header_v2_0 *hdr;
5101         const __le32 *fw_data;
5102         unsigned i, fw_size;
5103
5104         if (!adev->gfx.rlc_fw)
5105                 return -EINVAL;
5106
5107         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5108         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5109
5110         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5111                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5112         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5113
5114         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5115                      RLCG_UCODE_LOADING_START_ADDRESS);
5116
5117         for (i = 0; i < fw_size; i++)
5118                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5119                              le32_to_cpup(fw_data++));
5120
5121         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5122
5123         return 0;
5124 }
5125
5126 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5127 {
5128         int r;
5129
5130         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
5131
5132                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5133                 if (r)
5134                         return r;
5135
5136                 gfx_v10_0_init_csb(adev);
5137
5138                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5139                         gfx_v10_0_rlc_enable_srm(adev);
5140         } else {
5141                 if (amdgpu_sriov_vf(adev)) {
5142                         gfx_v10_0_init_csb(adev);
5143                         return 0;
5144                 }
5145
5146                 adev->gfx.rlc.funcs->stop(adev);
5147
5148                 /* disable CG */
5149                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5150
5151                 /* disable PG */
5152                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5153
5154                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5155                         /* legacy rlc firmware loading */
5156                         r = gfx_v10_0_rlc_load_microcode(adev);
5157                         if (r)
5158                                 return r;
5159                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5160                         /* rlc backdoor autoload firmware */
5161                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5162                         if (r)
5163                                 return r;
5164                 }
5165
5166                 gfx_v10_0_init_csb(adev);
5167
5168                 adev->gfx.rlc.funcs->start(adev);
5169
5170                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5171                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5172                         if (r)
5173                                 return r;
5174                 }
5175         }
5176         return 0;
5177 }
5178
5179 static struct {
5180         FIRMWARE_ID     id;
5181         unsigned int    offset;
5182         unsigned int    size;
5183 } rlc_autoload_info[FIRMWARE_ID_MAX];
5184
5185 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5186 {
5187         int ret;
5188         RLC_TABLE_OF_CONTENT *rlc_toc;
5189
5190         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5191                                         AMDGPU_GEM_DOMAIN_GTT,
5192                                         &adev->gfx.rlc.rlc_toc_bo,
5193                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5194                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5195         if (ret) {
5196                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5197                 return ret;
5198         }
5199
5200         /* Copy toc from psp sos fw to rlc toc buffer */
5201         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5202
5203         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5204         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5205                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5206                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5207                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5208                         /* Offset needs 4KB alignment */
5209                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5210                 }
5211
5212                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5213                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5214                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5215
5216                 rlc_toc++;
5217         }
5218
5219         return 0;
5220 }
5221
5222 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5223 {
5224         uint32_t total_size = 0;
5225         FIRMWARE_ID id;
5226         int ret;
5227
5228         ret = gfx_v10_0_parse_rlc_toc(adev);
5229         if (ret) {
5230                 dev_err(adev->dev, "failed to parse rlc toc\n");
5231                 return 0;
5232         }
5233
5234         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5235                 total_size += rlc_autoload_info[id].size;
5236
5237         /* In case the offset in rlc toc ucode is aligned */
5238         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5239                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5240                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5241
5242         return total_size;
5243 }
5244
5245 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5246 {
5247         int r;
5248         uint32_t total_size;
5249
5250         total_size = gfx_v10_0_calc_toc_total_size(adev);
5251
5252         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5253                                       AMDGPU_GEM_DOMAIN_GTT,
5254                                       &adev->gfx.rlc.rlc_autoload_bo,
5255                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5256                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5257         if (r) {
5258                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5259                 return r;
5260         }
5261
5262         return 0;
5263 }
5264
5265 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5266 {
5267         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5268                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5269                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5270         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5271                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5272                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5273 }
5274
5275 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5276                                                        FIRMWARE_ID id,
5277                                                        const void *fw_data,
5278                                                        uint32_t fw_size)
5279 {
5280         uint32_t toc_offset;
5281         uint32_t toc_fw_size;
5282         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5283
5284         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5285                 return;
5286
5287         toc_offset = rlc_autoload_info[id].offset;
5288         toc_fw_size = rlc_autoload_info[id].size;
5289
5290         if (fw_size == 0)
5291                 fw_size = toc_fw_size;
5292
5293         if (fw_size > toc_fw_size)
5294                 fw_size = toc_fw_size;
5295
5296         memcpy(ptr + toc_offset, fw_data, fw_size);
5297
5298         if (fw_size < toc_fw_size)
5299                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5300 }
5301
5302 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5303 {
5304         void *data;
5305         uint32_t size;
5306
5307         data = adev->gfx.rlc.rlc_toc_buf;
5308         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5309
5310         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5311                                                    FIRMWARE_ID_RLC_TOC,
5312                                                    data, size);
5313 }
5314
5315 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5316 {
5317         const __le32 *fw_data;
5318         uint32_t fw_size;
5319         const struct gfx_firmware_header_v1_0 *cp_hdr;
5320         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5321
5322         /* pfp ucode */
5323         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5324                 adev->gfx.pfp_fw->data;
5325         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5326                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5327         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5328         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5329                                                    FIRMWARE_ID_CP_PFP,
5330                                                    fw_data, fw_size);
5331
5332         /* ce ucode */
5333         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5334                 adev->gfx.ce_fw->data;
5335         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5336                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5337         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5338         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5339                                                    FIRMWARE_ID_CP_CE,
5340                                                    fw_data, fw_size);
5341
5342         /* me ucode */
5343         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5344                 adev->gfx.me_fw->data;
5345         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5346                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5347         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5348         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5349                                                    FIRMWARE_ID_CP_ME,
5350                                                    fw_data, fw_size);
5351
5352         /* rlc ucode */
5353         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5354                 adev->gfx.rlc_fw->data;
5355         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5356                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5357         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5358         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5359                                                    FIRMWARE_ID_RLC_G_UCODE,
5360                                                    fw_data, fw_size);
5361
5362         /* mec1 ucode */
5363         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5364                 adev->gfx.mec_fw->data;
5365         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5366                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5367         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5368                 cp_hdr->jt_size * 4;
5369         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5370                                                    FIRMWARE_ID_CP_MEC,
5371                                                    fw_data, fw_size);
5372         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5373 }
5374
5375 /* Temporarily put sdma part here */
5376 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5377 {
5378         const __le32 *fw_data;
5379         uint32_t fw_size;
5380         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5381         int i;
5382
5383         for (i = 0; i < adev->sdma.num_instances; i++) {
5384                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5385                         adev->sdma.instance[i].fw->data;
5386                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5387                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5388                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5389
5390                 if (i == 0) {
5391                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5392                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5393                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5394                                 FIRMWARE_ID_SDMA0_JT,
5395                                 (uint32_t *)fw_data +
5396                                 sdma_hdr->jt_offset,
5397                                 sdma_hdr->jt_size * 4);
5398                 } else if (i == 1) {
5399                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5400                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5401                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5402                                 FIRMWARE_ID_SDMA1_JT,
5403                                 (uint32_t *)fw_data +
5404                                 sdma_hdr->jt_offset,
5405                                 sdma_hdr->jt_size * 4);
5406                 }
5407         }
5408 }
5409
5410 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5411 {
5412         uint32_t rlc_g_offset, rlc_g_size, tmp;
5413         uint64_t gpu_addr;
5414
5415         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5416         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5417         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5418
5419         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5420         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5421         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5422
5423         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5424         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5425         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5426
5427         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5428         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5429                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5430                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5431                 return -EINVAL;
5432         }
5433
5434         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5435         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5436                 DRM_ERROR("RLC ROM should halt itself\n");
5437                 return -EINVAL;
5438         }
5439
5440         return 0;
5441 }
5442
5443 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5444 {
5445         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5446         uint32_t tmp;
5447         int i;
5448         uint64_t addr;
5449
5450         /* Trigger an invalidation of the L1 instruction caches */
5451         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5452         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5453         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5454
5455         /* Wait for invalidation complete */
5456         for (i = 0; i < usec_timeout; i++) {
5457                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5458                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5459                         INVALIDATE_CACHE_COMPLETE))
5460                         break;
5461                 udelay(1);
5462         }
5463
5464         if (i >= usec_timeout) {
5465                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5466                 return -EINVAL;
5467         }
5468
5469         /* Program me ucode address into intruction cache address register */
5470         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5471                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5472         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5473                         lower_32_bits(addr) & 0xFFFFF000);
5474         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5475                         upper_32_bits(addr));
5476
5477         return 0;
5478 }
5479
5480 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5481 {
5482         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5483         uint32_t tmp;
5484         int i;
5485         uint64_t addr;
5486
5487         /* Trigger an invalidation of the L1 instruction caches */
5488         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5489         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5490         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5491
5492         /* Wait for invalidation complete */
5493         for (i = 0; i < usec_timeout; i++) {
5494                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5495                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5496                         INVALIDATE_CACHE_COMPLETE))
5497                         break;
5498                 udelay(1);
5499         }
5500
5501         if (i >= usec_timeout) {
5502                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5503                 return -EINVAL;
5504         }
5505
5506         /* Program ce ucode address into intruction cache address register */
5507         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5508                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5509         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5510                         lower_32_bits(addr) & 0xFFFFF000);
5511         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5512                         upper_32_bits(addr));
5513
5514         return 0;
5515 }
5516
5517 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5518 {
5519         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5520         uint32_t tmp;
5521         int i;
5522         uint64_t addr;
5523
5524         /* Trigger an invalidation of the L1 instruction caches */
5525         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5526         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5527         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5528
5529         /* Wait for invalidation complete */
5530         for (i = 0; i < usec_timeout; i++) {
5531                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5532                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5533                         INVALIDATE_CACHE_COMPLETE))
5534                         break;
5535                 udelay(1);
5536         }
5537
5538         if (i >= usec_timeout) {
5539                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5540                 return -EINVAL;
5541         }
5542
5543         /* Program pfp ucode address into intruction cache address register */
5544         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5545                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5546         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5547                         lower_32_bits(addr) & 0xFFFFF000);
5548         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5549                         upper_32_bits(addr));
5550
5551         return 0;
5552 }
5553
5554 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5555 {
5556         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5557         uint32_t tmp;
5558         int i;
5559         uint64_t addr;
5560
5561         /* Trigger an invalidation of the L1 instruction caches */
5562         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5563         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5564         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5565
5566         /* Wait for invalidation complete */
5567         for (i = 0; i < usec_timeout; i++) {
5568                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5569                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5570                         INVALIDATE_CACHE_COMPLETE))
5571                         break;
5572                 udelay(1);
5573         }
5574
5575         if (i >= usec_timeout) {
5576                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5577                 return -EINVAL;
5578         }
5579
5580         /* Program mec1 ucode address into intruction cache address register */
5581         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5582                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5583         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5584                         lower_32_bits(addr) & 0xFFFFF000);
5585         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5586                         upper_32_bits(addr));
5587
5588         return 0;
5589 }
5590
5591 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5592 {
5593         uint32_t cp_status;
5594         uint32_t bootload_status;
5595         int i, r;
5596
5597         for (i = 0; i < adev->usec_timeout; i++) {
5598                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5599                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5600                 if ((cp_status == 0) &&
5601                     (REG_GET_FIELD(bootload_status,
5602                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5603                         break;
5604                 }
5605                 udelay(1);
5606         }
5607
5608         if (i >= adev->usec_timeout) {
5609                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5610                 return -ETIMEDOUT;
5611         }
5612
5613         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5614                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5615                 if (r)
5616                         return r;
5617
5618                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5619                 if (r)
5620                         return r;
5621
5622                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5623                 if (r)
5624                         return r;
5625
5626                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5627                 if (r)
5628                         return r;
5629         }
5630
5631         return 0;
5632 }
5633
5634 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5635 {
5636         int i;
5637         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5638
5639         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5640         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5641         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5642
5643         if (adev->asic_type == CHIP_NAVI12) {
5644                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5645         } else {
5646                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5647         }
5648
5649         for (i = 0; i < adev->usec_timeout; i++) {
5650                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5651                         break;
5652                 udelay(1);
5653         }
5654
5655         if (i >= adev->usec_timeout)
5656                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5657
5658         return 0;
5659 }
5660
5661 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5662 {
5663         int r;
5664         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5665         const __le32 *fw_data;
5666         unsigned i, fw_size;
5667         uint32_t tmp;
5668         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5669
5670         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5671                 adev->gfx.pfp_fw->data;
5672
5673         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5674
5675         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5676                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5677         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5678
5679         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5680                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5681                                       &adev->gfx.pfp.pfp_fw_obj,
5682                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5683                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5684         if (r) {
5685                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5686                 gfx_v10_0_pfp_fini(adev);
5687                 return r;
5688         }
5689
5690         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5691
5692         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5693         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5694
5695         /* Trigger an invalidation of the L1 instruction caches */
5696         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5697         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5698         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5699
5700         /* Wait for invalidation complete */
5701         for (i = 0; i < usec_timeout; i++) {
5702                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5703                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5704                         INVALIDATE_CACHE_COMPLETE))
5705                         break;
5706                 udelay(1);
5707         }
5708
5709         if (i >= usec_timeout) {
5710                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5711                 return -EINVAL;
5712         }
5713
5714         if (amdgpu_emu_mode == 1)
5715                 adev->hdp.funcs->flush_hdp(adev, NULL);
5716
5717         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5718         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5719         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5720         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5721         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5722         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5723         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5724                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5725         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5726                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5727
5728         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5729
5730         for (i = 0; i < pfp_hdr->jt_size; i++)
5731                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5732                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5733
5734         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5735
5736         return 0;
5737 }
5738
5739 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5740 {
5741         int r;
5742         const struct gfx_firmware_header_v1_0 *ce_hdr;
5743         const __le32 *fw_data;
5744         unsigned i, fw_size;
5745         uint32_t tmp;
5746         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5747
5748         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5749                 adev->gfx.ce_fw->data;
5750
5751         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5752
5753         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5754                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5755         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5756
5757         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5758                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5759                                       &adev->gfx.ce.ce_fw_obj,
5760                                       &adev->gfx.ce.ce_fw_gpu_addr,
5761                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5762         if (r) {
5763                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5764                 gfx_v10_0_ce_fini(adev);
5765                 return r;
5766         }
5767
5768         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5769
5770         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5771         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5772
5773         /* Trigger an invalidation of the L1 instruction caches */
5774         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5775         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5776         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5777
5778         /* Wait for invalidation complete */
5779         for (i = 0; i < usec_timeout; i++) {
5780                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5781                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5782                         INVALIDATE_CACHE_COMPLETE))
5783                         break;
5784                 udelay(1);
5785         }
5786
5787         if (i >= usec_timeout) {
5788                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5789                 return -EINVAL;
5790         }
5791
5792         if (amdgpu_emu_mode == 1)
5793                 adev->hdp.funcs->flush_hdp(adev, NULL);
5794
5795         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5796         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5797         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5798         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5799         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5800         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5801                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5802         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5803                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5804
5805         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5806
5807         for (i = 0; i < ce_hdr->jt_size; i++)
5808                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5809                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5810
5811         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5812
5813         return 0;
5814 }
5815
5816 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5817 {
5818         int r;
5819         const struct gfx_firmware_header_v1_0 *me_hdr;
5820         const __le32 *fw_data;
5821         unsigned i, fw_size;
5822         uint32_t tmp;
5823         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5824
5825         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5826                 adev->gfx.me_fw->data;
5827
5828         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5829
5830         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5831                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5832         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5833
5834         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5835                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5836                                       &adev->gfx.me.me_fw_obj,
5837                                       &adev->gfx.me.me_fw_gpu_addr,
5838                                       (void **)&adev->gfx.me.me_fw_ptr);
5839         if (r) {
5840                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5841                 gfx_v10_0_me_fini(adev);
5842                 return r;
5843         }
5844
5845         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5846
5847         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5848         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5849
5850         /* Trigger an invalidation of the L1 instruction caches */
5851         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5852         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5853         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5854
5855         /* Wait for invalidation complete */
5856         for (i = 0; i < usec_timeout; i++) {
5857                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5858                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5859                         INVALIDATE_CACHE_COMPLETE))
5860                         break;
5861                 udelay(1);
5862         }
5863
5864         if (i >= usec_timeout) {
5865                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5866                 return -EINVAL;
5867         }
5868
5869         if (amdgpu_emu_mode == 1)
5870                 adev->hdp.funcs->flush_hdp(adev, NULL);
5871
5872         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5873         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5874         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5875         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5876         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5877         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5878                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5879         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5880                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5881
5882         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5883
5884         for (i = 0; i < me_hdr->jt_size; i++)
5885                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5886                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5887
5888         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5889
5890         return 0;
5891 }
5892
5893 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5894 {
5895         int r;
5896
5897         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5898                 return -EINVAL;
5899
5900         gfx_v10_0_cp_gfx_enable(adev, false);
5901
5902         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5903         if (r) {
5904                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5905                 return r;
5906         }
5907
5908         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5909         if (r) {
5910                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5911                 return r;
5912         }
5913
5914         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5915         if (r) {
5916                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5917                 return r;
5918         }
5919
5920         return 0;
5921 }
5922
5923 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5924 {
5925         struct amdgpu_ring *ring;
5926         const struct cs_section_def *sect = NULL;
5927         const struct cs_extent_def *ext = NULL;
5928         int r, i;
5929         int ctx_reg_offset;
5930
5931         /* init the CP */
5932         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5933                      adev->gfx.config.max_hw_contexts - 1);
5934         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5935
5936         gfx_v10_0_cp_gfx_enable(adev, true);
5937
5938         ring = &adev->gfx.gfx_ring[0];
5939         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5940         if (r) {
5941                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5942                 return r;
5943         }
5944
5945         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5946         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5947
5948         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5949         amdgpu_ring_write(ring, 0x80000000);
5950         amdgpu_ring_write(ring, 0x80000000);
5951
5952         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5953                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5954                         if (sect->id == SECT_CONTEXT) {
5955                                 amdgpu_ring_write(ring,
5956                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5957                                                           ext->reg_count));
5958                                 amdgpu_ring_write(ring, ext->reg_index -
5959                                                   PACKET3_SET_CONTEXT_REG_START);
5960                                 for (i = 0; i < ext->reg_count; i++)
5961                                         amdgpu_ring_write(ring, ext->extent[i]);
5962                         }
5963                 }
5964         }
5965
5966         ctx_reg_offset =
5967                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5968         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5969         amdgpu_ring_write(ring, ctx_reg_offset);
5970         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5971
5972         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5973         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5974
5975         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5976         amdgpu_ring_write(ring, 0);
5977
5978         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5979         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5980         amdgpu_ring_write(ring, 0x8000);
5981         amdgpu_ring_write(ring, 0x8000);
5982
5983         amdgpu_ring_commit(ring);
5984
5985         /* submit cs packet to copy state 0 to next available state */
5986         if (adev->gfx.num_gfx_rings > 1) {
5987                 /* maximum supported gfx ring is 2 */
5988                 ring = &adev->gfx.gfx_ring[1];
5989                 r = amdgpu_ring_alloc(ring, 2);
5990                 if (r) {
5991                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5992                         return r;
5993                 }
5994
5995                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5996                 amdgpu_ring_write(ring, 0);
5997
5998                 amdgpu_ring_commit(ring);
5999         }
6000         return 0;
6001 }
6002
6003 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6004                                          CP_PIPE_ID pipe)
6005 {
6006         u32 tmp;
6007
6008         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6009         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6010
6011         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6012 }
6013
6014 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6015                                           struct amdgpu_ring *ring)
6016 {
6017         u32 tmp;
6018
6019         if (!amdgpu_async_gfx_ring) {
6020                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6021                 if (ring->use_doorbell) {
6022                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6023                                                 DOORBELL_OFFSET, ring->doorbell_index);
6024                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6025                                                 DOORBELL_EN, 1);
6026                 } else {
6027                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6028                                                 DOORBELL_EN, 0);
6029                 }
6030                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6031         }
6032         switch (adev->asic_type) {
6033         case CHIP_SIENNA_CICHLID:
6034         case CHIP_NAVY_FLOUNDER:
6035         case CHIP_VANGOGH:
6036         case CHIP_DIMGREY_CAVEFISH:
6037                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6038                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6039                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6040
6041                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6042                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6043                 break;
6044         default:
6045                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6046                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6047                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6048
6049                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6050                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6051                 break;
6052         }
6053 }
6054
6055 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6056 {
6057         struct amdgpu_ring *ring;
6058         u32 tmp;
6059         u32 rb_bufsz;
6060         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6061         u32 i;
6062
6063         /* Set the write pointer delay */
6064         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6065
6066         /* set the RB to use vmid 0 */
6067         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6068
6069         /* Init gfx ring 0 for pipe 0 */
6070         mutex_lock(&adev->srbm_mutex);
6071         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6072
6073         /* Set ring buffer size */
6074         ring = &adev->gfx.gfx_ring[0];
6075         rb_bufsz = order_base_2(ring->ring_size / 8);
6076         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6077         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6078 #ifdef __BIG_ENDIAN
6079         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6080 #endif
6081         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6082
6083         /* Initialize the ring buffer's write pointers */
6084         ring->wptr = 0;
6085         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6086         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6087
6088         /* set the wb address wether it's enabled or not */
6089         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6090         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6091         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6092                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6093
6094         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6095         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6096                      lower_32_bits(wptr_gpu_addr));
6097         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6098                      upper_32_bits(wptr_gpu_addr));
6099
6100         mdelay(1);
6101         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6102
6103         rb_addr = ring->gpu_addr >> 8;
6104         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6105         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6106
6107         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6108
6109         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6110         mutex_unlock(&adev->srbm_mutex);
6111
6112         /* Init gfx ring 1 for pipe 1 */
6113         if (adev->gfx.num_gfx_rings > 1) {
6114                 mutex_lock(&adev->srbm_mutex);
6115                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6116                 /* maximum supported gfx ring is 2 */
6117                 ring = &adev->gfx.gfx_ring[1];
6118                 rb_bufsz = order_base_2(ring->ring_size / 8);
6119                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6120                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6121                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6122                 /* Initialize the ring buffer's write pointers */
6123                 ring->wptr = 0;
6124                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6125                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6126                 /* Set the wb address wether it's enabled or not */
6127                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6128                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6129                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6130                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6131                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6132                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6133                              lower_32_bits(wptr_gpu_addr));
6134                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6135                              upper_32_bits(wptr_gpu_addr));
6136
6137                 mdelay(1);
6138                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6139
6140                 rb_addr = ring->gpu_addr >> 8;
6141                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6142                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6143                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6144
6145                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6146                 mutex_unlock(&adev->srbm_mutex);
6147         }
6148         /* Switch to pipe 0 */
6149         mutex_lock(&adev->srbm_mutex);
6150         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6151         mutex_unlock(&adev->srbm_mutex);
6152
6153         /* start the ring */
6154         gfx_v10_0_cp_gfx_start(adev);
6155
6156         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6157                 ring = &adev->gfx.gfx_ring[i];
6158                 ring->sched.ready = true;
6159         }
6160
6161         return 0;
6162 }
6163
6164 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6165 {
6166         if (enable) {
6167                 switch (adev->asic_type) {
6168                 case CHIP_SIENNA_CICHLID:
6169                 case CHIP_NAVY_FLOUNDER:
6170                 case CHIP_VANGOGH:
6171                 case CHIP_DIMGREY_CAVEFISH:
6172                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6173                         break;
6174                 default:
6175                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6176                         break;
6177                 }
6178         } else {
6179                 switch (adev->asic_type) {
6180                 case CHIP_SIENNA_CICHLID:
6181                 case CHIP_NAVY_FLOUNDER:
6182                 case CHIP_VANGOGH:
6183                 case CHIP_DIMGREY_CAVEFISH:
6184                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6185                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6186                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6187                         break;
6188                 default:
6189                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6190                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6191                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6192                         break;
6193                 }
6194                 adev->gfx.kiq.ring.sched.ready = false;
6195         }
6196         udelay(50);
6197 }
6198
6199 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6200 {
6201         const struct gfx_firmware_header_v1_0 *mec_hdr;
6202         const __le32 *fw_data;
6203         unsigned i;
6204         u32 tmp;
6205         u32 usec_timeout = 50000; /* Wait for 50 ms */
6206
6207         if (!adev->gfx.mec_fw)
6208                 return -EINVAL;
6209
6210         gfx_v10_0_cp_compute_enable(adev, false);
6211
6212         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6213         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6214
6215         fw_data = (const __le32 *)
6216                 (adev->gfx.mec_fw->data +
6217                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6218
6219         /* Trigger an invalidation of the L1 instruction caches */
6220         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6221         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6222         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6223
6224         /* Wait for invalidation complete */
6225         for (i = 0; i < usec_timeout; i++) {
6226                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6227                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6228                                        INVALIDATE_CACHE_COMPLETE))
6229                         break;
6230                 udelay(1);
6231         }
6232
6233         if (i >= usec_timeout) {
6234                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6235                 return -EINVAL;
6236         }
6237
6238         if (amdgpu_emu_mode == 1)
6239                 adev->hdp.funcs->flush_hdp(adev, NULL);
6240
6241         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6242         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6243         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6244         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6245         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6246
6247         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6248                      0xFFFFF000);
6249         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6250                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6251
6252         /* MEC1 */
6253         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6254
6255         for (i = 0; i < mec_hdr->jt_size; i++)
6256                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6257                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6258
6259         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6260
6261         /*
6262          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6263          * different microcode than MEC1.
6264          */
6265
6266         return 0;
6267 }
6268
6269 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6270 {
6271         uint32_t tmp;
6272         struct amdgpu_device *adev = ring->adev;
6273
6274         /* tell RLC which is KIQ queue */
6275         switch (adev->asic_type) {
6276         case CHIP_SIENNA_CICHLID:
6277         case CHIP_NAVY_FLOUNDER:
6278         case CHIP_VANGOGH:
6279         case CHIP_DIMGREY_CAVEFISH:
6280                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6281                 tmp &= 0xffffff00;
6282                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6283                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6284                 tmp |= 0x80;
6285                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6286                 break;
6287         default:
6288                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6289                 tmp &= 0xffffff00;
6290                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6291                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6292                 tmp |= 0x80;
6293                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6294                 break;
6295         }
6296 }
6297
6298 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6299 {
6300         struct amdgpu_device *adev = ring->adev;
6301         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6302         uint64_t hqd_gpu_addr, wb_gpu_addr;
6303         uint32_t tmp;
6304         uint32_t rb_bufsz;
6305
6306         /* set up gfx hqd wptr */
6307         mqd->cp_gfx_hqd_wptr = 0;
6308         mqd->cp_gfx_hqd_wptr_hi = 0;
6309
6310         /* set the pointer to the MQD */
6311         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6312         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6313
6314         /* set up mqd control */
6315         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6316         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6317         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6318         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6319         mqd->cp_gfx_mqd_control = tmp;
6320
6321         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6322         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6323         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6324         mqd->cp_gfx_hqd_vmid = 0;
6325
6326         /* set up default queue priority level
6327          * 0x0 = low priority, 0x1 = high priority */
6328         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6329         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6330         mqd->cp_gfx_hqd_queue_priority = tmp;
6331
6332         /* set up time quantum */
6333         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6334         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6335         mqd->cp_gfx_hqd_quantum = tmp;
6336
6337         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6338         hqd_gpu_addr = ring->gpu_addr >> 8;
6339         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6340         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6341
6342         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6343         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6344         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6345         mqd->cp_gfx_hqd_rptr_addr_hi =
6346                 upper_32_bits(wb_gpu_addr) & 0xffff;
6347
6348         /* set up rb_wptr_poll addr */
6349         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6350         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6351         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6352
6353         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6354         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6355         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6356         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6357         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6358 #ifdef __BIG_ENDIAN
6359         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6360 #endif
6361         mqd->cp_gfx_hqd_cntl = tmp;
6362
6363         /* set up cp_doorbell_control */
6364         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6365         if (ring->use_doorbell) {
6366                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6367                                     DOORBELL_OFFSET, ring->doorbell_index);
6368                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6369                                     DOORBELL_EN, 1);
6370         } else
6371                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6372                                     DOORBELL_EN, 0);
6373         mqd->cp_rb_doorbell_control = tmp;
6374
6375         /*if there are 2 gfx rings, set the lower doorbell range of the first ring,
6376          *otherwise the range of the second ring will override the first ring */
6377         if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6378                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6379
6380         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6381         ring->wptr = 0;
6382         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6383
6384         /* active the queue */
6385         mqd->cp_gfx_hqd_active = 1;
6386
6387         return 0;
6388 }
6389
6390 #ifdef BRING_UP_DEBUG
6391 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6392 {
6393         struct amdgpu_device *adev = ring->adev;
6394         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6395
6396         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6397         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6398         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6399
6400         /* set GFX_MQD_BASE */
6401         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6402         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6403
6404         /* set GFX_MQD_CONTROL */
6405         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6406
6407         /* set GFX_HQD_VMID to 0 */
6408         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6409
6410         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6411                         mqd->cp_gfx_hqd_queue_priority);
6412         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6413
6414         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6415         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6416         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6417
6418         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6419         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6420         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6421
6422         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6423         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6424
6425         /* set RB_WPTR_POLL_ADDR */
6426         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6427         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6428
6429         /* set RB_DOORBELL_CONTROL */
6430         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6431
6432         /* active the queue */
6433         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6434
6435         return 0;
6436 }
6437 #endif
6438
6439 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6440 {
6441         struct amdgpu_device *adev = ring->adev;
6442         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6443         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6444
6445         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6446                 memset((void *)mqd, 0, sizeof(*mqd));
6447                 mutex_lock(&adev->srbm_mutex);
6448                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6449                 gfx_v10_0_gfx_mqd_init(ring);
6450 #ifdef BRING_UP_DEBUG
6451                 gfx_v10_0_gfx_queue_init_register(ring);
6452 #endif
6453                 nv_grbm_select(adev, 0, 0, 0, 0);
6454                 mutex_unlock(&adev->srbm_mutex);
6455                 if (adev->gfx.me.mqd_backup[mqd_idx])
6456                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6457         } else if (amdgpu_in_reset(adev)) {
6458                 /* reset mqd with the backup copy */
6459                 if (adev->gfx.me.mqd_backup[mqd_idx])
6460                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6461                 /* reset the ring */
6462                 ring->wptr = 0;
6463                 adev->wb.wb[ring->wptr_offs] = 0;
6464                 amdgpu_ring_clear_ring(ring);
6465 #ifdef BRING_UP_DEBUG
6466                 mutex_lock(&adev->srbm_mutex);
6467                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6468                 gfx_v10_0_gfx_queue_init_register(ring);
6469                 nv_grbm_select(adev, 0, 0, 0, 0);
6470                 mutex_unlock(&adev->srbm_mutex);
6471 #endif
6472         } else {
6473                 amdgpu_ring_clear_ring(ring);
6474         }
6475
6476         return 0;
6477 }
6478
6479 #ifndef BRING_UP_DEBUG
6480 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6481 {
6482         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6483         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6484         int r, i;
6485
6486         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6487                 return -EINVAL;
6488
6489         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6490                                         adev->gfx.num_gfx_rings);
6491         if (r) {
6492                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6493                 return r;
6494         }
6495
6496         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6497                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6498
6499         return amdgpu_ring_test_helper(kiq_ring);
6500 }
6501 #endif
6502
6503 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6504 {
6505         int r, i;
6506         struct amdgpu_ring *ring;
6507
6508         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6509                 ring = &adev->gfx.gfx_ring[i];
6510
6511                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6512                 if (unlikely(r != 0))
6513                         goto done;
6514
6515                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6516                 if (!r) {
6517                         r = gfx_v10_0_gfx_init_queue(ring);
6518                         amdgpu_bo_kunmap(ring->mqd_obj);
6519                         ring->mqd_ptr = NULL;
6520                 }
6521                 amdgpu_bo_unreserve(ring->mqd_obj);
6522                 if (r)
6523                         goto done;
6524         }
6525 #ifndef BRING_UP_DEBUG
6526         r = gfx_v10_0_kiq_enable_kgq(adev);
6527         if (r)
6528                 goto done;
6529 #endif
6530         r = gfx_v10_0_cp_gfx_start(adev);
6531         if (r)
6532                 goto done;
6533
6534         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6535                 ring = &adev->gfx.gfx_ring[i];
6536                 ring->sched.ready = true;
6537         }
6538 done:
6539         return r;
6540 }
6541
6542 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6543 {
6544         struct amdgpu_device *adev = ring->adev;
6545
6546         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6547                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
6548                                                               ring->queue)) {
6549                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6550                         mqd->cp_hqd_queue_priority =
6551                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6552                 }
6553         }
6554 }
6555
6556 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6557 {
6558         struct amdgpu_device *adev = ring->adev;
6559         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6560         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6561         uint32_t tmp;
6562
6563         mqd->header = 0xC0310800;
6564         mqd->compute_pipelinestat_enable = 0x00000001;
6565         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6566         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6567         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6568         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6569         mqd->compute_misc_reserved = 0x00000003;
6570
6571         eop_base_addr = ring->eop_gpu_addr >> 8;
6572         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6573         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6574
6575         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6576         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6577         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6578                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6579
6580         mqd->cp_hqd_eop_control = tmp;
6581
6582         /* enable doorbell? */
6583         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6584
6585         if (ring->use_doorbell) {
6586                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6587                                     DOORBELL_OFFSET, ring->doorbell_index);
6588                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6589                                     DOORBELL_EN, 1);
6590                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6591                                     DOORBELL_SOURCE, 0);
6592                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6593                                     DOORBELL_HIT, 0);
6594         } else {
6595                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6596                                     DOORBELL_EN, 0);
6597         }
6598
6599         mqd->cp_hqd_pq_doorbell_control = tmp;
6600
6601         /* disable the queue if it's active */
6602         ring->wptr = 0;
6603         mqd->cp_hqd_dequeue_request = 0;
6604         mqd->cp_hqd_pq_rptr = 0;
6605         mqd->cp_hqd_pq_wptr_lo = 0;
6606         mqd->cp_hqd_pq_wptr_hi = 0;
6607
6608         /* set the pointer to the MQD */
6609         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6610         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6611
6612         /* set MQD vmid to 0 */
6613         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6614         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6615         mqd->cp_mqd_control = tmp;
6616
6617         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6618         hqd_gpu_addr = ring->gpu_addr >> 8;
6619         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6620         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6621
6622         /* set up the HQD, this is similar to CP_RB0_CNTL */
6623         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6624         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6625                             (order_base_2(ring->ring_size / 4) - 1));
6626         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6627                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6628 #ifdef __BIG_ENDIAN
6629         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6630 #endif
6631         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6632         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6633         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6634         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6635         mqd->cp_hqd_pq_control = tmp;
6636
6637         /* set the wb address whether it's enabled or not */
6638         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6639         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6640         mqd->cp_hqd_pq_rptr_report_addr_hi =
6641                 upper_32_bits(wb_gpu_addr) & 0xffff;
6642
6643         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6644         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6645         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6646         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6647
6648         tmp = 0;
6649         /* enable the doorbell if requested */
6650         if (ring->use_doorbell) {
6651                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6652                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6653                                 DOORBELL_OFFSET, ring->doorbell_index);
6654
6655                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6656                                     DOORBELL_EN, 1);
6657                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6658                                     DOORBELL_SOURCE, 0);
6659                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6660                                     DOORBELL_HIT, 0);
6661         }
6662
6663         mqd->cp_hqd_pq_doorbell_control = tmp;
6664
6665         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6666         ring->wptr = 0;
6667         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6668
6669         /* set the vmid for the queue */
6670         mqd->cp_hqd_vmid = 0;
6671
6672         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6673         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6674         mqd->cp_hqd_persistent_state = tmp;
6675
6676         /* set MIN_IB_AVAIL_SIZE */
6677         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6678         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6679         mqd->cp_hqd_ib_control = tmp;
6680
6681         /* set static priority for a compute queue/ring */
6682         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6683
6684         /* map_queues packet doesn't need activate the queue,
6685          * so only kiq need set this field.
6686          */
6687         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6688                 mqd->cp_hqd_active = 1;
6689
6690         return 0;
6691 }
6692
6693 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6694 {
6695         struct amdgpu_device *adev = ring->adev;
6696         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6697         int j;
6698
6699         /* inactivate the queue */
6700         if (amdgpu_sriov_vf(adev))
6701                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6702
6703         /* disable wptr polling */
6704         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6705
6706         /* write the EOP addr */
6707         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6708                mqd->cp_hqd_eop_base_addr_lo);
6709         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6710                mqd->cp_hqd_eop_base_addr_hi);
6711
6712         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6713         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6714                mqd->cp_hqd_eop_control);
6715
6716         /* enable doorbell? */
6717         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6718                mqd->cp_hqd_pq_doorbell_control);
6719
6720         /* disable the queue if it's active */
6721         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6722                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6723                 for (j = 0; j < adev->usec_timeout; j++) {
6724                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6725                                 break;
6726                         udelay(1);
6727                 }
6728                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6729                        mqd->cp_hqd_dequeue_request);
6730                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6731                        mqd->cp_hqd_pq_rptr);
6732                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6733                        mqd->cp_hqd_pq_wptr_lo);
6734                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6735                        mqd->cp_hqd_pq_wptr_hi);
6736         }
6737
6738         /* set the pointer to the MQD */
6739         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6740                mqd->cp_mqd_base_addr_lo);
6741         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6742                mqd->cp_mqd_base_addr_hi);
6743
6744         /* set MQD vmid to 0 */
6745         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6746                mqd->cp_mqd_control);
6747
6748         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6749         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6750                mqd->cp_hqd_pq_base_lo);
6751         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6752                mqd->cp_hqd_pq_base_hi);
6753
6754         /* set up the HQD, this is similar to CP_RB0_CNTL */
6755         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6756                mqd->cp_hqd_pq_control);
6757
6758         /* set the wb address whether it's enabled or not */
6759         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6760                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6761         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6762                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6763
6764         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6765         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6766                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6767         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6768                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6769
6770         /* enable the doorbell if requested */
6771         if (ring->use_doorbell) {
6772                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6773                         (adev->doorbell_index.kiq * 2) << 2);
6774                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6775                         (adev->doorbell_index.userqueue_end * 2) << 2);
6776         }
6777
6778         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6779                mqd->cp_hqd_pq_doorbell_control);
6780
6781         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6782         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6783                mqd->cp_hqd_pq_wptr_lo);
6784         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6785                mqd->cp_hqd_pq_wptr_hi);
6786
6787         /* set the vmid for the queue */
6788         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6789
6790         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6791                mqd->cp_hqd_persistent_state);
6792
6793         /* activate the queue */
6794         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6795                mqd->cp_hqd_active);
6796
6797         if (ring->use_doorbell)
6798                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6799
6800         return 0;
6801 }
6802
6803 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6804 {
6805         struct amdgpu_device *adev = ring->adev;
6806         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6807         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6808
6809         gfx_v10_0_kiq_setting(ring);
6810
6811         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6812                 /* reset MQD to a clean status */
6813                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6814                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6815
6816                 /* reset ring buffer */
6817                 ring->wptr = 0;
6818                 amdgpu_ring_clear_ring(ring);
6819
6820                 mutex_lock(&adev->srbm_mutex);
6821                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6822                 gfx_v10_0_kiq_init_register(ring);
6823                 nv_grbm_select(adev, 0, 0, 0, 0);
6824                 mutex_unlock(&adev->srbm_mutex);
6825         } else {
6826                 memset((void *)mqd, 0, sizeof(*mqd));
6827                 mutex_lock(&adev->srbm_mutex);
6828                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6829                 gfx_v10_0_compute_mqd_init(ring);
6830                 gfx_v10_0_kiq_init_register(ring);
6831                 nv_grbm_select(adev, 0, 0, 0, 0);
6832                 mutex_unlock(&adev->srbm_mutex);
6833
6834                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6835                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6836         }
6837
6838         return 0;
6839 }
6840
6841 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6842 {
6843         struct amdgpu_device *adev = ring->adev;
6844         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6845         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6846
6847         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6848                 memset((void *)mqd, 0, sizeof(*mqd));
6849                 mutex_lock(&adev->srbm_mutex);
6850                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6851                 gfx_v10_0_compute_mqd_init(ring);
6852                 nv_grbm_select(adev, 0, 0, 0, 0);
6853                 mutex_unlock(&adev->srbm_mutex);
6854
6855                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6856                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6857         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6858                 /* reset MQD to a clean status */
6859                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6860                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6861
6862                 /* reset ring buffer */
6863                 ring->wptr = 0;
6864                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6865                 amdgpu_ring_clear_ring(ring);
6866         } else {
6867                 amdgpu_ring_clear_ring(ring);
6868         }
6869
6870         return 0;
6871 }
6872
6873 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6874 {
6875         struct amdgpu_ring *ring;
6876         int r;
6877
6878         ring = &adev->gfx.kiq.ring;
6879
6880         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6881         if (unlikely(r != 0))
6882                 return r;
6883
6884         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6885         if (unlikely(r != 0))
6886                 return r;
6887
6888         gfx_v10_0_kiq_init_queue(ring);
6889         amdgpu_bo_kunmap(ring->mqd_obj);
6890         ring->mqd_ptr = NULL;
6891         amdgpu_bo_unreserve(ring->mqd_obj);
6892         ring->sched.ready = true;
6893         return 0;
6894 }
6895
6896 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6897 {
6898         struct amdgpu_ring *ring = NULL;
6899         int r = 0, i;
6900
6901         gfx_v10_0_cp_compute_enable(adev, true);
6902
6903         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6904                 ring = &adev->gfx.compute_ring[i];
6905
6906                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6907                 if (unlikely(r != 0))
6908                         goto done;
6909                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6910                 if (!r) {
6911                         r = gfx_v10_0_kcq_init_queue(ring);
6912                         amdgpu_bo_kunmap(ring->mqd_obj);
6913                         ring->mqd_ptr = NULL;
6914                 }
6915                 amdgpu_bo_unreserve(ring->mqd_obj);
6916                 if (r)
6917                         goto done;
6918         }
6919
6920         r = amdgpu_gfx_enable_kcq(adev);
6921 done:
6922         return r;
6923 }
6924
6925 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6926 {
6927         int r, i;
6928         struct amdgpu_ring *ring;
6929
6930         if (!(adev->flags & AMD_IS_APU))
6931                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6932
6933         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6934                 /* legacy firmware loading */
6935                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6936                 if (r)
6937                         return r;
6938
6939                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6940                 if (r)
6941                         return r;
6942         }
6943
6944         r = gfx_v10_0_kiq_resume(adev);
6945         if (r)
6946                 return r;
6947
6948         r = gfx_v10_0_kcq_resume(adev);
6949         if (r)
6950                 return r;
6951
6952         if (!amdgpu_async_gfx_ring) {
6953                 r = gfx_v10_0_cp_gfx_resume(adev);
6954                 if (r)
6955                         return r;
6956         } else {
6957                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6958                 if (r)
6959                         return r;
6960         }
6961
6962         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6963                 ring = &adev->gfx.gfx_ring[i];
6964                 r = amdgpu_ring_test_helper(ring);
6965                 if (r)
6966                         return r;
6967         }
6968
6969         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6970                 ring = &adev->gfx.compute_ring[i];
6971                 r = amdgpu_ring_test_helper(ring);
6972                 if (r)
6973                         return r;
6974         }
6975
6976         return 0;
6977 }
6978
6979 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6980 {
6981         gfx_v10_0_cp_gfx_enable(adev, enable);
6982         gfx_v10_0_cp_compute_enable(adev, enable);
6983 }
6984
6985 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6986 {
6987         uint32_t data, pattern = 0xDEADBEEF;
6988
6989         /* check if mmVGT_ESGS_RING_SIZE_UMD
6990          * has been remapped to mmVGT_ESGS_RING_SIZE */
6991         switch (adev->asic_type) {
6992         case CHIP_SIENNA_CICHLID:
6993         case CHIP_NAVY_FLOUNDER:
6994         case CHIP_DIMGREY_CAVEFISH:
6995                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6996                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6997                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6998
6999                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7000                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
7001                         return true;
7002                 } else {
7003                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7004                         return false;
7005                 }
7006                 break;
7007         case CHIP_VANGOGH:
7008                 return true;
7009         default:
7010                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7011                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7012                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7013
7014                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7015                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7016                         return true;
7017                 } else {
7018                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7019                         return false;
7020                 }
7021                 break;
7022         }
7023 }
7024
7025 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7026 {
7027         uint32_t data;
7028
7029         /* initialize cam_index to 0
7030          * index will auto-inc after each data writting */
7031         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7032
7033         switch (adev->asic_type) {
7034         case CHIP_SIENNA_CICHLID:
7035         case CHIP_NAVY_FLOUNDER:
7036         case CHIP_VANGOGH:
7037         case CHIP_DIMGREY_CAVEFISH:
7038                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7039                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7040                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7041                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7042                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7043                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7044                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7045
7046                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7047                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7048                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7049                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7050                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7051                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7052                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7053
7054                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7055                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7056                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7057                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7058                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7059                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7060                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7061
7062                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7063                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7064                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7065                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7066                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7067                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7068                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7069
7070                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7071                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7072                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7073                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7074                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7075                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7076                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7077
7078                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7079                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7080                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7081                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7082                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7083                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7084                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7085
7086                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7087                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7088                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7089                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7090                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7091                 break;
7092         default:
7093                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7094                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7095                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7096                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7097                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7098                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7099                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7100
7101                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7102                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7103                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7104                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7105                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7106                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7107                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7108
7109                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7110                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7111                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7112                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7113                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7114                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7115                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7116
7117                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7118                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7119                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7120                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7121                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7122                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7123                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7124
7125                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7126                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7127                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7128                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7129                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7130                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7131                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7132
7133                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7134                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7135                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7136                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7137                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7138                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7139                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7140
7141                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7142                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7143                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7144                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7145                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7146                 break;
7147         }
7148
7149         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7150         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7151 }
7152
7153 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7154 {
7155         uint32_t data;
7156         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7157         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7158         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7159
7160         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7161         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7162         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7163 }
7164
7165 static int gfx_v10_0_hw_init(void *handle)
7166 {
7167         int r;
7168         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7169
7170         if (!amdgpu_emu_mode)
7171                 gfx_v10_0_init_golden_registers(adev);
7172
7173         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7174                 /**
7175                  * For gfx 10, rlc firmware loading relies on smu firmware is
7176                  * loaded firstly, so in direct type, it has to load smc ucode
7177                  * here before rlc.
7178                  */
7179                 if (adev->smu.ppt_funcs != NULL && !(adev->flags & AMD_IS_APU)) {
7180                         r = smu_load_microcode(&adev->smu);
7181                         if (r)
7182                                 return r;
7183
7184                         r = smu_check_fw_status(&adev->smu);
7185                         if (r) {
7186                                 pr_err("SMC firmware status is not correct\n");
7187                                 return r;
7188                         }
7189                 }
7190                 gfx_v10_0_disable_gpa_mode(adev);
7191         }
7192
7193         /* if GRBM CAM not remapped, set up the remapping */
7194         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7195                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7196
7197         gfx_v10_0_constants_init(adev);
7198
7199         r = gfx_v10_0_rlc_resume(adev);
7200         if (r)
7201                 return r;
7202
7203         /*
7204          * init golden registers and rlc resume may override some registers,
7205          * reconfig them here
7206          */
7207         gfx_v10_0_tcp_harvest(adev);
7208
7209         r = gfx_v10_0_cp_resume(adev);
7210         if (r)
7211                 return r;
7212
7213         if (adev->asic_type == CHIP_SIENNA_CICHLID)
7214                 gfx_v10_3_program_pbb_mode(adev);
7215
7216         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
7217                 gfx_v10_3_set_power_brake_sequence(adev);
7218
7219         return r;
7220 }
7221
7222 #ifndef BRING_UP_DEBUG
7223 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7224 {
7225         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7226         struct amdgpu_ring *kiq_ring = &kiq->ring;
7227         int i;
7228
7229         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7230                 return -EINVAL;
7231
7232         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7233                                         adev->gfx.num_gfx_rings))
7234                 return -ENOMEM;
7235
7236         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7237                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7238                                            PREEMPT_QUEUES, 0, 0);
7239
7240         return amdgpu_ring_test_helper(kiq_ring);
7241 }
7242 #endif
7243
7244 static int gfx_v10_0_hw_fini(void *handle)
7245 {
7246         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7247         int r;
7248         uint32_t tmp;
7249
7250         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7251         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7252
7253         if (!adev->in_pci_err_recovery) {
7254 #ifndef BRING_UP_DEBUG
7255                 if (amdgpu_async_gfx_ring) {
7256                         r = gfx_v10_0_kiq_disable_kgq(adev);
7257                         if (r)
7258                                 DRM_ERROR("KGQ disable failed\n");
7259                 }
7260 #endif
7261                 if (amdgpu_gfx_disable_kcq(adev))
7262                         DRM_ERROR("KCQ disable failed\n");
7263         }
7264
7265         if (amdgpu_sriov_vf(adev)) {
7266                 gfx_v10_0_cp_gfx_enable(adev, false);
7267                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7268                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7269                 tmp &= 0xffffff00;
7270                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7271
7272                 return 0;
7273         }
7274         gfx_v10_0_cp_enable(adev, false);
7275         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7276
7277         return 0;
7278 }
7279
7280 static int gfx_v10_0_suspend(void *handle)
7281 {
7282         return gfx_v10_0_hw_fini(handle);
7283 }
7284
7285 static int gfx_v10_0_resume(void *handle)
7286 {
7287         return gfx_v10_0_hw_init(handle);
7288 }
7289
7290 static bool gfx_v10_0_is_idle(void *handle)
7291 {
7292         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7293
7294         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7295                                 GRBM_STATUS, GUI_ACTIVE))
7296                 return false;
7297         else
7298                 return true;
7299 }
7300
7301 static int gfx_v10_0_wait_for_idle(void *handle)
7302 {
7303         unsigned i;
7304         u32 tmp;
7305         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7306
7307         for (i = 0; i < adev->usec_timeout; i++) {
7308                 /* read MC_STATUS */
7309                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7310                         GRBM_STATUS__GUI_ACTIVE_MASK;
7311
7312                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7313                         return 0;
7314                 udelay(1);
7315         }
7316         return -ETIMEDOUT;
7317 }
7318
7319 static int gfx_v10_0_soft_reset(void *handle)
7320 {
7321         u32 grbm_soft_reset = 0;
7322         u32 tmp;
7323         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7324
7325         /* GRBM_STATUS */
7326         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7327         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7328                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7329                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7330                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7331                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7332                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7333                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7334                                                 1);
7335                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7336                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7337                                                 1);
7338         }
7339
7340         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7341                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7342                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7343                                                 1);
7344         }
7345
7346         /* GRBM_STATUS2 */
7347         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7348         switch (adev->asic_type) {
7349         case CHIP_SIENNA_CICHLID:
7350         case CHIP_NAVY_FLOUNDER:
7351         case CHIP_VANGOGH:
7352         case CHIP_DIMGREY_CAVEFISH:
7353                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7354                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7355                                                         GRBM_SOFT_RESET,
7356                                                         SOFT_RESET_RLC,
7357                                                         1);
7358                 break;
7359         default:
7360                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7361                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7362                                                         GRBM_SOFT_RESET,
7363                                                         SOFT_RESET_RLC,
7364                                                         1);
7365                 break;
7366         }
7367
7368         if (grbm_soft_reset) {
7369                 /* stop the rlc */
7370                 gfx_v10_0_rlc_stop(adev);
7371
7372                 /* Disable GFX parsing/prefetching */
7373                 gfx_v10_0_cp_gfx_enable(adev, false);
7374
7375                 /* Disable MEC parsing/prefetching */
7376                 gfx_v10_0_cp_compute_enable(adev, false);
7377
7378                 if (grbm_soft_reset) {
7379                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7380                         tmp |= grbm_soft_reset;
7381                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7382                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7383                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7384
7385                         udelay(50);
7386
7387                         tmp &= ~grbm_soft_reset;
7388                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7389                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7390                 }
7391
7392                 /* Wait a little for things to settle down */
7393                 udelay(50);
7394         }
7395         return 0;
7396 }
7397
7398 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7399 {
7400         uint64_t clock;
7401
7402         amdgpu_gfx_off_ctrl(adev, false);
7403         mutex_lock(&adev->gfx.gpu_clock_mutex);
7404         switch (adev->asic_type) {
7405         case CHIP_VANGOGH:
7406                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
7407                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
7408                 break;
7409         default:
7410                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7411                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7412                 break;
7413         }
7414         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7415         amdgpu_gfx_off_ctrl(adev, true);
7416         return clock;
7417 }
7418
7419 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7420                                            uint32_t vmid,
7421                                            uint32_t gds_base, uint32_t gds_size,
7422                                            uint32_t gws_base, uint32_t gws_size,
7423                                            uint32_t oa_base, uint32_t oa_size)
7424 {
7425         struct amdgpu_device *adev = ring->adev;
7426
7427         /* GDS Base */
7428         gfx_v10_0_write_data_to_reg(ring, 0, false,
7429                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7430                                     gds_base);
7431
7432         /* GDS Size */
7433         gfx_v10_0_write_data_to_reg(ring, 0, false,
7434                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7435                                     gds_size);
7436
7437         /* GWS */
7438         gfx_v10_0_write_data_to_reg(ring, 0, false,
7439                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7440                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7441
7442         /* OA */
7443         gfx_v10_0_write_data_to_reg(ring, 0, false,
7444                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7445                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7446 }
7447
7448 static int gfx_v10_0_early_init(void *handle)
7449 {
7450         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7451
7452         switch (adev->asic_type) {
7453         case CHIP_NAVI10:
7454         case CHIP_NAVI14:
7455         case CHIP_NAVI12:
7456                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7457                 break;
7458         case CHIP_SIENNA_CICHLID:
7459         case CHIP_NAVY_FLOUNDER:
7460         case CHIP_VANGOGH:
7461         case CHIP_DIMGREY_CAVEFISH:
7462                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7463                 break;
7464         default:
7465                 break;
7466         }
7467
7468         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7469                                           AMDGPU_MAX_COMPUTE_RINGS);
7470
7471         gfx_v10_0_set_kiq_pm4_funcs(adev);
7472         gfx_v10_0_set_ring_funcs(adev);
7473         gfx_v10_0_set_irq_funcs(adev);
7474         gfx_v10_0_set_gds_init(adev);
7475         gfx_v10_0_set_rlc_funcs(adev);
7476
7477         return 0;
7478 }
7479
7480 static int gfx_v10_0_late_init(void *handle)
7481 {
7482         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7483         int r;
7484
7485         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7486         if (r)
7487                 return r;
7488
7489         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7490         if (r)
7491                 return r;
7492
7493         return 0;
7494 }
7495
7496 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7497 {
7498         uint32_t rlc_cntl;
7499
7500         /* if RLC is not enabled, do nothing */
7501         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7502         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7503 }
7504
7505 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7506 {
7507         uint32_t data;
7508         unsigned i;
7509
7510         data = RLC_SAFE_MODE__CMD_MASK;
7511         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7512
7513         switch (adev->asic_type) {
7514         case CHIP_SIENNA_CICHLID:
7515         case CHIP_NAVY_FLOUNDER:
7516         case CHIP_VANGOGH:
7517         case CHIP_DIMGREY_CAVEFISH:
7518                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7519
7520                 /* wait for RLC_SAFE_MODE */
7521                 for (i = 0; i < adev->usec_timeout; i++) {
7522                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7523                                            RLC_SAFE_MODE, CMD))
7524                                 break;
7525                         udelay(1);
7526                 }
7527                 break;
7528         default:
7529                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7530
7531                 /* wait for RLC_SAFE_MODE */
7532                 for (i = 0; i < adev->usec_timeout; i++) {
7533                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7534                                            RLC_SAFE_MODE, CMD))
7535                                 break;
7536                         udelay(1);
7537                 }
7538                 break;
7539         }
7540 }
7541
7542 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7543 {
7544         uint32_t data;
7545
7546         data = RLC_SAFE_MODE__CMD_MASK;
7547         switch (adev->asic_type) {
7548         case CHIP_SIENNA_CICHLID:
7549         case CHIP_NAVY_FLOUNDER:
7550         case CHIP_VANGOGH:
7551         case CHIP_DIMGREY_CAVEFISH:
7552                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7553                 break;
7554         default:
7555                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7556                 break;
7557         }
7558 }
7559
7560 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7561                                                       bool enable)
7562 {
7563         uint32_t data, def;
7564
7565         /* It is disabled by HW by default */
7566         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7567                 /* 0 - Disable some blocks' MGCG */
7568                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7569                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7570                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7571                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7572
7573                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7574                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7575                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7576                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7577                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7578                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7579                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7580
7581                 if (def != data)
7582                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7583
7584                 /* MGLS is a global flag to control all MGLS in GFX */
7585                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7586                         /* 2 - RLC memory Light sleep */
7587                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7588                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7589                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7590                                 if (def != data)
7591                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7592                         }
7593                         /* 3 - CP memory Light sleep */
7594                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7595                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7596                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7597                                 if (def != data)
7598                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7599                         }
7600                 }
7601         } else {
7602                 /* 1 - MGCG_OVERRIDE */
7603                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7604                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7605                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7606                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7607                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7608                 if (def != data)
7609                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7610
7611                 /* 2 - disable MGLS in CP */
7612                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7613                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7614                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7615                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7616                 }
7617
7618                 /* 3 - disable MGLS in RLC */
7619                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7620                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7621                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7622                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7623                 }
7624
7625         }
7626 }
7627
7628 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7629                                            bool enable)
7630 {
7631         uint32_t data, def;
7632
7633         /* Enable 3D CGCG/CGLS */
7634         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7635                 /* write cmd to clear cgcg/cgls ov */
7636                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7637                 /* unset CGCG override */
7638                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7639                 /* update CGCG and CGLS override bits */
7640                 if (def != data)
7641                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7642                 /* enable 3Dcgcg FSM(0x0000363f) */
7643                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7644                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7645                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7646                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7647                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7648                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7649                 if (def != data)
7650                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7651
7652                 /* set IDLE_POLL_COUNT(0x00900100) */
7653                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7654                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7655                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7656                 if (def != data)
7657                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7658         } else {
7659                 /* Disable CGCG/CGLS */
7660                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7661                 /* disable cgcg, cgls should be disabled */
7662                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7663                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7664                 /* disable cgcg and cgls in FSM */
7665                 if (def != data)
7666                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7667         }
7668 }
7669
7670 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7671                                                       bool enable)
7672 {
7673         uint32_t def, data;
7674
7675         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7676                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7677                 /* unset CGCG override */
7678                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7679                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7680                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7681                 else
7682                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7683                 /* update CGCG and CGLS override bits */
7684                 if (def != data)
7685                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7686
7687                 /* enable cgcg FSM(0x0000363F) */
7688                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7689                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7690                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7691                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7692                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7693                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7694                 if (def != data)
7695                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7696
7697                 /* set IDLE_POLL_COUNT(0x00900100) */
7698                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7699                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7700                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7701                 if (def != data)
7702                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7703         } else {
7704                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7705                 /* reset CGCG/CGLS bits */
7706                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7707                 /* disable cgcg and cgls in FSM */
7708                 if (def != data)
7709                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7710         }
7711 }
7712
7713 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7714                                                       bool enable)
7715 {
7716         uint32_t def, data;
7717
7718         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) {
7719                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7720                 /* unset FGCG override */
7721                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7722                 /* update FGCG override bits */
7723                 if (def != data)
7724                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7725
7726                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7727                 /* unset RLC SRAM CLK GATER override */
7728                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7729                 /* update RLC SRAM CLK GATER override bits */
7730                 if (def != data)
7731                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7732         } else {
7733                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7734                 /* reset FGCG bits */
7735                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7736                 /* disable FGCG*/
7737                 if (def != data)
7738                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7739
7740                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7741                 /* reset RLC SRAM CLK GATER bits */
7742                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7743                 /* disable RLC SRAM CLK*/
7744                 if (def != data)
7745                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7746         }
7747 }
7748
7749 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7750                                             bool enable)
7751 {
7752         amdgpu_gfx_rlc_enter_safe_mode(adev);
7753
7754         if (enable) {
7755                 /* enable FGCG firstly*/
7756                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7757                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7758                  * ===  MGCG + MGLS ===
7759                  */
7760                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7761                 /* ===  CGCG /CGLS for GFX 3D Only === */
7762                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7763                 /* ===  CGCG + CGLS === */
7764                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7765         } else {
7766                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7767                  * ===  CGCG + CGLS ===
7768                  */
7769                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7770                 /* ===  CGCG /CGLS for GFX 3D Only === */
7771                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7772                 /* ===  MGCG + MGLS === */
7773                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7774                 /* disable fgcg at last*/
7775                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7776         }
7777
7778         if (adev->cg_flags &
7779             (AMD_CG_SUPPORT_GFX_MGCG |
7780              AMD_CG_SUPPORT_GFX_CGLS |
7781              AMD_CG_SUPPORT_GFX_CGCG |
7782              AMD_CG_SUPPORT_GFX_3D_CGCG |
7783              AMD_CG_SUPPORT_GFX_3D_CGLS))
7784                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7785
7786         amdgpu_gfx_rlc_exit_safe_mode(adev);
7787
7788         return 0;
7789 }
7790
7791 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7792 {
7793         u32 reg, data;
7794
7795         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7796         if (amdgpu_sriov_is_pp_one_vf(adev))
7797                 data = RREG32_NO_KIQ(reg);
7798         else
7799                 data = RREG32(reg);
7800
7801         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7802         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7803
7804         if (amdgpu_sriov_is_pp_one_vf(adev))
7805                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7806         else
7807                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7808 }
7809
7810 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7811                                         uint32_t offset,
7812                                         struct soc15_reg_rlcg *entries, int arr_size)
7813 {
7814         int i;
7815         uint32_t reg;
7816
7817         if (!entries)
7818                 return false;
7819
7820         for (i = 0; i < arr_size; i++) {
7821                 const struct soc15_reg_rlcg *entry;
7822
7823                 entry = &entries[i];
7824                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7825                 if (offset == reg)
7826                         return true;
7827         }
7828
7829         return false;
7830 }
7831
7832 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7833 {
7834         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7835 }
7836
7837 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
7838 {
7839         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
7840
7841         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
7842                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7843         else
7844                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7845
7846         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
7847
7848         /*
7849          * CGPG enablement required and the register to program the hysteresis value
7850          * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
7851          * in refclk count. Note that RLC FW is modified to take 16 bits from
7852          * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
7853          *
7854          * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us(0x4E20)
7855          * as part of CGPG enablement starting point.
7856          */
7857         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) {
7858                 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
7859                 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
7860         }
7861 }
7862
7863 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
7864 {
7865         amdgpu_gfx_rlc_enter_safe_mode(adev);
7866
7867         gfx_v10_cntl_power_gating(adev, enable);
7868
7869         amdgpu_gfx_rlc_exit_safe_mode(adev);
7870 }
7871
7872 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7873         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7874         .set_safe_mode = gfx_v10_0_set_safe_mode,
7875         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7876         .init = gfx_v10_0_rlc_init,
7877         .get_csb_size = gfx_v10_0_get_csb_size,
7878         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7879         .resume = gfx_v10_0_rlc_resume,
7880         .stop = gfx_v10_0_rlc_stop,
7881         .reset = gfx_v10_0_rlc_reset,
7882         .start = gfx_v10_0_rlc_start,
7883         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7884 };
7885
7886 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7887         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7888         .set_safe_mode = gfx_v10_0_set_safe_mode,
7889         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7890         .init = gfx_v10_0_rlc_init,
7891         .get_csb_size = gfx_v10_0_get_csb_size,
7892         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7893         .resume = gfx_v10_0_rlc_resume,
7894         .stop = gfx_v10_0_rlc_stop,
7895         .reset = gfx_v10_0_rlc_reset,
7896         .start = gfx_v10_0_rlc_start,
7897         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7898         .rlcg_wreg = gfx_v10_rlcg_wreg,
7899         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7900 };
7901
7902 static int gfx_v10_0_set_powergating_state(void *handle,
7903                                           enum amd_powergating_state state)
7904 {
7905         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7906         bool enable = (state == AMD_PG_STATE_GATE);
7907
7908         if (amdgpu_sriov_vf(adev))
7909                 return 0;
7910
7911         switch (adev->asic_type) {
7912         case CHIP_NAVI10:
7913         case CHIP_NAVI14:
7914         case CHIP_NAVI12:
7915         case CHIP_SIENNA_CICHLID:
7916         case CHIP_NAVY_FLOUNDER:
7917         case CHIP_DIMGREY_CAVEFISH:
7918                 amdgpu_gfx_off_ctrl(adev, enable);
7919                 break;
7920         case CHIP_VANGOGH:
7921                 gfx_v10_cntl_pg(adev, enable);
7922                 amdgpu_gfx_off_ctrl(adev, enable);
7923                 break;
7924         default:
7925                 break;
7926         }
7927         return 0;
7928 }
7929
7930 static int gfx_v10_0_set_clockgating_state(void *handle,
7931                                           enum amd_clockgating_state state)
7932 {
7933         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7934
7935         if (amdgpu_sriov_vf(adev))
7936                 return 0;
7937
7938         switch (adev->asic_type) {
7939         case CHIP_NAVI10:
7940         case CHIP_NAVI14:
7941         case CHIP_NAVI12:
7942         case CHIP_SIENNA_CICHLID:
7943         case CHIP_NAVY_FLOUNDER:
7944         case CHIP_VANGOGH:
7945         case CHIP_DIMGREY_CAVEFISH:
7946                 gfx_v10_0_update_gfx_clock_gating(adev,
7947                                                  state == AMD_CG_STATE_GATE);
7948                 break;
7949         default:
7950                 break;
7951         }
7952         return 0;
7953 }
7954
7955 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7956 {
7957         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7958         int data;
7959
7960         /* AMD_CG_SUPPORT_GFX_FGCG */
7961         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7962         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
7963                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
7964
7965         /* AMD_CG_SUPPORT_GFX_MGCG */
7966         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7967         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7968                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
7969
7970         /* AMD_CG_SUPPORT_GFX_CGCG */
7971         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
7972         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7973                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
7974
7975         /* AMD_CG_SUPPORT_GFX_CGLS */
7976         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7977                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
7978
7979         /* AMD_CG_SUPPORT_GFX_RLC_LS */
7980         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
7981         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7982                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7983
7984         /* AMD_CG_SUPPORT_GFX_CP_LS */
7985         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
7986         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7987                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7988
7989         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
7990         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
7991         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7992                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7993
7994         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
7995         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7996                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7997 }
7998
7999 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8000 {
8001         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
8002 }
8003
8004 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8005 {
8006         struct amdgpu_device *adev = ring->adev;
8007         u64 wptr;
8008
8009         /* XXX check if swapping is necessary on BE */
8010         if (ring->use_doorbell) {
8011                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
8012         } else {
8013                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8014                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8015         }
8016
8017         return wptr;
8018 }
8019
8020 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8021 {
8022         struct amdgpu_device *adev = ring->adev;
8023
8024         if (ring->use_doorbell) {
8025                 /* XXX check if swapping is necessary on BE */
8026                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8027                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8028         } else {
8029                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
8030                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
8031         }
8032 }
8033
8034 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8035 {
8036         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
8037 }
8038
8039 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8040 {
8041         u64 wptr;
8042
8043         /* XXX check if swapping is necessary on BE */
8044         if (ring->use_doorbell)
8045                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
8046         else
8047                 BUG();
8048         return wptr;
8049 }
8050
8051 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8052 {
8053         struct amdgpu_device *adev = ring->adev;
8054
8055         /* XXX check if swapping is necessary on BE */
8056         if (ring->use_doorbell) {
8057                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8058                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8059         } else {
8060                 BUG(); /* only DOORBELL method supported on gfx10 now */
8061         }
8062 }
8063
8064 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8065 {
8066         struct amdgpu_device *adev = ring->adev;
8067         u32 ref_and_mask, reg_mem_engine;
8068         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8069
8070         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8071                 switch (ring->me) {
8072                 case 1:
8073                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8074                         break;
8075                 case 2:
8076                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8077                         break;
8078                 default:
8079                         return;
8080                 }
8081                 reg_mem_engine = 0;
8082         } else {
8083                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8084                 reg_mem_engine = 1; /* pfp */
8085         }
8086
8087         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8088                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8089                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8090                                ref_and_mask, ref_and_mask, 0x20);
8091 }
8092
8093 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8094                                        struct amdgpu_job *job,
8095                                        struct amdgpu_ib *ib,
8096                                        uint32_t flags)
8097 {
8098         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8099         u32 header, control = 0;
8100
8101         if (ib->flags & AMDGPU_IB_FLAG_CE)
8102                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8103         else
8104                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8105
8106         control |= ib->length_dw | (vmid << 24);
8107
8108         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8109                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8110
8111                 if (flags & AMDGPU_IB_PREEMPTED)
8112                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8113
8114                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8115                         gfx_v10_0_ring_emit_de_meta(ring,
8116                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8117         }
8118
8119         amdgpu_ring_write(ring, header);
8120         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8121         amdgpu_ring_write(ring,
8122 #ifdef __BIG_ENDIAN
8123                 (2 << 0) |
8124 #endif
8125                 lower_32_bits(ib->gpu_addr));
8126         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8127         amdgpu_ring_write(ring, control);
8128 }
8129
8130 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8131                                            struct amdgpu_job *job,
8132                                            struct amdgpu_ib *ib,
8133                                            uint32_t flags)
8134 {
8135         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8136         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8137
8138         /* Currently, there is a high possibility to get wave ID mismatch
8139          * between ME and GDS, leading to a hw deadlock, because ME generates
8140          * different wave IDs than the GDS expects. This situation happens
8141          * randomly when at least 5 compute pipes use GDS ordered append.
8142          * The wave IDs generated by ME are also wrong after suspend/resume.
8143          * Those are probably bugs somewhere else in the kernel driver.
8144          *
8145          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8146          * GDS to 0 for this ring (me/pipe).
8147          */
8148         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8149                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8150                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8151                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8152         }
8153
8154         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8155         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8156         amdgpu_ring_write(ring,
8157 #ifdef __BIG_ENDIAN
8158                                 (2 << 0) |
8159 #endif
8160                                 lower_32_bits(ib->gpu_addr));
8161         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8162         amdgpu_ring_write(ring, control);
8163 }
8164
8165 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8166                                      u64 seq, unsigned flags)
8167 {
8168         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8169         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8170
8171         /* RELEASE_MEM - flush caches, send int */
8172         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8173         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8174                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8175                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8176                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8177                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8178                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8179                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8180         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8181                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8182
8183         /*
8184          * the address should be Qword aligned if 64bit write, Dword
8185          * aligned if only send 32bit data low (discard data high)
8186          */
8187         if (write64bit)
8188                 BUG_ON(addr & 0x7);
8189         else
8190                 BUG_ON(addr & 0x3);
8191         amdgpu_ring_write(ring, lower_32_bits(addr));
8192         amdgpu_ring_write(ring, upper_32_bits(addr));
8193         amdgpu_ring_write(ring, lower_32_bits(seq));
8194         amdgpu_ring_write(ring, upper_32_bits(seq));
8195         amdgpu_ring_write(ring, 0);
8196 }
8197
8198 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8199 {
8200         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8201         uint32_t seq = ring->fence_drv.sync_seq;
8202         uint64_t addr = ring->fence_drv.gpu_addr;
8203
8204         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8205                                upper_32_bits(addr), seq, 0xffffffff, 4);
8206 }
8207
8208 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8209                                          unsigned vmid, uint64_t pd_addr)
8210 {
8211         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8212
8213         /* compute doesn't have PFP */
8214         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8215                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8216                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8217                 amdgpu_ring_write(ring, 0x0);
8218         }
8219 }
8220
8221 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8222                                           u64 seq, unsigned int flags)
8223 {
8224         struct amdgpu_device *adev = ring->adev;
8225
8226         /* we only allocate 32bit for each seq wb address */
8227         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8228
8229         /* write fence seq to the "addr" */
8230         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8231         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8232                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8233         amdgpu_ring_write(ring, lower_32_bits(addr));
8234         amdgpu_ring_write(ring, upper_32_bits(addr));
8235         amdgpu_ring_write(ring, lower_32_bits(seq));
8236
8237         if (flags & AMDGPU_FENCE_FLAG_INT) {
8238                 /* set register to trigger INT */
8239                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8240                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8241                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8242                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8243                 amdgpu_ring_write(ring, 0);
8244                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8245         }
8246 }
8247
8248 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8249 {
8250         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8251         amdgpu_ring_write(ring, 0);
8252 }
8253
8254 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8255                                          uint32_t flags)
8256 {
8257         uint32_t dw2 = 0;
8258
8259         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8260                 gfx_v10_0_ring_emit_ce_meta(ring,
8261                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8262
8263         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8264         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8265                 /* set load_global_config & load_global_uconfig */
8266                 dw2 |= 0x8001;
8267                 /* set load_cs_sh_regs */
8268                 dw2 |= 0x01000000;
8269                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8270                 dw2 |= 0x10002;
8271
8272                 /* set load_ce_ram if preamble presented */
8273                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8274                         dw2 |= 0x10000000;
8275         } else {
8276                 /* still load_ce_ram if this is the first time preamble presented
8277                  * although there is no context switch happens.
8278                  */
8279                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8280                         dw2 |= 0x10000000;
8281         }
8282
8283         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8284         amdgpu_ring_write(ring, dw2);
8285         amdgpu_ring_write(ring, 0);
8286 }
8287
8288 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8289 {
8290         unsigned ret;
8291
8292         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8293         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8294         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8295         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8296         ret = ring->wptr & ring->buf_mask;
8297         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8298
8299         return ret;
8300 }
8301
8302 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8303 {
8304         unsigned cur;
8305         BUG_ON(offset > ring->buf_mask);
8306         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8307
8308         cur = (ring->wptr - 1) & ring->buf_mask;
8309         if (likely(cur > offset))
8310                 ring->ring[offset] = cur - offset;
8311         else
8312                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8313 }
8314
8315 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8316 {
8317         int i, r = 0;
8318         struct amdgpu_device *adev = ring->adev;
8319         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8320         struct amdgpu_ring *kiq_ring = &kiq->ring;
8321         unsigned long flags;
8322
8323         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8324                 return -EINVAL;
8325
8326         spin_lock_irqsave(&kiq->ring_lock, flags);
8327
8328         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8329                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8330                 return -ENOMEM;
8331         }
8332
8333         /* assert preemption condition */
8334         amdgpu_ring_set_preempt_cond_exec(ring, false);
8335
8336         /* assert IB preemption, emit the trailing fence */
8337         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8338                                    ring->trail_fence_gpu_addr,
8339                                    ++ring->trail_seq);
8340         amdgpu_ring_commit(kiq_ring);
8341
8342         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8343
8344         /* poll the trailing fence */
8345         for (i = 0; i < adev->usec_timeout; i++) {
8346                 if (ring->trail_seq ==
8347                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8348                         break;
8349                 udelay(1);
8350         }
8351
8352         if (i >= adev->usec_timeout) {
8353                 r = -EINVAL;
8354                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8355         }
8356
8357         /* deassert preemption condition */
8358         amdgpu_ring_set_preempt_cond_exec(ring, true);
8359         return r;
8360 }
8361
8362 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8363 {
8364         struct amdgpu_device *adev = ring->adev;
8365         struct v10_ce_ib_state ce_payload = {0};
8366         uint64_t csa_addr;
8367         int cnt;
8368
8369         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8370         csa_addr = amdgpu_csa_vaddr(ring->adev);
8371
8372         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8373         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8374                                  WRITE_DATA_DST_SEL(8) |
8375                                  WR_CONFIRM) |
8376                                  WRITE_DATA_CACHE_POLICY(0));
8377         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8378                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8379         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8380                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8381
8382         if (resume)
8383                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8384                                            offsetof(struct v10_gfx_meta_data,
8385                                                     ce_payload),
8386                                            sizeof(ce_payload) >> 2);
8387         else
8388                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8389                                            sizeof(ce_payload) >> 2);
8390 }
8391
8392 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8393 {
8394         struct amdgpu_device *adev = ring->adev;
8395         struct v10_de_ib_state de_payload = {0};
8396         uint64_t csa_addr, gds_addr;
8397         int cnt;
8398
8399         csa_addr = amdgpu_csa_vaddr(ring->adev);
8400         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8401                          PAGE_SIZE);
8402         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8403         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8404
8405         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8406         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8407         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8408                                  WRITE_DATA_DST_SEL(8) |
8409                                  WR_CONFIRM) |
8410                                  WRITE_DATA_CACHE_POLICY(0));
8411         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8412                               offsetof(struct v10_gfx_meta_data, de_payload)));
8413         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8414                               offsetof(struct v10_gfx_meta_data, de_payload)));
8415
8416         if (resume)
8417                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8418                                            offsetof(struct v10_gfx_meta_data,
8419                                                     de_payload),
8420                                            sizeof(de_payload) >> 2);
8421         else
8422                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8423                                            sizeof(de_payload) >> 2);
8424 }
8425
8426 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8427                                     bool secure)
8428 {
8429         uint32_t v = secure ? FRAME_TMZ : 0;
8430
8431         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8432         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8433 }
8434
8435 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8436                                      uint32_t reg_val_offs)
8437 {
8438         struct amdgpu_device *adev = ring->adev;
8439
8440         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8441         amdgpu_ring_write(ring, 0 |     /* src: register*/
8442                                 (5 << 8) |      /* dst: memory */
8443                                 (1 << 20));     /* write confirm */
8444         amdgpu_ring_write(ring, reg);
8445         amdgpu_ring_write(ring, 0);
8446         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8447                                 reg_val_offs * 4));
8448         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8449                                 reg_val_offs * 4));
8450 }
8451
8452 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8453                                    uint32_t val)
8454 {
8455         uint32_t cmd = 0;
8456
8457         switch (ring->funcs->type) {
8458         case AMDGPU_RING_TYPE_GFX:
8459                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8460                 break;
8461         case AMDGPU_RING_TYPE_KIQ:
8462                 cmd = (1 << 16); /* no inc addr */
8463                 break;
8464         default:
8465                 cmd = WR_CONFIRM;
8466                 break;
8467         }
8468         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8469         amdgpu_ring_write(ring, cmd);
8470         amdgpu_ring_write(ring, reg);
8471         amdgpu_ring_write(ring, 0);
8472         amdgpu_ring_write(ring, val);
8473 }
8474
8475 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8476                                         uint32_t val, uint32_t mask)
8477 {
8478         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8479 }
8480
8481 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8482                                                    uint32_t reg0, uint32_t reg1,
8483                                                    uint32_t ref, uint32_t mask)
8484 {
8485         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8486         struct amdgpu_device *adev = ring->adev;
8487         bool fw_version_ok = false;
8488
8489         fw_version_ok = adev->gfx.cp_fw_write_wait;
8490
8491         if (fw_version_ok)
8492                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8493                                        ref, mask, 0x20);
8494         else
8495                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8496                                                            ref, mask);
8497 }
8498
8499 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8500                                          unsigned vmid)
8501 {
8502         struct amdgpu_device *adev = ring->adev;
8503         uint32_t value = 0;
8504
8505         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8506         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8507         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8508         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8509         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8510 }
8511
8512 static void
8513 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8514                                       uint32_t me, uint32_t pipe,
8515                                       enum amdgpu_interrupt_state state)
8516 {
8517         uint32_t cp_int_cntl, cp_int_cntl_reg;
8518
8519         if (!me) {
8520                 switch (pipe) {
8521                 case 0:
8522                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8523                         break;
8524                 case 1:
8525                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8526                         break;
8527                 default:
8528                         DRM_DEBUG("invalid pipe %d\n", pipe);
8529                         return;
8530                 }
8531         } else {
8532                 DRM_DEBUG("invalid me %d\n", me);
8533                 return;
8534         }
8535
8536         switch (state) {
8537         case AMDGPU_IRQ_STATE_DISABLE:
8538                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8539                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8540                                             TIME_STAMP_INT_ENABLE, 0);
8541                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8542                 break;
8543         case AMDGPU_IRQ_STATE_ENABLE:
8544                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8545                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8546                                             TIME_STAMP_INT_ENABLE, 1);
8547                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8548                 break;
8549         default:
8550                 break;
8551         }
8552 }
8553
8554 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8555                                                      int me, int pipe,
8556                                                      enum amdgpu_interrupt_state state)
8557 {
8558         u32 mec_int_cntl, mec_int_cntl_reg;
8559
8560         /*
8561          * amdgpu controls only the first MEC. That's why this function only
8562          * handles the setting of interrupts for this specific MEC. All other
8563          * pipes' interrupts are set by amdkfd.
8564          */
8565
8566         if (me == 1) {
8567                 switch (pipe) {
8568                 case 0:
8569                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8570                         break;
8571                 case 1:
8572                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8573                         break;
8574                 case 2:
8575                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8576                         break;
8577                 case 3:
8578                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8579                         break;
8580                 default:
8581                         DRM_DEBUG("invalid pipe %d\n", pipe);
8582                         return;
8583                 }
8584         } else {
8585                 DRM_DEBUG("invalid me %d\n", me);
8586                 return;
8587         }
8588
8589         switch (state) {
8590         case AMDGPU_IRQ_STATE_DISABLE:
8591                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8592                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8593                                              TIME_STAMP_INT_ENABLE, 0);
8594                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8595                 break;
8596         case AMDGPU_IRQ_STATE_ENABLE:
8597                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8598                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8599                                              TIME_STAMP_INT_ENABLE, 1);
8600                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8601                 break;
8602         default:
8603                 break;
8604         }
8605 }
8606
8607 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8608                                             struct amdgpu_irq_src *src,
8609                                             unsigned type,
8610                                             enum amdgpu_interrupt_state state)
8611 {
8612         switch (type) {
8613         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8614                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8615                 break;
8616         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8617                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8618                 break;
8619         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8620                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8621                 break;
8622         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8623                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8624                 break;
8625         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8626                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8627                 break;
8628         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8629                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8630                 break;
8631         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8632                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8633                 break;
8634         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8635                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8636                 break;
8637         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8638                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8639                 break;
8640         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8641                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8642                 break;
8643         default:
8644                 break;
8645         }
8646         return 0;
8647 }
8648
8649 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8650                              struct amdgpu_irq_src *source,
8651                              struct amdgpu_iv_entry *entry)
8652 {
8653         int i;
8654         u8 me_id, pipe_id, queue_id;
8655         struct amdgpu_ring *ring;
8656
8657         DRM_DEBUG("IH: CP EOP\n");
8658         me_id = (entry->ring_id & 0x0c) >> 2;
8659         pipe_id = (entry->ring_id & 0x03) >> 0;
8660         queue_id = (entry->ring_id & 0x70) >> 4;
8661
8662         switch (me_id) {
8663         case 0:
8664                 if (pipe_id == 0)
8665                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8666                 else
8667                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8668                 break;
8669         case 1:
8670         case 2:
8671                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8672                         ring = &adev->gfx.compute_ring[i];
8673                         /* Per-queue interrupt is supported for MEC starting from VI.
8674                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8675                           */
8676                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8677                                 amdgpu_fence_process(ring);
8678                 }
8679                 break;
8680         }
8681         return 0;
8682 }
8683
8684 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8685                                               struct amdgpu_irq_src *source,
8686                                               unsigned type,
8687                                               enum amdgpu_interrupt_state state)
8688 {
8689         switch (state) {
8690         case AMDGPU_IRQ_STATE_DISABLE:
8691         case AMDGPU_IRQ_STATE_ENABLE:
8692                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8693                                PRIV_REG_INT_ENABLE,
8694                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8695                 break;
8696         default:
8697                 break;
8698         }
8699
8700         return 0;
8701 }
8702
8703 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8704                                                struct amdgpu_irq_src *source,
8705                                                unsigned type,
8706                                                enum amdgpu_interrupt_state state)
8707 {
8708         switch (state) {
8709         case AMDGPU_IRQ_STATE_DISABLE:
8710         case AMDGPU_IRQ_STATE_ENABLE:
8711                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8712                                PRIV_INSTR_INT_ENABLE,
8713                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8714                 break;
8715         default:
8716                 break;
8717         }
8718
8719         return 0;
8720 }
8721
8722 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8723                                         struct amdgpu_iv_entry *entry)
8724 {
8725         u8 me_id, pipe_id, queue_id;
8726         struct amdgpu_ring *ring;
8727         int i;
8728
8729         me_id = (entry->ring_id & 0x0c) >> 2;
8730         pipe_id = (entry->ring_id & 0x03) >> 0;
8731         queue_id = (entry->ring_id & 0x70) >> 4;
8732
8733         switch (me_id) {
8734         case 0:
8735                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8736                         ring = &adev->gfx.gfx_ring[i];
8737                         /* we only enabled 1 gfx queue per pipe for now */
8738                         if (ring->me == me_id && ring->pipe == pipe_id)
8739                                 drm_sched_fault(&ring->sched);
8740                 }
8741                 break;
8742         case 1:
8743         case 2:
8744                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8745                         ring = &adev->gfx.compute_ring[i];
8746                         if (ring->me == me_id && ring->pipe == pipe_id &&
8747                             ring->queue == queue_id)
8748                                 drm_sched_fault(&ring->sched);
8749                 }
8750                 break;
8751         default:
8752                 BUG();
8753         }
8754 }
8755
8756 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8757                                   struct amdgpu_irq_src *source,
8758                                   struct amdgpu_iv_entry *entry)
8759 {
8760         DRM_ERROR("Illegal register access in command stream\n");
8761         gfx_v10_0_handle_priv_fault(adev, entry);
8762         return 0;
8763 }
8764
8765 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8766                                    struct amdgpu_irq_src *source,
8767                                    struct amdgpu_iv_entry *entry)
8768 {
8769         DRM_ERROR("Illegal instruction in command stream\n");
8770         gfx_v10_0_handle_priv_fault(adev, entry);
8771         return 0;
8772 }
8773
8774 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8775                                              struct amdgpu_irq_src *src,
8776                                              unsigned int type,
8777                                              enum amdgpu_interrupt_state state)
8778 {
8779         uint32_t tmp, target;
8780         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8781
8782         if (ring->me == 1)
8783                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8784         else
8785                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8786         target += ring->pipe;
8787
8788         switch (type) {
8789         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8790                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8791                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8792                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8793                                             GENERIC2_INT_ENABLE, 0);
8794                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8795
8796                         tmp = RREG32(target);
8797                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8798                                             GENERIC2_INT_ENABLE, 0);
8799                         WREG32(target, tmp);
8800                 } else {
8801                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8802                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8803                                             GENERIC2_INT_ENABLE, 1);
8804                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8805
8806                         tmp = RREG32(target);
8807                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8808                                             GENERIC2_INT_ENABLE, 1);
8809                         WREG32(target, tmp);
8810                 }
8811                 break;
8812         default:
8813                 BUG(); /* kiq only support GENERIC2_INT now */
8814                 break;
8815         }
8816         return 0;
8817 }
8818
8819 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8820                              struct amdgpu_irq_src *source,
8821                              struct amdgpu_iv_entry *entry)
8822 {
8823         u8 me_id, pipe_id, queue_id;
8824         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8825
8826         me_id = (entry->ring_id & 0x0c) >> 2;
8827         pipe_id = (entry->ring_id & 0x03) >> 0;
8828         queue_id = (entry->ring_id & 0x70) >> 4;
8829         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8830                    me_id, pipe_id, queue_id);
8831
8832         amdgpu_fence_process(ring);
8833         return 0;
8834 }
8835
8836 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8837 {
8838         const unsigned int gcr_cntl =
8839                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8840                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8841                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8842                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8843                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8844                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8845                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8846                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8847
8848         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8849         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8850         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8851         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8852         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8853         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8854         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8855         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8856         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8857 }
8858
8859 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8860         .name = "gfx_v10_0",
8861         .early_init = gfx_v10_0_early_init,
8862         .late_init = gfx_v10_0_late_init,
8863         .sw_init = gfx_v10_0_sw_init,
8864         .sw_fini = gfx_v10_0_sw_fini,
8865         .hw_init = gfx_v10_0_hw_init,
8866         .hw_fini = gfx_v10_0_hw_fini,
8867         .suspend = gfx_v10_0_suspend,
8868         .resume = gfx_v10_0_resume,
8869         .is_idle = gfx_v10_0_is_idle,
8870         .wait_for_idle = gfx_v10_0_wait_for_idle,
8871         .soft_reset = gfx_v10_0_soft_reset,
8872         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8873         .set_powergating_state = gfx_v10_0_set_powergating_state,
8874         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8875 };
8876
8877 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8878         .type = AMDGPU_RING_TYPE_GFX,
8879         .align_mask = 0xff,
8880         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8881         .support_64bit_ptrs = true,
8882         .vmhub = AMDGPU_GFXHUB_0,
8883         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8884         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8885         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8886         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8887                 5 + /* COND_EXEC */
8888                 7 + /* PIPELINE_SYNC */
8889                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8890                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8891                 2 + /* VM_FLUSH */
8892                 8 + /* FENCE for VM_FLUSH */
8893                 20 + /* GDS switch */
8894                 4 + /* double SWITCH_BUFFER,
8895                      * the first COND_EXEC jump to the place
8896                      * just prior to this double SWITCH_BUFFER
8897                      */
8898                 5 + /* COND_EXEC */
8899                 7 + /* HDP_flush */
8900                 4 + /* VGT_flush */
8901                 14 + /* CE_META */
8902                 31 + /* DE_META */
8903                 3 + /* CNTX_CTRL */
8904                 5 + /* HDP_INVL */
8905                 8 + 8 + /* FENCE x2 */
8906                 2 + /* SWITCH_BUFFER */
8907                 8, /* gfx_v10_0_emit_mem_sync */
8908         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8909         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8910         .emit_fence = gfx_v10_0_ring_emit_fence,
8911         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8912         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8913         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8914         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8915         .test_ring = gfx_v10_0_ring_test_ring,
8916         .test_ib = gfx_v10_0_ring_test_ib,
8917         .insert_nop = amdgpu_ring_insert_nop,
8918         .pad_ib = amdgpu_ring_generic_pad_ib,
8919         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8920         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8921         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8922         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8923         .preempt_ib = gfx_v10_0_ring_preempt_ib,
8924         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8925         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8926         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8927         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8928         .soft_recovery = gfx_v10_0_ring_soft_recovery,
8929         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8930 };
8931
8932 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8933         .type = AMDGPU_RING_TYPE_COMPUTE,
8934         .align_mask = 0xff,
8935         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8936         .support_64bit_ptrs = true,
8937         .vmhub = AMDGPU_GFXHUB_0,
8938         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8939         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8940         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8941         .emit_frame_size =
8942                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8943                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8944                 5 + /* hdp invalidate */
8945                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8946                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8947                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8948                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8949                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8950                 8, /* gfx_v10_0_emit_mem_sync */
8951         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8952         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8953         .emit_fence = gfx_v10_0_ring_emit_fence,
8954         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8955         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8956         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8957         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8958         .test_ring = gfx_v10_0_ring_test_ring,
8959         .test_ib = gfx_v10_0_ring_test_ib,
8960         .insert_nop = amdgpu_ring_insert_nop,
8961         .pad_ib = amdgpu_ring_generic_pad_ib,
8962         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8963         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8964         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8965         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8966 };
8967
8968 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8969         .type = AMDGPU_RING_TYPE_KIQ,
8970         .align_mask = 0xff,
8971         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8972         .support_64bit_ptrs = true,
8973         .vmhub = AMDGPU_GFXHUB_0,
8974         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8975         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8976         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8977         .emit_frame_size =
8978                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8979                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8980                 5 + /*hdp invalidate */
8981                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8982                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8983                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8984                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8985                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8986         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8987         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8988         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8989         .test_ring = gfx_v10_0_ring_test_ring,
8990         .test_ib = gfx_v10_0_ring_test_ib,
8991         .insert_nop = amdgpu_ring_insert_nop,
8992         .pad_ib = amdgpu_ring_generic_pad_ib,
8993         .emit_rreg = gfx_v10_0_ring_emit_rreg,
8994         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8995         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8996         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8997 };
8998
8999 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9000 {
9001         int i;
9002
9003         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9004
9005         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9006                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9007
9008         for (i = 0; i < adev->gfx.num_compute_rings; i++)
9009                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9010 }
9011
9012 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9013         .set = gfx_v10_0_set_eop_interrupt_state,
9014         .process = gfx_v10_0_eop_irq,
9015 };
9016
9017 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9018         .set = gfx_v10_0_set_priv_reg_fault_state,
9019         .process = gfx_v10_0_priv_reg_irq,
9020 };
9021
9022 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9023         .set = gfx_v10_0_set_priv_inst_fault_state,
9024         .process = gfx_v10_0_priv_inst_irq,
9025 };
9026
9027 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9028         .set = gfx_v10_0_kiq_set_interrupt_state,
9029         .process = gfx_v10_0_kiq_irq,
9030 };
9031
9032 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9033 {
9034         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9035         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9036
9037         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9038         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9039
9040         adev->gfx.priv_reg_irq.num_types = 1;
9041         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9042
9043         adev->gfx.priv_inst_irq.num_types = 1;
9044         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9045 }
9046
9047 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9048 {
9049         switch (adev->asic_type) {
9050         case CHIP_NAVI10:
9051         case CHIP_NAVI14:
9052         case CHIP_SIENNA_CICHLID:
9053         case CHIP_NAVY_FLOUNDER:
9054         case CHIP_VANGOGH:
9055         case CHIP_DIMGREY_CAVEFISH:
9056                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9057                 break;
9058         case CHIP_NAVI12:
9059                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9060                 break;
9061         default:
9062                 break;
9063         }
9064 }
9065
9066 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9067 {
9068         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9069                             adev->gfx.config.max_sh_per_se *
9070                             adev->gfx.config.max_shader_engines;
9071
9072         adev->gds.gds_size = 0x10000;
9073         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9074         adev->gds.gws_size = 64;
9075         adev->gds.oa_size = 16;
9076 }
9077
9078 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9079                                                           u32 bitmap)
9080 {
9081         u32 data;
9082
9083         if (!bitmap)
9084                 return;
9085
9086         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9087         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9088
9089         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9090 }
9091
9092 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9093 {
9094         u32 data, wgp_bitmask;
9095         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9096         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9097
9098         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9099         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9100
9101         wgp_bitmask =
9102                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9103
9104         return (~data) & wgp_bitmask;
9105 }
9106
9107 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9108 {
9109         u32 wgp_idx, wgp_active_bitmap;
9110         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9111
9112         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9113         cu_active_bitmap = 0;
9114
9115         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9116                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9117                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9118                 if (wgp_active_bitmap & (1 << wgp_idx))
9119                         cu_active_bitmap |= cu_bitmap_per_wgp;
9120         }
9121
9122         return cu_active_bitmap;
9123 }
9124
9125 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9126                                  struct amdgpu_cu_info *cu_info)
9127 {
9128         int i, j, k, counter, active_cu_number = 0;
9129         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9130         unsigned disable_masks[4 * 2];
9131
9132         if (!adev || !cu_info)
9133                 return -EINVAL;
9134
9135         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9136
9137         mutex_lock(&adev->grbm_idx_mutex);
9138         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9139                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9140                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9141                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
9142                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9143                                 continue;
9144                         mask = 1;
9145                         ao_bitmap = 0;
9146                         counter = 0;
9147                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9148                         if (i < 4 && j < 2)
9149                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9150                                         adev, disable_masks[i * 2 + j]);
9151                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9152                         cu_info->bitmap[i][j] = bitmap;
9153
9154                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9155                                 if (bitmap & mask) {
9156                                         if (counter < adev->gfx.config.max_cu_per_sh)
9157                                                 ao_bitmap |= mask;
9158                                         counter++;
9159                                 }
9160                                 mask <<= 1;
9161                         }
9162                         active_cu_number += counter;
9163                         if (i < 2 && j < 2)
9164                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9165                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9166                 }
9167         }
9168         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9169         mutex_unlock(&adev->grbm_idx_mutex);
9170
9171         cu_info->number = active_cu_number;
9172         cu_info->ao_cu_mask = ao_cu_mask;
9173         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9174
9175         return 0;
9176 }
9177
9178 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9179 {
9180         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9181
9182         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9183         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9184         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9185
9186         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9187         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9188         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9189
9190         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9191                                                 adev->gfx.config.max_shader_engines);
9192         disabled_sa = efuse_setting | vbios_setting;
9193         disabled_sa &= max_sa_mask;
9194
9195         return disabled_sa;
9196 }
9197
9198 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9199 {
9200         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9201         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9202
9203         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9204
9205         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9206         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9207         max_shader_engines = adev->gfx.config.max_shader_engines;
9208
9209         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9210                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9211                 disabled_sa_per_se &= max_sa_per_se_mask;
9212                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9213                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9214                         break;
9215                 }
9216         }
9217 }
9218
9219 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9220 {
9221         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9222                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9223                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9224                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9225
9226         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9227         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9228                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9229                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9230                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9231                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9232
9233         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9234                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9235                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9236                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9237
9238         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9239
9240         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9241                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9242 }
9243
9244 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9245 {
9246         .type = AMD_IP_BLOCK_TYPE_GFX,
9247         .major = 10,
9248         .minor = 0,
9249         .rev = 0,
9250         .funcs = &gfx_v10_0_ip_funcs,
9251 };