drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_uvd.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "soc15_common.h"
  31 #include "mmsch_v1_0.h"
  32
  33 #include "uvd/uvd_7_0_offset.h"
  34 #include "uvd/uvd_7_0_sh_mask.h"
  35 #include "vce/vce_4_0_offset.h"
  36 #include "vce/vce_4_0_default.h"
  37 #include "vce/vce_4_0_sh_mask.h"
  38 #include "nbif/nbif_6_1_offset.h"
  39 #include "hdp/hdp_4_0_offset.h"
  40 #include "mmhub/mmhub_1_0_offset.h"
  41 #include "mmhub/mmhub_1_0_sh_mask.h"
  42 #include "ivsrcid/uvd/irqsrcs_uvd_7_0.h"
  43
  44 #define mmUVD_PG0_CC_UVD_HARVESTING                                                                    0x00c7
  45 #define mmUVD_PG0_CC_UVD_HARVESTING_BASE_IDX                                                           1
  46 //UVD_PG0_CC_UVD_HARVESTING
  47 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE__SHIFT                                                         0x1
  48 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK                                                           0x00000002L
  49
  50 #define UVD7_MAX_HW_INSTANCES_VEGA20                    2
  51
  52 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  53 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  54 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  55 static int uvd_v7_0_start(struct amdgpu_device *adev);
  56 static void uvd_v7_0_stop(struct amdgpu_device *adev);
  57 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev);
  58
  59 static int amdgpu_ih_clientid_uvds[] = {
  60         SOC15_IH_CLIENTID_UVD,
  61         SOC15_IH_CLIENTID_UVD1
  62 };
  63
  64 /**
  65  * uvd_v7_0_ring_get_rptr - get read pointer
  66  *
  67  * @ring: amdgpu_ring pointer
  68  *
  69  * Returns the current hardware read pointer
  70  */
  71 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
  72 {
  73         struct amdgpu_device *adev = ring->adev;
  74
  75         return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
  76 }
  77
  78 /**
  79  * uvd_v7_0_enc_ring_get_rptr - get enc read pointer
  80  *
  81  * @ring: amdgpu_ring pointer
  82  *
  83  * Returns the current hardware enc read pointer
  84  */
  85 static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
  86 {
  87         struct amdgpu_device *adev = ring->adev;
  88
  89         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
  90                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
  91         else
  92                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);
  93 }
  94
  95 /**
  96  * uvd_v7_0_ring_get_wptr - get write pointer
  97  *
  98  * @ring: amdgpu_ring pointer
  99  *
 100  * Returns the current hardware write pointer
 101  */
 102 static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring)
 103 {
 104         struct amdgpu_device *adev = ring->adev;
 105
 106         return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
 107 }
 108
 109 /**
 110  * uvd_v7_0_enc_ring_get_wptr - get enc write pointer
 111  *
 112  * @ring: amdgpu_ring pointer
 113  *
 114  * Returns the current hardware enc write pointer
 115  */
 116 static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 117 {
 118         struct amdgpu_device *adev = ring->adev;
 119
 120         if (ring->use_doorbell)
 121                 return adev->wb.wb[ring->wptr_offs];
 122
 123         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
 124                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);
 125         else
 126                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);
 127 }
 128
 129 /**
 130  * uvd_v7_0_ring_set_wptr - set write pointer
 131  *
 132  * @ring: amdgpu_ring pointer
 133  *
 134  * Commits the write pointer to the hardware
 135  */
 136 static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring)
 137 {
 138         struct amdgpu_device *adev = ring->adev;
 139
 140         WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 141 }
 142
 143 /**
 144  * uvd_v7_0_enc_ring_set_wptr - set enc write pointer
 145  *
 146  * @ring: amdgpu_ring pointer
 147  *
 148  * Commits the enc write pointer to the hardware
 149  */
 150 static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 151 {
 152         struct amdgpu_device *adev = ring->adev;
 153
 154         if (ring->use_doorbell) {
 155                 /* XXX check if swapping is necessary on BE */
 156                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
 157                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 158                 return;
 159         }
 160
 161         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
 162                 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR,
 163                         lower_32_bits(ring->wptr));
 164         else
 165                 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2,
 166                         lower_32_bits(ring->wptr));
 167 }
 168
 169 /**
 170  * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working
 171  *
 172  * @ring: the engine to test on
 173  *
 174  */
 175 static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
 176 {
 177         struct amdgpu_device *adev = ring->adev;
 178         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 179         unsigned i;
 180         int r;
 181
 182         if (amdgpu_sriov_vf(adev))
 183                 return 0;
 184
 185         r = amdgpu_ring_alloc(ring, 16);
 186         if (r)
 187                 return r;
 188         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
 189         amdgpu_ring_commit(ring);
 190
 191         for (i = 0; i < adev->usec_timeout; i++) {
 192                 if (amdgpu_ring_get_rptr(ring) != rptr)
 193                         break;
 194                 DRM_UDELAY(1);
 195         }
 196
 197         if (i >= adev->usec_timeout)
 198                 r = -ETIMEDOUT;
 199
 200         return r;
 201 }
 202
 203 /**
 204  * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg
 205  *
 206  * @adev: amdgpu_device pointer
 207  * @ring: ring we should submit the msg to
 208  * @handle: session handle to use
 209  * @fence: optional fence to return
 210  *
 211  * Open up a stream for HW test
 212  */
 213 static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 214                                        struct dma_fence **fence)
 215 {
 216         const unsigned ib_size_dw = 16;
 217         struct amdgpu_job *job;
 218         struct amdgpu_ib *ib;
 219         struct dma_fence *f = NULL;
 220         uint64_t dummy;
 221         int i, r;
 222
 223         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 224         if (r)
 225                 return r;
 226
 227         ib = &job->ibs[0];
 228         dummy = ib->gpu_addr + 1024;
 229
 230         ib->length_dw = 0;
 231         ib->ptr[ib->length_dw++] = 0x00000018;
 232         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 233         ib->ptr[ib->length_dw++] = handle;
 234         ib->ptr[ib->length_dw++] = 0x00000000;
 235         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 236         ib->ptr[ib->length_dw++] = dummy;
 237
 238         ib->ptr[ib->length_dw++] = 0x00000014;
 239         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 240         ib->ptr[ib->length_dw++] = 0x0000001c;
 241         ib->ptr[ib->length_dw++] = 0x00000000;
 242         ib->ptr[ib->length_dw++] = 0x00000000;
 243
 244         ib->ptr[ib->length_dw++] = 0x00000008;
 245         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 246
 247         for (i = ib->length_dw; i < ib_size_dw; ++i)
 248                 ib->ptr[i] = 0x0;
 249
 250         r = amdgpu_job_submit_direct(job, ring, &f);
 251         if (r)
 252                 goto err;
 253
 254         if (fence)
 255                 *fence = dma_fence_get(f);
 256         dma_fence_put(f);
 257         return 0;
 258
 259 err:
 260         amdgpu_job_free(job);
 261         return r;
 262 }
 263
 264 /**
 265  * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
 266  *
 267  * @adev: amdgpu_device pointer
 268  * @ring: ring we should submit the msg to
 269  * @handle: session handle to use
 270  * @fence: optional fence to return
 271  *
 272  * Close up a stream for HW test or if userspace failed to do so
 273  */
 274 static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 275                                 struct dma_fence **fence)
 276 {
 277         const unsigned ib_size_dw = 16;
 278         struct amdgpu_job *job;
 279         struct amdgpu_ib *ib;
 280         struct dma_fence *f = NULL;
 281         uint64_t dummy;
 282         int i, r;
 283
 284         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 285         if (r)
 286                 return r;
 287
 288         ib = &job->ibs[0];
 289         dummy = ib->gpu_addr + 1024;
 290
 291         ib->length_dw = 0;
 292         ib->ptr[ib->length_dw++] = 0x00000018;
 293         ib->ptr[ib->length_dw++] = 0x00000001;
 294         ib->ptr[ib->length_dw++] = handle;
 295         ib->ptr[ib->length_dw++] = 0x00000000;
 296         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 297         ib->ptr[ib->length_dw++] = dummy;
 298
 299         ib->ptr[ib->length_dw++] = 0x00000014;
 300         ib->ptr[ib->length_dw++] = 0x00000002;
 301         ib->ptr[ib->length_dw++] = 0x0000001c;
 302         ib->ptr[ib->length_dw++] = 0x00000000;
 303         ib->ptr[ib->length_dw++] = 0x00000000;
 304
 305         ib->ptr[ib->length_dw++] = 0x00000008;
 306         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 307
 308         for (i = ib->length_dw; i < ib_size_dw; ++i)
 309                 ib->ptr[i] = 0x0;
 310
 311         r = amdgpu_job_submit_direct(job, ring, &f);
 312         if (r)
 313                 goto err;
 314
 315         if (fence)
 316                 *fence = dma_fence_get(f);
 317         dma_fence_put(f);
 318         return 0;
 319
 320 err:
 321         amdgpu_job_free(job);
 322         return r;
 323 }
 324
 325 /**
 326  * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working
 327  *
 328  * @ring: the engine to test on
 329  *
 330  */
 331 static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 332 {
 333         struct dma_fence *fence = NULL;
 334         long r;
 335
 336         r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL);
 337         if (r) {
 338                 DRM_ERROR("amdgpu: (%d)failed to get create msg (%ld).\n", ring->me, r);
 339                 goto error;
 340         }
 341
 342         r = uvd_v7_0_enc_get_destroy_msg(ring, 1, &fence);
 343         if (r) {
 344                 DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n", ring->me, r);
 345                 goto error;
 346         }
 347
 348         r = dma_fence_wait_timeout(fence, false, timeout);
 349         if (r == 0) {
 350                 DRM_ERROR("amdgpu: (%d)IB test timed out.\n", ring->me);
 351                 r = -ETIMEDOUT;
 352         } else if (r < 0) {
 353                 DRM_ERROR("amdgpu: (%d)fence wait failed (%ld).\n", ring->me, r);
 354         } else {
 355                 DRM_DEBUG("ib test on (%d)ring %d succeeded\n", ring->me, ring->idx);
 356                 r = 0;
 357         }
 358 error:
 359         dma_fence_put(fence);
 360         return r;
 361 }
 362
 363 static int uvd_v7_0_early_init(void *handle)
 364 {
 365         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 366
 367         if (adev->asic_type == CHIP_VEGA20) {
 368                 u32 harvest;
 369                 int i;
 370
 371                 adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20;
 372                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 373                         harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING);
 374                         if (harvest & UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK) {
 375                                 adev->uvd.harvest_config |= 1 << i;
 376                         }
 377                 }
 378                 if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 |
 379                                                  AMDGPU_UVD_HARVEST_UVD1))
 380                         /* both instances are harvested, disable the block */
 381                         return -ENOENT;
 382         } else {
 383                 adev->uvd.num_uvd_inst = 1;
 384         }
 385
 386         if (amdgpu_sriov_vf(adev))
 387                 adev->uvd.num_enc_rings = 1;
 388         else
 389                 adev->uvd.num_enc_rings = 2;
 390         uvd_v7_0_set_ring_funcs(adev);
 391         uvd_v7_0_set_enc_ring_funcs(adev);
 392         uvd_v7_0_set_irq_funcs(adev);
 393
 394         return 0;
 395 }
 396
 397 static int uvd_v7_0_sw_init(void *handle)
 398 {
 399         struct amdgpu_ring *ring;
 400
 401         int i, j, r;
 402         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 403
 404         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 405                 if (adev->uvd.harvest_config & (1 << j))
 406                         continue;
 407                 /* UVD TRAP */
 408                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq);
 409                 if (r)
 410                         return r;
 411
 412                 /* UVD ENC TRAP */
 413                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 414                         r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq);
 415                         if (r)
 416                                 return r;
 417                 }
 418         }
 419
 420         r = amdgpu_uvd_sw_init(adev);
 421         if (r)
 422                 return r;
 423
 424         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 425                 const struct common_firmware_header *hdr;
 426                 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 427                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD;
 428                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
 429                 adev->firmware.fw_size +=
 430                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 431
 432                 if (adev->uvd.num_uvd_inst == UVD7_MAX_HW_INSTANCES_VEGA20) {
 433                         adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].ucode_id = AMDGPU_UCODE_ID_UVD1;
 434                         adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].fw = adev->uvd.fw;
 435                         adev->firmware.fw_size +=
 436                                 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 437                 }
 438                 DRM_INFO("PSP loading UVD firmware\n");
 439         }
 440
 441         r = amdgpu_uvd_resume(adev);
 442         if (r)
 443                 return r;
 444
 445         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 446                 if (adev->uvd.harvest_config & (1 << j))
 447                         continue;
 448                 if (!amdgpu_sriov_vf(adev)) {
 449                         ring = &adev->uvd.inst[j].ring;
 450                         sprintf(ring->name, "uvd<%d>", j);
 451                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
 452                         if (r)
 453                                 return r;
 454                 }
 455
 456                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 457                         ring = &adev->uvd.inst[j].ring_enc[i];
 458                         sprintf(ring->name, "uvd_enc%d<%d>", i, j);
 459                         if (amdgpu_sriov_vf(adev)) {
 460                                 ring->use_doorbell = true;
 461
 462                                 /* currently only use the first enconding ring for
 463                                  * sriov, so set unused location for other unused rings.
 464                                  */
 465                                 if (i == 0)
 466                                         ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
 467                                 else
 468                                         ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1;
 469                         }
 470                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
 471                         if (r)
 472                                 return r;
 473                 }
 474         }
 475
 476         r = amdgpu_uvd_entity_init(adev);
 477         if (r)
 478                 return r;
 479
 480         r = amdgpu_virt_alloc_mm_table(adev);
 481         if (r)
 482                 return r;
 483
 484         return r;
 485 }
 486
 487 static int uvd_v7_0_sw_fini(void *handle)
 488 {
 489         int i, j, r;
 490         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 491
 492         amdgpu_virt_free_mm_table(adev);
 493
 494         r = amdgpu_uvd_suspend(adev);
 495         if (r)
 496                 return r;
 497
 498         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 499                 if (adev->uvd.harvest_config & (1 << j))
 500                         continue;
 501                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 502                         amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
 503         }
 504         return amdgpu_uvd_sw_fini(adev);
 505 }
 506
 507 /**
 508  * uvd_v7_0_hw_init - start and test UVD block
 509  *
 510  * @adev: amdgpu_device pointer
 511  *
 512  * Initialize the hardware, boot up the VCPU and do some testing
 513  */
 514 static int uvd_v7_0_hw_init(void *handle)
 515 {
 516         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 517         struct amdgpu_ring *ring;
 518         uint32_t tmp;
 519         int i, j, r;
 520
 521         if (amdgpu_sriov_vf(adev))
 522                 r = uvd_v7_0_sriov_start(adev);
 523         else
 524                 r = uvd_v7_0_start(adev);
 525         if (r)
 526                 goto done;
 527
 528         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 529                 if (adev->uvd.harvest_config & (1 << j))
 530                         continue;
 531                 ring = &adev->uvd.inst[j].ring;
 532
 533                 if (!amdgpu_sriov_vf(adev)) {
 534                         r = amdgpu_ring_test_helper(ring);
 535                         if (r)
 536                                 goto done;
 537
 538                         r = amdgpu_ring_alloc(ring, 10);
 539                         if (r) {
 540                                 DRM_ERROR("amdgpu: (%d)ring failed to lock UVD ring (%d).\n", j, r);
 541                                 goto done;
 542                         }
 543
 544                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 545                                 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);
 546                         amdgpu_ring_write(ring, tmp);
 547                         amdgpu_ring_write(ring, 0xFFFFF);
 548
 549                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 550                                 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);
 551                         amdgpu_ring_write(ring, tmp);
 552                         amdgpu_ring_write(ring, 0xFFFFF);
 553
 554                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 555                                 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);
 556                         amdgpu_ring_write(ring, tmp);
 557                         amdgpu_ring_write(ring, 0xFFFFF);
 558
 559                         /* Clear timeout status bits */
 560                         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
 561                                 mmUVD_SEMA_TIMEOUT_STATUS), 0));
 562                         amdgpu_ring_write(ring, 0x8);
 563
 564                         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
 565                                 mmUVD_SEMA_CNTL), 0));
 566                         amdgpu_ring_write(ring, 3);
 567
 568                         amdgpu_ring_commit(ring);
 569                 }
 570
 571                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 572                         ring = &adev->uvd.inst[j].ring_enc[i];
 573                         r = amdgpu_ring_test_helper(ring);
 574                         if (r)
 575                                 goto done;
 576                 }
 577         }
 578 done:
 579         if (!r)
 580                 DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 581
 582         return r;
 583 }
 584
 585 /**
 586  * uvd_v7_0_hw_fini - stop the hardware block
 587  *
 588  * @adev: amdgpu_device pointer
 589  *
 590  * Stop the UVD block, mark ring as not ready any more
 591  */
 592 static int uvd_v7_0_hw_fini(void *handle)
 593 {
 594         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 595         int i;
 596
 597         if (!amdgpu_sriov_vf(adev))
 598                 uvd_v7_0_stop(adev);
 599         else {
 600                 /* full access mode, so don't touch any UVD register */
 601                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
 602         }
 603
 604         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 605                 if (adev->uvd.harvest_config & (1 << i))
 606                         continue;
 607                 adev->uvd.inst[i].ring.sched.ready = false;
 608         }
 609
 610         return 0;
 611 }
 612
 613 static int uvd_v7_0_suspend(void *handle)
 614 {
 615         int r;
 616         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 617
 618         r = uvd_v7_0_hw_fini(adev);
 619         if (r)
 620                 return r;
 621
 622         return amdgpu_uvd_suspend(adev);
 623 }
 624
 625 static int uvd_v7_0_resume(void *handle)
 626 {
 627         int r;
 628         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 629
 630         r = amdgpu_uvd_resume(adev);
 631         if (r)
 632                 return r;
 633
 634         return uvd_v7_0_hw_init(adev);
 635 }
 636
 637 /**
 638  * uvd_v7_0_mc_resume - memory controller programming
 639  *
 640  * @adev: amdgpu_device pointer
 641  *
 642  * Let the UVD memory controller know it's offsets
 643  */
 644 static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
 645 {
 646         uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
 647         uint32_t offset;
 648         int i;
 649
 650         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 651                 if (adev->uvd.harvest_config & (1 << i))
 652                         continue;
 653                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 654                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 655                                 i == 0 ?
 656                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo:
 657                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_lo);
 658                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 659                                 i == 0 ?
 660                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi:
 661                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_hi);
 662                         WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
 663                         offset = 0;
 664                 } else {
 665                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 666                                 lower_32_bits(adev->uvd.inst[i].gpu_addr));
 667                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 668                                 upper_32_bits(adev->uvd.inst[i].gpu_addr));
 669                         offset = size;
 670                         WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
 671                                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 672                 }
 673
 674                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
 675
 676                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 677                                 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 678                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 679                                 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 680                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));
 681                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE);
 682
 683                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 684                                 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 685                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 686                                 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 687                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));
 688                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2,
 689                                 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 690
 691                 WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG,
 692                                 adev->gfx.config.gb_addr_config);
 693                 WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG,
 694                                 adev->gfx.config.gb_addr_config);
 695                 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG,
 696                                 adev->gfx.config.gb_addr_config);
 697
 698                 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 699         }
 700 }
 701
 702 static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
 703                                 struct amdgpu_mm_table *table)
 704 {
 705         uint32_t data = 0, loop;
 706         uint64_t addr = table->gpu_addr;
 707         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr;
 708         uint32_t size;
 709         int i;
 710
 711         size = header->header_size + header->vce_table_size + header->uvd_table_size;
 712
 713         /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */
 714         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
 715         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
 716
 717         /* 2, update vmid of descriptor */
 718         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID);
 719         data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK;
 720         data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */
 721         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data);
 722
 723         /* 3, notify mmsch about the size of this descriptor */
 724         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size);
 725
 726         /* 4, set resp to zero */
 727         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
 728
 729         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 730                 if (adev->uvd.harvest_config & (1 << i))
 731                         continue;
 732                 WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0);
 733                 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0;
 734                 adev->uvd.inst[i].ring_enc[0].wptr = 0;
 735                 adev->uvd.inst[i].ring_enc[0].wptr_old = 0;
 736         }
 737         /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
 738         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);
 739
 740         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 741         loop = 1000;
 742         while ((data & 0x10000002) != 0x10000002) {
 743                 udelay(10);
 744                 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 745                 loop--;
 746                 if (!loop)
 747                         break;
 748         }
 749
 750         if (!loop) {
 751                 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
 752                 return -EBUSY;
 753         }
 754
 755         return 0;
 756 }
 757
 758 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
 759 {
 760         struct amdgpu_ring *ring;
 761         uint32_t offset, size, tmp;
 762         uint32_t table_size = 0;
 763         struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} };
 764         struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
 765         struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} };
 766         struct mmsch_v1_0_cmd_end end = { {0} };
 767         uint32_t *init_table = adev->virt.mm_table.cpu_addr;
 768         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table;
 769         uint8_t i = 0;
 770
 771         direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
 772         direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
 773         direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING;
 774         end.cmd_header.command_type = MMSCH_COMMAND__END;
 775
 776         if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) {
 777                 header->version = MMSCH_VERSION;
 778                 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2;
 779
 780                 if (header->vce_table_offset == 0 && header->vce_table_size == 0)
 781                         header->uvd_table_offset = header->header_size;
 782                 else
 783                         header->uvd_table_offset = header->vce_table_size + header->vce_table_offset;
 784
 785                 init_table += header->uvd_table_offset;
 786
 787                 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 788                         if (adev->uvd.harvest_config & (1 << i))
 789                                 continue;
 790                         ring = &adev->uvd.inst[i].ring;
 791                         ring->wptr = 0;
 792                         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 793
 794                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
 795                                                            0xFFFFFFFF, 0x00000004);
 796                         /* mc resume*/
 797                         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 798                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 799                                                             lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 800                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 801                                                             upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 802                                 offset = 0;
 803                         } else {
 804                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 805                                                             lower_32_bits(adev->uvd.inst[i].gpu_addr));
 806                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 807                                                             upper_32_bits(adev->uvd.inst[i].gpu_addr));
 808                                 offset = size;
 809                         }
 810
 811                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
 812                                                     AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 813                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);
 814
 815                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 816                                                     lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 817                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 818                                                     upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 819                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
 820                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
 821
 822                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 823                                                     lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 824                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 825                                                     upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 826                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
 827                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
 828                                                     AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 829
 830                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
 831                         /* mc resume end*/
 832
 833                         /* disable clock gating */
 834                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL),
 835                                                            ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0);
 836
 837                         /* disable interupt */
 838                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
 839                                                            ~UVD_MASTINT_EN__VCPU_EN_MASK, 0);
 840
 841                         /* stall UMC and register bus before resetting VCPU */
 842                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
 843                                                            ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 844                                                            UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 845
 846                         /* put LMI, VCPU, RBC etc... into reset */
 847                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
 848                                                     (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 849                                                                UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 850                                                                UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 851                                                                UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 852                                                                UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 853                                                                UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 854                                                                UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 855                                                                UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK));
 856
 857                         /* initialize UVD memory controller */
 858                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),
 859                                                     (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 860                                                                UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 861                                                                UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 862                                                                UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 863                                                                UVD_LMI_CTRL__REQ_MODE_MASK |
 864                                                                0x00100000L));
 865
 866                         /* take all subblocks out of reset, except VCPU */
 867                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
 868                                                     UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 869
 870                         /* enable VCPU clock */
 871                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
 872                                                     UVD_VCPU_CNTL__CLK_EN_MASK);
 873
 874                         /* enable master interrupt */
 875                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
 876                                                            ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 877                                                            (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 878
 879                         /* clear the bit 4 of UVD_STATUS */
 880                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
 881                                                            ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0);
 882
 883                         /* force RBC into idle state */
 884                         size = order_base_2(ring->ring_size);
 885                         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
 886                         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 887                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
 888
 889                         ring = &adev->uvd.inst[i].ring_enc[0];
 890                         ring->wptr = 0;
 891                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr);
 892                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
 893                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4);
 894
 895                         /* boot up the VCPU */
 896                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0);
 897
 898                         /* enable UMC */
 899                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
 900                                                                                            ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
 901
 902                         MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02);
 903                 }
 904                 /* add end packet */
 905                 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
 906                 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
 907                 header->uvd_table_size = table_size;
 908
 909         }
 910         return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table);
 911 }
 912
 913 /**
 914  * uvd_v7_0_start - start UVD block
 915  *
 916  * @adev: amdgpu_device pointer
 917  *
 918  * Setup and start the UVD block
 919  */
 920 static int uvd_v7_0_start(struct amdgpu_device *adev)
 921 {
 922         struct amdgpu_ring *ring;
 923         uint32_t rb_bufsz, tmp;
 924         uint32_t lmi_swap_cntl;
 925         uint32_t mp_swap_cntl;
 926         int i, j, k, r;
 927
 928         for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
 929                 if (adev->uvd.harvest_config & (1 << k))
 930                         continue;
 931                 /* disable DPG */
 932                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,
 933                                 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 934         }
 935
 936         /* disable byte swapping */
 937         lmi_swap_cntl = 0;
 938         mp_swap_cntl = 0;
 939
 940         uvd_v7_0_mc_resume(adev);
 941
 942         for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
 943                 if (adev->uvd.harvest_config & (1 << k))
 944                         continue;
 945                 ring = &adev->uvd.inst[k].ring;
 946                 /* disable clock gating */
 947                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,
 948                                 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
 949
 950                 /* disable interupt */
 951                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,
 952                                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
 953
 954                 /* stall UMC and register bus before resetting VCPU */
 955                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),
 956                                 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 957                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 958                 mdelay(1);
 959
 960                 /* put LMI, VCPU, RBC etc... into reset */
 961                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
 962                         UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 963                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 964                         UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 965                         UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 966                         UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 967                         UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 968                         UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 969                         UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 970                 mdelay(5);
 971
 972                 /* initialize UVD memory controller */
 973                 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL,
 974                         (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 975                         UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 976                         UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 977                         UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 978                         UVD_LMI_CTRL__REQ_MODE_MASK |
 979                         0x00100000L);
 980
 981 #ifdef __BIG_ENDIAN
 982                 /* swap (8 in 32) RB and IB */
 983                 lmi_swap_cntl = 0xa;
 984                 mp_swap_cntl = 0;
 985 #endif
 986                 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 987                 WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 988
 989                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040);
 990                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0);
 991                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040);
 992                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0);
 993                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0);
 994                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88);
 995
 996                 /* take all subblocks out of reset, except VCPU */
 997                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
 998                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 999                 mdelay(5);
1000
1001                 /* enable VCPU clock */
1002                 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL,
1003                                 UVD_VCPU_CNTL__CLK_EN_MASK);
1004
1005                 /* enable UMC */
1006                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,
1007                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1008
1009                 /* boot up the VCPU */
1010                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0);
1011                 mdelay(10);
1012
1013                 for (i = 0; i < 10; ++i) {
1014                         uint32_t status;
1015
1016                         for (j = 0; j < 100; ++j) {
1017                                 status = RREG32_SOC15(UVD, k, mmUVD_STATUS);
1018                                 if (status & 2)
1019                                         break;
1020                                 mdelay(10);
1021                         }
1022                         r = 0;
1023                         if (status & 2)
1024                                 break;
1025
1026                         DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k);
1027                         WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),
1028                                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1029                                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1030                         mdelay(10);
1031                         WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,
1032                                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1033                         mdelay(10);
1034                         r = -1;
1035                 }
1036
1037                 if (r) {
1038                         DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k);
1039                         return r;
1040                 }
1041                 /* enable master interrupt */
1042                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),
1043                         (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
1044                         ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
1045
1046                 /* clear the bit 4 of UVD_STATUS */
1047                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,
1048                                 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1049
1050                 /* force RBC into idle state */
1051                 rb_bufsz = order_base_2(ring->ring_size);
1052                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1053                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1054                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1055                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
1056                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1057                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1058                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp);
1059
1060                 /* set the write pointer delay */
1061                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0);
1062
1063                 /* set the wb address */
1064                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR,
1065                                 (upper_32_bits(ring->gpu_addr) >> 2));
1066
1067                 /* programm the RB_BASE for ring buffer */
1068                 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1069                                 lower_32_bits(ring->gpu_addr));
1070                 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1071                                 upper_32_bits(ring->gpu_addr));
1072
1073                 /* Initialize the ring buffer's read and write pointers */
1074                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0);
1075
1076                 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);
1077                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR,
1078                                 lower_32_bits(ring->wptr));
1079
1080                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,
1081                                 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1082
1083                 ring = &adev->uvd.inst[k].ring_enc[0];
1084                 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1085                 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1086                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr);
1087                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1088                 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4);
1089
1090                 ring = &adev->uvd.inst[k].ring_enc[1];
1091                 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1092                 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1093                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1094                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1095                 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4);
1096         }
1097         return 0;
1098 }
1099
1100 /**
1101  * uvd_v7_0_stop - stop UVD block
1102  *
1103  * @adev: amdgpu_device pointer
1104  *
1105  * stop the UVD block
1106  */
1107 static void uvd_v7_0_stop(struct amdgpu_device *adev)
1108 {
1109         uint8_t i = 0;
1110
1111         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1112                 if (adev->uvd.harvest_config & (1 << i))
1113                         continue;
1114                 /* force RBC into idle state */
1115                 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101);
1116
1117                 /* Stall UMC and register bus before resetting VCPU */
1118                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
1119                                 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1120                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1121                 mdelay(1);
1122
1123                 /* put VCPU into reset */
1124                 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET,
1125                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1126                 mdelay(5);
1127
1128                 /* disable VCPU clock */
1129                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0);
1130
1131                 /* Unstall UMC and register bus */
1132                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
1133                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1134         }
1135 }
1136
1137 /**
1138  * uvd_v7_0_ring_emit_fence - emit an fence & trap command
1139  *
1140  * @ring: amdgpu_ring pointer
1141  * @fence: fence to emit
1142  *
1143  * Write a fence and a trap command to the ring.
1144  */
1145 static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1146                                      unsigned flags)
1147 {
1148         struct amdgpu_device *adev = ring->adev;
1149
1150         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1151
1152         amdgpu_ring_write(ring,
1153                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1154         amdgpu_ring_write(ring, seq);
1155         amdgpu_ring_write(ring,
1156                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1157         amdgpu_ring_write(ring, addr & 0xffffffff);
1158         amdgpu_ring_write(ring,
1159                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1160         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1161         amdgpu_ring_write(ring,
1162                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1163         amdgpu_ring_write(ring, 0);
1164
1165         amdgpu_ring_write(ring,
1166                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1167         amdgpu_ring_write(ring, 0);
1168         amdgpu_ring_write(ring,
1169                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1170         amdgpu_ring_write(ring, 0);
1171         amdgpu_ring_write(ring,
1172                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1173         amdgpu_ring_write(ring, 2);
1174 }
1175
1176 /**
1177  * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command
1178  *
1179  * @ring: amdgpu_ring pointer
1180  * @fence: fence to emit
1181  *
1182  * Write enc a fence and a trap command to the ring.
1183  */
1184 static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1185                         u64 seq, unsigned flags)
1186 {
1187
1188         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1189
1190         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
1191         amdgpu_ring_write(ring, addr);
1192         amdgpu_ring_write(ring, upper_32_bits(addr));
1193         amdgpu_ring_write(ring, seq);
1194         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
1195 }
1196
1197 /**
1198  * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing
1199  *
1200  * @ring: amdgpu_ring pointer
1201  */
1202 static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1203 {
1204         /* The firmware doesn't seem to like touching registers at this point. */
1205 }
1206
1207 /**
1208  * uvd_v7_0_ring_test_ring - register write test
1209  *
1210  * @ring: amdgpu_ring pointer
1211  *
1212  * Test if we can successfully write to the context register
1213  */
1214 static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1215 {
1216         struct amdgpu_device *adev = ring->adev;
1217         uint32_t tmp = 0;
1218         unsigned i;
1219         int r;
1220
1221         WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD);
1222         r = amdgpu_ring_alloc(ring, 3);
1223         if (r)
1224                 return r;
1225
1226         amdgpu_ring_write(ring,
1227                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1228         amdgpu_ring_write(ring, 0xDEADBEEF);
1229         amdgpu_ring_commit(ring);
1230         for (i = 0; i < adev->usec_timeout; i++) {
1231                 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);
1232                 if (tmp == 0xDEADBEEF)
1233                         break;
1234                 DRM_UDELAY(1);
1235         }
1236
1237         if (i >= adev->usec_timeout)
1238                 r = -ETIMEDOUT;
1239
1240         return r;
1241 }
1242
1243 /**
1244  * uvd_v7_0_ring_patch_cs_in_place - Patch the IB for command submission.
1245  *
1246  * @p: the CS parser with the IBs
1247  * @ib_idx: which IB to patch
1248  *
1249  */
1250 static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1251                                            uint32_t ib_idx)
1252 {
1253         struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
1254         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
1255         unsigned i;
1256
1257         /* No patching necessary for the first instance */
1258         if (!ring->me)
1259                 return 0;
1260
1261         for (i = 0; i < ib->length_dw; i += 2) {
1262                 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i);
1263
1264                 reg -= p->adev->reg_offset[UVD_HWIP][0][1];
1265                 reg += p->adev->reg_offset[UVD_HWIP][1][1];
1266
1267                 amdgpu_set_ib_value(p, ib_idx, i, reg);
1268         }
1269         return 0;
1270 }
1271
1272 /**
1273  * uvd_v7_0_ring_emit_ib - execute indirect buffer
1274  *
1275  * @ring: amdgpu_ring pointer
1276  * @ib: indirect buffer to execute
1277  *
1278  * Write ring commands to execute the indirect buffer
1279  */
1280 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
1281                                   struct amdgpu_ib *ib,
1282                                   unsigned vmid, bool ctx_switch)
1283 {
1284         struct amdgpu_device *adev = ring->adev;
1285
1286         amdgpu_ring_write(ring,
1287                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));
1288         amdgpu_ring_write(ring, vmid);
1289
1290         amdgpu_ring_write(ring,
1291                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1292         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1293         amdgpu_ring_write(ring,
1294                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1295         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1296         amdgpu_ring_write(ring,
1297                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));
1298         amdgpu_ring_write(ring, ib->length_dw);
1299 }
1300
1301 /**
1302  * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer
1303  *
1304  * @ring: amdgpu_ring pointer
1305  * @ib: indirect buffer to execute
1306  *
1307  * Write enc ring commands to execute the indirect buffer
1308  */
1309 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1310                 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1311 {
1312         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1313         amdgpu_ring_write(ring, vmid);
1314         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1315         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1316         amdgpu_ring_write(ring, ib->length_dw);
1317 }
1318
1319 static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
1320                                     uint32_t reg, uint32_t val)
1321 {
1322         struct amdgpu_device *adev = ring->adev;
1323
1324         amdgpu_ring_write(ring,
1325                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1326         amdgpu_ring_write(ring, reg << 2);
1327         amdgpu_ring_write(ring,
1328                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1329         amdgpu_ring_write(ring, val);
1330         amdgpu_ring_write(ring,
1331                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1332         amdgpu_ring_write(ring, 8);
1333 }
1334
1335 static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1336                                         uint32_t val, uint32_t mask)
1337 {
1338         struct amdgpu_device *adev = ring->adev;
1339
1340         amdgpu_ring_write(ring,
1341                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1342         amdgpu_ring_write(ring, reg << 2);
1343         amdgpu_ring_write(ring,
1344                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1345         amdgpu_ring_write(ring, val);
1346         amdgpu_ring_write(ring,
1347                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));
1348         amdgpu_ring_write(ring, mask);
1349         amdgpu_ring_write(ring,
1350                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1351         amdgpu_ring_write(ring, 12);
1352 }
1353
1354 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1355                                         unsigned vmid, uint64_t pd_addr)
1356 {
1357         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1358         uint32_t data0, data1, mask;
1359
1360         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1361
1362         /* wait for reg writes */
1363         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1364         data1 = lower_32_bits(pd_addr);
1365         mask = 0xffffffff;
1366         uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask);
1367 }
1368
1369 static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1370 {
1371         struct amdgpu_device *adev = ring->adev;
1372         int i;
1373
1374         WARN_ON(ring->wptr % 2 || count % 2);
1375
1376         for (i = 0; i < count / 2; i++) {
1377                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));
1378                 amdgpu_ring_write(ring, 0);
1379         }
1380 }
1381
1382 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1383 {
1384         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1385 }
1386
1387 static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1388                                             uint32_t reg, uint32_t val,
1389                                             uint32_t mask)
1390 {
1391         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1392         amdgpu_ring_write(ring, reg << 2);
1393         amdgpu_ring_write(ring, mask);
1394         amdgpu_ring_write(ring, val);
1395 }
1396
1397 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1398                                             unsigned int vmid, uint64_t pd_addr)
1399 {
1400         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1401
1402         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1403
1404         /* wait for reg writes */
1405         uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1406                                         lower_32_bits(pd_addr), 0xffffffff);
1407 }
1408
1409 static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1410                                         uint32_t reg, uint32_t val)
1411 {
1412         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1413         amdgpu_ring_write(ring, reg << 2);
1414         amdgpu_ring_write(ring, val);
1415 }
1416
1417 #if 0
1418 static bool uvd_v7_0_is_idle(void *handle)
1419 {
1420         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1421
1422         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1423 }
1424
1425 static int uvd_v7_0_wait_for_idle(void *handle)
1426 {
1427         unsigned i;
1428         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1429
1430         for (i = 0; i < adev->usec_timeout; i++) {
1431                 if (uvd_v7_0_is_idle(handle))
1432                         return 0;
1433         }
1434         return -ETIMEDOUT;
1435 }
1436
1437 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
1438 static bool uvd_v7_0_check_soft_reset(void *handle)
1439 {
1440         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1441         u32 srbm_soft_reset = 0;
1442         u32 tmp = RREG32(mmSRBM_STATUS);
1443
1444         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1445             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1446             (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
1447                     AMDGPU_UVD_STATUS_BUSY_MASK))
1448                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1449                                 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1450
1451         if (srbm_soft_reset) {
1452                 adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset;
1453                 return true;
1454         } else {
1455                 adev->uvd.inst[ring->me].srbm_soft_reset = 0;
1456                 return false;
1457         }
1458 }
1459
1460 static int uvd_v7_0_pre_soft_reset(void *handle)
1461 {
1462         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1463
1464         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1465                 return 0;
1466
1467         uvd_v7_0_stop(adev);
1468         return 0;
1469 }
1470
1471 static int uvd_v7_0_soft_reset(void *handle)
1472 {
1473         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1474         u32 srbm_soft_reset;
1475
1476         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1477                 return 0;
1478         srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset;
1479
1480         if (srbm_soft_reset) {
1481                 u32 tmp;
1482
1483                 tmp = RREG32(mmSRBM_SOFT_RESET);
1484                 tmp |= srbm_soft_reset;
1485                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1486                 WREG32(mmSRBM_SOFT_RESET, tmp);
1487                 tmp = RREG32(mmSRBM_SOFT_RESET);
1488
1489                 udelay(50);
1490
1491                 tmp &= ~srbm_soft_reset;
1492                 WREG32(mmSRBM_SOFT_RESET, tmp);
1493                 tmp = RREG32(mmSRBM_SOFT_RESET);
1494
1495                 /* Wait a little for things to settle down */
1496                 udelay(50);
1497         }
1498
1499         return 0;
1500 }
1501
1502 static int uvd_v7_0_post_soft_reset(void *handle)
1503 {
1504         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1505
1506         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1507                 return 0;
1508
1509         mdelay(5);
1510
1511         return uvd_v7_0_start(adev);
1512 }
1513 #endif
1514
1515 static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev,
1516                                         struct amdgpu_irq_src *source,
1517                                         unsigned type,
1518                                         enum amdgpu_interrupt_state state)
1519 {
1520         // TODO
1521         return 0;
1522 }
1523
1524 static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev,
1525                                       struct amdgpu_irq_src *source,
1526                                       struct amdgpu_iv_entry *entry)
1527 {
1528         uint32_t ip_instance;
1529
1530         switch (entry->client_id) {
1531         case SOC15_IH_CLIENTID_UVD:
1532                 ip_instance = 0;
1533                 break;
1534         case SOC15_IH_CLIENTID_UVD1:
1535                 ip_instance = 1;
1536                 break;
1537         default:
1538                 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1539                 return 0;
1540         }
1541
1542         DRM_DEBUG("IH: UVD TRAP\n");
1543
1544         switch (entry->src_id) {
1545         case 124:
1546                 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring);
1547                 break;
1548         case 119:
1549                 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]);
1550                 break;
1551         case 120:
1552                 if (!amdgpu_sriov_vf(adev))
1553                         amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]);
1554                 break;
1555         default:
1556                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1557                           entry->src_id, entry->src_data[0]);
1558                 break;
1559         }
1560
1561         return 0;
1562 }
1563
1564 #if 0
1565 static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)
1566 {
1567         uint32_t data, data1, data2, suvd_flags;
1568
1569         data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1570         data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1571         data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);
1572
1573         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1574                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1575
1576         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1577                      UVD_SUVD_CGC_GATE__SIT_MASK |
1578                      UVD_SUVD_CGC_GATE__SMP_MASK |
1579                      UVD_SUVD_CGC_GATE__SCM_MASK |
1580                      UVD_SUVD_CGC_GATE__SDB_MASK;
1581
1582         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1583                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1584                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1585
1586         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1587                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1588                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1589                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1590                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1591                         UVD_CGC_CTRL__SYS_MODE_MASK |
1592                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1593                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1594                         UVD_CGC_CTRL__REGS_MODE_MASK |
1595                         UVD_CGC_CTRL__RBC_MODE_MASK |
1596                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1597                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1598                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1599                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1600                         UVD_CGC_CTRL__MPC_MODE_MASK |
1601                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1602                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1603                         UVD_CGC_CTRL__WCB_MODE_MASK |
1604                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1605                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1606                         UVD_CGC_CTRL__JPEG2_MODE_MASK |
1607                         UVD_CGC_CTRL__SCPU_MODE_MASK);
1608         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1609                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1610                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1611                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1612                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1613         data1 |= suvd_flags;
1614
1615         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
1616         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);
1617         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1618         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);
1619 }
1620
1621 static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)
1622 {
1623         uint32_t data, data1, cgc_flags, suvd_flags;
1624
1625         data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);
1626         data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1627
1628         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1629                 UVD_CGC_GATE__UDEC_MASK |
1630                 UVD_CGC_GATE__MPEG2_MASK |
1631                 UVD_CGC_GATE__RBC_MASK |
1632                 UVD_CGC_GATE__LMI_MC_MASK |
1633                 UVD_CGC_GATE__IDCT_MASK |
1634                 UVD_CGC_GATE__MPRD_MASK |
1635                 UVD_CGC_GATE__MPC_MASK |
1636                 UVD_CGC_GATE__LBSI_MASK |
1637                 UVD_CGC_GATE__LRBBM_MASK |
1638                 UVD_CGC_GATE__UDEC_RE_MASK |
1639                 UVD_CGC_GATE__UDEC_CM_MASK |
1640                 UVD_CGC_GATE__UDEC_IT_MASK |
1641                 UVD_CGC_GATE__UDEC_DB_MASK |
1642                 UVD_CGC_GATE__UDEC_MP_MASK |
1643                 UVD_CGC_GATE__WCB_MASK |
1644                 UVD_CGC_GATE__VCPU_MASK |
1645                 UVD_CGC_GATE__SCPU_MASK |
1646                 UVD_CGC_GATE__JPEG_MASK |
1647                 UVD_CGC_GATE__JPEG2_MASK;
1648
1649         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1650                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1651                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1652                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1653                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1654
1655         data |= cgc_flags;
1656         data1 |= suvd_flags;
1657
1658         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);
1659         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1660 }
1661
1662 static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
1663 {
1664         u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
1665
1666         if (enable)
1667                 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1668                         GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1669         else
1670                 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1671                          GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1672
1673         WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
1674 }
1675
1676
1677 static int uvd_v7_0_set_clockgating_state(void *handle,
1678                                           enum amd_clockgating_state state)
1679 {
1680         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1681         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1682
1683         uvd_v7_0_set_bypass_mode(adev, enable);
1684
1685         if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
1686                 return 0;
1687
1688         if (enable) {
1689                 /* disable HW gating and enable Sw gating */
1690                 uvd_v7_0_set_sw_clock_gating(adev);
1691         } else {
1692                 /* wait for STATUS to clear */
1693                 if (uvd_v7_0_wait_for_idle(handle))
1694                         return -EBUSY;
1695
1696                 /* enable HW gates because UVD is idle */
1697                 /* uvd_v7_0_set_hw_clock_gating(adev); */
1698         }
1699
1700         return 0;
1701 }
1702
1703 static int uvd_v7_0_set_powergating_state(void *handle,
1704                                           enum amd_powergating_state state)
1705 {
1706         /* This doesn't actually powergate the UVD block.
1707          * That's done in the dpm code via the SMC.  This
1708          * just re-inits the block as necessary.  The actual
1709          * gating still happens in the dpm code.  We should
1710          * revisit this when there is a cleaner line between
1711          * the smc and the hw blocks
1712          */
1713         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1714
1715         if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1716                 return 0;
1717
1718         WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1719
1720         if (state == AMD_PG_STATE_GATE) {
1721                 uvd_v7_0_stop(adev);
1722                 return 0;
1723         } else {
1724                 return uvd_v7_0_start(adev);
1725         }
1726 }
1727 #endif
1728
1729 static int uvd_v7_0_set_clockgating_state(void *handle,
1730                                           enum amd_clockgating_state state)
1731 {
1732         /* needed for driver unload*/
1733         return 0;
1734 }
1735
1736 const struct amd_ip_funcs uvd_v7_0_ip_funcs = {
1737         .name = "uvd_v7_0",
1738         .early_init = uvd_v7_0_early_init,
1739         .late_init = NULL,
1740         .sw_init = uvd_v7_0_sw_init,
1741         .sw_fini = uvd_v7_0_sw_fini,
1742         .hw_init = uvd_v7_0_hw_init,
1743         .hw_fini = uvd_v7_0_hw_fini,
1744         .suspend = uvd_v7_0_suspend,
1745         .resume = uvd_v7_0_resume,
1746         .is_idle = NULL /* uvd_v7_0_is_idle */,
1747         .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */,
1748         .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */,
1749         .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */,
1750         .soft_reset = NULL /* uvd_v7_0_soft_reset */,
1751         .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */,
1752         .set_clockgating_state = uvd_v7_0_set_clockgating_state,
1753         .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */,
1754 };
1755
1756 static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
1757         .type = AMDGPU_RING_TYPE_UVD,
1758         .align_mask = 0xf,
1759         .support_64bit_ptrs = false,
1760         .vmhub = AMDGPU_MMHUB,
1761         .get_rptr = uvd_v7_0_ring_get_rptr,
1762         .get_wptr = uvd_v7_0_ring_get_wptr,
1763         .set_wptr = uvd_v7_0_ring_set_wptr,
1764         .patch_cs_in_place = uvd_v7_0_ring_patch_cs_in_place,
1765         .emit_frame_size =
1766                 6 + /* hdp invalidate */
1767                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1768                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1769                 8 + /* uvd_v7_0_ring_emit_vm_flush */
1770                 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
1771         .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
1772         .emit_ib = uvd_v7_0_ring_emit_ib,
1773         .emit_fence = uvd_v7_0_ring_emit_fence,
1774         .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
1775         .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
1776         .test_ring = uvd_v7_0_ring_test_ring,
1777         .test_ib = amdgpu_uvd_ring_test_ib,
1778         .insert_nop = uvd_v7_0_ring_insert_nop,
1779         .pad_ib = amdgpu_ring_generic_pad_ib,
1780         .begin_use = amdgpu_uvd_ring_begin_use,
1781         .end_use = amdgpu_uvd_ring_end_use,
1782         .emit_wreg = uvd_v7_0_ring_emit_wreg,
1783         .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait,
1784         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1785 };
1786
1787 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
1788         .type = AMDGPU_RING_TYPE_UVD_ENC,
1789         .align_mask = 0x3f,
1790         .nop = HEVC_ENC_CMD_NO_OP,
1791         .support_64bit_ptrs = false,
1792         .vmhub = AMDGPU_MMHUB,
1793         .get_rptr = uvd_v7_0_enc_ring_get_rptr,
1794         .get_wptr = uvd_v7_0_enc_ring_get_wptr,
1795         .set_wptr = uvd_v7_0_enc_ring_set_wptr,
1796         .emit_frame_size =
1797                 3 + 3 + /* hdp flush / invalidate */
1798                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1799                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1800                 4 + /* uvd_v7_0_enc_ring_emit_vm_flush */
1801                 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
1802                 1, /* uvd_v7_0_enc_ring_insert_end */
1803         .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */
1804         .emit_ib = uvd_v7_0_enc_ring_emit_ib,
1805         .emit_fence = uvd_v7_0_enc_ring_emit_fence,
1806         .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush,
1807         .test_ring = uvd_v7_0_enc_ring_test_ring,
1808         .test_ib = uvd_v7_0_enc_ring_test_ib,
1809         .insert_nop = amdgpu_ring_insert_nop,
1810         .insert_end = uvd_v7_0_enc_ring_insert_end,
1811         .pad_ib = amdgpu_ring_generic_pad_ib,
1812         .begin_use = amdgpu_uvd_ring_begin_use,
1813         .end_use = amdgpu_uvd_ring_end_use,
1814         .emit_wreg = uvd_v7_0_enc_ring_emit_wreg,
1815         .emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait,
1816         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1817 };
1818
1819 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
1820 {
1821         int i;
1822
1823         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
1824                 if (adev->uvd.harvest_config & (1 << i))
1825                         continue;
1826                 adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs;
1827                 adev->uvd.inst[i].ring.me = i;
1828                 DRM_INFO("UVD(%d) is enabled in VM mode\n", i);
1829         }
1830 }
1831
1832 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1833 {
1834         int i, j;
1835
1836         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
1837                 if (adev->uvd.harvest_config & (1 << j))
1838                         continue;
1839                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
1840                         adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
1841                         adev->uvd.inst[j].ring_enc[i].me = j;
1842                 }
1843
1844                 DRM_INFO("UVD(%d) ENC is enabled in VM mode\n", j);
1845         }
1846 }
1847
1848 static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = {
1849         .set = uvd_v7_0_set_interrupt_state,
1850         .process = uvd_v7_0_process_interrupt,
1851 };
1852
1853 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1854 {
1855         int i;
1856
1857         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
1858                 if (adev->uvd.harvest_config & (1 << i))
1859                         continue;
1860                 adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1;
1861                 adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs;
1862         }
1863 }
1864
1865 const struct amdgpu_ip_block_version uvd_v7_0_ip_block =
1866 {
1867                 .type = AMD_IP_BLOCK_TYPE_UVD,
1868                 .major = 7,
1869                 .minor = 0,
1870                 .rev = 0,
1871                 .funcs = &uvd_v7_0_ip_funcs,
1872 };