drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_2_4_d.h"
  33 #include "oss/oss_2_4_sh_mask.h"
  34
  35 #include "gmc/gmc_7_1_d.h"
  36 #include "gmc/gmc_7_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "iceland_sdma_pkt_open.h"
  46
  47 #include "ivsrcid/ivsrcid_vislands30.h"
  48
  49 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
  50 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
  51 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
  52 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
  53
  54 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
  55 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
  56
  57 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  58 {
  59         SDMA0_REGISTER_OFFSET,
  60         SDMA1_REGISTER_OFFSET
  61 };
  62
  63 static const u32 golden_settings_iceland_a11[] =
  64 {
  65         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  66         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  67         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  68         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  69 };
  70
  71 static const u32 iceland_mgcg_cgcg_init[] =
  72 {
  73         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  74         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  75 };
  76
  77 /*
  78  * sDMA - System DMA
  79  * Starting with CIK, the GPU has new asynchronous
  80  * DMA engines.  These engines are used for compute
  81  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  82  * and each one supports 1 ring buffer used for gfx
  83  * and 2 queues used for compute.
  84  *
  85  * The programming model is very similar to the CP
  86  * (ring buffer, IBs, etc.), but sDMA has it's own
  87  * packet format that is different from the PM4 format
  88  * used by the CP. sDMA supports copying data, writing
  89  * embedded data, solid fills, and a number of other
  90  * things.  It also has support for tiling/detiling of
  91  * buffers.
  92  */
  93
  94 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
  95 {
  96         switch (adev->asic_type) {
  97         case CHIP_TOPAZ:
  98                 amdgpu_device_program_register_sequence(adev,
  99                                                         iceland_mgcg_cgcg_init,
 100                                                         ARRAY_SIZE(iceland_mgcg_cgcg_init));
 101                 amdgpu_device_program_register_sequence(adev,
 102                                                         golden_settings_iceland_a11,
 103                                                         ARRAY_SIZE(golden_settings_iceland_a11));
 104                 break;
 105         default:
 106                 break;
 107         }
 108 }
 109
 110 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
 111 {
 112         int i;
 113         for (i = 0; i < adev->sdma.num_instances; i++) {
 114                 release_firmware(adev->sdma.instance[i].fw);
 115                 adev->sdma.instance[i].fw = NULL;
 116         }
 117 }
 118
 119 /**
 120  * sdma_v2_4_init_microcode - load ucode images from disk
 121  *
 122  * @adev: amdgpu_device pointer
 123  *
 124  * Use the firmware interface to load the ucode images into
 125  * the driver (not loaded into hw).
 126  * Returns 0 on success, error on failure.
 127  */
 128 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
 129 {
 130         const char *chip_name;
 131         char fw_name[30];
 132         int err = 0, i;
 133         struct amdgpu_firmware_info *info = NULL;
 134         const struct common_firmware_header *header = NULL;
 135         const struct sdma_firmware_header_v1_0 *hdr;
 136
 137         DRM_DEBUG("\n");
 138
 139         switch (adev->asic_type) {
 140         case CHIP_TOPAZ:
 141                 chip_name = "topaz";
 142                 break;
 143         default: BUG();
 144         }
 145
 146         for (i = 0; i < adev->sdma.num_instances; i++) {
 147                 if (i == 0)
 148                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 149                 else
 150                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 151                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 152                 if (err)
 153                         goto out;
 154                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 155                 if (err)
 156                         goto out;
 157                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 158                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 159                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 160                 if (adev->sdma.instance[i].feature_version >= 20)
 161                         adev->sdma.instance[i].burst_nop = true;
 162
 163                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
 164                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 165                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 166                         info->fw = adev->sdma.instance[i].fw;
 167                         header = (const struct common_firmware_header *)info->fw->data;
 168                         adev->firmware.fw_size +=
 169                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 170                 }
 171         }
 172
 173 out:
 174         if (err) {
 175                 pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name);
 176                 for (i = 0; i < adev->sdma.num_instances; i++) {
 177                         release_firmware(adev->sdma.instance[i].fw);
 178                         adev->sdma.instance[i].fw = NULL;
 179                 }
 180         }
 181         return err;
 182 }
 183
 184 /**
 185  * sdma_v2_4_ring_get_rptr - get the current read pointer
 186  *
 187  * @ring: amdgpu ring pointer
 188  *
 189  * Get the current rptr from the hardware (VI+).
 190  */
 191 static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
 192 {
 193         /* XXX check if swapping is necessary on BE */
 194         return ring->adev->wb.wb[ring->rptr_offs] >> 2;
 195 }
 196
 197 /**
 198  * sdma_v2_4_ring_get_wptr - get the current write pointer
 199  *
 200  * @ring: amdgpu ring pointer
 201  *
 202  * Get the current wptr from the hardware (VI+).
 203  */
 204 static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
 205 {
 206         struct amdgpu_device *adev = ring->adev;
 207         u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
 208
 209         return wptr;
 210 }
 211
 212 /**
 213  * sdma_v2_4_ring_set_wptr - commit the write pointer
 214  *
 215  * @ring: amdgpu ring pointer
 216  *
 217  * Write the wptr back to the hardware (VI+).
 218  */
 219 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
 220 {
 221         struct amdgpu_device *adev = ring->adev;
 222
 223         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
 224 }
 225
 226 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 227 {
 228         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 229         int i;
 230
 231         for (i = 0; i < count; i++)
 232                 if (sdma && sdma->burst_nop && (i == 0))
 233                         amdgpu_ring_write(ring, ring->funcs->nop |
 234                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 235                 else
 236                         amdgpu_ring_write(ring, ring->funcs->nop);
 237 }
 238
 239 /**
 240  * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
 241  *
 242  * @ring: amdgpu ring pointer
 243  * @ib: IB object to schedule
 244  *
 245  * Schedule an IB in the DMA ring (VI).
 246  */
 247 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
 248                                    struct amdgpu_ib *ib,
 249                                    unsigned vmid, bool ctx_switch)
 250 {
 251         /* IB packet must end on a 8 DW boundary */
 252         sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 253
 254         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 255                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 256         /* base must be 32 byte aligned */
 257         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 258         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 259         amdgpu_ring_write(ring, ib->length_dw);
 260         amdgpu_ring_write(ring, 0);
 261         amdgpu_ring_write(ring, 0);
 262
 263 }
 264
 265 /**
 266  * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
 267  *
 268  * @ring: amdgpu ring pointer
 269  *
 270  * Emit an hdp flush packet on the requested DMA ring.
 271  */
 272 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 273 {
 274         u32 ref_and_mask = 0;
 275
 276         if (ring->me == 0)
 277                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 278         else
 279                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 280
 281         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 282                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 283                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 284         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 285         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 286         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 287         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 288         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 289                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 290 }
 291
 292 /**
 293  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
 294  *
 295  * @ring: amdgpu ring pointer
 296  * @fence: amdgpu fence object
 297  *
 298  * Add a DMA fence packet to the ring to write
 299  * the fence seq number and DMA trap packet to generate
 300  * an interrupt if needed (VI).
 301  */
 302 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 303                                       unsigned flags)
 304 {
 305         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 306         /* write the fence */
 307         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 308         amdgpu_ring_write(ring, lower_32_bits(addr));
 309         amdgpu_ring_write(ring, upper_32_bits(addr));
 310         amdgpu_ring_write(ring, lower_32_bits(seq));
 311
 312         /* optionally write high bits as well */
 313         if (write64bit) {
 314                 addr += 4;
 315                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 316                 amdgpu_ring_write(ring, lower_32_bits(addr));
 317                 amdgpu_ring_write(ring, upper_32_bits(addr));
 318                 amdgpu_ring_write(ring, upper_32_bits(seq));
 319         }
 320
 321         /* generate an interrupt */
 322         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 323         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 324 }
 325
 326 /**
 327  * sdma_v2_4_gfx_stop - stop the gfx async dma engines
 328  *
 329  * @adev: amdgpu_device pointer
 330  *
 331  * Stop the gfx async dma ring buffers (VI).
 332  */
 333 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
 334 {
 335         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 336         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 337         u32 rb_cntl, ib_cntl;
 338         int i;
 339
 340         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 341             (adev->mman.buffer_funcs_ring == sdma1))
 342                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 343
 344         for (i = 0; i < adev->sdma.num_instances; i++) {
 345                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 346                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 347                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 348                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 349                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 350                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 351         }
 352         sdma0->sched.ready = false;
 353         sdma1->sched.ready = false;
 354 }
 355
 356 /**
 357  * sdma_v2_4_rlc_stop - stop the compute async dma engines
 358  *
 359  * @adev: amdgpu_device pointer
 360  *
 361  * Stop the compute async dma queues (VI).
 362  */
 363 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
 364 {
 365         /* XXX todo */
 366 }
 367
 368 /**
 369  * sdma_v2_4_enable - stop the async dma engines
 370  *
 371  * @adev: amdgpu_device pointer
 372  * @enable: enable/disable the DMA MEs.
 373  *
 374  * Halt or unhalt the async dma engines (VI).
 375  */
 376 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
 377 {
 378         u32 f32_cntl;
 379         int i;
 380
 381         if (!enable) {
 382                 sdma_v2_4_gfx_stop(adev);
 383                 sdma_v2_4_rlc_stop(adev);
 384         }
 385
 386         for (i = 0; i < adev->sdma.num_instances; i++) {
 387                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 388                 if (enable)
 389                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 390                 else
 391                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 392                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 393         }
 394 }
 395
 396 /**
 397  * sdma_v2_4_gfx_resume - setup and start the async dma engines
 398  *
 399  * @adev: amdgpu_device pointer
 400  *
 401  * Set up the gfx DMA ring buffers and enable them (VI).
 402  * Returns 0 for success, error for failure.
 403  */
 404 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
 405 {
 406         struct amdgpu_ring *ring;
 407         u32 rb_cntl, ib_cntl;
 408         u32 rb_bufsz;
 409         u32 wb_offset;
 410         int i, j, r;
 411
 412         for (i = 0; i < adev->sdma.num_instances; i++) {
 413                 ring = &adev->sdma.instance[i].ring;
 414                 wb_offset = (ring->rptr_offs * 4);
 415
 416                 mutex_lock(&adev->srbm_mutex);
 417                 for (j = 0; j < 16; j++) {
 418                         vi_srbm_select(adev, 0, 0, 0, j);
 419                         /* SDMA GFX */
 420                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 421                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 422                 }
 423                 vi_srbm_select(adev, 0, 0, 0, 0);
 424                 mutex_unlock(&adev->srbm_mutex);
 425
 426                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 427                        adev->gfx.config.gb_addr_config & 0x70);
 428
 429                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 430
 431                 /* Set ring buffer size in dwords */
 432                 rb_bufsz = order_base_2(ring->ring_size / 4);
 433                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 434                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 435 #ifdef __BIG_ENDIAN
 436                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 437                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 438                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 439 #endif
 440                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 441
 442                 /* Initialize the ring buffer's read and write pointers */
 443                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 444                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 445                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 446                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 447
 448                 /* set the wb address whether it's enabled or not */
 449                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 450                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 451                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 452                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 453
 454                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 455
 456                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 457                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 458
 459                 ring->wptr = 0;
 460                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
 461
 462                 /* enable DMA RB */
 463                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 464                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 465
 466                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 467                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 468 #ifdef __BIG_ENDIAN
 469                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 470 #endif
 471                 /* enable DMA IBs */
 472                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 473
 474                 ring->sched.ready = true;
 475         }
 476
 477         sdma_v2_4_enable(adev, true);
 478         for (i = 0; i < adev->sdma.num_instances; i++) {
 479                 ring = &adev->sdma.instance[i].ring;
 480                 r = amdgpu_ring_test_helper(ring);
 481                 if (r)
 482                         return r;
 483
 484                 if (adev->mman.buffer_funcs_ring == ring)
 485                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 486         }
 487
 488         return 0;
 489 }
 490
 491 /**
 492  * sdma_v2_4_rlc_resume - setup and start the async dma engines
 493  *
 494  * @adev: amdgpu_device pointer
 495  *
 496  * Set up the compute DMA queues and enable them (VI).
 497  * Returns 0 for success, error for failure.
 498  */
 499 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
 500 {
 501         /* XXX todo */
 502         return 0;
 503 }
 504
 505
 506 /**
 507  * sdma_v2_4_start - setup and start the async dma engines
 508  *
 509  * @adev: amdgpu_device pointer
 510  *
 511  * Set up the DMA engines and enable them (VI).
 512  * Returns 0 for success, error for failure.
 513  */
 514 static int sdma_v2_4_start(struct amdgpu_device *adev)
 515 {
 516         int r;
 517
 518         /* halt the engine before programing */
 519         sdma_v2_4_enable(adev, false);
 520
 521         /* start the gfx rings and rlc compute queues */
 522         r = sdma_v2_4_gfx_resume(adev);
 523         if (r)
 524                 return r;
 525         r = sdma_v2_4_rlc_resume(adev);
 526         if (r)
 527                 return r;
 528
 529         return 0;
 530 }
 531
 532 /**
 533  * sdma_v2_4_ring_test_ring - simple async dma engine test
 534  *
 535  * @ring: amdgpu_ring structure holding ring information
 536  *
 537  * Test the DMA engine by writing using it to write an
 538  * value to memory. (VI).
 539  * Returns 0 for success, error for failure.
 540  */
 541 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
 542 {
 543         struct amdgpu_device *adev = ring->adev;
 544         unsigned i;
 545         unsigned index;
 546         int r;
 547         u32 tmp;
 548         u64 gpu_addr;
 549
 550         r = amdgpu_device_wb_get(adev, &index);
 551         if (r)
 552                 return r;
 553
 554         gpu_addr = adev->wb.gpu_addr + (index * 4);
 555         tmp = 0xCAFEDEAD;
 556         adev->wb.wb[index] = cpu_to_le32(tmp);
 557
 558         r = amdgpu_ring_alloc(ring, 5);
 559         if (r)
 560                 goto error_free_wb;
 561
 562         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 563                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 564         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 565         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 566         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 567         amdgpu_ring_write(ring, 0xDEADBEEF);
 568         amdgpu_ring_commit(ring);
 569
 570         for (i = 0; i < adev->usec_timeout; i++) {
 571                 tmp = le32_to_cpu(adev->wb.wb[index]);
 572                 if (tmp == 0xDEADBEEF)
 573                         break;
 574                 DRM_UDELAY(1);
 575         }
 576
 577         if (i >= adev->usec_timeout)
 578                 r = -ETIMEDOUT;
 579
 580 error_free_wb:
 581         amdgpu_device_wb_free(adev, index);
 582         return r;
 583 }
 584
 585 /**
 586  * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
 587  *
 588  * @ring: amdgpu_ring structure holding ring information
 589  *
 590  * Test a simple IB in the DMA ring (VI).
 591  * Returns 0 on success, error on failure.
 592  */
 593 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 594 {
 595         struct amdgpu_device *adev = ring->adev;
 596         struct amdgpu_ib ib;
 597         struct dma_fence *f = NULL;
 598         unsigned index;
 599         u32 tmp = 0;
 600         u64 gpu_addr;
 601         long r;
 602
 603         r = amdgpu_device_wb_get(adev, &index);
 604         if (r) {
 605                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 606                 return r;
 607         }
 608
 609         gpu_addr = adev->wb.gpu_addr + (index * 4);
 610         tmp = 0xCAFEDEAD;
 611         adev->wb.wb[index] = cpu_to_le32(tmp);
 612         memset(&ib, 0, sizeof(ib));
 613         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 614         if (r) {
 615                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 616                 goto err0;
 617         }
 618
 619         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 620                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 621         ib.ptr[1] = lower_32_bits(gpu_addr);
 622         ib.ptr[2] = upper_32_bits(gpu_addr);
 623         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 624         ib.ptr[4] = 0xDEADBEEF;
 625         ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 626         ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 627         ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 628         ib.length_dw = 8;
 629
 630         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 631         if (r)
 632                 goto err1;
 633
 634         r = dma_fence_wait_timeout(f, false, timeout);
 635         if (r == 0) {
 636                 DRM_ERROR("amdgpu: IB test timed out\n");
 637                 r = -ETIMEDOUT;
 638                 goto err1;
 639         } else if (r < 0) {
 640                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 641                 goto err1;
 642         }
 643         tmp = le32_to_cpu(adev->wb.wb[index]);
 644         if (tmp == 0xDEADBEEF) {
 645                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 646                 r = 0;
 647         } else {
 648                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 649                 r = -EINVAL;
 650         }
 651
 652 err1:
 653         amdgpu_ib_free(adev, &ib, NULL);
 654         dma_fence_put(f);
 655 err0:
 656         amdgpu_device_wb_free(adev, index);
 657         return r;
 658 }
 659
 660 /**
 661  * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
 662  *
 663  * @ib: indirect buffer to fill with commands
 664  * @pe: addr of the page entry
 665  * @src: src addr to copy from
 666  * @count: number of page entries to update
 667  *
 668  * Update PTEs by copying them from the GART using sDMA (CIK).
 669  */
 670 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
 671                                   uint64_t pe, uint64_t src,
 672                                   unsigned count)
 673 {
 674         unsigned bytes = count * 8;
 675
 676         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 677                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 678         ib->ptr[ib->length_dw++] = bytes;
 679         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 680         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 681         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 682         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 683         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 684 }
 685
 686 /**
 687  * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
 688  *
 689  * @ib: indirect buffer to fill with commands
 690  * @pe: addr of the page entry
 691  * @value: dst addr to write into pe
 692  * @count: number of page entries to update
 693  * @incr: increase next addr by incr bytes
 694  *
 695  * Update PTEs by writing them manually using sDMA (CIK).
 696  */
 697 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 698                                    uint64_t value, unsigned count,
 699                                    uint32_t incr)
 700 {
 701         unsigned ndw = count * 2;
 702
 703         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 704                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 705         ib->ptr[ib->length_dw++] = pe;
 706         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 707         ib->ptr[ib->length_dw++] = ndw;
 708         for (; ndw > 0; ndw -= 2) {
 709                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 710                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 711                 value += incr;
 712         }
 713 }
 714
 715 /**
 716  * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
 717  *
 718  * @ib: indirect buffer to fill with commands
 719  * @pe: addr of the page entry
 720  * @addr: dst addr to write into pe
 721  * @count: number of page entries to update
 722  * @incr: increase next addr by incr bytes
 723  * @flags: access flags
 724  *
 725  * Update the page tables using sDMA (CIK).
 726  */
 727 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 728                                      uint64_t addr, unsigned count,
 729                                      uint32_t incr, uint64_t flags)
 730 {
 731         /* for physically contiguous pages (vram) */
 732         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 733         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 734         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 735         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
 736         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
 737         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 738         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 739         ib->ptr[ib->length_dw++] = incr; /* increment size */
 740         ib->ptr[ib->length_dw++] = 0;
 741         ib->ptr[ib->length_dw++] = count; /* number of entries */
 742 }
 743
 744 /**
 745  * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
 746  *
 747  * @ib: indirect buffer to fill with padding
 748  *
 749  */
 750 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 751 {
 752         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 753         u32 pad_count;
 754         int i;
 755
 756         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 757         for (i = 0; i < pad_count; i++)
 758                 if (sdma && sdma->burst_nop && (i == 0))
 759                         ib->ptr[ib->length_dw++] =
 760                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
 761                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
 762                 else
 763                         ib->ptr[ib->length_dw++] =
 764                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 765 }
 766
 767 /**
 768  * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
 769  *
 770  * @ring: amdgpu_ring pointer
 771  *
 772  * Make sure all previous operations are completed (CIK).
 773  */
 774 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 775 {
 776         uint32_t seq = ring->fence_drv.sync_seq;
 777         uint64_t addr = ring->fence_drv.gpu_addr;
 778
 779         /* wait for idle */
 780         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 781                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 782                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
 783                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
 784         amdgpu_ring_write(ring, addr & 0xfffffffc);
 785         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 786         amdgpu_ring_write(ring, seq); /* reference */
 787         amdgpu_ring_write(ring, 0xffffffff); /* mask */
 788         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 789                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
 790 }
 791
 792 /**
 793  * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
 794  *
 795  * @ring: amdgpu_ring pointer
 796  * @vm: amdgpu_vm pointer
 797  *
 798  * Update the page table base and flush the VM TLB
 799  * using sDMA (VI).
 800  */
 801 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
 802                                          unsigned vmid, uint64_t pd_addr)
 803 {
 804         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
 805
 806         /* wait for flush */
 807         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 808                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 809                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
 810         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 811         amdgpu_ring_write(ring, 0);
 812         amdgpu_ring_write(ring, 0); /* reference */
 813         amdgpu_ring_write(ring, 0); /* mask */
 814         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 815                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 816 }
 817
 818 static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring,
 819                                      uint32_t reg, uint32_t val)
 820 {
 821         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 822                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 823         amdgpu_ring_write(ring, reg);
 824         amdgpu_ring_write(ring, val);
 825 }
 826
 827 static int sdma_v2_4_early_init(void *handle)
 828 {
 829         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 830
 831         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 832
 833         sdma_v2_4_set_ring_funcs(adev);
 834         sdma_v2_4_set_buffer_funcs(adev);
 835         sdma_v2_4_set_vm_pte_funcs(adev);
 836         sdma_v2_4_set_irq_funcs(adev);
 837
 838         return 0;
 839 }
 840
 841 static int sdma_v2_4_sw_init(void *handle)
 842 {
 843         struct amdgpu_ring *ring;
 844         int r, i;
 845         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 846
 847         /* SDMA trap event */
 848         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
 849                               &adev->sdma.trap_irq);
 850         if (r)
 851                 return r;
 852
 853         /* SDMA Privileged inst */
 854         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
 855                               &adev->sdma.illegal_inst_irq);
 856         if (r)
 857                 return r;
 858
 859         /* SDMA Privileged inst */
 860         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
 861                               &adev->sdma.illegal_inst_irq);
 862         if (r)
 863                 return r;
 864
 865         r = sdma_v2_4_init_microcode(adev);
 866         if (r) {
 867                 DRM_ERROR("Failed to load sdma firmware!\n");
 868                 return r;
 869         }
 870
 871         for (i = 0; i < adev->sdma.num_instances; i++) {
 872                 ring = &adev->sdma.instance[i].ring;
 873                 ring->ring_obj = NULL;
 874                 ring->use_doorbell = false;
 875                 sprintf(ring->name, "sdma%d", i);
 876                 r = amdgpu_ring_init(adev, ring, 1024,
 877                                      &adev->sdma.trap_irq,
 878                                      (i == 0) ?
 879                                      AMDGPU_SDMA_IRQ_TRAP0 :
 880                                      AMDGPU_SDMA_IRQ_TRAP1);
 881                 if (r)
 882                         return r;
 883         }
 884
 885         return r;
 886 }
 887
 888 static int sdma_v2_4_sw_fini(void *handle)
 889 {
 890         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 891         int i;
 892
 893         for (i = 0; i < adev->sdma.num_instances; i++)
 894                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 895
 896         sdma_v2_4_free_microcode(adev);
 897         return 0;
 898 }
 899
 900 static int sdma_v2_4_hw_init(void *handle)
 901 {
 902         int r;
 903         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 904
 905         sdma_v2_4_init_golden_registers(adev);
 906
 907         r = sdma_v2_4_start(adev);
 908         if (r)
 909                 return r;
 910
 911         return r;
 912 }
 913
 914 static int sdma_v2_4_hw_fini(void *handle)
 915 {
 916         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 917
 918         sdma_v2_4_enable(adev, false);
 919
 920         return 0;
 921 }
 922
 923 static int sdma_v2_4_suspend(void *handle)
 924 {
 925         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 926
 927         return sdma_v2_4_hw_fini(adev);
 928 }
 929
 930 static int sdma_v2_4_resume(void *handle)
 931 {
 932         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 933
 934         return sdma_v2_4_hw_init(adev);
 935 }
 936
 937 static bool sdma_v2_4_is_idle(void *handle)
 938 {
 939         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 940         u32 tmp = RREG32(mmSRBM_STATUS2);
 941
 942         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
 943                    SRBM_STATUS2__SDMA1_BUSY_MASK))
 944             return false;
 945
 946         return true;
 947 }
 948
 949 static int sdma_v2_4_wait_for_idle(void *handle)
 950 {
 951         unsigned i;
 952         u32 tmp;
 953         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 954
 955         for (i = 0; i < adev->usec_timeout; i++) {
 956                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
 957                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
 958
 959                 if (!tmp)
 960                         return 0;
 961                 udelay(1);
 962         }
 963         return -ETIMEDOUT;
 964 }
 965
 966 static int sdma_v2_4_soft_reset(void *handle)
 967 {
 968         u32 srbm_soft_reset = 0;
 969         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 970         u32 tmp = RREG32(mmSRBM_STATUS2);
 971
 972         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
 973                 /* sdma0 */
 974                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
 975                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
 976                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
 977                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
 978         }
 979         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
 980                 /* sdma1 */
 981                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
 982                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
 983                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
 984                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
 985         }
 986
 987         if (srbm_soft_reset) {
 988                 tmp = RREG32(mmSRBM_SOFT_RESET);
 989                 tmp |= srbm_soft_reset;
 990                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 991                 WREG32(mmSRBM_SOFT_RESET, tmp);
 992                 tmp = RREG32(mmSRBM_SOFT_RESET);
 993
 994                 udelay(50);
 995
 996                 tmp &= ~srbm_soft_reset;
 997                 WREG32(mmSRBM_SOFT_RESET, tmp);
 998                 tmp = RREG32(mmSRBM_SOFT_RESET);
 999
1000                 /* Wait a little for things to settle down */
1001                 udelay(50);
1002         }
1003
1004         return 0;
1005 }
1006
1007 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1008                                         struct amdgpu_irq_src *src,
1009                                         unsigned type,
1010                                         enum amdgpu_interrupt_state state)
1011 {
1012         u32 sdma_cntl;
1013
1014         switch (type) {
1015         case AMDGPU_SDMA_IRQ_TRAP0:
1016                 switch (state) {
1017                 case AMDGPU_IRQ_STATE_DISABLE:
1018                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1019                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1020                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1021                         break;
1022                 case AMDGPU_IRQ_STATE_ENABLE:
1023                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1024                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1025                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1026                         break;
1027                 default:
1028                         break;
1029                 }
1030                 break;
1031         case AMDGPU_SDMA_IRQ_TRAP1:
1032                 switch (state) {
1033                 case AMDGPU_IRQ_STATE_DISABLE:
1034                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1035                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1036                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1037                         break;
1038                 case AMDGPU_IRQ_STATE_ENABLE:
1039                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1040                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1041                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1042                         break;
1043                 default:
1044                         break;
1045                 }
1046                 break;
1047         default:
1048                 break;
1049         }
1050         return 0;
1051 }
1052
1053 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1054                                       struct amdgpu_irq_src *source,
1055                                       struct amdgpu_iv_entry *entry)
1056 {
1057         u8 instance_id, queue_id;
1058
1059         instance_id = (entry->ring_id & 0x3) >> 0;
1060         queue_id = (entry->ring_id & 0xc) >> 2;
1061         DRM_DEBUG("IH: SDMA trap\n");
1062         switch (instance_id) {
1063         case 0:
1064                 switch (queue_id) {
1065                 case 0:
1066                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1067                         break;
1068                 case 1:
1069                         /* XXX compute */
1070                         break;
1071                 case 2:
1072                         /* XXX compute */
1073                         break;
1074                 }
1075                 break;
1076         case 1:
1077                 switch (queue_id) {
1078                 case 0:
1079                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1080                         break;
1081                 case 1:
1082                         /* XXX compute */
1083                         break;
1084                 case 2:
1085                         /* XXX compute */
1086                         break;
1087                 }
1088                 break;
1089         }
1090         return 0;
1091 }
1092
1093 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1094                                               struct amdgpu_irq_src *source,
1095                                               struct amdgpu_iv_entry *entry)
1096 {
1097         u8 instance_id, queue_id;
1098
1099         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1100         instance_id = (entry->ring_id & 0x3) >> 0;
1101         queue_id = (entry->ring_id & 0xc) >> 2;
1102
1103         if (instance_id <= 1 && queue_id == 0)
1104                 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1105         return 0;
1106 }
1107
1108 static int sdma_v2_4_set_clockgating_state(void *handle,
1109                                           enum amd_clockgating_state state)
1110 {
1111         /* XXX handled via the smc on VI */
1112         return 0;
1113 }
1114
1115 static int sdma_v2_4_set_powergating_state(void *handle,
1116                                           enum amd_powergating_state state)
1117 {
1118         return 0;
1119 }
1120
1121 static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1122         .name = "sdma_v2_4",
1123         .early_init = sdma_v2_4_early_init,
1124         .late_init = NULL,
1125         .sw_init = sdma_v2_4_sw_init,
1126         .sw_fini = sdma_v2_4_sw_fini,
1127         .hw_init = sdma_v2_4_hw_init,
1128         .hw_fini = sdma_v2_4_hw_fini,
1129         .suspend = sdma_v2_4_suspend,
1130         .resume = sdma_v2_4_resume,
1131         .is_idle = sdma_v2_4_is_idle,
1132         .wait_for_idle = sdma_v2_4_wait_for_idle,
1133         .soft_reset = sdma_v2_4_soft_reset,
1134         .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1135         .set_powergating_state = sdma_v2_4_set_powergating_state,
1136 };
1137
1138 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1139         .type = AMDGPU_RING_TYPE_SDMA,
1140         .align_mask = 0xf,
1141         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1142         .support_64bit_ptrs = false,
1143         .get_rptr = sdma_v2_4_ring_get_rptr,
1144         .get_wptr = sdma_v2_4_ring_get_wptr,
1145         .set_wptr = sdma_v2_4_ring_set_wptr,
1146         .emit_frame_size =
1147                 6 + /* sdma_v2_4_ring_emit_hdp_flush */
1148                 3 + /* hdp invalidate */
1149                 6 + /* sdma_v2_4_ring_emit_pipeline_sync */
1150                 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */
1151                 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */
1152         .emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */
1153         .emit_ib = sdma_v2_4_ring_emit_ib,
1154         .emit_fence = sdma_v2_4_ring_emit_fence,
1155         .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
1156         .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1157         .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1158         .test_ring = sdma_v2_4_ring_test_ring,
1159         .test_ib = sdma_v2_4_ring_test_ib,
1160         .insert_nop = sdma_v2_4_ring_insert_nop,
1161         .pad_ib = sdma_v2_4_ring_pad_ib,
1162         .emit_wreg = sdma_v2_4_ring_emit_wreg,
1163 };
1164
1165 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1166 {
1167         int i;
1168
1169         for (i = 0; i < adev->sdma.num_instances; i++) {
1170                 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1171                 adev->sdma.instance[i].ring.me = i;
1172         }
1173 }
1174
1175 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1176         .set = sdma_v2_4_set_trap_irq_state,
1177         .process = sdma_v2_4_process_trap_irq,
1178 };
1179
1180 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1181         .process = sdma_v2_4_process_illegal_inst_irq,
1182 };
1183
1184 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1185 {
1186         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1187         adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1188         adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1189 }
1190
1191 /**
1192  * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1193  *
1194  * @ring: amdgpu_ring structure holding ring information
1195  * @src_offset: src GPU address
1196  * @dst_offset: dst GPU address
1197  * @byte_count: number of bytes to xfer
1198  *
1199  * Copy GPU buffers using the DMA engine (VI).
1200  * Used by the amdgpu ttm implementation to move pages if
1201  * registered as the asic copy callback.
1202  */
1203 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1204                                        uint64_t src_offset,
1205                                        uint64_t dst_offset,
1206                                        uint32_t byte_count)
1207 {
1208         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1209                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1210         ib->ptr[ib->length_dw++] = byte_count;
1211         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1212         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1213         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1214         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1215         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1216 }
1217
1218 /**
1219  * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1220  *
1221  * @ring: amdgpu_ring structure holding ring information
1222  * @src_data: value to write to buffer
1223  * @dst_offset: dst GPU address
1224  * @byte_count: number of bytes to xfer
1225  *
1226  * Fill GPU buffers using the DMA engine (VI).
1227  */
1228 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1229                                        uint32_t src_data,
1230                                        uint64_t dst_offset,
1231                                        uint32_t byte_count)
1232 {
1233         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1234         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1235         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1236         ib->ptr[ib->length_dw++] = src_data;
1237         ib->ptr[ib->length_dw++] = byte_count;
1238 }
1239
1240 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1241         .copy_max_bytes = 0x1fffff,
1242         .copy_num_dw = 7,
1243         .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1244
1245         .fill_max_bytes = 0x1fffff,
1246         .fill_num_dw = 7,
1247         .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1248 };
1249
1250 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1251 {
1252         adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1253         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1254 }
1255
1256 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1257         .copy_pte_num_dw = 7,
1258         .copy_pte = sdma_v2_4_vm_copy_pte,
1259
1260         .write_pte = sdma_v2_4_vm_write_pte,
1261         .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1262 };
1263
1264 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1265 {
1266         struct drm_gpu_scheduler *sched;
1267         unsigned i;
1268
1269         adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1270         for (i = 0; i < adev->sdma.num_instances; i++) {
1271                 sched = &adev->sdma.instance[i].ring.sched;
1272                 adev->vm_manager.vm_pte_rqs[i] =
1273                         &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1274         }
1275         adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
1276 }
1277
1278 const struct amdgpu_ip_block_version sdma_v2_4_ip_block =
1279 {
1280         .type = AMD_IP_BLOCK_TYPE_SDMA,
1281         .major = 2,
1282         .minor = 4,
1283         .rev = 0,
1284         .funcs = &sdma_v2_4_ip_funcs,
1285 };