drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/kernel.h>
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "amdgpu_atomfirmware.h"
  31
  32 #include "gc/gc_9_0_offset.h"
  33 #include "gc/gc_9_0_sh_mask.h"
  34 #include "vega10_enum.h"
  35 #include "hdp/hdp_4_0_offset.h"
  36
  37 #include "soc15_common.h"
  38 #include "clearstate_gfx9.h"
  39 #include "v9_structs.h"
  40
  41 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
  42
  43 #define GFX9_NUM_GFX_RINGS     1
  44 #define GFX9_MEC_HPD_SIZE 4096
  45 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
  46 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
  47
  48 #define mmPWR_MISC_CNTL_STATUS                                  0x0183
  49 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX                         0
  50 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT        0x0
  51 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT          0x1
  52 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK          0x00000001L
  53 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK            0x00000006L
  54
  55 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
  56 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
  57 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
  58 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
  59 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
  60 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
  61
  62 MODULE_FIRMWARE("amdgpu/vega12_ce.bin");
  63 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin");
  64 MODULE_FIRMWARE("amdgpu/vega12_me.bin");
  65 MODULE_FIRMWARE("amdgpu/vega12_mec.bin");
  66 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin");
  67 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin");
  68
  69 MODULE_FIRMWARE("amdgpu/vega20_ce.bin");
  70 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin");
  71 MODULE_FIRMWARE("amdgpu/vega20_me.bin");
  72 MODULE_FIRMWARE("amdgpu/vega20_mec.bin");
  73 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin");
  74 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin");
  75
  76 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
  77 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
  78 MODULE_FIRMWARE("amdgpu/raven_me.bin");
  79 MODULE_FIRMWARE("amdgpu/raven_mec.bin");
  80 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
  81 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
  82
  83 MODULE_FIRMWARE("amdgpu/picasso_ce.bin");
  84 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin");
  85 MODULE_FIRMWARE("amdgpu/picasso_me.bin");
  86 MODULE_FIRMWARE("amdgpu/picasso_mec.bin");
  87 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin");
  88 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin");
  89
  90 MODULE_FIRMWARE("amdgpu/raven2_ce.bin");
  91 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin");
  92 MODULE_FIRMWARE("amdgpu/raven2_me.bin");
  93 MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
  94 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
  95 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
  96
  97 static const struct soc15_reg_golden golden_settings_gc_9_0[] =
  98 {
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
 113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
 116 };
 117
 118 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
 119 {
 120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107),
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
 125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
 126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042),
 127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
 128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000),
 129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
 130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
 131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
 132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
 133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
 134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
 136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800),
 137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080),
 138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
 139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
 140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
 141 };
 142
 143 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
 144 {
 145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080),
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),
 149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042),
 150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400),
 151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000),
 152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000),
 153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000),
 155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000)
 156 };
 157
 158 static const struct soc15_reg_golden golden_settings_gc_9_1[] =
 159 {
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
 167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
 171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
 172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
 184 };
 185
 186 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
 187 {
 188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
 195 };
 196
 197 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] =
 198 {
 199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000),
 200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
 202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080),
 203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080),
 204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080),
 205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041),
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080),
 213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080),
 214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010),
 216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
 217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
 218 };
 219
 220 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
 221 {
 222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
 223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382)
 224 };
 225
 226 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] =
 227 {
 228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
 244 };
 245
 246 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
 247 {
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
 261 };
 262
 263 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
 264 {
 265         mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 266         mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 267         mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 268         mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 269         mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 270         mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 271         mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 272         mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 273 };
 274
 275 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
 276 {
 277         mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 278         mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 279         mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 280         mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 281         mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 282         mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 283         mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 284         mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 285 };
 286
 287 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
 288 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
 289 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
 290 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041
 291
 292 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
 293 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
 294 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
 295 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
 296 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
 297                                  struct amdgpu_cu_info *cu_info);
 298 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 299 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
 300 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 301
 302 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
 303 {
 304         switch (adev->asic_type) {
 305         case CHIP_VEGA10:
 306                 soc15_program_register_sequence(adev,
 307                                                  golden_settings_gc_9_0,
 308                                                  ARRAY_SIZE(golden_settings_gc_9_0));
 309                 soc15_program_register_sequence(adev,
 310                                                  golden_settings_gc_9_0_vg10,
 311                                                  ARRAY_SIZE(golden_settings_gc_9_0_vg10));
 312                 break;
 313         case CHIP_VEGA12:
 314                 soc15_program_register_sequence(adev,
 315                                                 golden_settings_gc_9_2_1,
 316                                                 ARRAY_SIZE(golden_settings_gc_9_2_1));
 317                 soc15_program_register_sequence(adev,
 318                                                 golden_settings_gc_9_2_1_vg12,
 319                                                 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));
 320                 break;
 321         case CHIP_VEGA20:
 322                 soc15_program_register_sequence(adev,
 323                                                 golden_settings_gc_9_0,
 324                                                 ARRAY_SIZE(golden_settings_gc_9_0));
 325                 soc15_program_register_sequence(adev,
 326                                                 golden_settings_gc_9_0_vg20,
 327                                                 ARRAY_SIZE(golden_settings_gc_9_0_vg20));
 328                 break;
 329         case CHIP_RAVEN:
 330                 soc15_program_register_sequence(adev, golden_settings_gc_9_1,
 331                                                 ARRAY_SIZE(golden_settings_gc_9_1));
 332                 if (adev->rev_id >= 8)
 333                         soc15_program_register_sequence(adev,
 334                                                         golden_settings_gc_9_1_rv2,
 335                                                         ARRAY_SIZE(golden_settings_gc_9_1_rv2));
 336                 else
 337                         soc15_program_register_sequence(adev,
 338                                                         golden_settings_gc_9_1_rv1,
 339                                                         ARRAY_SIZE(golden_settings_gc_9_1_rv1));
 340                 break;
 341         default:
 342                 break;
 343         }
 344
 345         soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
 346                                         (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
 347 }
 348
 349 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
 350 {
 351         adev->gfx.scratch.num_reg = 8;
 352         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 353         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 354 }
 355
 356 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 357                                        bool wc, uint32_t reg, uint32_t val)
 358 {
 359         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 360         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 361                                 WRITE_DATA_DST_SEL(0) |
 362                                 (wc ? WR_CONFIRM : 0));
 363         amdgpu_ring_write(ring, reg);
 364         amdgpu_ring_write(ring, 0);
 365         amdgpu_ring_write(ring, val);
 366 }
 367
 368 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 369                                   int mem_space, int opt, uint32_t addr0,
 370                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 371                                   uint32_t inv)
 372 {
 373         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 374         amdgpu_ring_write(ring,
 375                                  /* memory (1) or register (0) */
 376                                  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 377                                  WAIT_REG_MEM_OPERATION(opt) | /* wait */
 378                                  WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 379                                  WAIT_REG_MEM_ENGINE(eng_sel)));
 380
 381         if (mem_space)
 382                 BUG_ON(addr0 & 0x3); /* Dword align */
 383         amdgpu_ring_write(ring, addr0);
 384         amdgpu_ring_write(ring, addr1);
 385         amdgpu_ring_write(ring, ref);
 386         amdgpu_ring_write(ring, mask);
 387         amdgpu_ring_write(ring, inv); /* poll interval */
 388 }
 389
 390 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
 391 {
 392         struct amdgpu_device *adev = ring->adev;
 393         uint32_t scratch;
 394         uint32_t tmp = 0;
 395         unsigned i;
 396         int r;
 397
 398         r = amdgpu_gfx_scratch_get(adev, &scratch);
 399         if (r)
 400                 return r;
 401
 402         WREG32(scratch, 0xCAFEDEAD);
 403         r = amdgpu_ring_alloc(ring, 3);
 404         if (r)
 405                 goto error_free_scratch;
 406
 407         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 408         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 409         amdgpu_ring_write(ring, 0xDEADBEEF);
 410         amdgpu_ring_commit(ring);
 411
 412         for (i = 0; i < adev->usec_timeout; i++) {
 413                 tmp = RREG32(scratch);
 414                 if (tmp == 0xDEADBEEF)
 415                         break;
 416                 DRM_UDELAY(1);
 417         }
 418
 419         if (i >= adev->usec_timeout)
 420                 r = -ETIMEDOUT;
 421
 422 error_free_scratch:
 423         amdgpu_gfx_scratch_free(adev, scratch);
 424         return r;
 425 }
 426
 427 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 428 {
 429         struct amdgpu_device *adev = ring->adev;
 430         struct amdgpu_ib ib;
 431         struct dma_fence *f = NULL;
 432
 433         unsigned index;
 434         uint64_t gpu_addr;
 435         uint32_t tmp;
 436         long r;
 437
 438         r = amdgpu_device_wb_get(adev, &index);
 439         if (r) {
 440                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 441                 return r;
 442         }
 443
 444         gpu_addr = adev->wb.gpu_addr + (index * 4);
 445         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 446         memset(&ib, 0, sizeof(ib));
 447         r = amdgpu_ib_get(adev, NULL, 16, &ib);
 448         if (r) {
 449                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 450                 goto err1;
 451         }
 452         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 453         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 454         ib.ptr[2] = lower_32_bits(gpu_addr);
 455         ib.ptr[3] = upper_32_bits(gpu_addr);
 456         ib.ptr[4] = 0xDEADBEEF;
 457         ib.length_dw = 5;
 458
 459         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 460         if (r)
 461                 goto err2;
 462
 463         r = dma_fence_wait_timeout(f, false, timeout);
 464         if (r == 0) {
 465                         DRM_ERROR("amdgpu: IB test timed out.\n");
 466                         r = -ETIMEDOUT;
 467                         goto err2;
 468         } else if (r < 0) {
 469                         DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 470                         goto err2;
 471         }
 472
 473         tmp = adev->wb.wb[index];
 474         if (tmp == 0xDEADBEEF) {
 475                         DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 476                         r = 0;
 477         } else {
 478                         DRM_ERROR("ib test on ring %d failed\n", ring->idx);
 479                         r = -EINVAL;
 480         }
 481
 482 err2:
 483         amdgpu_ib_free(adev, &ib, NULL);
 484         dma_fence_put(f);
 485 err1:
 486         amdgpu_device_wb_free(adev, index);
 487         return r;
 488 }
 489
 490
 491 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
 492 {
 493         release_firmware(adev->gfx.pfp_fw);
 494         adev->gfx.pfp_fw = NULL;
 495         release_firmware(adev->gfx.me_fw);
 496         adev->gfx.me_fw = NULL;
 497         release_firmware(adev->gfx.ce_fw);
 498         adev->gfx.ce_fw = NULL;
 499         release_firmware(adev->gfx.rlc_fw);
 500         adev->gfx.rlc_fw = NULL;
 501         release_firmware(adev->gfx.mec_fw);
 502         adev->gfx.mec_fw = NULL;
 503         release_firmware(adev->gfx.mec2_fw);
 504         adev->gfx.mec2_fw = NULL;
 505
 506         kfree(adev->gfx.rlc.register_list_format);
 507 }
 508
 509 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
 510 {
 511         const struct rlc_firmware_header_v2_1 *rlc_hdr;
 512
 513         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
 514         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
 515         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
 516         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
 517         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
 518         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
 519         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
 520         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
 521         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
 522         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
 523         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
 524         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
 525         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
 526         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
 527                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
 528 }
 529
 530 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
 531 {
 532         adev->gfx.me_fw_write_wait = false;
 533         adev->gfx.mec_fw_write_wait = false;
 534
 535         switch (adev->asic_type) {
 536         case CHIP_VEGA10:
 537                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 538                     (adev->gfx.me_feature_version >= 42) &&
 539                     (adev->gfx.pfp_fw_version >=  0x000000b1) &&
 540                     (adev->gfx.pfp_feature_version >= 42))
 541                         adev->gfx.me_fw_write_wait = true;
 542
 543                 if ((adev->gfx.mec_fw_version >=  0x00000193) &&
 544                     (adev->gfx.mec_feature_version >= 42))
 545                         adev->gfx.mec_fw_write_wait = true;
 546                 break;
 547         case CHIP_VEGA12:
 548                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 549                     (adev->gfx.me_feature_version >= 44) &&
 550                     (adev->gfx.pfp_fw_version >=  0x000000b2) &&
 551                     (adev->gfx.pfp_feature_version >= 44))
 552                         adev->gfx.me_fw_write_wait = true;
 553
 554                 if ((adev->gfx.mec_fw_version >=  0x00000196) &&
 555                     (adev->gfx.mec_feature_version >= 44))
 556                         adev->gfx.mec_fw_write_wait = true;
 557                 break;
 558         case CHIP_VEGA20:
 559                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 560                     (adev->gfx.me_feature_version >= 44) &&
 561                     (adev->gfx.pfp_fw_version >=  0x000000b2) &&
 562                     (adev->gfx.pfp_feature_version >= 44))
 563                         adev->gfx.me_fw_write_wait = true;
 564
 565                 if ((adev->gfx.mec_fw_version >=  0x00000197) &&
 566                     (adev->gfx.mec_feature_version >= 44))
 567                         adev->gfx.mec_fw_write_wait = true;
 568                 break;
 569         case CHIP_RAVEN:
 570                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 571                     (adev->gfx.me_feature_version >= 42) &&
 572                     (adev->gfx.pfp_fw_version >=  0x000000b1) &&
 573                     (adev->gfx.pfp_feature_version >= 42))
 574                         adev->gfx.me_fw_write_wait = true;
 575
 576                 if ((adev->gfx.mec_fw_version >=  0x00000192) &&
 577                     (adev->gfx.mec_feature_version >= 42))
 578                         adev->gfx.mec_fw_write_wait = true;
 579                 break;
 580         default:
 581                 break;
 582         }
 583 }
 584
 585 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 586 {
 587         const char *chip_name;
 588         char fw_name[30];
 589         int err;
 590         struct amdgpu_firmware_info *info = NULL;
 591         const struct common_firmware_header *header = NULL;
 592         const struct gfx_firmware_header_v1_0 *cp_hdr;
 593         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 594         unsigned int *tmp = NULL;
 595         unsigned int i = 0;
 596         uint16_t version_major;
 597         uint16_t version_minor;
 598
 599         DRM_DEBUG("\n");
 600
 601         switch (adev->asic_type) {
 602         case CHIP_VEGA10:
 603                 chip_name = "vega10";
 604                 break;
 605         case CHIP_VEGA12:
 606                 chip_name = "vega12";
 607                 break;
 608         case CHIP_VEGA20:
 609                 chip_name = "vega20";
 610                 break;
 611         case CHIP_RAVEN:
 612                 if (adev->rev_id >= 8)
 613                         chip_name = "raven2";
 614                 else if (adev->pdev->device == 0x15d8)
 615                         chip_name = "picasso";
 616                 else
 617                         chip_name = "raven";
 618                 break;
 619         default:
 620                 BUG();
 621         }
 622
 623         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 624         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 625         if (err)
 626                 goto out;
 627         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 628         if (err)
 629                 goto out;
 630         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 631         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 632         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 633
 634         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 635         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 636         if (err)
 637                 goto out;
 638         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 639         if (err)
 640                 goto out;
 641         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 642         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 643         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 644
 645         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 646         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 647         if (err)
 648                 goto out;
 649         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 650         if (err)
 651                 goto out;
 652         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 653         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 654         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 655
 656         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 657         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 658         if (err)
 659                 goto out;
 660         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 661         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 662
 663         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 664         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 665         if (version_major == 2 && version_minor == 1)
 666                 adev->gfx.rlc.is_rlc_v2_1 = true;
 667
 668         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 669         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 670         adev->gfx.rlc.save_and_restore_offset =
 671                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
 672         adev->gfx.rlc.clear_state_descriptor_offset =
 673                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
 674         adev->gfx.rlc.avail_scratch_ram_locations =
 675                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
 676         adev->gfx.rlc.reg_restore_list_size =
 677                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
 678         adev->gfx.rlc.reg_list_format_start =
 679                         le32_to_cpu(rlc_hdr->reg_list_format_start);
 680         adev->gfx.rlc.reg_list_format_separate_start =
 681                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
 682         adev->gfx.rlc.starting_offsets_start =
 683                         le32_to_cpu(rlc_hdr->starting_offsets_start);
 684         adev->gfx.rlc.reg_list_format_size_bytes =
 685                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
 686         adev->gfx.rlc.reg_list_size_bytes =
 687                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
 688         adev->gfx.rlc.register_list_format =
 689                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
 690                                 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
 691         if (!adev->gfx.rlc.register_list_format) {
 692                 err = -ENOMEM;
 693                 goto out;
 694         }
 695
 696         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 697                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 698         for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
 699                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
 700
 701         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
 702
 703         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 704                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 705         for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
 706                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
 707
 708         if (adev->gfx.rlc.is_rlc_v2_1)
 709                 gfx_v9_0_init_rlc_ext_microcode(adev);
 710
 711         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 712         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 713         if (err)
 714                 goto out;
 715         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 716         if (err)
 717                 goto out;
 718         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 719         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 720         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 721
 722
 723         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 724         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 725         if (!err) {
 726                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 727                 if (err)
 728                         goto out;
 729                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 730                 adev->gfx.mec2_fw->data;
 731                 adev->gfx.mec2_fw_version =
 732                 le32_to_cpu(cp_hdr->header.ucode_version);
 733                 adev->gfx.mec2_feature_version =
 734                 le32_to_cpu(cp_hdr->ucode_feature_version);
 735         } else {
 736                 err = 0;
 737                 adev->gfx.mec2_fw = NULL;
 738         }
 739
 740         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 741                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 742                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 743                 info->fw = adev->gfx.pfp_fw;
 744                 header = (const struct common_firmware_header *)info->fw->data;
 745                 adev->firmware.fw_size +=
 746                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 747
 748                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 749                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 750                 info->fw = adev->gfx.me_fw;
 751                 header = (const struct common_firmware_header *)info->fw->data;
 752                 adev->firmware.fw_size +=
 753                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 754
 755                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 756                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 757                 info->fw = adev->gfx.ce_fw;
 758                 header = (const struct common_firmware_header *)info->fw->data;
 759                 adev->firmware.fw_size +=
 760                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 761
 762                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 763                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 764                 info->fw = adev->gfx.rlc_fw;
 765                 header = (const struct common_firmware_header *)info->fw->data;
 766                 adev->firmware.fw_size +=
 767                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 768
 769                 if (adev->gfx.rlc.is_rlc_v2_1 &&
 770                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
 771                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
 772                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
 773                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
 774                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
 775                         info->fw = adev->gfx.rlc_fw;
 776                         adev->firmware.fw_size +=
 777                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
 778
 779                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
 780                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
 781                         info->fw = adev->gfx.rlc_fw;
 782                         adev->firmware.fw_size +=
 783                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
 784
 785                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
 786                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
 787                         info->fw = adev->gfx.rlc_fw;
 788                         adev->firmware.fw_size +=
 789                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
 790                 }
 791
 792                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 793                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 794                 info->fw = adev->gfx.mec_fw;
 795                 header = (const struct common_firmware_header *)info->fw->data;
 796                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 797                 adev->firmware.fw_size +=
 798                         ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 799
 800                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
 801                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
 802                 info->fw = adev->gfx.mec_fw;
 803                 adev->firmware.fw_size +=
 804                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 805
 806                 if (adev->gfx.mec2_fw) {
 807                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 808                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 809                         info->fw = adev->gfx.mec2_fw;
 810                         header = (const struct common_firmware_header *)info->fw->data;
 811                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 812                         adev->firmware.fw_size +=
 813                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 814                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 815                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 816                         info->fw = adev->gfx.mec2_fw;
 817                         adev->firmware.fw_size +=
 818                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 819                 }
 820
 821         }
 822
 823 out:
 824         gfx_v9_0_check_fw_write_wait(adev);
 825         if (err) {
 826                 dev_err(adev->dev,
 827                         "gfx9: Failed to load firmware \"%s\"\n",
 828                         fw_name);
 829                 release_firmware(adev->gfx.pfp_fw);
 830                 adev->gfx.pfp_fw = NULL;
 831                 release_firmware(adev->gfx.me_fw);
 832                 adev->gfx.me_fw = NULL;
 833                 release_firmware(adev->gfx.ce_fw);
 834                 adev->gfx.ce_fw = NULL;
 835                 release_firmware(adev->gfx.rlc_fw);
 836                 adev->gfx.rlc_fw = NULL;
 837                 release_firmware(adev->gfx.mec_fw);
 838                 adev->gfx.mec_fw = NULL;
 839                 release_firmware(adev->gfx.mec2_fw);
 840                 adev->gfx.mec2_fw = NULL;
 841         }
 842         return err;
 843 }
 844
 845 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
 846 {
 847         u32 count = 0;
 848         const struct cs_section_def *sect = NULL;
 849         const struct cs_extent_def *ext = NULL;
 850
 851         /* begin clear state */
 852         count += 2;
 853         /* context control state */
 854         count += 3;
 855
 856         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
 857                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 858                         if (sect->id == SECT_CONTEXT)
 859                                 count += 2 + ext->reg_count;
 860                         else
 861                                 return 0;
 862                 }
 863         }
 864
 865         /* end clear state */
 866         count += 2;
 867         /* clear state */
 868         count += 2;
 869
 870         return count;
 871 }
 872
 873 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
 874                                     volatile u32 *buffer)
 875 {
 876         u32 count = 0, i;
 877         const struct cs_section_def *sect = NULL;
 878         const struct cs_extent_def *ext = NULL;
 879
 880         if (adev->gfx.rlc.cs_data == NULL)
 881                 return;
 882         if (buffer == NULL)
 883                 return;
 884
 885         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 886         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 887
 888         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 889         buffer[count++] = cpu_to_le32(0x80000000);
 890         buffer[count++] = cpu_to_le32(0x80000000);
 891
 892         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 893                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 894                         if (sect->id == SECT_CONTEXT) {
 895                                 buffer[count++] =
 896                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 897                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 898                                                 PACKET3_SET_CONTEXT_REG_START);
 899                                 for (i = 0; i < ext->reg_count; i++)
 900                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 901                         } else {
 902                                 return;
 903                         }
 904                 }
 905         }
 906
 907         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 908         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 909
 910         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 911         buffer[count++] = cpu_to_le32(0);
 912 }
 913
 914 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev)
 915 {
 916         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
 917         uint32_t pg_always_on_cu_num = 2;
 918         uint32_t always_on_cu_num;
 919         uint32_t i, j, k;
 920         uint32_t mask, cu_bitmap, counter;
 921
 922         if (adev->flags & AMD_IS_APU)
 923                 always_on_cu_num = 4;
 924         else if (adev->asic_type == CHIP_VEGA12)
 925                 always_on_cu_num = 8;
 926         else
 927                 always_on_cu_num = 12;
 928
 929         mutex_lock(&adev->grbm_idx_mutex);
 930         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
 931                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
 932                         mask = 1;
 933                         cu_bitmap = 0;
 934                         counter = 0;
 935                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
 936
 937                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
 938                                 if (cu_info->bitmap[i][j] & mask) {
 939                                         if (counter == pg_always_on_cu_num)
 940                                                 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap);
 941                                         if (counter < always_on_cu_num)
 942                                                 cu_bitmap |= mask;
 943                                         else
 944                                                 break;
 945                                         counter++;
 946                                 }
 947                                 mask <<= 1;
 948                         }
 949
 950                         WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap);
 951                         cu_info->ao_cu_bitmap[i][j] = cu_bitmap;
 952                 }
 953         }
 954         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 955         mutex_unlock(&adev->grbm_idx_mutex);
 956 }
 957
 958 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
 959 {
 960         uint32_t data;
 961
 962         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
 963         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
 964         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
 965         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
 966         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
 967
 968         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
 969         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
 970
 971         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
 972         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
 973
 974         mutex_lock(&adev->grbm_idx_mutex);
 975         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
 976         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 977         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
 978
 979         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
 980         data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
 981         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
 982         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
 983         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
 984
 985         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
 986         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
 987         data &= 0x0000FFFF;
 988         data |= 0x00C00000;
 989         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
 990
 991         /*
 992          * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven),
 993          * programmed in gfx_v9_0_init_always_on_cu_mask()
 994          */
 995
 996         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
 997          * but used for RLC_LB_CNTL configuration */
 998         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
 999         data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
1000         data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
1001         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
1002         mutex_unlock(&adev->grbm_idx_mutex);
1003
1004         gfx_v9_0_init_always_on_cu_mask(adev);
1005 }
1006
1007 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev)
1008 {
1009         uint32_t data;
1010
1011         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
1012         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
1013         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8);
1014         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
1015         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16));
1016
1017         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
1018         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
1019
1020         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
1021         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800);
1022
1023         mutex_lock(&adev->grbm_idx_mutex);
1024         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
1025         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1026         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
1027
1028         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
1029         data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
1030         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
1031         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
1032         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
1033
1034         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
1035         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
1036         data &= 0x0000FFFF;
1037         data |= 0x00C00000;
1038         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
1039
1040         /*
1041          * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON),
1042          * programmed in gfx_v9_0_init_always_on_cu_mask()
1043          */
1044
1045         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1046          * but used for RLC_LB_CNTL configuration */
1047         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
1048         data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
1049         data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
1050         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
1051         mutex_unlock(&adev->grbm_idx_mutex);
1052
1053         gfx_v9_0_init_always_on_cu_mask(adev);
1054 }
1055
1056 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
1057 {
1058         WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
1059 }
1060
1061 static void rv_init_cp_jump_table(struct amdgpu_device *adev)
1062 {
1063         const __le32 *fw_data;
1064         volatile u32 *dst_ptr;
1065         int me, i, max_me = 5;
1066         u32 bo_offset = 0;
1067         u32 table_offset, table_size;
1068
1069         /* write the cp table buffer */
1070         dst_ptr = adev->gfx.rlc.cp_table_ptr;
1071         for (me = 0; me < max_me; me++) {
1072                 if (me == 0) {
1073                         const struct gfx_firmware_header_v1_0 *hdr =
1074                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1075                         fw_data = (const __le32 *)
1076                                 (adev->gfx.ce_fw->data +
1077                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1078                         table_offset = le32_to_cpu(hdr->jt_offset);
1079                         table_size = le32_to_cpu(hdr->jt_size);
1080                 } else if (me == 1) {
1081                         const struct gfx_firmware_header_v1_0 *hdr =
1082                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1083                         fw_data = (const __le32 *)
1084                                 (adev->gfx.pfp_fw->data +
1085                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1086                         table_offset = le32_to_cpu(hdr->jt_offset);
1087                         table_size = le32_to_cpu(hdr->jt_size);
1088                 } else if (me == 2) {
1089                         const struct gfx_firmware_header_v1_0 *hdr =
1090                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1091                         fw_data = (const __le32 *)
1092                                 (adev->gfx.me_fw->data +
1093                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1094                         table_offset = le32_to_cpu(hdr->jt_offset);
1095                         table_size = le32_to_cpu(hdr->jt_size);
1096                 } else if (me == 3) {
1097                         const struct gfx_firmware_header_v1_0 *hdr =
1098                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1099                         fw_data = (const __le32 *)
1100                                 (adev->gfx.mec_fw->data +
1101                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1102                         table_offset = le32_to_cpu(hdr->jt_offset);
1103                         table_size = le32_to_cpu(hdr->jt_size);
1104                 } else  if (me == 4) {
1105                         const struct gfx_firmware_header_v1_0 *hdr =
1106                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
1107                         fw_data = (const __le32 *)
1108                                 (adev->gfx.mec2_fw->data +
1109                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1110                         table_offset = le32_to_cpu(hdr->jt_offset);
1111                         table_size = le32_to_cpu(hdr->jt_size);
1112                 }
1113
1114                 for (i = 0; i < table_size; i ++) {
1115                         dst_ptr[bo_offset + i] =
1116                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
1117                 }
1118
1119                 bo_offset += table_size;
1120         }
1121 }
1122
1123 static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
1124 {
1125         /* clear state block */
1126         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1127                         &adev->gfx.rlc.clear_state_gpu_addr,
1128                         (void **)&adev->gfx.rlc.cs_ptr);
1129
1130         /* jump table block */
1131         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1132                         &adev->gfx.rlc.cp_table_gpu_addr,
1133                         (void **)&adev->gfx.rlc.cp_table_ptr);
1134 }
1135
1136 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
1137 {
1138         volatile u32 *dst_ptr;
1139         u32 dws;
1140         const struct cs_section_def *cs_data;
1141         int r;
1142
1143         adev->gfx.rlc.cs_data = gfx9_cs_data;
1144
1145         cs_data = adev->gfx.rlc.cs_data;
1146
1147         if (cs_data) {
1148                 /* clear state block */
1149                 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
1150                 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
1151                                               AMDGPU_GEM_DOMAIN_VRAM,
1152                                               &adev->gfx.rlc.clear_state_obj,
1153                                               &adev->gfx.rlc.clear_state_gpu_addr,
1154                                               (void **)&adev->gfx.rlc.cs_ptr);
1155                 if (r) {
1156                         dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
1157                                 r);
1158                         gfx_v9_0_rlc_fini(adev);
1159                         return r;
1160                 }
1161                 /* set up the cs buffer */
1162                 dst_ptr = adev->gfx.rlc.cs_ptr;
1163                 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
1164                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
1165                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1166                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1167         }
1168
1169         if (adev->asic_type == CHIP_RAVEN) {
1170                 /* TODO: double check the cp_table_size for RV */
1171                 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1172                 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
1173                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1174                                               &adev->gfx.rlc.cp_table_obj,
1175                                               &adev->gfx.rlc.cp_table_gpu_addr,
1176                                               (void **)&adev->gfx.rlc.cp_table_ptr);
1177                 if (r) {
1178                         dev_err(adev->dev,
1179                                 "(%d) failed to create cp table bo\n", r);
1180                         gfx_v9_0_rlc_fini(adev);
1181                         return r;
1182                 }
1183
1184                 rv_init_cp_jump_table(adev);
1185                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
1186                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
1187         }
1188
1189         switch (adev->asic_type) {
1190         case CHIP_RAVEN:
1191                 gfx_v9_0_init_lbpw(adev);
1192                 break;
1193         case CHIP_VEGA20:
1194                 gfx_v9_4_init_lbpw(adev);
1195                 break;
1196         default:
1197                 break;
1198         }
1199
1200         return 0;
1201 }
1202
1203 static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
1204 {
1205         int r;
1206
1207         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1208         if (unlikely(r != 0))
1209                 return r;
1210
1211         r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
1212                         AMDGPU_GEM_DOMAIN_VRAM);
1213         if (!r)
1214                 adev->gfx.rlc.clear_state_gpu_addr =
1215                         amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
1216
1217         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1218
1219         return r;
1220 }
1221
1222 static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
1223 {
1224         int r;
1225
1226         if (!adev->gfx.rlc.clear_state_obj)
1227                 return;
1228
1229         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
1230         if (likely(r == 0)) {
1231                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1232                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1233         }
1234 }
1235
1236 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
1237 {
1238         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1239         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1240 }
1241
1242 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
1243 {
1244         int r;
1245         u32 *hpd;
1246         const __le32 *fw_data;
1247         unsigned fw_size;
1248         u32 *fw;
1249         size_t mec_hpd_size;
1250
1251         const struct gfx_firmware_header_v1_0 *mec_hdr;
1252
1253         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1254
1255         /* take ownership of the relevant compute queues */
1256         amdgpu_gfx_compute_queue_acquire(adev);
1257         mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
1258
1259         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1260                                       AMDGPU_GEM_DOMAIN_VRAM,
1261                                       &adev->gfx.mec.hpd_eop_obj,
1262                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1263                                       (void **)&hpd);
1264         if (r) {
1265                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1266                 gfx_v9_0_mec_fini(adev);
1267                 return r;
1268         }
1269
1270         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1271
1272         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1273         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1274
1275         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1276
1277         fw_data = (const __le32 *)
1278                 (adev->gfx.mec_fw->data +
1279                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1280         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
1281
1282         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1283                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1284                                       &adev->gfx.mec.mec_fw_obj,
1285                                       &adev->gfx.mec.mec_fw_gpu_addr,
1286                                       (void **)&fw);
1287         if (r) {
1288                 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
1289                 gfx_v9_0_mec_fini(adev);
1290                 return r;
1291         }
1292
1293         memcpy(fw, fw_data, fw_size);
1294
1295         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1296         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1297
1298         return 0;
1299 }
1300
1301 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1302 {
1303         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1304                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1305                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1306                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
1307                 (SQ_IND_INDEX__FORCE_READ_MASK));
1308         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1309 }
1310
1311 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
1312                            uint32_t wave, uint32_t thread,
1313                            uint32_t regno, uint32_t num, uint32_t *out)
1314 {
1315         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1316                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1317                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1318                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1319                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
1320                 (SQ_IND_INDEX__FORCE_READ_MASK) |
1321                 (SQ_IND_INDEX__AUTO_INCR_MASK));
1322         while (num--)
1323                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1324 }
1325
1326 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1327 {
1328         /* type 1 wave data */
1329         dst[(*no_fields)++] = 1;
1330         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1331         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1332         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1333         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1334         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1335         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
1336         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1337         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1338         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
1339         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
1340         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
1341         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1342         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
1343         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
1344 }
1345
1346 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1347                                      uint32_t wave, uint32_t start,
1348                                      uint32_t size, uint32_t *dst)
1349 {
1350         wave_read_regs(
1351                 adev, simd, wave, 0,
1352                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
1353 }
1354
1355 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1356                                      uint32_t wave, uint32_t thread,
1357                                      uint32_t start, uint32_t size,
1358                                      uint32_t *dst)
1359 {
1360         wave_read_regs(
1361                 adev, simd, wave, thread,
1362                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1363 }
1364
1365 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
1366                                   u32 me, u32 pipe, u32 q)
1367 {
1368         soc15_grbm_select(adev, me, pipe, q, 0);
1369 }
1370
1371 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1372         .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1373         .select_se_sh = &gfx_v9_0_select_se_sh,
1374         .read_wave_data = &gfx_v9_0_read_wave_data,
1375         .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1376         .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
1377         .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q
1378 };
1379
1380 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1381 {
1382         u32 gb_addr_config;
1383         int err;
1384
1385         adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1386
1387         switch (adev->asic_type) {
1388         case CHIP_VEGA10:
1389                 adev->gfx.config.max_hw_contexts = 8;
1390                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1391                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1392                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1393                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1394                 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1395                 break;
1396         case CHIP_VEGA12:
1397                 adev->gfx.config.max_hw_contexts = 8;
1398                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1399                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1400                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1401                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1402                 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN;
1403                 DRM_INFO("fix gfx.config for vega12\n");
1404                 break;
1405         case CHIP_VEGA20:
1406                 adev->gfx.config.max_hw_contexts = 8;
1407                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1408                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1409                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1410                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1411                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1412                 gb_addr_config &= ~0xf3e777ff;
1413                 gb_addr_config |= 0x22014042;
1414                 /* check vbios table if gpu info is not available */
1415                 err = amdgpu_atomfirmware_get_gfx_info(adev);
1416                 if (err)
1417                         return err;
1418                 break;
1419         case CHIP_RAVEN:
1420                 adev->gfx.config.max_hw_contexts = 8;
1421                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1422                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1423                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1424                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1425                 if (adev->rev_id >= 8)
1426                         gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN;
1427                 else
1428                         gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1429                 break;
1430         default:
1431                 BUG();
1432                 break;
1433         }
1434
1435         adev->gfx.config.gb_addr_config = gb_addr_config;
1436
1437         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1438                         REG_GET_FIELD(
1439                                         adev->gfx.config.gb_addr_config,
1440                                         GB_ADDR_CONFIG,
1441                                         NUM_PIPES);
1442
1443         adev->gfx.config.max_tile_pipes =
1444                 adev->gfx.config.gb_addr_config_fields.num_pipes;
1445
1446         adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1447                         REG_GET_FIELD(
1448                                         adev->gfx.config.gb_addr_config,
1449                                         GB_ADDR_CONFIG,
1450                                         NUM_BANKS);
1451         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1452                         REG_GET_FIELD(
1453                                         adev->gfx.config.gb_addr_config,
1454                                         GB_ADDR_CONFIG,
1455                                         MAX_COMPRESSED_FRAGS);
1456         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1457                         REG_GET_FIELD(
1458                                         adev->gfx.config.gb_addr_config,
1459                                         GB_ADDR_CONFIG,
1460                                         NUM_RB_PER_SE);
1461         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1462                         REG_GET_FIELD(
1463                                         adev->gfx.config.gb_addr_config,
1464                                         GB_ADDR_CONFIG,
1465                                         NUM_SHADER_ENGINES);
1466         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1467                         REG_GET_FIELD(
1468                                         adev->gfx.config.gb_addr_config,
1469                                         GB_ADDR_CONFIG,
1470                                         PIPE_INTERLEAVE_SIZE));
1471
1472         return 0;
1473 }
1474
1475 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1476                                    struct amdgpu_ngg_buf *ngg_buf,
1477                                    int size_se,
1478                                    int default_size_se)
1479 {
1480         int r;
1481
1482         if (size_se < 0) {
1483                 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1484                 return -EINVAL;
1485         }
1486         size_se = size_se ? size_se : default_size_se;
1487
1488         ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
1489         r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1490                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1491                                     &ngg_buf->bo,
1492                                     &ngg_buf->gpu_addr,
1493                                     NULL);
1494         if (r) {
1495                 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1496                 return r;
1497         }
1498         ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1499
1500         return r;
1501 }
1502
1503 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1504 {
1505         int i;
1506
1507         for (i = 0; i < NGG_BUF_MAX; i++)
1508                 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1509                                       &adev->gfx.ngg.buf[i].gpu_addr,
1510                                       NULL);
1511
1512         memset(&adev->gfx.ngg.buf[0], 0,
1513                         sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1514
1515         adev->gfx.ngg.init = false;
1516
1517         return 0;
1518 }
1519
1520 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1521 {
1522         int r;
1523
1524         if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1525                 return 0;
1526
1527         /* GDS reserve memory: 64 bytes alignment */
1528         adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1529         adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1530         adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1531         adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
1532         adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
1533
1534         /* Primitive Buffer */
1535         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
1536                                     amdgpu_prim_buf_per_se,
1537                                     64 * 1024);
1538         if (r) {
1539                 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1540                 goto err;
1541         }
1542
1543         /* Position Buffer */
1544         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
1545                                     amdgpu_pos_buf_per_se,
1546                                     256 * 1024);
1547         if (r) {
1548                 dev_err(adev->dev, "Failed to create Position Buffer\n");
1549                 goto err;
1550         }
1551
1552         /* Control Sideband */
1553         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
1554                                     amdgpu_cntl_sb_buf_per_se,
1555                                     256);
1556         if (r) {
1557                 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1558                 goto err;
1559         }
1560
1561         /* Parameter Cache, not created by default */
1562         if (amdgpu_param_buf_per_se <= 0)
1563                 goto out;
1564
1565         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
1566                                     amdgpu_param_buf_per_se,
1567                                     512 * 1024);
1568         if (r) {
1569                 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1570                 goto err;
1571         }
1572
1573 out:
1574         adev->gfx.ngg.init = true;
1575         return 0;
1576 err:
1577         gfx_v9_0_ngg_fini(adev);
1578         return r;
1579 }
1580
1581 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1582 {
1583         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1584         int r;
1585         u32 data, base;
1586
1587         if (!amdgpu_ngg)
1588                 return 0;
1589
1590         /* Program buffer size */
1591         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
1592                              adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
1593         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
1594                              adev->gfx.ngg.buf[NGG_POS].size >> 8);
1595         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
1596
1597         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
1598                              adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
1599         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
1600                              adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
1601         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
1602
1603         /* Program buffer base address */
1604         base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1605         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
1606         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
1607
1608         base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1609         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
1610         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
1611
1612         base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1613         data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
1614         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
1615
1616         base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1617         data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
1618         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
1619
1620         base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1621         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
1622         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
1623
1624         base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1625         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
1626         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
1627
1628         /* Clear GDS reserved memory */
1629         r = amdgpu_ring_alloc(ring, 17);
1630         if (r) {
1631                 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1632                           ring->idx, r);
1633                 return r;
1634         }
1635
1636         gfx_v9_0_write_data_to_reg(ring, 0, false,
1637                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
1638                                    (adev->gds.mem.total_size +
1639                                     adev->gfx.ngg.gds_reserve_size));
1640
1641         amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1642         amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1643                                 PACKET3_DMA_DATA_DST_SEL(1) |
1644                                 PACKET3_DMA_DATA_SRC_SEL(2)));
1645         amdgpu_ring_write(ring, 0);
1646         amdgpu_ring_write(ring, 0);
1647         amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1648         amdgpu_ring_write(ring, 0);
1649         amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
1650                                 adev->gfx.ngg.gds_reserve_size);
1651
1652         gfx_v9_0_write_data_to_reg(ring, 0, false,
1653                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
1654
1655         amdgpu_ring_commit(ring);
1656
1657         return 0;
1658 }
1659
1660 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1661                                       int mec, int pipe, int queue)
1662 {
1663         int r;
1664         unsigned irq_type;
1665         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1666
1667         ring = &adev->gfx.compute_ring[ring_id];
1668
1669         /* mec0 is me1 */
1670         ring->me = mec + 1;
1671         ring->pipe = pipe;
1672         ring->queue = queue;
1673
1674         ring->ring_obj = NULL;
1675         ring->use_doorbell = true;
1676         ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
1677         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1678                                 + (ring_id * GFX9_MEC_HPD_SIZE);
1679         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1680
1681         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1682                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1683                 + ring->pipe;
1684
1685         /* type-2 packets are deprecated on MEC, use type-3 instead */
1686         r = amdgpu_ring_init(adev, ring, 1024,
1687                              &adev->gfx.eop_irq, irq_type);
1688         if (r)
1689                 return r;
1690
1691
1692         return 0;
1693 }
1694
1695 static int gfx_v9_0_sw_init(void *handle)
1696 {
1697         int i, j, k, r, ring_id;
1698         struct amdgpu_ring *ring;
1699         struct amdgpu_kiq *kiq;
1700         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1701
1702         switch (adev->asic_type) {
1703         case CHIP_VEGA10:
1704         case CHIP_VEGA12:
1705         case CHIP_VEGA20:
1706         case CHIP_RAVEN:
1707                 adev->gfx.mec.num_mec = 2;
1708                 break;
1709         default:
1710                 adev->gfx.mec.num_mec = 1;
1711                 break;
1712         }
1713
1714         adev->gfx.mec.num_pipe_per_mec = 4;
1715         adev->gfx.mec.num_queue_per_pipe = 8;
1716
1717         /* EOP Event */
1718         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
1719         if (r)
1720                 return r;
1721
1722         /* Privileged reg */
1723         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
1724                               &adev->gfx.priv_reg_irq);
1725         if (r)
1726                 return r;
1727
1728         /* Privileged inst */
1729         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
1730                               &adev->gfx.priv_inst_irq);
1731         if (r)
1732                 return r;
1733
1734         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1735
1736         gfx_v9_0_scratch_init(adev);
1737
1738         r = gfx_v9_0_init_microcode(adev);
1739         if (r) {
1740                 DRM_ERROR("Failed to load gfx firmware!\n");
1741                 return r;
1742         }
1743
1744         r = gfx_v9_0_rlc_init(adev);
1745         if (r) {
1746                 DRM_ERROR("Failed to init rlc BOs!\n");
1747                 return r;
1748         }
1749
1750         r = gfx_v9_0_mec_init(adev);
1751         if (r) {
1752                 DRM_ERROR("Failed to init MEC BOs!\n");
1753                 return r;
1754         }
1755
1756         /* set up the gfx ring */
1757         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1758                 ring = &adev->gfx.gfx_ring[i];
1759                 ring->ring_obj = NULL;
1760                 if (!i)
1761                         sprintf(ring->name, "gfx");
1762                 else
1763                         sprintf(ring->name, "gfx_%d", i);
1764                 ring->use_doorbell = true;
1765                 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1766                 r = amdgpu_ring_init(adev, ring, 1024,
1767                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1768                 if (r)
1769                         return r;
1770         }
1771
1772         /* set up the compute queues - allocate horizontally across pipes */
1773         ring_id = 0;
1774         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1775                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1776                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1777                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1778                                         continue;
1779
1780                                 r = gfx_v9_0_compute_ring_init(adev,
1781                                                                ring_id,
1782                                                                i, k, j);
1783                                 if (r)
1784                                         return r;
1785
1786                                 ring_id++;
1787                         }
1788                 }
1789         }
1790
1791         r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
1792         if (r) {
1793                 DRM_ERROR("Failed to init KIQ BOs!\n");
1794                 return r;
1795         }
1796
1797         kiq = &adev->gfx.kiq;
1798         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1799         if (r)
1800                 return r;
1801
1802         /* create MQD for all compute queues as wel as KIQ for SRIOV case */
1803         r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
1804         if (r)
1805                 return r;
1806
1807         adev->gfx.ce_ram_size = 0x8000;
1808
1809         r = gfx_v9_0_gpu_early_init(adev);
1810         if (r)
1811                 return r;
1812
1813         r = gfx_v9_0_ngg_init(adev);
1814         if (r)
1815                 return r;
1816
1817         return 0;
1818 }
1819
1820
1821 static int gfx_v9_0_sw_fini(void *handle)
1822 {
1823         int i;
1824         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1825
1826         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1827         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1828         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1829
1830         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1831                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1832         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1833                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1834
1835         amdgpu_gfx_compute_mqd_sw_fini(adev);
1836         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1837         amdgpu_gfx_kiq_fini(adev);
1838
1839         gfx_v9_0_mec_fini(adev);
1840         gfx_v9_0_ngg_fini(adev);
1841         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1842                                 &adev->gfx.rlc.clear_state_gpu_addr,
1843                                 (void **)&adev->gfx.rlc.cs_ptr);
1844         if (adev->asic_type == CHIP_RAVEN) {
1845                 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1846                                 &adev->gfx.rlc.cp_table_gpu_addr,
1847                                 (void **)&adev->gfx.rlc.cp_table_ptr);
1848         }
1849         gfx_v9_0_free_microcode(adev);
1850
1851         return 0;
1852 }
1853
1854
1855 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1856 {
1857         /* TODO */
1858 }
1859
1860 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1861 {
1862         u32 data;
1863
1864         if (instance == 0xffffffff)
1865                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1866         else
1867                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1868
1869         if (se_num == 0xffffffff)
1870                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1871         else
1872                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1873
1874         if (sh_num == 0xffffffff)
1875                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1876         else
1877                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1878
1879         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1880 }
1881
1882 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1883 {
1884         u32 data, mask;
1885
1886         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1887         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1888
1889         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1890         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1891
1892         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1893                                          adev->gfx.config.max_sh_per_se);
1894
1895         return (~data) & mask;
1896 }
1897
1898 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1899 {
1900         int i, j;
1901         u32 data;
1902         u32 active_rbs = 0;
1903         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1904                                         adev->gfx.config.max_sh_per_se;
1905
1906         mutex_lock(&adev->grbm_idx_mutex);
1907         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1908                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1909                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1910                         data = gfx_v9_0_get_rb_active_bitmap(adev);
1911                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1912                                                rb_bitmap_width_per_sh);
1913                 }
1914         }
1915         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1916         mutex_unlock(&adev->grbm_idx_mutex);
1917
1918         adev->gfx.config.backend_enable_mask = active_rbs;
1919         adev->gfx.config.num_rbs = hweight32(active_rbs);
1920 }
1921
1922 #define DEFAULT_SH_MEM_BASES    (0x6000)
1923 #define FIRST_COMPUTE_VMID      (8)
1924 #define LAST_COMPUTE_VMID       (16)
1925 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1926 {
1927         int i;
1928         uint32_t sh_mem_config;
1929         uint32_t sh_mem_bases;
1930
1931         /*
1932          * Configure apertures:
1933          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1934          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1935          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1936          */
1937         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1938
1939         sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1940                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1941                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1942
1943         mutex_lock(&adev->srbm_mutex);
1944         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1945                 soc15_grbm_select(adev, 0, 0, 0, i);
1946                 /* CP and shaders */
1947                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1948                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1949         }
1950         soc15_grbm_select(adev, 0, 0, 0, 0);
1951         mutex_unlock(&adev->srbm_mutex);
1952 }
1953
1954 static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
1955 {
1956         u32 tmp;
1957         int i;
1958
1959         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1960
1961         gfx_v9_0_tiling_mode_table_init(adev);
1962
1963         gfx_v9_0_setup_rb(adev);
1964         gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1965         adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
1966
1967         /* XXX SH_MEM regs */
1968         /* where to put LDS, scratch, GPUVM in FSA64 space */
1969         mutex_lock(&adev->srbm_mutex);
1970         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
1971                 soc15_grbm_select(adev, 0, 0, 0, i);
1972                 /* CP and shaders */
1973                 if (i == 0) {
1974                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1975                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1976                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1977                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
1978                 } else {
1979                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1980                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1981                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1982                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1983                                 (adev->gmc.private_aperture_start >> 48));
1984                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1985                                 (adev->gmc.shared_aperture_start >> 48));
1986                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1987                 }
1988         }
1989         soc15_grbm_select(adev, 0, 0, 0, 0);
1990
1991         mutex_unlock(&adev->srbm_mutex);
1992
1993         gfx_v9_0_init_compute_vmid(adev);
1994
1995         mutex_lock(&adev->grbm_idx_mutex);
1996         /*
1997          * making sure that the following register writes will be broadcasted
1998          * to all the shaders
1999          */
2000         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2001
2002         WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
2003                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
2004                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2005                    (adev->gfx.config.sc_prim_fifo_size_backend <<
2006                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2007                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
2008                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2009                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2010                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2011         mutex_unlock(&adev->grbm_idx_mutex);
2012
2013 }
2014
2015 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2016 {
2017         u32 i, j, k;
2018         u32 mask;
2019
2020         mutex_lock(&adev->grbm_idx_mutex);
2021         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2022                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2023                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
2024                         for (k = 0; k < adev->usec_timeout; k++) {
2025                                 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2026                                         break;
2027                                 udelay(1);
2028                         }
2029                         if (k == adev->usec_timeout) {
2030                                 gfx_v9_0_select_se_sh(adev, 0xffffffff,
2031                                                       0xffffffff, 0xffffffff);
2032                                 mutex_unlock(&adev->grbm_idx_mutex);
2033                                 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
2034                                          i, j);
2035                                 return;
2036                         }
2037                 }
2038         }
2039         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2040         mutex_unlock(&adev->grbm_idx_mutex);
2041
2042         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2043                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2044                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2045                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2046         for (k = 0; k < adev->usec_timeout; k++) {
2047                 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2048                         break;
2049                 udelay(1);
2050         }
2051 }
2052
2053 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2054                                                bool enable)
2055 {
2056         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
2057
2058         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
2059         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
2060         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
2061         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
2062
2063         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
2064 }
2065
2066 static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
2067 {
2068         /* csib */
2069         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
2070                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
2071         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
2072                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
2073         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
2074                         adev->gfx.rlc.clear_state_size);
2075 }
2076
2077 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format,
2078                                 int indirect_offset,
2079                                 int list_size,
2080                                 int *unique_indirect_regs,
2081                                 int unique_indirect_reg_count,
2082                                 int *indirect_start_offsets,
2083                                 int *indirect_start_offsets_count,
2084                                 int max_start_offsets_count)
2085 {
2086         int idx;
2087
2088         for (; indirect_offset < list_size; indirect_offset++) {
2089                 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count);
2090                 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
2091                 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
2092
2093                 while (register_list_format[indirect_offset] != 0xFFFFFFFF) {
2094                         indirect_offset += 2;
2095
2096                         /* look for the matching indice */
2097                         for (idx = 0; idx < unique_indirect_reg_count; idx++) {
2098                                 if (unique_indirect_regs[idx] ==
2099                                         register_list_format[indirect_offset] ||
2100                                         !unique_indirect_regs[idx])
2101                                         break;
2102                         }
2103
2104                         BUG_ON(idx >= unique_indirect_reg_count);
2105
2106                         if (!unique_indirect_regs[idx])
2107                                 unique_indirect_regs[idx] = register_list_format[indirect_offset];
2108
2109                         indirect_offset++;
2110                 }
2111         }
2112 }
2113
2114 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
2115 {
2116         int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2117         int unique_indirect_reg_count = 0;
2118
2119         int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2120         int indirect_start_offsets_count = 0;
2121
2122         int list_size = 0;
2123         int i = 0, j = 0;
2124         u32 tmp = 0;
2125
2126         u32 *register_list_format =
2127                 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
2128         if (!register_list_format)
2129                 return -ENOMEM;
2130         memcpy(register_list_format, adev->gfx.rlc.register_list_format,
2131                 adev->gfx.rlc.reg_list_format_size_bytes);
2132
2133         /* setup unique_indirect_regs array and indirect_start_offsets array */
2134         unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
2135         gfx_v9_1_parse_ind_reg_list(register_list_format,
2136                                     adev->gfx.rlc.reg_list_format_direct_reg_list_length,
2137                                     adev->gfx.rlc.reg_list_format_size_bytes >> 2,
2138                                     unique_indirect_regs,
2139                                     unique_indirect_reg_count,
2140                                     indirect_start_offsets,
2141                                     &indirect_start_offsets_count,
2142                                     ARRAY_SIZE(indirect_start_offsets));
2143
2144         /* enable auto inc in case it is disabled */
2145         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
2146         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
2147         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
2148
2149         /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
2150         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
2151                 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
2152         for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
2153                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
2154                         adev->gfx.rlc.register_restore[i]);
2155
2156         /* load indirect register */
2157         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2158                 adev->gfx.rlc.reg_list_format_start);
2159
2160         /* direct register portion */
2161         for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
2162                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2163                         register_list_format[i]);
2164
2165         /* indirect register portion */
2166         while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) {
2167                 if (register_list_format[i] == 0xFFFFFFFF) {
2168                         WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2169                         continue;
2170                 }
2171
2172                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2173                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2174
2175                 for (j = 0; j < unique_indirect_reg_count; j++) {
2176                         if (register_list_format[i] == unique_indirect_regs[j]) {
2177                                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);
2178                                 break;
2179                         }
2180                 }
2181
2182                 BUG_ON(j >= unique_indirect_reg_count);
2183
2184                 i++;
2185         }
2186
2187         /* set save/restore list size */
2188         list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
2189         list_size = list_size >> 1;
2190         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2191                 adev->gfx.rlc.reg_restore_list_size);
2192         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
2193
2194         /* write the starting offsets to RLC scratch ram */
2195         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2196                 adev->gfx.rlc.starting_offsets_start);
2197         for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
2198                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2199                        indirect_start_offsets[i]);
2200
2201         /* load unique indirect regs*/
2202         for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
2203                 if (unique_indirect_regs[i] != 0) {
2204                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
2205                                + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i],
2206                                unique_indirect_regs[i] & 0x3FFFF);
2207
2208                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
2209                                + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i],
2210                                unique_indirect_regs[i] >> 20);
2211                 }
2212         }
2213
2214         kfree(register_list_format);
2215         return 0;
2216 }
2217
2218 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
2219 {
2220         WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
2221 }
2222
2223 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
2224                                              bool enable)
2225 {
2226         uint32_t data = 0;
2227         uint32_t default_data = 0;
2228
2229         default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
2230         if (enable == true) {
2231                 /* enable GFXIP control over CGPG */
2232                 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2233                 if(default_data != data)
2234                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2235
2236                 /* update status */
2237                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
2238                 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
2239                 if(default_data != data)
2240                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2241         } else {
2242                 /* restore GFXIP control over GCPG */
2243                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2244                 if(default_data != data)
2245                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2246         }
2247 }
2248
2249 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
2250 {
2251         uint32_t data = 0;
2252
2253         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2254                               AMD_PG_SUPPORT_GFX_SMG |
2255                               AMD_PG_SUPPORT_GFX_DMG)) {
2256                 /* init IDLE_POLL_COUNT = 60 */
2257                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2258                 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
2259                 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2260                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2261
2262                 /* init RLC PG Delay */
2263                 data = 0;
2264                 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
2265                 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
2266                 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
2267                 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
2268                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
2269
2270                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
2271                 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
2272                 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
2273                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
2274
2275                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
2276                 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
2277                 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
2278                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
2279
2280                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
2281                 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2282
2283                 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
2284                 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2285                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
2286
2287                 pwr_10_0_gfxip_control_over_cgpg(adev, true);
2288         }
2289 }
2290
2291 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
2292                                                 bool enable)
2293 {
2294         uint32_t data = 0;
2295         uint32_t default_data = 0;
2296
2297         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2298         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2299                              SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
2300                              enable ? 1 : 0);
2301         if (default_data != data)
2302                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2303 }
2304
2305 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
2306                                                 bool enable)
2307 {
2308         uint32_t data = 0;
2309         uint32_t default_data = 0;
2310
2311         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2312         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2313                              SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
2314                              enable ? 1 : 0);
2315         if(default_data != data)
2316                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2317 }
2318
2319 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
2320                                         bool enable)
2321 {
2322         uint32_t data = 0;
2323         uint32_t default_data = 0;
2324
2325         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2326         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2327                              CP_PG_DISABLE,
2328                              enable ? 0 : 1);
2329         if(default_data != data)
2330                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2331 }
2332
2333 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
2334                                                 bool enable)
2335 {
2336         uint32_t data, default_data;
2337
2338         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2339         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2340                              GFX_POWER_GATING_ENABLE,
2341                              enable ? 1 : 0);
2342         if(default_data != data)
2343                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2344 }
2345
2346 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
2347                                                 bool enable)
2348 {
2349         uint32_t data, default_data;
2350
2351         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2352         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2353                              GFX_PIPELINE_PG_ENABLE,
2354                              enable ? 1 : 0);
2355         if(default_data != data)
2356                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2357
2358         if (!enable)
2359                 /* read any GFX register to wake up GFX */
2360                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
2361 }
2362
2363 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
2364                                                        bool enable)
2365 {
2366         uint32_t data, default_data;
2367
2368         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2369         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2370                              STATIC_PER_CU_PG_ENABLE,
2371                              enable ? 1 : 0);
2372         if(default_data != data)
2373                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2374 }
2375
2376 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
2377                                                 bool enable)
2378 {
2379         uint32_t data, default_data;
2380
2381         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2382         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2383                              DYN_PER_CU_PG_ENABLE,
2384                              enable ? 1 : 0);
2385         if(default_data != data)
2386                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2387 }
2388
2389 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2390 {
2391         gfx_v9_0_init_csb(adev);
2392
2393         /*
2394          * Rlc save restore list is workable since v2_1.
2395          * And it's needed by gfxoff feature.
2396          */
2397         if (adev->gfx.rlc.is_rlc_v2_1) {
2398                 gfx_v9_1_init_rlc_save_restore_list(adev);
2399                 gfx_v9_0_enable_save_restore_machine(adev);
2400         }
2401
2402         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2403                               AMD_PG_SUPPORT_GFX_SMG |
2404                               AMD_PG_SUPPORT_GFX_DMG |
2405                               AMD_PG_SUPPORT_CP |
2406                               AMD_PG_SUPPORT_GDS |
2407                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2408                 WREG32(mmRLC_JUMP_TABLE_RESTORE,
2409                        adev->gfx.rlc.cp_table_gpu_addr >> 8);
2410                 gfx_v9_0_init_gfx_power_gating(adev);
2411         }
2412 }
2413
2414 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2415 {
2416         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
2417         gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2418         gfx_v9_0_wait_for_rlc_serdes(adev);
2419 }
2420
2421 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2422 {
2423         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2424         udelay(50);
2425         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2426         udelay(50);
2427 }
2428
2429 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2430 {
2431 #ifdef AMDGPU_RLC_DEBUG_RETRY
2432         u32 rlc_ucode_ver;
2433 #endif
2434
2435         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
2436
2437         /* carrizo do enable cp interrupt after cp inited */
2438         if (!(adev->flags & AMD_IS_APU))
2439                 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2440
2441         udelay(50);
2442
2443 #ifdef AMDGPU_RLC_DEBUG_RETRY
2444         /* RLC_GPM_GENERAL_6 : RLC Ucode version */
2445         rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
2446         if(rlc_ucode_ver == 0x108) {
2447                 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2448                                 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2449                 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2450                  * default is 0x9C4 to create a 100us interval */
2451                 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
2452                 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
2453                  * to disable the page fault retry interrupts, default is
2454                  * 0x100 (256) */
2455                 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
2456         }
2457 #endif
2458 }
2459
2460 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2461 {
2462         const struct rlc_firmware_header_v2_0 *hdr;
2463         const __le32 *fw_data;
2464         unsigned i, fw_size;
2465
2466         if (!adev->gfx.rlc_fw)
2467                 return -EINVAL;
2468
2469         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2470         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2471
2472         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2473                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2474         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2475
2476         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
2477                         RLCG_UCODE_LOADING_START_ADDRESS);
2478         for (i = 0; i < fw_size; i++)
2479                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2480         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2481
2482         return 0;
2483 }
2484
2485 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2486 {
2487         int r;
2488
2489         if (amdgpu_sriov_vf(adev)) {
2490                 gfx_v9_0_init_csb(adev);
2491                 return 0;
2492         }
2493
2494         gfx_v9_0_rlc_stop(adev);
2495
2496         /* disable CG */
2497         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
2498
2499         gfx_v9_0_rlc_reset(adev);
2500
2501         gfx_v9_0_init_pg(adev);
2502
2503         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2504                 /* legacy rlc firmware loading */
2505                 r = gfx_v9_0_rlc_load_microcode(adev);
2506                 if (r)
2507                         return r;
2508         }
2509
2510         if (adev->asic_type == CHIP_RAVEN ||
2511             adev->asic_type == CHIP_VEGA20) {
2512                 if (amdgpu_lbpw != 0)
2513                         gfx_v9_0_enable_lbpw(adev, true);
2514                 else
2515                         gfx_v9_0_enable_lbpw(adev, false);
2516         }
2517
2518         gfx_v9_0_rlc_start(adev);
2519
2520         return 0;
2521 }
2522
2523 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2524 {
2525         int i;
2526         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2527
2528         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2529         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2530         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2531         if (!enable) {
2532                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2533                         adev->gfx.gfx_ring[i].sched.ready = false;
2534         }
2535         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2536         udelay(50);
2537 }
2538
2539 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2540 {
2541         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2542         const struct gfx_firmware_header_v1_0 *ce_hdr;
2543         const struct gfx_firmware_header_v1_0 *me_hdr;
2544         const __le32 *fw_data;
2545         unsigned i, fw_size;
2546
2547         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2548                 return -EINVAL;
2549
2550         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2551                 adev->gfx.pfp_fw->data;
2552         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2553                 adev->gfx.ce_fw->data;
2554         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2555                 adev->gfx.me_fw->data;
2556
2557         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2558         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2559         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2560
2561         gfx_v9_0_cp_gfx_enable(adev, false);
2562
2563         /* PFP */
2564         fw_data = (const __le32 *)
2565                 (adev->gfx.pfp_fw->data +
2566                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2567         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2568         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
2569         for (i = 0; i < fw_size; i++)
2570                 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2571         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2572
2573         /* CE */
2574         fw_data = (const __le32 *)
2575                 (adev->gfx.ce_fw->data +
2576                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2577         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2578         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
2579         for (i = 0; i < fw_size; i++)
2580                 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2581         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2582
2583         /* ME */
2584         fw_data = (const __le32 *)
2585                 (adev->gfx.me_fw->data +
2586                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2587         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2588         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
2589         for (i = 0; i < fw_size; i++)
2590                 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2591         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2592
2593         return 0;
2594 }
2595
2596 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2597 {
2598         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2599         const struct cs_section_def *sect = NULL;
2600         const struct cs_extent_def *ext = NULL;
2601         int r, i, tmp;
2602
2603         /* init the CP */
2604         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2605         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2606
2607         gfx_v9_0_cp_gfx_enable(adev, true);
2608
2609         r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
2610         if (r) {
2611                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2612                 return r;
2613         }
2614
2615         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2616         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2617
2618         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2619         amdgpu_ring_write(ring, 0x80000000);
2620         amdgpu_ring_write(ring, 0x80000000);
2621
2622         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2623                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2624                         if (sect->id == SECT_CONTEXT) {
2625                                 amdgpu_ring_write(ring,
2626                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2627                                                ext->reg_count));
2628                                 amdgpu_ring_write(ring,
2629                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2630                                 for (i = 0; i < ext->reg_count; i++)
2631                                         amdgpu_ring_write(ring, ext->extent[i]);
2632                         }
2633                 }
2634         }
2635
2636         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2637         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2638
2639         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2640         amdgpu_ring_write(ring, 0);
2641
2642         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2643         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2644         amdgpu_ring_write(ring, 0x8000);
2645         amdgpu_ring_write(ring, 0x8000);
2646
2647         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2648         tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2649                 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2650         amdgpu_ring_write(ring, tmp);
2651         amdgpu_ring_write(ring, 0);
2652
2653         amdgpu_ring_commit(ring);
2654
2655         return 0;
2656 }
2657
2658 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2659 {
2660         struct amdgpu_ring *ring;
2661         u32 tmp;
2662         u32 rb_bufsz;
2663         u64 rb_addr, rptr_addr, wptr_gpu_addr;
2664
2665         /* Set the write pointer delay */
2666         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2667
2668         /* set the RB to use vmid 0 */
2669         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2670
2671         /* Set ring buffer size */
2672         ring = &adev->gfx.gfx_ring[0];
2673         rb_bufsz = order_base_2(ring->ring_size / 8);
2674         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2675         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2676 #ifdef __BIG_ENDIAN
2677         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2678 #endif
2679         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2680
2681         /* Initialize the ring buffer's write pointers */
2682         ring->wptr = 0;
2683         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2684         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2685
2686         /* set the wb address wether it's enabled or not */
2687         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2688         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2689         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2690
2691         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2692         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2693         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
2694
2695         mdelay(1);
2696         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2697
2698         rb_addr = ring->gpu_addr >> 8;
2699         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2700         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2701
2702         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2703         if (ring->use_doorbell) {
2704                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2705                                     DOORBELL_OFFSET, ring->doorbell_index);
2706                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2707                                     DOORBELL_EN, 1);
2708         } else {
2709                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2710         }
2711         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2712
2713         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2714                         DOORBELL_RANGE_LOWER, ring->doorbell_index);
2715         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2716
2717         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2718                        CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2719
2720
2721         /* start the ring */
2722         gfx_v9_0_cp_gfx_start(adev);
2723         ring->sched.ready = true;
2724
2725         return 0;
2726 }
2727
2728 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2729 {
2730         int i;
2731
2732         if (enable) {
2733                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2734         } else {
2735                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2736                         (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2737                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2738                         adev->gfx.compute_ring[i].sched.ready = false;
2739                 adev->gfx.kiq.ring.sched.ready = false;
2740         }
2741         udelay(50);
2742 }
2743
2744 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2745 {
2746         const struct gfx_firmware_header_v1_0 *mec_hdr;
2747         const __le32 *fw_data;
2748         unsigned i;
2749         u32 tmp;
2750
2751         if (!adev->gfx.mec_fw)
2752                 return -EINVAL;
2753
2754         gfx_v9_0_cp_compute_enable(adev, false);
2755
2756         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2757         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2758
2759         fw_data = (const __le32 *)
2760                 (adev->gfx.mec_fw->data +
2761                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2762         tmp = 0;
2763         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2764         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2765         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2766
2767         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2768                 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
2769         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2770                 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2771
2772         /* MEC1 */
2773         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2774                          mec_hdr->jt_offset);
2775         for (i = 0; i < mec_hdr->jt_size; i++)
2776                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2777                         le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2778
2779         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2780                         adev->gfx.mec_fw_version);
2781         /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2782
2783         return 0;
2784 }
2785
2786 /* KIQ functions */
2787 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2788 {
2789         uint32_t tmp;
2790         struct amdgpu_device *adev = ring->adev;
2791
2792         /* tell RLC which is KIQ queue */
2793         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2794         tmp &= 0xffffff00;
2795         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2796         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2797         tmp |= 0x80;
2798         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2799 }
2800
2801 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
2802 {
2803         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2804         uint64_t queue_mask = 0;
2805         int r, i;
2806
2807         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2808                 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2809                         continue;
2810
2811                 /* This situation may be hit in the future if a new HW
2812                  * generation exposes more than 64 queues. If so, the
2813                  * definition of queue_mask needs updating */
2814                 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
2815                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2816                         break;
2817                 }
2818
2819                 queue_mask |= (1ull << i);
2820         }
2821
2822         r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 8);
2823         if (r) {
2824                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2825                 return r;
2826         }
2827
2828         /* set resources */
2829         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2830         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2831                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
2832         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2833         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
2834         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2835         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2836         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2837         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
2838         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2839                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2840                 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2841                 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2842
2843                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2844                 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2845                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2846                                   PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2847                                   PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2848                                   PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2849                                   PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2850                                   PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2851                                   PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2852                                   PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
2853                                   PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2854                                   PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2855                 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2856                 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2857                 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2858                 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2859                 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2860         }
2861
2862         r = amdgpu_ring_test_helper(kiq_ring);
2863         if (r)
2864                 DRM_ERROR("KCQ enable failed\n");
2865
2866         return r;
2867 }
2868
2869 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
2870 {
2871         struct amdgpu_device *adev = ring->adev;
2872         struct v9_mqd *mqd = ring->mqd_ptr;
2873         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2874         uint32_t tmp;
2875
2876         mqd->header = 0xC0310800;
2877         mqd->compute_pipelinestat_enable = 0x00000001;
2878         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2879         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2880         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2881         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2882         mqd->compute_misc_reserved = 0x00000003;
2883
2884         mqd->dynamic_cu_mask_addr_lo =
2885                 lower_32_bits(ring->mqd_gpu_addr
2886                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2887         mqd->dynamic_cu_mask_addr_hi =
2888                 upper_32_bits(ring->mqd_gpu_addr
2889                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2890
2891         eop_base_addr = ring->eop_gpu_addr >> 8;
2892         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2893         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2894
2895         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2896         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
2897         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2898                         (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
2899
2900         mqd->cp_hqd_eop_control = tmp;
2901
2902         /* enable doorbell? */
2903         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2904
2905         if (ring->use_doorbell) {
2906                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2907                                     DOORBELL_OFFSET, ring->doorbell_index);
2908                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2909                                     DOORBELL_EN, 1);
2910                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2911                                     DOORBELL_SOURCE, 0);
2912                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2913                                     DOORBELL_HIT, 0);
2914         } else {
2915                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2916                                          DOORBELL_EN, 0);
2917         }
2918
2919         mqd->cp_hqd_pq_doorbell_control = tmp;
2920
2921         /* disable the queue if it's active */
2922         ring->wptr = 0;
2923         mqd->cp_hqd_dequeue_request = 0;
2924         mqd->cp_hqd_pq_rptr = 0;
2925         mqd->cp_hqd_pq_wptr_lo = 0;
2926         mqd->cp_hqd_pq_wptr_hi = 0;
2927
2928         /* set the pointer to the MQD */
2929         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2930         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2931
2932         /* set MQD vmid to 0 */
2933         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
2934         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2935         mqd->cp_mqd_control = tmp;
2936
2937         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2938         hqd_gpu_addr = ring->gpu_addr >> 8;
2939         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2940         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2941
2942         /* set up the HQD, this is similar to CP_RB0_CNTL */
2943         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
2944         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2945                             (order_base_2(ring->ring_size / 4) - 1));
2946         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2947                         ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2948 #ifdef __BIG_ENDIAN
2949         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2950 #endif
2951         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2952         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2953         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2954         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2955         mqd->cp_hqd_pq_control = tmp;
2956
2957         /* set the wb address whether it's enabled or not */
2958         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2959         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2960         mqd->cp_hqd_pq_rptr_report_addr_hi =
2961                 upper_32_bits(wb_gpu_addr) & 0xffff;
2962
2963         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2964         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2965         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2966         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2967
2968         tmp = 0;
2969         /* enable the doorbell if requested */
2970         if (ring->use_doorbell) {
2971                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2972                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2973                                 DOORBELL_OFFSET, ring->doorbell_index);
2974
2975                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2976                                          DOORBELL_EN, 1);
2977                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2978                                          DOORBELL_SOURCE, 0);
2979                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2980                                          DOORBELL_HIT, 0);
2981         }
2982
2983         mqd->cp_hqd_pq_doorbell_control = tmp;
2984
2985         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2986         ring->wptr = 0;
2987         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
2988
2989         /* set the vmid for the queue */
2990         mqd->cp_hqd_vmid = 0;
2991
2992         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
2993         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2994         mqd->cp_hqd_persistent_state = tmp;
2995
2996         /* set MIN_IB_AVAIL_SIZE */
2997         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2998         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2999         mqd->cp_hqd_ib_control = tmp;
3000
3001         /* activate the queue */
3002         mqd->cp_hqd_active = 1;
3003
3004         return 0;
3005 }
3006
3007 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
3008 {
3009         struct amdgpu_device *adev = ring->adev;
3010         struct v9_mqd *mqd = ring->mqd_ptr;
3011         int j;
3012
3013         /* disable wptr polling */
3014         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3015
3016         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
3017                mqd->cp_hqd_eop_base_addr_lo);
3018         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
3019                mqd->cp_hqd_eop_base_addr_hi);
3020
3021         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3022         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
3023                mqd->cp_hqd_eop_control);
3024
3025         /* enable doorbell? */
3026         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3027                mqd->cp_hqd_pq_doorbell_control);
3028
3029         /* disable the queue if it's active */
3030         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3031                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3032                 for (j = 0; j < adev->usec_timeout; j++) {
3033                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3034                                 break;
3035                         udelay(1);
3036                 }
3037                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3038                        mqd->cp_hqd_dequeue_request);
3039                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
3040                        mqd->cp_hqd_pq_rptr);
3041                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3042                        mqd->cp_hqd_pq_wptr_lo);
3043                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3044                        mqd->cp_hqd_pq_wptr_hi);
3045         }
3046
3047         /* set the pointer to the MQD */
3048         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
3049                mqd->cp_mqd_base_addr_lo);
3050         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
3051                mqd->cp_mqd_base_addr_hi);
3052
3053         /* set MQD vmid to 0 */
3054         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
3055                mqd->cp_mqd_control);
3056
3057         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3058         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
3059                mqd->cp_hqd_pq_base_lo);
3060         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
3061                mqd->cp_hqd_pq_base_hi);
3062
3063         /* set up the HQD, this is similar to CP_RB0_CNTL */
3064         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
3065                mqd->cp_hqd_pq_control);
3066
3067         /* set the wb address whether it's enabled or not */
3068         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3069                                 mqd->cp_hqd_pq_rptr_report_addr_lo);
3070         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3071                                 mqd->cp_hqd_pq_rptr_report_addr_hi);
3072
3073         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3074         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
3075                mqd->cp_hqd_pq_wptr_poll_addr_lo);
3076         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3077                mqd->cp_hqd_pq_wptr_poll_addr_hi);
3078
3079         /* enable the doorbell if requested */
3080         if (ring->use_doorbell) {
3081                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
3082                                         (AMDGPU_DOORBELL64_KIQ *2) << 2);
3083                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3084                                         (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
3085         }
3086
3087         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3088                mqd->cp_hqd_pq_doorbell_control);
3089
3090         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3091         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3092                mqd->cp_hqd_pq_wptr_lo);
3093         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3094                mqd->cp_hqd_pq_wptr_hi);
3095
3096         /* set the vmid for the queue */
3097         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3098
3099         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
3100                mqd->cp_hqd_persistent_state);
3101
3102         /* activate the queue */
3103         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
3104                mqd->cp_hqd_active);
3105
3106         if (ring->use_doorbell)
3107                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3108
3109         return 0;
3110 }
3111
3112 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring)
3113 {
3114         struct amdgpu_device *adev = ring->adev;
3115         int j;
3116
3117         /* disable the queue if it's active */
3118         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3119
3120                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3121
3122                 for (j = 0; j < adev->usec_timeout; j++) {
3123                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3124                                 break;
3125                         udelay(1);
3126                 }
3127
3128                 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
3129                         DRM_DEBUG("KIQ dequeue request failed.\n");
3130
3131                         /* Manual disable if dequeue request times out */
3132                         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
3133                 }
3134
3135                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3136                       0);
3137         }
3138
3139         WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0);
3140         WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0);
3141         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
3142         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
3143         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
3144         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0);
3145         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
3146         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
3147
3148         return 0;
3149 }
3150
3151 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
3152 {
3153         struct amdgpu_device *adev = ring->adev;
3154         struct v9_mqd *mqd = ring->mqd_ptr;
3155         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3156
3157         gfx_v9_0_kiq_setting(ring);
3158
3159         if (adev->in_gpu_reset) { /* for GPU_RESET case */
3160                 /* reset MQD to a clean status */
3161                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3162                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3163
3164                 /* reset ring buffer */
3165                 ring->wptr = 0;
3166                 amdgpu_ring_clear_ring(ring);
3167
3168                 mutex_lock(&adev->srbm_mutex);
3169                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3170                 gfx_v9_0_kiq_init_register(ring);
3171                 soc15_grbm_select(adev, 0, 0, 0, 0);
3172                 mutex_unlock(&adev->srbm_mutex);
3173         } else {
3174                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3175                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3176                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3177                 mutex_lock(&adev->srbm_mutex);
3178                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3179                 gfx_v9_0_mqd_init(ring);
3180                 gfx_v9_0_kiq_init_register(ring);
3181                 soc15_grbm_select(adev, 0, 0, 0, 0);
3182                 mutex_unlock(&adev->srbm_mutex);
3183
3184                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3185                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3186         }
3187
3188         return 0;
3189 }
3190
3191 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
3192 {
3193         struct amdgpu_device *adev = ring->adev;
3194         struct v9_mqd *mqd = ring->mqd_ptr;
3195         int mqd_idx = ring - &adev->gfx.compute_ring[0];
3196
3197         if (!adev->in_gpu_reset && !adev->in_suspend) {
3198                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3199                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3200                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3201                 mutex_lock(&adev->srbm_mutex);
3202                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3203                 gfx_v9_0_mqd_init(ring);
3204                 soc15_grbm_select(adev, 0, 0, 0, 0);
3205                 mutex_unlock(&adev->srbm_mutex);
3206
3207                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3208                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3209         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
3210                 /* reset MQD to a clean status */
3211                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3212                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3213
3214                 /* reset ring buffer */
3215                 ring->wptr = 0;
3216                 amdgpu_ring_clear_ring(ring);
3217         } else {
3218                 amdgpu_ring_clear_ring(ring);
3219         }
3220
3221         return 0;
3222 }
3223
3224 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3225 {
3226         struct amdgpu_ring *ring;
3227         int r;
3228
3229         ring = &adev->gfx.kiq.ring;
3230
3231         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3232         if (unlikely(r != 0))
3233                 return r;
3234
3235         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3236         if (unlikely(r != 0))
3237                 return r;
3238
3239         gfx_v9_0_kiq_init_queue(ring);
3240         amdgpu_bo_kunmap(ring->mqd_obj);
3241         ring->mqd_ptr = NULL;
3242         amdgpu_bo_unreserve(ring->mqd_obj);
3243         ring->sched.ready = true;
3244         return 0;
3245 }
3246
3247 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)
3248 {
3249         struct amdgpu_ring *ring = NULL;
3250         int r = 0, i;
3251
3252         gfx_v9_0_cp_compute_enable(adev, true);
3253
3254         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3255                 ring = &adev->gfx.compute_ring[i];
3256
3257                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3258                 if (unlikely(r != 0))
3259                         goto done;
3260                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3261                 if (!r) {
3262                         r = gfx_v9_0_kcq_init_queue(ring);
3263                         amdgpu_bo_kunmap(ring->mqd_obj);
3264                         ring->mqd_ptr = NULL;
3265                 }
3266                 amdgpu_bo_unreserve(ring->mqd_obj);
3267                 if (r)
3268                         goto done;
3269         }
3270
3271         r = gfx_v9_0_kiq_kcq_enable(adev);
3272 done:
3273         return r;
3274 }
3275
3276 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
3277 {
3278         int r, i;
3279         struct amdgpu_ring *ring;
3280
3281         if (!(adev->flags & AMD_IS_APU))
3282                 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
3283
3284         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3285                 /* legacy firmware loading */
3286                 r = gfx_v9_0_cp_gfx_load_microcode(adev);
3287                 if (r)
3288                         return r;
3289
3290                 r = gfx_v9_0_cp_compute_load_microcode(adev);
3291                 if (r)
3292                         return r;
3293         }
3294
3295         r = gfx_v9_0_kiq_resume(adev);
3296         if (r)
3297                 return r;
3298
3299         r = gfx_v9_0_cp_gfx_resume(adev);
3300         if (r)
3301                 return r;
3302
3303         r = gfx_v9_0_kcq_resume(adev);
3304         if (r)
3305                 return r;
3306
3307         ring = &adev->gfx.gfx_ring[0];
3308         r = amdgpu_ring_test_helper(ring);
3309         if (r)
3310                 return r;
3311
3312         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3313                 ring = &adev->gfx.compute_ring[i];
3314                 amdgpu_ring_test_helper(ring);
3315         }
3316
3317         gfx_v9_0_enable_gui_idle_interrupt(adev, true);
3318
3319         return 0;
3320 }
3321
3322 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
3323 {
3324         gfx_v9_0_cp_gfx_enable(adev, enable);
3325         gfx_v9_0_cp_compute_enable(adev, enable);
3326 }
3327
3328 static int gfx_v9_0_hw_init(void *handle)
3329 {
3330         int r;
3331         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3332
3333         gfx_v9_0_init_golden_registers(adev);
3334
3335         gfx_v9_0_constants_init(adev);
3336
3337         r = gfx_v9_0_csb_vram_pin(adev);
3338         if (r)
3339                 return r;
3340
3341         r = gfx_v9_0_rlc_resume(adev);
3342         if (r)
3343                 return r;
3344
3345         r = gfx_v9_0_cp_resume(adev);
3346         if (r)
3347                 return r;
3348
3349         r = gfx_v9_0_ngg_en(adev);
3350         if (r)
3351                 return r;
3352
3353         return r;
3354 }
3355
3356 static int gfx_v9_0_kcq_disable(struct amdgpu_device *adev)
3357 {
3358         int r, i;
3359         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
3360
3361         r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings);
3362         if (r)
3363                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3364
3365         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3366                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3367
3368                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3369                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3370                                                 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
3371                                                 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3372                                                 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
3373                                                 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3374                 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3375                 amdgpu_ring_write(kiq_ring, 0);
3376                 amdgpu_ring_write(kiq_ring, 0);
3377                 amdgpu_ring_write(kiq_ring, 0);
3378         }
3379         r = amdgpu_ring_test_helper(kiq_ring);
3380         if (r)
3381                 DRM_ERROR("KCQ disable failed\n");
3382
3383         return r;
3384 }
3385
3386 static int gfx_v9_0_hw_fini(void *handle)
3387 {
3388         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3389
3390         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3391         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3392
3393         /* disable KCQ to avoid CPC touch memory not valid anymore */
3394         gfx_v9_0_kcq_disable(adev);
3395
3396         if (amdgpu_sriov_vf(adev)) {
3397                 gfx_v9_0_cp_gfx_enable(adev, false);
3398                 /* must disable polling for SRIOV when hw finished, otherwise
3399                  * CPC engine may still keep fetching WB address which is already
3400                  * invalid after sw finished and trigger DMAR reading error in
3401                  * hypervisor side.
3402                  */
3403                 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3404                 return 0;
3405         }
3406
3407         /* Use deinitialize sequence from CAIL when unbinding device from driver,
3408          * otherwise KIQ is hanging when binding back
3409          */
3410         if (!adev->in_gpu_reset && !adev->in_suspend) {
3411                 mutex_lock(&adev->srbm_mutex);
3412                 soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
3413                                 adev->gfx.kiq.ring.pipe,
3414                                 adev->gfx.kiq.ring.queue, 0);
3415                 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
3416                 soc15_grbm_select(adev, 0, 0, 0, 0);
3417                 mutex_unlock(&adev->srbm_mutex);
3418         }
3419
3420         gfx_v9_0_cp_enable(adev, false);
3421         gfx_v9_0_rlc_stop(adev);
3422
3423         gfx_v9_0_csb_vram_unpin(adev);
3424
3425         return 0;
3426 }
3427
3428 static int gfx_v9_0_suspend(void *handle)
3429 {
3430         return gfx_v9_0_hw_fini(handle);
3431 }
3432
3433 static int gfx_v9_0_resume(void *handle)
3434 {
3435         return gfx_v9_0_hw_init(handle);
3436 }
3437
3438 static bool gfx_v9_0_is_idle(void *handle)
3439 {
3440         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3441
3442         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3443                                 GRBM_STATUS, GUI_ACTIVE))
3444                 return false;
3445         else
3446                 return true;
3447 }
3448
3449 static int gfx_v9_0_wait_for_idle(void *handle)
3450 {
3451         unsigned i;
3452         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3453
3454         for (i = 0; i < adev->usec_timeout; i++) {
3455                 if (gfx_v9_0_is_idle(handle))
3456                         return 0;
3457                 udelay(1);
3458         }
3459         return -ETIMEDOUT;
3460 }
3461
3462 static int gfx_v9_0_soft_reset(void *handle)
3463 {
3464         u32 grbm_soft_reset = 0;
3465         u32 tmp;
3466         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3467
3468         /* GRBM_STATUS */
3469         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3470         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3471                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3472                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3473                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3474                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3475                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3476                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3477                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3478                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3479                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3480         }
3481
3482         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3483                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3484                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3485         }
3486
3487         /* GRBM_STATUS2 */
3488         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3489         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3490                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3491                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3492
3493
3494         if (grbm_soft_reset) {
3495                 /* stop the rlc */
3496                 gfx_v9_0_rlc_stop(adev);
3497
3498                 /* Disable GFX parsing/prefetching */
3499                 gfx_v9_0_cp_gfx_enable(adev, false);
3500
3501                 /* Disable MEC parsing/prefetching */
3502                 gfx_v9_0_cp_compute_enable(adev, false);
3503
3504                 if (grbm_soft_reset) {
3505                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3506                         tmp |= grbm_soft_reset;
3507                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3508                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3509                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3510
3511                         udelay(50);
3512
3513                         tmp &= ~grbm_soft_reset;
3514                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3515                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3516                 }
3517
3518                 /* Wait a little for things to settle down */
3519                 udelay(50);
3520         }
3521         return 0;
3522 }
3523
3524 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3525 {
3526         uint64_t clock;
3527
3528         mutex_lock(&adev->gfx.gpu_clock_mutex);
3529         WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3530         clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3531                 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3532         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3533         return clock;
3534 }
3535
3536 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3537                                           uint32_t vmid,
3538                                           uint32_t gds_base, uint32_t gds_size,
3539                                           uint32_t gws_base, uint32_t gws_size,
3540                                           uint32_t oa_base, uint32_t oa_size)
3541 {
3542         struct amdgpu_device *adev = ring->adev;
3543
3544         /* GDS Base */
3545         gfx_v9_0_write_data_to_reg(ring, 0, false,
3546                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3547                                    gds_base);
3548
3549         /* GDS Size */
3550         gfx_v9_0_write_data_to_reg(ring, 0, false,
3551                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3552                                    gds_size);
3553
3554         /* GWS */
3555         gfx_v9_0_write_data_to_reg(ring, 0, false,
3556                                    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3557                                    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3558
3559         /* OA */
3560         gfx_v9_0_write_data_to_reg(ring, 0, false,
3561                                    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3562                                    (1 << (oa_size + oa_base)) - (1 << oa_base));
3563 }
3564
3565 static int gfx_v9_0_early_init(void *handle)
3566 {
3567         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3568
3569         adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
3570         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3571         gfx_v9_0_set_ring_funcs(adev);
3572         gfx_v9_0_set_irq_funcs(adev);
3573         gfx_v9_0_set_gds_init(adev);
3574         gfx_v9_0_set_rlc_funcs(adev);
3575
3576         return 0;
3577 }
3578
3579 static int gfx_v9_0_late_init(void *handle)
3580 {
3581         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3582         int r;
3583
3584         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3585         if (r)
3586                 return r;
3587
3588         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3589         if (r)
3590                 return r;
3591
3592         return 0;
3593 }
3594
3595 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3596 {
3597         uint32_t rlc_setting, data;
3598         unsigned i;
3599
3600         if (adev->gfx.rlc.in_safe_mode)
3601                 return;
3602
3603         /* if RLC is not enabled, do nothing */
3604         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3605         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3606                 return;
3607
3608         if (adev->cg_flags &
3609             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3610              AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3611                 data = RLC_SAFE_MODE__CMD_MASK;
3612                 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3613                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3614
3615                 /* wait for RLC_SAFE_MODE */
3616                 for (i = 0; i < adev->usec_timeout; i++) {
3617                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3618                                 break;
3619                         udelay(1);
3620                 }
3621                 adev->gfx.rlc.in_safe_mode = true;
3622         }
3623 }
3624
3625 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3626 {
3627         uint32_t rlc_setting, data;
3628
3629         if (!adev->gfx.rlc.in_safe_mode)
3630                 return;
3631
3632         /* if RLC is not enabled, do nothing */
3633         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3634         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3635                 return;
3636
3637         if (adev->cg_flags &
3638             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3639                 /*
3640                  * Try to exit safe mode only if it is already in safe
3641                  * mode.
3642                  */
3643                 data = RLC_SAFE_MODE__CMD_MASK;
3644                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3645                 adev->gfx.rlc.in_safe_mode = false;
3646         }
3647 }
3648
3649 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3650                                                 bool enable)
3651 {
3652         gfx_v9_0_enter_rlc_safe_mode(adev);
3653
3654         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3655                 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3656                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3657                         gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3658         } else {
3659                 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3660                 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3661         }
3662
3663         gfx_v9_0_exit_rlc_safe_mode(adev);
3664 }
3665
3666 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3667                                                 bool enable)
3668 {
3669         /* TODO: double check if we need to perform under safe mode */
3670         /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3671
3672         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3673                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3674         else
3675                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3676
3677         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3678                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3679         else
3680                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3681
3682         /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3683 }
3684
3685 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3686                                                       bool enable)
3687 {
3688         uint32_t data, def;
3689
3690         /* It is disabled by HW by default */
3691         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3692                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
3693                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3694
3695                 if (adev->asic_type != CHIP_VEGA12)
3696                         data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
3697
3698                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3699                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3700                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3701
3702                 /* only for Vega10 & Raven1 */
3703                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3704
3705                 if (def != data)
3706                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3707
3708                 /* MGLS is a global flag to control all MGLS in GFX */
3709                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3710                         /* 2 - RLC memory Light sleep */
3711                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
3712                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3713                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3714                                 if (def != data)
3715                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3716                         }
3717                         /* 3 - CP memory Light sleep */
3718                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3719                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3720                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3721                                 if (def != data)
3722                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3723                         }
3724                 }
3725         } else {
3726                 /* 1 - MGCG_OVERRIDE */
3727                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3728
3729                 if (adev->asic_type != CHIP_VEGA12)
3730                         data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
3731
3732                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3733                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3734                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3735                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3736
3737                 if (def != data)
3738                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3739
3740                 /* 2 - disable MGLS in RLC */
3741                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3742                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3743                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3744                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3745                 }
3746
3747                 /* 3 - disable MGLS in CP */
3748                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3749                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3750                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3751                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3752                 }
3753         }
3754 }
3755
3756 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3757                                            bool enable)
3758 {
3759         uint32_t data, def;
3760
3761         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3762
3763         /* Enable 3D CGCG/CGLS */
3764         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3765                 /* write cmd to clear cgcg/cgls ov */
3766                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3767                 /* unset CGCG override */
3768                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3769                 /* update CGCG and CGLS override bits */
3770                 if (def != data)
3771                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3772
3773                 /* enable 3Dcgcg FSM(0x0000363f) */
3774                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3775
3776                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3777                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3778                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3779                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3780                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3781                 if (def != data)
3782                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3783
3784                 /* set IDLE_POLL_COUNT(0x00900100) */
3785                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3786                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3787                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3788                 if (def != data)
3789                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3790         } else {
3791                 /* Disable CGCG/CGLS */
3792                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3793                 /* disable cgcg, cgls should be disabled */
3794                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3795                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3796                 /* disable cgcg and cgls in FSM */
3797                 if (def != data)
3798                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3799         }
3800
3801         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3802 }
3803
3804 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3805                                                       bool enable)
3806 {
3807         uint32_t def, data;
3808
3809         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3810
3811         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3812                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3813                 /* unset CGCG override */
3814                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3815                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3816                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3817                 else
3818                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3819                 /* update CGCG and CGLS override bits */
3820                 if (def != data)
3821                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3822
3823                 /* enable cgcg FSM(0x0000363F) */
3824                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3825
3826                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3827                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3828                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3829                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3830                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3831                 if (def != data)
3832                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3833
3834                 /* set IDLE_POLL_COUNT(0x00900100) */
3835                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3836                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3837                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3838                 if (def != data)
3839                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3840         } else {
3841                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3842                 /* reset CGCG/CGLS bits */
3843                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3844                 /* disable cgcg and cgls in FSM */
3845                 if (def != data)
3846                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3847         }
3848
3849         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3850 }
3851
3852 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3853                                             bool enable)
3854 {
3855         if (enable) {
3856                 /* CGCG/CGLS should be enabled after MGCG/MGLS
3857                  * ===  MGCG + MGLS ===
3858                  */
3859                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3860                 /* ===  CGCG /CGLS for GFX 3D Only === */
3861                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3862                 /* ===  CGCG + CGLS === */
3863                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3864         } else {
3865                 /* CGCG/CGLS should be disabled before MGCG/MGLS
3866                  * ===  CGCG + CGLS ===
3867                  */
3868                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3869                 /* ===  CGCG /CGLS for GFX 3D Only === */
3870                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3871                 /* ===  MGCG + MGLS === */
3872                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3873         }
3874         return 0;
3875 }
3876
3877 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3878         .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3879         .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3880 };
3881
3882 static int gfx_v9_0_set_powergating_state(void *handle,
3883                                           enum amd_powergating_state state)
3884 {
3885         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3886         bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
3887
3888         switch (adev->asic_type) {
3889         case CHIP_RAVEN:
3890                 if (!enable) {
3891                         amdgpu_gfx_off_ctrl(adev, false);
3892                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
3893                 }
3894                 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3895                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3896                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3897                 } else {
3898                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3899                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3900                 }
3901
3902                 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3903                         gfx_v9_0_enable_cp_power_gating(adev, true);
3904                 else
3905                         gfx_v9_0_enable_cp_power_gating(adev, false);
3906
3907                 /* update gfx cgpg state */
3908                 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
3909
3910                 /* update mgcg state */
3911                 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
3912
3913                 if (enable)
3914                         amdgpu_gfx_off_ctrl(adev, true);
3915                 break;
3916         case CHIP_VEGA12:
3917                 if (!enable) {
3918                         amdgpu_gfx_off_ctrl(adev, false);
3919                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
3920                 } else {
3921                         amdgpu_gfx_off_ctrl(adev, true);
3922                 }
3923                 break;
3924         default:
3925                 break;
3926         }
3927
3928         return 0;
3929 }
3930
3931 static int gfx_v9_0_set_clockgating_state(void *handle,
3932                                           enum amd_clockgating_state state)
3933 {
3934         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3935
3936         if (amdgpu_sriov_vf(adev))
3937                 return 0;
3938
3939         switch (adev->asic_type) {
3940         case CHIP_VEGA10:
3941         case CHIP_VEGA12:
3942         case CHIP_VEGA20:
3943         case CHIP_RAVEN:
3944                 gfx_v9_0_update_gfx_clock_gating(adev,
3945                                                  state == AMD_CG_STATE_GATE ? true : false);
3946                 break;
3947         default:
3948                 break;
3949         }
3950         return 0;
3951 }
3952
3953 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3954 {
3955         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3956         int data;
3957
3958         if (amdgpu_sriov_vf(adev))
3959                 *flags = 0;
3960
3961         /* AMD_CG_SUPPORT_GFX_MGCG */
3962         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3963         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3964                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3965
3966         /* AMD_CG_SUPPORT_GFX_CGCG */
3967         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3968         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3969                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3970
3971         /* AMD_CG_SUPPORT_GFX_CGLS */
3972         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3973                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3974
3975         /* AMD_CG_SUPPORT_GFX_RLC_LS */
3976         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3977         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3978                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3979
3980         /* AMD_CG_SUPPORT_GFX_CP_LS */
3981         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3982         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3983                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3984
3985         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
3986         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3987         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3988                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3989
3990         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3991         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3992                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3993 }
3994
3995 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3996 {
3997         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3998 }
3999
4000 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4001 {
4002         struct amdgpu_device *adev = ring->adev;
4003         u64 wptr;
4004
4005         /* XXX check if swapping is necessary on BE */
4006         if (ring->use_doorbell) {
4007                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
4008         } else {
4009                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
4010                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
4011         }
4012
4013         return wptr;
4014 }
4015
4016 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4017 {
4018         struct amdgpu_device *adev = ring->adev;
4019
4020         if (ring->use_doorbell) {
4021                 /* XXX check if swapping is necessary on BE */
4022                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4023                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4024         } else {
4025                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4026                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
4027         }
4028 }
4029
4030 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4031 {
4032         struct amdgpu_device *adev = ring->adev;
4033         u32 ref_and_mask, reg_mem_engine;
4034         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
4035
4036         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4037                 switch (ring->me) {
4038                 case 1:
4039                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4040                         break;
4041                 case 2:
4042                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4043                         break;
4044                 default:
4045                         return;
4046                 }
4047                 reg_mem_engine = 0;
4048         } else {
4049                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4050                 reg_mem_engine = 1; /* pfp */
4051         }
4052
4053         gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
4054                               adev->nbio_funcs->get_hdp_flush_req_offset(adev),
4055                               adev->nbio_funcs->get_hdp_flush_done_offset(adev),
4056                               ref_and_mask, ref_and_mask, 0x20);
4057 }
4058
4059 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4060                                       struct amdgpu_ib *ib,
4061                                       unsigned vmid, bool ctx_switch)
4062 {
4063         u32 header, control = 0;
4064
4065         if (ib->flags & AMDGPU_IB_FLAG_CE)
4066                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
4067         else
4068                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4069
4070         control |= ib->length_dw | (vmid << 24);
4071
4072         if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
4073                 control |= INDIRECT_BUFFER_PRE_ENB(1);
4074
4075                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
4076                         gfx_v9_0_ring_emit_de_meta(ring);
4077         }
4078
4079         amdgpu_ring_write(ring, header);
4080         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4081         amdgpu_ring_write(ring,
4082 #ifdef __BIG_ENDIAN
4083                 (2 << 0) |
4084 #endif
4085                 lower_32_bits(ib->gpu_addr));
4086         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4087         amdgpu_ring_write(ring, control);
4088 }
4089
4090 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4091                                           struct amdgpu_ib *ib,
4092                                           unsigned vmid, bool ctx_switch)
4093 {
4094         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4095
4096         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4097         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4098         amdgpu_ring_write(ring,
4099 #ifdef __BIG_ENDIAN
4100                                 (2 << 0) |
4101 #endif
4102                                 lower_32_bits(ib->gpu_addr));
4103         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4104         amdgpu_ring_write(ring, control);
4105 }
4106
4107 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4108                                      u64 seq, unsigned flags)
4109 {
4110         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4111         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4112         bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
4113
4114         /* RELEASE_MEM - flush caches, send int */
4115         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4116         amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
4117                                                EOP_TC_NC_ACTION_EN) :
4118                                               (EOP_TCL1_ACTION_EN |
4119                                                EOP_TC_ACTION_EN |
4120                                                EOP_TC_WB_ACTION_EN |
4121                                                EOP_TC_MD_ACTION_EN)) |
4122                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4123                                  EVENT_INDEX(5)));
4124         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4125
4126         /*
4127          * the address should be Qword aligned if 64bit write, Dword
4128          * aligned if only send 32bit data low (discard data high)
4129          */
4130         if (write64bit)
4131                 BUG_ON(addr & 0x7);
4132         else
4133                 BUG_ON(addr & 0x3);
4134         amdgpu_ring_write(ring, lower_32_bits(addr));
4135         amdgpu_ring_write(ring, upper_32_bits(addr));
4136         amdgpu_ring_write(ring, lower_32_bits(seq));
4137         amdgpu_ring_write(ring, upper_32_bits(seq));
4138         amdgpu_ring_write(ring, 0);
4139 }
4140
4141 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4142 {
4143         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4144         uint32_t seq = ring->fence_drv.sync_seq;
4145         uint64_t addr = ring->fence_drv.gpu_addr;
4146
4147         gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
4148                               lower_32_bits(addr), upper_32_bits(addr),
4149                               seq, 0xffffffff, 4);
4150 }
4151
4152 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4153                                         unsigned vmid, uint64_t pd_addr)
4154 {
4155         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4156
4157         /* compute doesn't have PFP */
4158         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4159                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4160                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4161                 amdgpu_ring_write(ring, 0x0);
4162         }
4163 }
4164
4165 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4166 {
4167         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
4168 }
4169
4170 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4171 {
4172         u64 wptr;
4173
4174         /* XXX check if swapping is necessary on BE */
4175         if (ring->use_doorbell)
4176                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
4177         else
4178                 BUG();
4179         return wptr;
4180 }
4181
4182 static void gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
4183                                            bool acquire)
4184 {
4185         struct amdgpu_device *adev = ring->adev;
4186         int pipe_num, tmp, reg;
4187         int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
4188
4189         pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
4190
4191         /* first me only has 2 entries, GFX and HP3D */
4192         if (ring->me > 0)
4193                 pipe_num -= 2;
4194
4195         reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num;
4196         tmp = RREG32(reg);
4197         tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
4198         WREG32(reg, tmp);
4199 }
4200
4201 static void gfx_v9_0_pipe_reserve_resources(struct amdgpu_device *adev,
4202                                             struct amdgpu_ring *ring,
4203                                             bool acquire)
4204 {
4205         int i, pipe;
4206         bool reserve;
4207         struct amdgpu_ring *iring;
4208
4209         mutex_lock(&adev->gfx.pipe_reserve_mutex);
4210         pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0);
4211         if (acquire)
4212                 set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4213         else
4214                 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4215
4216         if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
4217                 /* Clear all reservations - everyone reacquires all resources */
4218                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
4219                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
4220                                                        true);
4221
4222                 for (i = 0; i < adev->gfx.num_compute_rings; ++i)
4223                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
4224                                                        true);
4225         } else {
4226                 /* Lower all pipes without a current reservation */
4227                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
4228                         iring = &adev->gfx.gfx_ring[i];
4229                         pipe = amdgpu_gfx_queue_to_bit(adev,
4230                                                        iring->me,
4231                                                        iring->pipe,
4232                                                        0);
4233                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4234                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4235                 }
4236
4237                 for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
4238                         iring = &adev->gfx.compute_ring[i];
4239                         pipe = amdgpu_gfx_queue_to_bit(adev,
4240                                                        iring->me,
4241                                                        iring->pipe,
4242                                                        0);
4243                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4244                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4245                 }
4246         }
4247
4248         mutex_unlock(&adev->gfx.pipe_reserve_mutex);
4249 }
4250
4251 static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev,
4252                                       struct amdgpu_ring *ring,
4253                                       bool acquire)
4254 {
4255         uint32_t pipe_priority = acquire ? 0x2 : 0x0;
4256         uint32_t queue_priority = acquire ? 0xf : 0x0;
4257
4258         mutex_lock(&adev->srbm_mutex);
4259         soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4260
4261         WREG32_SOC15(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority);
4262         WREG32_SOC15(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority);
4263
4264         soc15_grbm_select(adev, 0, 0, 0, 0);
4265         mutex_unlock(&adev->srbm_mutex);
4266 }
4267
4268 static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring,
4269                                                enum drm_sched_priority priority)
4270 {
4271         struct amdgpu_device *adev = ring->adev;
4272         bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
4273
4274         if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
4275                 return;
4276
4277         gfx_v9_0_hqd_set_priority(adev, ring, acquire);
4278         gfx_v9_0_pipe_reserve_resources(adev, ring, acquire);
4279 }
4280
4281 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4282 {
4283         struct amdgpu_device *adev = ring->adev;
4284
4285         /* XXX check if swapping is necessary on BE */
4286         if (ring->use_doorbell) {
4287                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4288                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4289         } else{
4290                 BUG(); /* only DOORBELL method supported on gfx9 now */
4291         }
4292 }
4293
4294 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4295                                          u64 seq, unsigned int flags)
4296 {
4297         struct amdgpu_device *adev = ring->adev;
4298
4299         /* we only allocate 32bit for each seq wb address */
4300         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4301
4302         /* write fence seq to the "addr" */
4303         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4304         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4305                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4306         amdgpu_ring_write(ring, lower_32_bits(addr));
4307         amdgpu_ring_write(ring, upper_32_bits(addr));
4308         amdgpu_ring_write(ring, lower_32_bits(seq));
4309
4310         if (flags & AMDGPU_FENCE_FLAG_INT) {
4311                 /* set register to trigger INT */
4312                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4313                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4314                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4315                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4316                 amdgpu_ring_write(ring, 0);
4317                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4318         }
4319 }
4320
4321 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
4322 {
4323         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4324         amdgpu_ring_write(ring, 0);
4325 }
4326
4327 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
4328 {
4329         struct v9_ce_ib_state ce_payload = {0};
4330         uint64_t csa_addr;
4331         int cnt;
4332
4333         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4334         csa_addr = amdgpu_csa_vaddr(ring->adev);
4335
4336         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4337         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4338                                  WRITE_DATA_DST_SEL(8) |
4339                                  WR_CONFIRM) |
4340                                  WRITE_DATA_CACHE_POLICY(0));
4341         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4342         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4343         amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
4344 }
4345
4346 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
4347 {
4348         struct v9_de_ib_state de_payload = {0};
4349         uint64_t csa_addr, gds_addr;
4350         int cnt;
4351
4352         csa_addr = amdgpu_csa_vaddr(ring->adev);
4353         gds_addr = csa_addr + 4096;
4354         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4355         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4356
4357         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4358         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4359         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4360                                  WRITE_DATA_DST_SEL(8) |
4361                                  WR_CONFIRM) |
4362                                  WRITE_DATA_CACHE_POLICY(0));
4363         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4364         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4365         amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
4366 }
4367
4368 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4369 {
4370         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4371         amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4372 }
4373
4374 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4375 {
4376         uint32_t dw2 = 0;
4377
4378         if (amdgpu_sriov_vf(ring->adev))
4379                 gfx_v9_0_ring_emit_ce_meta(ring);
4380
4381         gfx_v9_0_ring_emit_tmz(ring, true);
4382
4383         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4384         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4385                 /* set load_global_config & load_global_uconfig */
4386                 dw2 |= 0x8001;
4387                 /* set load_cs_sh_regs */
4388                 dw2 |= 0x01000000;
4389                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4390                 dw2 |= 0x10002;
4391
4392                 /* set load_ce_ram if preamble presented */
4393                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4394                         dw2 |= 0x10000000;
4395         } else {
4396                 /* still load_ce_ram if this is the first time preamble presented
4397                  * although there is no context switch happens.
4398                  */
4399                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4400                         dw2 |= 0x10000000;
4401         }
4402
4403         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4404         amdgpu_ring_write(ring, dw2);
4405         amdgpu_ring_write(ring, 0);
4406 }
4407
4408 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4409 {
4410         unsigned ret;
4411         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4412         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4413         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4414         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4415         ret = ring->wptr & ring->buf_mask;
4416         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4417         return ret;
4418 }
4419
4420 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4421 {
4422         unsigned cur;
4423         BUG_ON(offset > ring->buf_mask);
4424         BUG_ON(ring->ring[offset] != 0x55aa55aa);
4425
4426         cur = (ring->wptr & ring->buf_mask) - 1;
4427         if (likely(cur > offset))
4428                 ring->ring[offset] = cur - offset;
4429         else
4430                 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
4431 }
4432
4433 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4434 {
4435         struct amdgpu_device *adev = ring->adev;
4436
4437         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4438         amdgpu_ring_write(ring, 0 |     /* src: register*/
4439                                 (5 << 8) |      /* dst: memory */
4440                                 (1 << 20));     /* write confirm */
4441         amdgpu_ring_write(ring, reg);
4442         amdgpu_ring_write(ring, 0);
4443         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4444                                 adev->virt.reg_val_offs * 4));
4445         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4446                                 adev->virt.reg_val_offs * 4));
4447 }
4448
4449 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4450                                     uint32_t val)
4451 {
4452         uint32_t cmd = 0;
4453
4454         switch (ring->funcs->type) {
4455         case AMDGPU_RING_TYPE_GFX:
4456                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4457                 break;
4458         case AMDGPU_RING_TYPE_KIQ:
4459                 cmd = (1 << 16); /* no inc addr */
4460                 break;
4461         default:
4462                 cmd = WR_CONFIRM;
4463                 break;
4464         }
4465         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4466         amdgpu_ring_write(ring, cmd);
4467         amdgpu_ring_write(ring, reg);
4468         amdgpu_ring_write(ring, 0);
4469         amdgpu_ring_write(ring, val);
4470 }
4471
4472 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4473                                         uint32_t val, uint32_t mask)
4474 {
4475         gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4476 }
4477
4478 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4479                                                   uint32_t reg0, uint32_t reg1,
4480                                                   uint32_t ref, uint32_t mask)
4481 {
4482         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4483         struct amdgpu_device *adev = ring->adev;
4484         bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ?
4485                 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait;
4486
4487         if (fw_version_ok)
4488                 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4489                                       ref, mask, 0x20);
4490         else
4491                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
4492                                                            ref, mask);
4493 }
4494
4495 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
4496 {
4497         struct amdgpu_device *adev = ring->adev;
4498         uint32_t value = 0;
4499
4500         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
4501         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
4502         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
4503         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
4504         WREG32(mmSQ_CMD, value);
4505 }
4506
4507 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4508                                                  enum amdgpu_interrupt_state state)
4509 {
4510         switch (state) {
4511         case AMDGPU_IRQ_STATE_DISABLE:
4512         case AMDGPU_IRQ_STATE_ENABLE:
4513                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4514                                TIME_STAMP_INT_ENABLE,
4515                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4516                 break;
4517         default:
4518                 break;
4519         }
4520 }
4521
4522 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4523                                                      int me, int pipe,
4524                                                      enum amdgpu_interrupt_state state)
4525 {
4526         u32 mec_int_cntl, mec_int_cntl_reg;
4527
4528         /*
4529          * amdgpu controls only the first MEC. That's why this function only
4530          * handles the setting of interrupts for this specific MEC. All other
4531          * pipes' interrupts are set by amdkfd.
4532          */
4533
4534         if (me == 1) {
4535                 switch (pipe) {
4536                 case 0:
4537                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4538                         break;
4539                 case 1:
4540                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4541                         break;
4542                 case 2:
4543                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4544                         break;
4545                 case 3:
4546                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4547                         break;
4548                 default:
4549                         DRM_DEBUG("invalid pipe %d\n", pipe);
4550                         return;
4551                 }
4552         } else {
4553                 DRM_DEBUG("invalid me %d\n", me);
4554                 return;
4555         }
4556
4557         switch (state) {
4558         case AMDGPU_IRQ_STATE_DISABLE:
4559                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4560                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4561                                              TIME_STAMP_INT_ENABLE, 0);
4562                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4563                 break;
4564         case AMDGPU_IRQ_STATE_ENABLE:
4565                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4566                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4567                                              TIME_STAMP_INT_ENABLE, 1);
4568                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4569                 break;
4570         default:
4571                 break;
4572         }
4573 }
4574
4575 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4576                                              struct amdgpu_irq_src *source,
4577                                              unsigned type,
4578                                              enum amdgpu_interrupt_state state)
4579 {
4580         switch (state) {
4581         case AMDGPU_IRQ_STATE_DISABLE:
4582         case AMDGPU_IRQ_STATE_ENABLE:
4583                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4584                                PRIV_REG_INT_ENABLE,
4585                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4586                 break;
4587         default:
4588                 break;
4589         }
4590
4591         return 0;
4592 }
4593
4594 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4595                                               struct amdgpu_irq_src *source,
4596                                               unsigned type,
4597                                               enum amdgpu_interrupt_state state)
4598 {
4599         switch (state) {
4600         case AMDGPU_IRQ_STATE_DISABLE:
4601         case AMDGPU_IRQ_STATE_ENABLE:
4602                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4603                                PRIV_INSTR_INT_ENABLE,
4604                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4605         default:
4606                 break;
4607         }
4608
4609         return 0;
4610 }
4611
4612 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4613                                             struct amdgpu_irq_src *src,
4614                                             unsigned type,
4615                                             enum amdgpu_interrupt_state state)
4616 {
4617         switch (type) {
4618         case AMDGPU_CP_IRQ_GFX_EOP:
4619                 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4620                 break;
4621         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4622                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4623                 break;
4624         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4625                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4626                 break;
4627         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4628                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4629                 break;
4630         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4631                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4632                 break;
4633         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4634                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4635                 break;
4636         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4637                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4638                 break;
4639         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4640                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4641                 break;
4642         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4643                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4644                 break;
4645         default:
4646                 break;
4647         }
4648         return 0;
4649 }
4650
4651 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4652                             struct amdgpu_irq_src *source,
4653                             struct amdgpu_iv_entry *entry)
4654 {
4655         int i;
4656         u8 me_id, pipe_id, queue_id;
4657         struct amdgpu_ring *ring;
4658
4659         DRM_DEBUG("IH: CP EOP\n");
4660         me_id = (entry->ring_id & 0x0c) >> 2;
4661         pipe_id = (entry->ring_id & 0x03) >> 0;
4662         queue_id = (entry->ring_id & 0x70) >> 4;
4663
4664         switch (me_id) {
4665         case 0:
4666                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4667                 break;
4668         case 1:
4669         case 2:
4670                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4671                         ring = &adev->gfx.compute_ring[i];
4672                         /* Per-queue interrupt is supported for MEC starting from VI.
4673                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4674                           */
4675                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4676                                 amdgpu_fence_process(ring);
4677                 }
4678                 break;
4679         }
4680         return 0;
4681 }
4682
4683 static void gfx_v9_0_fault(struct amdgpu_device *adev,
4684                            struct amdgpu_iv_entry *entry)
4685 {
4686         u8 me_id, pipe_id, queue_id;
4687         struct amdgpu_ring *ring;
4688         int i;
4689
4690         me_id = (entry->ring_id & 0x0c) >> 2;
4691         pipe_id = (entry->ring_id & 0x03) >> 0;
4692         queue_id = (entry->ring_id & 0x70) >> 4;
4693
4694         switch (me_id) {
4695         case 0:
4696                 drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
4697                 break;
4698         case 1:
4699         case 2:
4700                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4701                         ring = &adev->gfx.compute_ring[i];
4702                         if (ring->me == me_id && ring->pipe == pipe_id &&
4703                             ring->queue == queue_id)
4704                                 drm_sched_fault(&ring->sched);
4705                 }
4706                 break;
4707         }
4708 }
4709
4710 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4711                                  struct amdgpu_irq_src *source,
4712                                  struct amdgpu_iv_entry *entry)
4713 {
4714         DRM_ERROR("Illegal register access in command stream\n");
4715         gfx_v9_0_fault(adev, entry);
4716         return 0;
4717 }
4718
4719 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4720                                   struct amdgpu_irq_src *source,
4721                                   struct amdgpu_iv_entry *entry)
4722 {
4723         DRM_ERROR("Illegal instruction in command stream\n");
4724         gfx_v9_0_fault(adev, entry);
4725         return 0;
4726 }
4727
4728 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4729         .name = "gfx_v9_0",
4730         .early_init = gfx_v9_0_early_init,
4731         .late_init = gfx_v9_0_late_init,
4732         .sw_init = gfx_v9_0_sw_init,
4733         .sw_fini = gfx_v9_0_sw_fini,
4734         .hw_init = gfx_v9_0_hw_init,
4735         .hw_fini = gfx_v9_0_hw_fini,
4736         .suspend = gfx_v9_0_suspend,
4737         .resume = gfx_v9_0_resume,
4738         .is_idle = gfx_v9_0_is_idle,
4739         .wait_for_idle = gfx_v9_0_wait_for_idle,
4740         .soft_reset = gfx_v9_0_soft_reset,
4741         .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4742         .set_powergating_state = gfx_v9_0_set_powergating_state,
4743         .get_clockgating_state = gfx_v9_0_get_clockgating_state,
4744 };
4745
4746 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4747         .type = AMDGPU_RING_TYPE_GFX,
4748         .align_mask = 0xff,
4749         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4750         .support_64bit_ptrs = true,
4751         .vmhub = AMDGPU_GFXHUB,
4752         .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4753         .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4754         .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
4755         .emit_frame_size = /* totally 242 maximum if 16 IBs */
4756                 5 +  /* COND_EXEC */
4757                 7 +  /* PIPELINE_SYNC */
4758                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4759                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4760                 2 + /* VM_FLUSH */
4761                 8 +  /* FENCE for VM_FLUSH */
4762                 20 + /* GDS switch */
4763                 4 + /* double SWITCH_BUFFER,
4764                        the first COND_EXEC jump to the place just
4765                            prior to this double SWITCH_BUFFER  */
4766                 5 + /* COND_EXEC */
4767                 7 +      /*     HDP_flush */
4768                 4 +      /*     VGT_flush */
4769                 14 + /* CE_META */
4770                 31 + /* DE_META */
4771                 3 + /* CNTX_CTRL */
4772                 5 + /* HDP_INVL */
4773                 8 + 8 + /* FENCE x2 */
4774                 2, /* SWITCH_BUFFER */
4775         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4776         .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4777         .emit_fence = gfx_v9_0_ring_emit_fence,
4778         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4779         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4780         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4781         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4782         .test_ring = gfx_v9_0_ring_test_ring,
4783         .test_ib = gfx_v9_0_ring_test_ib,
4784         .insert_nop = amdgpu_ring_insert_nop,
4785         .pad_ib = amdgpu_ring_generic_pad_ib,
4786         .emit_switch_buffer = gfx_v9_ring_emit_sb,
4787         .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
4788         .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4789         .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
4790         .emit_tmz = gfx_v9_0_ring_emit_tmz,
4791         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4792         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4793         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4794         .soft_recovery = gfx_v9_0_ring_soft_recovery,
4795 };
4796
4797 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4798         .type = AMDGPU_RING_TYPE_COMPUTE,
4799         .align_mask = 0xff,
4800         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4801         .support_64bit_ptrs = true,
4802         .vmhub = AMDGPU_GFXHUB,
4803         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4804         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4805         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4806         .emit_frame_size =
4807                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4808                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4809                 5 + /* hdp invalidate */
4810                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4811                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4812                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4813                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4814                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4815         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4816         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4817         .emit_fence = gfx_v9_0_ring_emit_fence,
4818         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4819         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4820         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4821         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4822         .test_ring = gfx_v9_0_ring_test_ring,
4823         .test_ib = gfx_v9_0_ring_test_ib,
4824         .insert_nop = amdgpu_ring_insert_nop,
4825         .pad_ib = amdgpu_ring_generic_pad_ib,
4826         .set_priority = gfx_v9_0_ring_set_priority_compute,
4827         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4828         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4829         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4830 };
4831
4832 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4833         .type = AMDGPU_RING_TYPE_KIQ,
4834         .align_mask = 0xff,
4835         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4836         .support_64bit_ptrs = true,
4837         .vmhub = AMDGPU_GFXHUB,
4838         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4839         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4840         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4841         .emit_frame_size =
4842                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4843                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4844                 5 + /* hdp invalidate */
4845                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4846                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4847                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4848                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4849                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4850         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4851         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4852         .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
4853         .test_ring = gfx_v9_0_ring_test_ring,
4854         .test_ib = gfx_v9_0_ring_test_ib,
4855         .insert_nop = amdgpu_ring_insert_nop,
4856         .pad_ib = amdgpu_ring_generic_pad_ib,
4857         .emit_rreg = gfx_v9_0_ring_emit_rreg,
4858         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4859         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4860         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4861 };
4862
4863 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4864 {
4865         int i;
4866
4867         adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4868
4869         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4870                 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4871
4872         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4873                 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4874 }
4875
4876 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4877         .set = gfx_v9_0_set_eop_interrupt_state,
4878         .process = gfx_v9_0_eop_irq,
4879 };
4880
4881 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4882         .set = gfx_v9_0_set_priv_reg_fault_state,
4883         .process = gfx_v9_0_priv_reg_irq,
4884 };
4885
4886 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4887         .set = gfx_v9_0_set_priv_inst_fault_state,
4888         .process = gfx_v9_0_priv_inst_irq,
4889 };
4890
4891 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4892 {
4893         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4894         adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4895
4896         adev->gfx.priv_reg_irq.num_types = 1;
4897         adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4898
4899         adev->gfx.priv_inst_irq.num_types = 1;
4900         adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
4901 }
4902
4903 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4904 {
4905         switch (adev->asic_type) {
4906         case CHIP_VEGA10:
4907         case CHIP_VEGA12:
4908         case CHIP_VEGA20:
4909         case CHIP_RAVEN:
4910                 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4911                 break;
4912         default:
4913                 break;
4914         }
4915 }
4916
4917 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4918 {
4919         /* init asci gds info */
4920         switch (adev->asic_type) {
4921         case CHIP_VEGA10:
4922         case CHIP_VEGA12:
4923         case CHIP_VEGA20:
4924                 adev->gds.mem.total_size = 0x10000;
4925                 break;
4926         case CHIP_RAVEN:
4927                 adev->gds.mem.total_size = 0x1000;
4928                 break;
4929         default:
4930                 adev->gds.mem.total_size = 0x10000;
4931                 break;
4932         }
4933
4934         adev->gds.gws.total_size = 64;
4935         adev->gds.oa.total_size = 16;
4936
4937         if (adev->gds.mem.total_size == 64 * 1024) {
4938                 adev->gds.mem.gfx_partition_size = 4096;
4939                 adev->gds.mem.cs_partition_size = 4096;
4940
4941                 adev->gds.gws.gfx_partition_size = 4;
4942                 adev->gds.gws.cs_partition_size = 4;
4943
4944                 adev->gds.oa.gfx_partition_size = 4;
4945                 adev->gds.oa.cs_partition_size = 1;
4946         } else {
4947                 adev->gds.mem.gfx_partition_size = 1024;
4948                 adev->gds.mem.cs_partition_size = 1024;
4949
4950                 adev->gds.gws.gfx_partition_size = 16;
4951                 adev->gds.gws.cs_partition_size = 16;
4952
4953                 adev->gds.oa.gfx_partition_size = 4;
4954                 adev->gds.oa.cs_partition_size = 4;
4955         }
4956 }
4957
4958 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4959                                                  u32 bitmap)
4960 {
4961         u32 data;
4962
4963         if (!bitmap)
4964                 return;
4965
4966         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4967         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4968
4969         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4970 }
4971
4972 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4973 {
4974         u32 data, mask;
4975
4976         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4977         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
4978
4979         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4980         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4981
4982         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4983
4984         return (~data) & mask;
4985 }
4986
4987 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4988                                  struct amdgpu_cu_info *cu_info)
4989 {
4990         int i, j, k, counter, active_cu_number = 0;
4991         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4992         unsigned disable_masks[4 * 2];
4993
4994         if (!adev || !cu_info)
4995                 return -EINVAL;
4996
4997         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4998
4999         mutex_lock(&adev->grbm_idx_mutex);
5000         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5001                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5002                         mask = 1;
5003                         ao_bitmap = 0;
5004                         counter = 0;
5005                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
5006                         if (i < 4 && j < 2)
5007                                 gfx_v9_0_set_user_cu_inactive_bitmap(
5008                                         adev, disable_masks[i * 2 + j]);
5009                         bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
5010                         cu_info->bitmap[i][j] = bitmap;
5011
5012                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
5013                                 if (bitmap & mask) {
5014                                         if (counter < adev->gfx.config.max_cu_per_sh)
5015                                                 ao_bitmap |= mask;
5016                                         counter ++;
5017                                 }
5018                                 mask <<= 1;
5019                         }
5020                         active_cu_number += counter;
5021                         if (i < 2 && j < 2)
5022                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5023                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
5024                 }
5025         }
5026         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5027         mutex_unlock(&adev->grbm_idx_mutex);
5028
5029         cu_info->number = active_cu_number;
5030         cu_info->ao_cu_mask = ao_cu_mask;
5031         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5032
5033         return 0;
5034 }
5035
5036 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
5037 {
5038         .type = AMD_IP_BLOCK_TYPE_GFX,
5039         .major = 9,
5040         .minor = 0,
5041         .rev = 0,
5042         .funcs = &gfx_v9_0_ip_funcs,
5043 };