drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_xcp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_trace.h"
  33
  34 #include "sdma/sdma_4_4_2_offset.h"
  35 #include "sdma/sdma_4_4_2_sh_mask.h"
  36
  37 #include "soc15_common.h"
  38 #include "soc15.h"
  39 #include "vega10_sdma_pkt_open.h"
  40
  41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
  42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
  43
  44 #include "amdgpu_ras.h"
  45
  46 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin");
  47
  48 #define WREG32_SDMA(instance, offset, value) \
  49         WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value)
  50 #define RREG32_SDMA(instance, offset) \
  51         RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)))
  52
  53 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev);
  54 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev);
  55 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev);
  56 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev);
  57 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev);
  58
  59 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev,
  60                 u32 instance, u32 offset)
  61 {
  62         u32 dev_inst = GET_INST(SDMA0, instance);
  63
  64         return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset);
  65 }
  66
  67 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num)
  68 {
  69         switch (seq_num) {
  70         case 0:
  71                 return SOC15_IH_CLIENTID_SDMA0;
  72         case 1:
  73                 return SOC15_IH_CLIENTID_SDMA1;
  74         case 2:
  75                 return SOC15_IH_CLIENTID_SDMA2;
  76         case 3:
  77                 return SOC15_IH_CLIENTID_SDMA3;
  78         default:
  79                 return -EINVAL;
  80         }
  81 }
  82
  83 static int sdma_v4_4_2_irq_id_to_seq(unsigned client_id)
  84 {
  85         switch (client_id) {
  86         case SOC15_IH_CLIENTID_SDMA0:
  87                 return 0;
  88         case SOC15_IH_CLIENTID_SDMA1:
  89                 return 1;
  90         case SOC15_IH_CLIENTID_SDMA2:
  91                 return 2;
  92         case SOC15_IH_CLIENTID_SDMA3:
  93                 return 3;
  94         default:
  95                 return -EINVAL;
  96         }
  97 }
  98
  99 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev,
 100                                                    uint32_t inst_mask)
 101 {
 102         u32 val;
 103         int i;
 104
 105         for (i = 0; i < adev->sdma.num_instances; i++) {
 106                 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG);
 107                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4);
 108                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG,
 109                                     PIPE_INTERLEAVE_SIZE, 0);
 110                 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val);
 111
 112                 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ);
 113                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS,
 114                                     4);
 115                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ,
 116                                     PIPE_INTERLEAVE_SIZE, 0);
 117                 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val);
 118         }
 119 }
 120
 121 /**
 122  * sdma_v4_4_2_init_microcode - load ucode images from disk
 123  *
 124  * @adev: amdgpu_device pointer
 125  *
 126  * Use the firmware interface to load the ucode images into
 127  * the driver (not loaded into hw).
 128  * Returns 0 on success, error on failure.
 129  */
 130 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev)
 131 {
 132         int ret, i;
 133
 134         for (i = 0; i < adev->sdma.num_instances; i++) {
 135                 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) ==
 136                     IP_VERSION(4, 4, 2)) {
 137                         ret = amdgpu_sdma_init_microcode(adev, 0, true);
 138                         break;
 139                 } else {
 140                         ret = amdgpu_sdma_init_microcode(adev, i, false);
 141                         if (ret)
 142                                 return ret;
 143                 }
 144         }
 145
 146         return ret;
 147 }
 148
 149 /**
 150  * sdma_v4_4_2_ring_get_rptr - get the current read pointer
 151  *
 152  * @ring: amdgpu ring pointer
 153  *
 154  * Get the current rptr from the hardware.
 155  */
 156 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring)
 157 {
 158         u64 rptr;
 159
 160         /* XXX check if swapping is necessary on BE */
 161         rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs]));
 162
 163         DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr);
 164         return rptr >> 2;
 165 }
 166
 167 /**
 168  * sdma_v4_4_2_ring_get_wptr - get the current write pointer
 169  *
 170  * @ring: amdgpu ring pointer
 171  *
 172  * Get the current wptr from the hardware.
 173  */
 174 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring)
 175 {
 176         struct amdgpu_device *adev = ring->adev;
 177         u64 wptr;
 178
 179         if (ring->use_doorbell) {
 180                 /* XXX check if swapping is necessary on BE */
 181                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 182                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 183         } else {
 184                 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI);
 185                 wptr = wptr << 32;
 186                 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR);
 187                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
 188                                 ring->me, wptr);
 189         }
 190
 191         return wptr >> 2;
 192 }
 193
 194 /**
 195  * sdma_v4_4_2_ring_set_wptr - commit the write pointer
 196  *
 197  * @ring: amdgpu ring pointer
 198  *
 199  * Write the wptr back to the hardware.
 200  */
 201 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring)
 202 {
 203         struct amdgpu_device *adev = ring->adev;
 204
 205         DRM_DEBUG("Setting write pointer\n");
 206         if (ring->use_doorbell) {
 207                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 208
 209                 DRM_DEBUG("Using doorbell -- "
 210                                 "wptr_offs == 0x%08x "
 211                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 212                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 213                                 ring->wptr_offs,
 214                                 lower_32_bits(ring->wptr << 2),
 215                                 upper_32_bits(ring->wptr << 2));
 216                 /* XXX check if swapping is necessary on BE */
 217                 WRITE_ONCE(*wb, (ring->wptr << 2));
 218                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 219                                 ring->doorbell_index, ring->wptr << 2);
 220                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 221         } else {
 222                 DRM_DEBUG("Not using doorbell -- "
 223                                 "regSDMA%i_GFX_RB_WPTR == 0x%08x "
 224                                 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 225                                 ring->me,
 226                                 lower_32_bits(ring->wptr << 2),
 227                                 ring->me,
 228                                 upper_32_bits(ring->wptr << 2));
 229                 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR,
 230                             lower_32_bits(ring->wptr << 2));
 231                 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI,
 232                             upper_32_bits(ring->wptr << 2));
 233         }
 234 }
 235
 236 /**
 237  * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer
 238  *
 239  * @ring: amdgpu ring pointer
 240  *
 241  * Get the current wptr from the hardware.
 242  */
 243 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring)
 244 {
 245         struct amdgpu_device *adev = ring->adev;
 246         u64 wptr;
 247
 248         if (ring->use_doorbell) {
 249                 /* XXX check if swapping is necessary on BE */
 250                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 251         } else {
 252                 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI);
 253                 wptr = wptr << 32;
 254                 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR);
 255         }
 256
 257         return wptr >> 2;
 258 }
 259
 260 /**
 261  * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer
 262  *
 263  * @ring: amdgpu ring pointer
 264  *
 265  * Write the wptr back to the hardware.
 266  */
 267 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring)
 268 {
 269         struct amdgpu_device *adev = ring->adev;
 270
 271         if (ring->use_doorbell) {
 272                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 273
 274                 /* XXX check if swapping is necessary on BE */
 275                 WRITE_ONCE(*wb, (ring->wptr << 2));
 276                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 277         } else {
 278                 uint64_t wptr = ring->wptr << 2;
 279
 280                 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR,
 281                             lower_32_bits(wptr));
 282                 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI,
 283                             upper_32_bits(wptr));
 284         }
 285 }
 286
 287 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 288 {
 289         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 290         int i;
 291
 292         for (i = 0; i < count; i++)
 293                 if (sdma && sdma->burst_nop && (i == 0))
 294                         amdgpu_ring_write(ring, ring->funcs->nop |
 295                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 296                 else
 297                         amdgpu_ring_write(ring, ring->funcs->nop);
 298 }
 299
 300 /**
 301  * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine
 302  *
 303  * @ring: amdgpu ring pointer
 304  * @job: job to retrieve vmid from
 305  * @ib: IB object to schedule
 306  * @flags: unused
 307  *
 308  * Schedule an IB in the DMA ring.
 309  */
 310 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring,
 311                                    struct amdgpu_job *job,
 312                                    struct amdgpu_ib *ib,
 313                                    uint32_t flags)
 314 {
 315         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 316
 317         /* IB packet must end on a 8 DW boundary */
 318         sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 319
 320         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 321                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 322         /* base must be 32 byte aligned */
 323         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 324         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 325         amdgpu_ring_write(ring, ib->length_dw);
 326         amdgpu_ring_write(ring, 0);
 327         amdgpu_ring_write(ring, 0);
 328
 329 }
 330
 331 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring,
 332                                    int mem_space, int hdp,
 333                                    uint32_t addr0, uint32_t addr1,
 334                                    uint32_t ref, uint32_t mask,
 335                                    uint32_t inv)
 336 {
 337         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 338                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
 339                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
 340                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 341         if (mem_space) {
 342                 /* memory */
 343                 amdgpu_ring_write(ring, addr0);
 344                 amdgpu_ring_write(ring, addr1);
 345         } else {
 346                 /* registers */
 347                 amdgpu_ring_write(ring, addr0 << 2);
 348                 amdgpu_ring_write(ring, addr1 << 2);
 349         }
 350         amdgpu_ring_write(ring, ref); /* reference */
 351         amdgpu_ring_write(ring, mask); /* mask */
 352         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 353                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
 354 }
 355
 356 /**
 357  * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 358  *
 359  * @ring: amdgpu ring pointer
 360  *
 361  * Emit an hdp flush packet on the requested DMA ring.
 362  */
 363 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 364 {
 365         struct amdgpu_device *adev = ring->adev;
 366         u32 ref_and_mask = 0;
 367         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 368
 369         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 370
 371         sdma_v4_4_2_wait_reg_mem(ring, 0, 1,
 372                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
 373                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
 374                                ref_and_mask, ref_and_mask, 10);
 375 }
 376
 377 /**
 378  * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring
 379  *
 380  * @ring: amdgpu ring pointer
 381  * @addr: address
 382  * @seq: sequence number
 383  * @flags: fence related flags
 384  *
 385  * Add a DMA fence packet to the ring to write
 386  * the fence seq number and DMA trap packet to generate
 387  * an interrupt if needed.
 388  */
 389 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 390                                       unsigned flags)
 391 {
 392         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 393         /* write the fence */
 394         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 395         /* zero in first two bits */
 396         BUG_ON(addr & 0x3);
 397         amdgpu_ring_write(ring, lower_32_bits(addr));
 398         amdgpu_ring_write(ring, upper_32_bits(addr));
 399         amdgpu_ring_write(ring, lower_32_bits(seq));
 400
 401         /* optionally write high bits as well */
 402         if (write64bit) {
 403                 addr += 4;
 404                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 405                 /* zero in first two bits */
 406                 BUG_ON(addr & 0x3);
 407                 amdgpu_ring_write(ring, lower_32_bits(addr));
 408                 amdgpu_ring_write(ring, upper_32_bits(addr));
 409                 amdgpu_ring_write(ring, upper_32_bits(seq));
 410         }
 411
 412         /* generate an interrupt */
 413         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 414         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 415 }
 416
 417
 418 /**
 419  * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines
 420  *
 421  * @adev: amdgpu_device pointer
 422  * @inst_mask: mask of dma engine instances to be disabled
 423  *
 424  * Stop the gfx async dma ring buffers.
 425  */
 426 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev,
 427                                       uint32_t inst_mask)
 428 {
 429         struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
 430         u32 rb_cntl, ib_cntl;
 431         int i, unset = 0;
 432
 433         for_each_inst(i, inst_mask) {
 434                 sdma[i] = &adev->sdma.instance[i].ring;
 435
 436                 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) {
 437                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
 438                         unset = 1;
 439                 }
 440
 441                 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
 442                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0);
 443                 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
 444                 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
 445                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0);
 446                 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
 447         }
 448 }
 449
 450 /**
 451  * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines
 452  *
 453  * @adev: amdgpu_device pointer
 454  * @inst_mask: mask of dma engine instances to be disabled
 455  *
 456  * Stop the compute async dma queues.
 457  */
 458 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev,
 459                                       uint32_t inst_mask)
 460 {
 461         /* XXX todo */
 462 }
 463
 464 /**
 465  * sdma_v4_4_2_inst_page_stop - stop the page async dma engines
 466  *
 467  * @adev: amdgpu_device pointer
 468  * @inst_mask: mask of dma engine instances to be disabled
 469  *
 470  * Stop the page async dma ring buffers.
 471  */
 472 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev,
 473                                        uint32_t inst_mask)
 474 {
 475         struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
 476         u32 rb_cntl, ib_cntl;
 477         int i;
 478         bool unset = false;
 479
 480         for_each_inst(i, inst_mask) {
 481                 sdma[i] = &adev->sdma.instance[i].page;
 482
 483                 if ((adev->mman.buffer_funcs_ring == sdma[i]) &&
 484                         (!unset)) {
 485                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
 486                         unset = true;
 487                 }
 488
 489                 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
 490                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
 491                                         RB_ENABLE, 0);
 492                 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
 493                 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
 494                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL,
 495                                         IB_ENABLE, 0);
 496                 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
 497         }
 498 }
 499
 500 /**
 501  * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch
 502  *
 503  * @adev: amdgpu_device pointer
 504  * @enable: enable/disable the DMA MEs context switch.
 505  * @inst_mask: mask of dma engine instances to be enabled
 506  *
 507  * Halt or unhalt the async dma engines context switch.
 508  */
 509 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev,
 510                                                bool enable, uint32_t inst_mask)
 511 {
 512         u32 f32_cntl, phase_quantum = 0;
 513         int i;
 514
 515         if (amdgpu_sdma_phase_quantum) {
 516                 unsigned value = amdgpu_sdma_phase_quantum;
 517                 unsigned unit = 0;
 518
 519                 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
 520                                 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) {
 521                         value = (value + 1) >> 1;
 522                         unit++;
 523                 }
 524                 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
 525                             SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) {
 526                         value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
 527                                  SDMA_PHASE0_QUANTUM__VALUE__SHIFT);
 528                         unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
 529                                 SDMA_PHASE0_QUANTUM__UNIT__SHIFT);
 530                         WARN_ONCE(1,
 531                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 532                                   value << unit);
 533                 }
 534                 phase_quantum =
 535                         value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT |
 536                         unit  << SDMA_PHASE0_QUANTUM__UNIT__SHIFT;
 537         }
 538
 539         for_each_inst(i, inst_mask) {
 540                 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL);
 541                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL,
 542                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 543                 if (enable && amdgpu_sdma_phase_quantum) {
 544                         WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum);
 545                         WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum);
 546                         WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum);
 547                 }
 548                 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl);
 549
 550                 /* Extend page fault timeout to avoid interrupt storm */
 551                 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080);
 552         }
 553 }
 554
 555 /**
 556  * sdma_v4_4_2_inst_enable - stop the async dma engines
 557  *
 558  * @adev: amdgpu_device pointer
 559  * @enable: enable/disable the DMA MEs.
 560  * @inst_mask: mask of dma engine instances to be enabled
 561  *
 562  * Halt or unhalt the async dma engines.
 563  */
 564 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable,
 565                                     uint32_t inst_mask)
 566 {
 567         u32 f32_cntl;
 568         int i;
 569
 570         if (!enable) {
 571                 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask);
 572                 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask);
 573                 if (adev->sdma.has_page_queue)
 574                         sdma_v4_4_2_inst_page_stop(adev, inst_mask);
 575
 576                 /* SDMA FW needs to respond to FREEZE requests during reset.
 577                  * Keep it running during reset */
 578                 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
 579                         return;
 580         }
 581
 582         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 583                 return;
 584
 585         for_each_inst(i, inst_mask) {
 586                 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL);
 587                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1);
 588                 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl);
 589         }
 590 }
 591
 592 /*
 593  * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl
 594  */
 595 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
 596 {
 597         /* Set ring buffer size in dwords */
 598         uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
 599
 600         barrier(); /* work around https://bugs.llvm.org/show_bug.cgi?id=42576 */
 601         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 602 #ifdef __BIG_ENDIAN
 603         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 604         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
 605                                 RPTR_WRITEBACK_SWAP_ENABLE, 1);
 606 #endif
 607         return rb_cntl;
 608 }
 609
 610 /**
 611  * sdma_v4_4_2_gfx_resume - setup and start the async dma engines
 612  *
 613  * @adev: amdgpu_device pointer
 614  * @i: instance to resume
 615  *
 616  * Set up the gfx DMA ring buffers and enable them.
 617  * Returns 0 for success, error for failure.
 618  */
 619 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i)
 620 {
 621         struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
 622         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 623         u32 wb_offset;
 624         u32 doorbell;
 625         u32 doorbell_offset;
 626         u64 wptr_gpu_addr;
 627
 628         wb_offset = (ring->rptr_offs * 4);
 629
 630         rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
 631         rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
 632         WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
 633
 634         /* Initialize the ring buffer's read and write pointers */
 635         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0);
 636         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0);
 637         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0);
 638         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0);
 639
 640         /* set the wb address whether it's enabled or not */
 641         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI,
 642                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 643         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO,
 644                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 645
 646         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
 647                                 RPTR_WRITEBACK_ENABLE, 1);
 648
 649         WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8);
 650         WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
 651
 652         ring->wptr = 0;
 653
 654         /* before programing wptr to a less value, need set minor_ptr_update first */
 655         WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1);
 656
 657         doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
 658         doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
 659
 660         doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE,
 661                                  ring->use_doorbell);
 662         doorbell_offset = REG_SET_FIELD(doorbell_offset,
 663                                         SDMA_GFX_DOORBELL_OFFSET,
 664                                         OFFSET, ring->doorbell_index);
 665         WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell);
 666         WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset);
 667
 668         sdma_v4_4_2_ring_set_wptr(ring);
 669
 670         /* set minor_ptr_update to 0 after wptr programed */
 671         WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0);
 672
 673         /* setup the wptr shadow polling */
 674         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 675         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO,
 676                     lower_32_bits(wptr_gpu_addr));
 677         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI,
 678                     upper_32_bits(wptr_gpu_addr));
 679         wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL);
 680         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 681                                        SDMA_GFX_RB_WPTR_POLL_CNTL,
 682                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
 683         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
 684
 685         /* enable DMA RB */
 686         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1);
 687         WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
 688
 689         ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
 690         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1);
 691 #ifdef __BIG_ENDIAN
 692         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 693 #endif
 694         /* enable DMA IBs */
 695         WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
 696 }
 697
 698 /**
 699  * sdma_v4_4_2_page_resume - setup and start the async dma engines
 700  *
 701  * @adev: amdgpu_device pointer
 702  * @i: instance to resume
 703  *
 704  * Set up the page DMA ring buffers and enable them.
 705  * Returns 0 for success, error for failure.
 706  */
 707 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i)
 708 {
 709         struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
 710         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 711         u32 wb_offset;
 712         u32 doorbell;
 713         u32 doorbell_offset;
 714         u64 wptr_gpu_addr;
 715
 716         wb_offset = (ring->rptr_offs * 4);
 717
 718         rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
 719         rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
 720         WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
 721
 722         /* Initialize the ring buffer's read and write pointers */
 723         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0);
 724         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0);
 725         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0);
 726         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0);
 727
 728         /* set the wb address whether it's enabled or not */
 729         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI,
 730                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 731         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO,
 732                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 733
 734         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
 735                                 RPTR_WRITEBACK_ENABLE, 1);
 736
 737         WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8);
 738         WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
 739
 740         ring->wptr = 0;
 741
 742         /* before programing wptr to a less value, need set minor_ptr_update first */
 743         WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1);
 744
 745         doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL);
 746         doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET);
 747
 748         doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE,
 749                                  ring->use_doorbell);
 750         doorbell_offset = REG_SET_FIELD(doorbell_offset,
 751                                         SDMA_PAGE_DOORBELL_OFFSET,
 752                                         OFFSET, ring->doorbell_index);
 753         WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell);
 754         WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset);
 755
 756         /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */
 757         sdma_v4_4_2_page_ring_set_wptr(ring);
 758
 759         /* set minor_ptr_update to 0 after wptr programed */
 760         WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0);
 761
 762         /* setup the wptr shadow polling */
 763         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 764         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO,
 765                     lower_32_bits(wptr_gpu_addr));
 766         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI,
 767                     upper_32_bits(wptr_gpu_addr));
 768         wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL);
 769         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 770                                        SDMA_PAGE_RB_WPTR_POLL_CNTL,
 771                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
 772         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
 773
 774         /* enable DMA RB */
 775         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1);
 776         WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
 777
 778         ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
 779         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1);
 780 #ifdef __BIG_ENDIAN
 781         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
 782 #endif
 783         /* enable DMA IBs */
 784         WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
 785 }
 786
 787 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev)
 788 {
 789
 790 }
 791
 792 /**
 793  * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines
 794  *
 795  * @adev: amdgpu_device pointer
 796  * @inst_mask: mask of dma engine instances to be enabled
 797  *
 798  * Set up the compute DMA queues and enable them.
 799  * Returns 0 for success, error for failure.
 800  */
 801 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev,
 802                                        uint32_t inst_mask)
 803 {
 804         sdma_v4_4_2_init_pg(adev);
 805
 806         return 0;
 807 }
 808
 809 /**
 810  * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode
 811  *
 812  * @adev: amdgpu_device pointer
 813  * @inst_mask: mask of dma engine instances to be enabled
 814  *
 815  * Loads the sDMA0/1 ucode.
 816  * Returns 0 for success, -EINVAL if the ucode is not available.
 817  */
 818 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev,
 819                                            uint32_t inst_mask)
 820 {
 821         const struct sdma_firmware_header_v1_0 *hdr;
 822         const __le32 *fw_data;
 823         u32 fw_size;
 824         int i, j;
 825
 826         /* halt the MEs */
 827         sdma_v4_4_2_inst_enable(adev, false, inst_mask);
 828
 829         for_each_inst(i, inst_mask) {
 830                 if (!adev->sdma.instance[i].fw)
 831                         return -EINVAL;
 832
 833                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 834                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 835                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 836
 837                 fw_data = (const __le32 *)
 838                         (adev->sdma.instance[i].fw->data +
 839                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 840
 841                 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0);
 842
 843                 for (j = 0; j < fw_size; j++)
 844                         WREG32_SDMA(i, regSDMA_UCODE_DATA,
 845                                     le32_to_cpup(fw_data++));
 846
 847                 WREG32_SDMA(i, regSDMA_UCODE_ADDR,
 848                             adev->sdma.instance[i].fw_version);
 849         }
 850
 851         return 0;
 852 }
 853
 854 /**
 855  * sdma_v4_4_2_inst_start - setup and start the async dma engines
 856  *
 857  * @adev: amdgpu_device pointer
 858  * @inst_mask: mask of dma engine instances to be enabled
 859  *
 860  * Set up the DMA engines and enable them.
 861  * Returns 0 for success, error for failure.
 862  */
 863 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev,
 864                                   uint32_t inst_mask)
 865 {
 866         struct amdgpu_ring *ring;
 867         uint32_t tmp_mask;
 868         int i, r = 0;
 869
 870         if (amdgpu_sriov_vf(adev)) {
 871                 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
 872                 sdma_v4_4_2_inst_enable(adev, false, inst_mask);
 873         } else {
 874                 /* bypass sdma microcode loading on Gopher */
 875                 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP &&
 876                     adev->sdma.instance[0].fw) {
 877                         r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask);
 878                         if (r)
 879                                 return r;
 880                 }
 881
 882                 /* unhalt the MEs */
 883                 sdma_v4_4_2_inst_enable(adev, true, inst_mask);
 884                 /* enable sdma ring preemption */
 885                 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
 886         }
 887
 888         /* start the gfx rings and rlc compute queues */
 889         tmp_mask = inst_mask;
 890         for_each_inst(i, tmp_mask) {
 891                 uint32_t temp;
 892
 893                 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
 894                 sdma_v4_4_2_gfx_resume(adev, i);
 895                 if (adev->sdma.has_page_queue)
 896                         sdma_v4_4_2_page_resume(adev, i);
 897
 898                 /* set utc l1 enable flag always to 1 */
 899                 temp = RREG32_SDMA(i, regSDMA_CNTL);
 900                 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1);
 901                 /* enable context empty interrupt during initialization */
 902                 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1);
 903                 WREG32_SDMA(i, regSDMA_CNTL, temp);
 904
 905                 if (!amdgpu_sriov_vf(adev)) {
 906                         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 907                                 /* unhalt engine */
 908                                 temp = RREG32_SDMA(i, regSDMA_F32_CNTL);
 909                                 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0);
 910                                 WREG32_SDMA(i, regSDMA_F32_CNTL, temp);
 911                         }
 912                 }
 913         }
 914
 915         if (amdgpu_sriov_vf(adev)) {
 916                 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
 917                 sdma_v4_4_2_inst_enable(adev, true, inst_mask);
 918         } else {
 919                 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask);
 920                 if (r)
 921                         return r;
 922         }
 923
 924         tmp_mask = inst_mask;
 925         for_each_inst(i, tmp_mask) {
 926                 ring = &adev->sdma.instance[i].ring;
 927
 928                 r = amdgpu_ring_test_helper(ring);
 929                 if (r)
 930                         return r;
 931
 932                 if (adev->sdma.has_page_queue) {
 933                         struct amdgpu_ring *page = &adev->sdma.instance[i].page;
 934
 935                         r = amdgpu_ring_test_helper(page);
 936                         if (r)
 937                                 return r;
 938
 939                         if (adev->mman.buffer_funcs_ring == page)
 940                                 amdgpu_ttm_set_buffer_funcs_status(adev, true);
 941                 }
 942
 943                 if (adev->mman.buffer_funcs_ring == ring)
 944                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 945         }
 946
 947         return r;
 948 }
 949
 950 /**
 951  * sdma_v4_4_2_ring_test_ring - simple async dma engine test
 952  *
 953  * @ring: amdgpu_ring structure holding ring information
 954  *
 955  * Test the DMA engine by writing using it to write an
 956  * value to memory.
 957  * Returns 0 for success, error for failure.
 958  */
 959 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring)
 960 {
 961         struct amdgpu_device *adev = ring->adev;
 962         unsigned i;
 963         unsigned index;
 964         int r;
 965         u32 tmp;
 966         u64 gpu_addr;
 967
 968         r = amdgpu_device_wb_get(adev, &index);
 969         if (r)
 970                 return r;
 971
 972         gpu_addr = adev->wb.gpu_addr + (index * 4);
 973         tmp = 0xCAFEDEAD;
 974         adev->wb.wb[index] = cpu_to_le32(tmp);
 975
 976         r = amdgpu_ring_alloc(ring, 5);
 977         if (r)
 978                 goto error_free_wb;
 979
 980         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 981                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 982         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 983         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 984         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 985         amdgpu_ring_write(ring, 0xDEADBEEF);
 986         amdgpu_ring_commit(ring);
 987
 988         for (i = 0; i < adev->usec_timeout; i++) {
 989                 tmp = le32_to_cpu(adev->wb.wb[index]);
 990                 if (tmp == 0xDEADBEEF)
 991                         break;
 992                 udelay(1);
 993         }
 994
 995         if (i >= adev->usec_timeout)
 996                 r = -ETIMEDOUT;
 997
 998 error_free_wb:
 999         amdgpu_device_wb_free(adev, index);
1000         return r;
1001 }
1002
1003 /**
1004  * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine
1005  *
1006  * @ring: amdgpu_ring structure holding ring information
1007  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1008  *
1009  * Test a simple IB in the DMA ring.
1010  * Returns 0 on success, error on failure.
1011  */
1012 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1013 {
1014         struct amdgpu_device *adev = ring->adev;
1015         struct amdgpu_ib ib;
1016         struct dma_fence *f = NULL;
1017         unsigned index;
1018         long r;
1019         u32 tmp = 0;
1020         u64 gpu_addr;
1021
1022         r = amdgpu_device_wb_get(adev, &index);
1023         if (r)
1024                 return r;
1025
1026         gpu_addr = adev->wb.gpu_addr + (index * 4);
1027         tmp = 0xCAFEDEAD;
1028         adev->wb.wb[index] = cpu_to_le32(tmp);
1029         memset(&ib, 0, sizeof(ib));
1030         r = amdgpu_ib_get(adev, NULL, 256,
1031                                         AMDGPU_IB_POOL_DIRECT, &ib);
1032         if (r)
1033                 goto err0;
1034
1035         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1036                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1037         ib.ptr[1] = lower_32_bits(gpu_addr);
1038         ib.ptr[2] = upper_32_bits(gpu_addr);
1039         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1040         ib.ptr[4] = 0xDEADBEEF;
1041         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1042         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1043         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1044         ib.length_dw = 8;
1045
1046         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1047         if (r)
1048                 goto err1;
1049
1050         r = dma_fence_wait_timeout(f, false, timeout);
1051         if (r == 0) {
1052                 r = -ETIMEDOUT;
1053                 goto err1;
1054         } else if (r < 0) {
1055                 goto err1;
1056         }
1057         tmp = le32_to_cpu(adev->wb.wb[index]);
1058         if (tmp == 0xDEADBEEF)
1059                 r = 0;
1060         else
1061                 r = -EINVAL;
1062
1063 err1:
1064         amdgpu_ib_free(adev, &ib, NULL);
1065         dma_fence_put(f);
1066 err0:
1067         amdgpu_device_wb_free(adev, index);
1068         return r;
1069 }
1070
1071
1072 /**
1073  * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART
1074  *
1075  * @ib: indirect buffer to fill with commands
1076  * @pe: addr of the page entry
1077  * @src: src addr to copy from
1078  * @count: number of page entries to update
1079  *
1080  * Update PTEs by copying them from the GART using sDMA.
1081  */
1082 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib,
1083                                   uint64_t pe, uint64_t src,
1084                                   unsigned count)
1085 {
1086         unsigned bytes = count * 8;
1087
1088         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1089                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1090         ib->ptr[ib->length_dw++] = bytes - 1;
1091         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1092         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1093         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1094         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1095         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1096
1097 }
1098
1099 /**
1100  * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually
1101  *
1102  * @ib: indirect buffer to fill with commands
1103  * @pe: addr of the page entry
1104  * @value: dst addr to write into pe
1105  * @count: number of page entries to update
1106  * @incr: increase next addr by incr bytes
1107  *
1108  * Update PTEs by writing them manually using sDMA.
1109  */
1110 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1111                                    uint64_t value, unsigned count,
1112                                    uint32_t incr)
1113 {
1114         unsigned ndw = count * 2;
1115
1116         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1117                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1118         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1119         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1120         ib->ptr[ib->length_dw++] = ndw - 1;
1121         for (; ndw > 0; ndw -= 2) {
1122                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1123                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1124                 value += incr;
1125         }
1126 }
1127
1128 /**
1129  * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA
1130  *
1131  * @ib: indirect buffer to fill with commands
1132  * @pe: addr of the page entry
1133  * @addr: dst addr to write into pe
1134  * @count: number of page entries to update
1135  * @incr: increase next addr by incr bytes
1136  * @flags: access flags
1137  *
1138  * Update the page tables using sDMA.
1139  */
1140 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1141                                      uint64_t pe,
1142                                      uint64_t addr, unsigned count,
1143                                      uint32_t incr, uint64_t flags)
1144 {
1145         /* for physically contiguous pages (vram) */
1146         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1147         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1148         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1149         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1150         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1151         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1152         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1153         ib->ptr[ib->length_dw++] = incr; /* increment size */
1154         ib->ptr[ib->length_dw++] = 0;
1155         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1156 }
1157
1158 /**
1159  * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw
1160  *
1161  * @ring: amdgpu_ring structure holding ring information
1162  * @ib: indirect buffer to fill with padding
1163  */
1164 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1165 {
1166         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1167         u32 pad_count;
1168         int i;
1169
1170         pad_count = (-ib->length_dw) & 7;
1171         for (i = 0; i < pad_count; i++)
1172                 if (sdma && sdma->burst_nop && (i == 0))
1173                         ib->ptr[ib->length_dw++] =
1174                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1175                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1176                 else
1177                         ib->ptr[ib->length_dw++] =
1178                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1179 }
1180
1181
1182 /**
1183  * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline
1184  *
1185  * @ring: amdgpu_ring pointer
1186  *
1187  * Make sure all previous operations are completed (CIK).
1188  */
1189 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1190 {
1191         uint32_t seq = ring->fence_drv.sync_seq;
1192         uint64_t addr = ring->fence_drv.gpu_addr;
1193
1194         /* wait for idle */
1195         sdma_v4_4_2_wait_reg_mem(ring, 1, 0,
1196                                addr & 0xfffffffc,
1197                                upper_32_bits(addr) & 0xffffffff,
1198                                seq, 0xffffffff, 4);
1199 }
1200
1201
1202 /**
1203  * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA
1204  *
1205  * @ring: amdgpu_ring pointer
1206  * @vmid: vmid number to use
1207  * @pd_addr: address
1208  *
1209  * Update the page table base and flush the VM TLB
1210  * using sDMA.
1211  */
1212 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1213                                          unsigned vmid, uint64_t pd_addr)
1214 {
1215         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1216 }
1217
1218 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring,
1219                                      uint32_t reg, uint32_t val)
1220 {
1221         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1222                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1223         amdgpu_ring_write(ring, reg);
1224         amdgpu_ring_write(ring, val);
1225 }
1226
1227 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1228                                          uint32_t val, uint32_t mask)
1229 {
1230         sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1231 }
1232
1233 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev)
1234 {
1235         switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1236         case IP_VERSION(4, 4, 2):
1237                 return false;
1238         default:
1239                 return false;
1240         }
1241 }
1242
1243 static int sdma_v4_4_2_early_init(void *handle)
1244 {
1245         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1246         int r;
1247
1248         r = sdma_v4_4_2_init_microcode(adev);
1249         if (r)
1250                 return r;
1251
1252         /* TODO: Page queue breaks driver reload under SRIOV */
1253         if (sdma_v4_4_2_fw_support_paging_queue(adev))
1254                 adev->sdma.has_page_queue = true;
1255
1256         sdma_v4_4_2_set_ring_funcs(adev);
1257         sdma_v4_4_2_set_buffer_funcs(adev);
1258         sdma_v4_4_2_set_vm_pte_funcs(adev);
1259         sdma_v4_4_2_set_irq_funcs(adev);
1260         sdma_v4_4_2_set_ras_funcs(adev);
1261
1262         return 0;
1263 }
1264
1265 #if 0
1266 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1267                 void *err_data,
1268                 struct amdgpu_iv_entry *entry);
1269 #endif
1270
1271 static int sdma_v4_4_2_late_init(void *handle)
1272 {
1273         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1274 #if 0
1275         struct ras_ih_if ih_info = {
1276                 .cb = sdma_v4_4_2_process_ras_data_cb,
1277         };
1278 #endif
1279         if (!amdgpu_persistent_edc_harvesting_supported(adev))
1280                 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA);
1281
1282         return 0;
1283 }
1284
1285 static int sdma_v4_4_2_sw_init(void *handle)
1286 {
1287         struct amdgpu_ring *ring;
1288         int r, i;
1289         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1290         u32 aid_id;
1291
1292         /* SDMA trap event */
1293         for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1294                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1295                                       SDMA0_4_0__SRCID__SDMA_TRAP,
1296                                       &adev->sdma.trap_irq);
1297                 if (r)
1298                         return r;
1299         }
1300
1301         /* SDMA SRAM ECC event */
1302         for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1303                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1304                                       SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1305                                       &adev->sdma.ecc_irq);
1306                 if (r)
1307                         return r;
1308         }
1309
1310         /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
1311         for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1312                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1313                                       SDMA0_4_0__SRCID__SDMA_VM_HOLE,
1314                                       &adev->sdma.vm_hole_irq);
1315                 if (r)
1316                         return r;
1317
1318                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1319                                       SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
1320                                       &adev->sdma.doorbell_invalid_irq);
1321                 if (r)
1322                         return r;
1323
1324                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1325                                       SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
1326                                       &adev->sdma.pool_timeout_irq);
1327                 if (r)
1328                         return r;
1329
1330                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1331                                       SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
1332                                       &adev->sdma.srbm_write_irq);
1333                 if (r)
1334                         return r;
1335         }
1336
1337         for (i = 0; i < adev->sdma.num_instances; i++) {
1338                 ring = &adev->sdma.instance[i].ring;
1339                 ring->ring_obj = NULL;
1340                 ring->use_doorbell = true;
1341                 aid_id = adev->sdma.instance[i].aid_id;
1342
1343                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1344                                 ring->use_doorbell?"true":"false");
1345
1346                 /* doorbell size is 2 dwords, get DWORD offset */
1347                 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1348                 ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1349
1350                 sprintf(ring->name, "sdma%d.%d", aid_id,
1351                                 i % adev->sdma.num_inst_per_aid);
1352                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1353                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1354                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1355                 if (r)
1356                         return r;
1357
1358                 if (adev->sdma.has_page_queue) {
1359                         ring = &adev->sdma.instance[i].page;
1360                         ring->ring_obj = NULL;
1361                         ring->use_doorbell = true;
1362
1363                         /* doorbell index of page queue is assigned right after
1364                          * gfx queue on the same instance
1365                          */
1366                         ring->doorbell_index =
1367                                 (adev->doorbell_index.sdma_engine[i] + 1) << 1;
1368                         ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1369
1370                         sprintf(ring->name, "page%d.%d", aid_id,
1371                                         i % adev->sdma.num_inst_per_aid);
1372                         r = amdgpu_ring_init(adev, ring, 1024,
1373                                              &adev->sdma.trap_irq,
1374                                              AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1375                                              AMDGPU_RING_PRIO_DEFAULT, NULL);
1376                         if (r)
1377                                 return r;
1378                 }
1379         }
1380
1381         if (amdgpu_sdma_ras_sw_init(adev)) {
1382                 dev_err(adev->dev, "fail to initialize sdma ras block\n");
1383                 return -EINVAL;
1384         }
1385
1386         return r;
1387 }
1388
1389 static int sdma_v4_4_2_sw_fini(void *handle)
1390 {
1391         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1392         int i;
1393
1394         for (i = 0; i < adev->sdma.num_instances; i++) {
1395                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1396                 if (adev->sdma.has_page_queue)
1397                         amdgpu_ring_fini(&adev->sdma.instance[i].page);
1398         }
1399
1400         if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2))
1401                 amdgpu_sdma_destroy_inst_ctx(adev, true);
1402         else
1403                 amdgpu_sdma_destroy_inst_ctx(adev, false);
1404
1405         return 0;
1406 }
1407
1408 static int sdma_v4_4_2_hw_init(void *handle)
1409 {
1410         int r;
1411         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1412         uint32_t inst_mask;
1413
1414         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1415         if (!amdgpu_sriov_vf(adev))
1416                 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
1417
1418         r = sdma_v4_4_2_inst_start(adev, inst_mask);
1419
1420         return r;
1421 }
1422
1423 static int sdma_v4_4_2_hw_fini(void *handle)
1424 {
1425         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1426         uint32_t inst_mask;
1427         int i;
1428
1429         if (amdgpu_sriov_vf(adev))
1430                 return 0;
1431
1432         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1433         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
1434                 for (i = 0; i < adev->sdma.num_instances; i++) {
1435                         amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1436                                        AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1437                 }
1438         }
1439
1440         sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
1441         sdma_v4_4_2_inst_enable(adev, false, inst_mask);
1442
1443         return 0;
1444 }
1445
1446 static int sdma_v4_4_2_set_clockgating_state(void *handle,
1447                                              enum amd_clockgating_state state);
1448
1449 static int sdma_v4_4_2_suspend(void *handle)
1450 {
1451         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1452
1453         if (amdgpu_in_reset(adev))
1454                 sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
1455
1456         return sdma_v4_4_2_hw_fini(adev);
1457 }
1458
1459 static int sdma_v4_4_2_resume(void *handle)
1460 {
1461         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1462
1463         return sdma_v4_4_2_hw_init(adev);
1464 }
1465
1466 static bool sdma_v4_4_2_is_idle(void *handle)
1467 {
1468         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1469         u32 i;
1470
1471         for (i = 0; i < adev->sdma.num_instances; i++) {
1472                 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG);
1473
1474                 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK))
1475                         return false;
1476         }
1477
1478         return true;
1479 }
1480
1481 static int sdma_v4_4_2_wait_for_idle(void *handle)
1482 {
1483         unsigned i, j;
1484         u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
1485         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1486
1487         for (i = 0; i < adev->usec_timeout; i++) {
1488                 for (j = 0; j < adev->sdma.num_instances; j++) {
1489                         sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG);
1490                         if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK))
1491                                 break;
1492                 }
1493                 if (j == adev->sdma.num_instances)
1494                         return 0;
1495                 udelay(1);
1496         }
1497         return -ETIMEDOUT;
1498 }
1499
1500 static int sdma_v4_4_2_soft_reset(void *handle)
1501 {
1502         /* todo */
1503
1504         return 0;
1505 }
1506
1507 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev,
1508                                         struct amdgpu_irq_src *source,
1509                                         unsigned type,
1510                                         enum amdgpu_interrupt_state state)
1511 {
1512         u32 sdma_cntl;
1513
1514         sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1515         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE,
1516                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1517         WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1518
1519         return 0;
1520 }
1521
1522 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev,
1523                                       struct amdgpu_irq_src *source,
1524                                       struct amdgpu_iv_entry *entry)
1525 {
1526         uint32_t instance, i;
1527
1528         DRM_DEBUG("IH: SDMA trap\n");
1529         instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1530
1531         /* Client id gives the SDMA instance in AID. To know the exact SDMA
1532          * instance, interrupt entry gives the node id which corresponds to the AID instance.
1533          * Match node id with the AID id associated with the SDMA instance. */
1534         for (i = instance; i < adev->sdma.num_instances;
1535              i += adev->sdma.num_inst_per_aid) {
1536                 if (adev->sdma.instance[i].aid_id ==
1537                     node_id_to_phys_map[entry->node_id])
1538                         break;
1539         }
1540
1541         if (i >= adev->sdma.num_instances) {
1542                 dev_WARN_ONCE(
1543                         adev->dev, 1,
1544                         "Couldn't find the right sdma instance in trap handler");
1545                 return 0;
1546         }
1547
1548         switch (entry->ring_id) {
1549         case 0:
1550                 amdgpu_fence_process(&adev->sdma.instance[i].ring);
1551                 break;
1552         default:
1553                 break;
1554         }
1555         return 0;
1556 }
1557
1558 #if 0
1559 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1560                 void *err_data,
1561                 struct amdgpu_iv_entry *entry)
1562 {
1563         int instance;
1564
1565         /* When “Full RAS” is enabled, the per-IP interrupt sources should
1566          * be disabled and the driver should only look for the aggregated
1567          * interrupt via sync flood
1568          */
1569         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA))
1570                 goto out;
1571
1572         instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1573         if (instance < 0)
1574                 goto out;
1575
1576         amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
1577
1578 out:
1579         return AMDGPU_RAS_SUCCESS;
1580 }
1581 #endif
1582
1583 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1584                                               struct amdgpu_irq_src *source,
1585                                               struct amdgpu_iv_entry *entry)
1586 {
1587         int instance;
1588
1589         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1590
1591         instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1592         if (instance < 0)
1593                 return 0;
1594
1595         switch (entry->ring_id) {
1596         case 0:
1597                 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
1598                 break;
1599         }
1600         return 0;
1601 }
1602
1603 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev,
1604                                         struct amdgpu_irq_src *source,
1605                                         unsigned type,
1606                                         enum amdgpu_interrupt_state state)
1607 {
1608         u32 sdma_cntl;
1609
1610         sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1611         switch (state) {
1612         case AMDGPU_IRQ_STATE_DISABLE:
1613                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL,
1614                                           DRAM_ECC_INT_ENABLE, 0);
1615                 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1616                 break;
1617         /* sdma ecc interrupt is enabled by default
1618          * driver doesn't need to do anything to
1619          * enable the interrupt */
1620         case AMDGPU_IRQ_STATE_ENABLE:
1621         default:
1622                 break;
1623         }
1624
1625         return 0;
1626 }
1627
1628 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev,
1629                                               struct amdgpu_iv_entry *entry)
1630 {
1631         int instance;
1632         struct amdgpu_task_info task_info;
1633         u64 addr;
1634
1635         instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1636         if (instance < 0 || instance >= adev->sdma.num_instances) {
1637                 dev_err(adev->dev, "sdma instance invalid %d\n", instance);
1638                 return -EINVAL;
1639         }
1640
1641         addr = (u64)entry->src_data[0] << 12;
1642         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
1643
1644         memset(&task_info, 0, sizeof(struct amdgpu_task_info));
1645         amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
1646
1647         dev_dbg_ratelimited(adev->dev,
1648                    "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
1649                    "pasid:%u, for process %s pid %d thread %s pid %d\n",
1650                    instance, addr, entry->src_id, entry->ring_id, entry->vmid,
1651                    entry->pasid, task_info.process_name, task_info.tgid,
1652                    task_info.task_name, task_info.pid);
1653         return 0;
1654 }
1655
1656 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev,
1657                                               struct amdgpu_irq_src *source,
1658                                               struct amdgpu_iv_entry *entry)
1659 {
1660         dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n");
1661         sdma_v4_4_2_print_iv_entry(adev, entry);
1662         return 0;
1663 }
1664
1665 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev,
1666                                               struct amdgpu_irq_src *source,
1667                                               struct amdgpu_iv_entry *entry)
1668 {
1669
1670         dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
1671         sdma_v4_4_2_print_iv_entry(adev, entry);
1672         return 0;
1673 }
1674
1675 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev,
1676                                               struct amdgpu_irq_src *source,
1677                                               struct amdgpu_iv_entry *entry)
1678 {
1679         dev_dbg_ratelimited(adev->dev,
1680                 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
1681         sdma_v4_4_2_print_iv_entry(adev, entry);
1682         return 0;
1683 }
1684
1685 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev,
1686                                               struct amdgpu_irq_src *source,
1687                                               struct amdgpu_iv_entry *entry)
1688 {
1689         dev_dbg_ratelimited(adev->dev,
1690                 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
1691         sdma_v4_4_2_print_iv_entry(adev, entry);
1692         return 0;
1693 }
1694
1695 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1696         struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1697 {
1698         uint32_t data, def;
1699         int i;
1700
1701         /* leave as default if it is not driver controlled */
1702         if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS))
1703                 return;
1704
1705         if (enable) {
1706                 for_each_inst(i, inst_mask) {
1707                         /* 1-not override: enable sdma mem light sleep */
1708                         def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1709                         data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1710                         if (def != data)
1711                                 WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1712                 }
1713         } else {
1714                 for_each_inst(i, inst_mask) {
1715                         /* 0-override:disable sdma mem light sleep */
1716                         def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1717                         data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1718                         if (def != data)
1719                                 WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1720                 }
1721         }
1722 }
1723
1724 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1725         struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1726 {
1727         uint32_t data, def;
1728         int i;
1729
1730         /* leave as default if it is not driver controlled */
1731         if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG))
1732                 return;
1733
1734         if (enable) {
1735                 for_each_inst(i, inst_mask) {
1736                         def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1737                         data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1738                                   SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1739                                   SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1740                                   SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1741                                   SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1742                                   SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1743                         if (def != data)
1744                                 WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1745                 }
1746         } else {
1747                 for_each_inst(i, inst_mask) {
1748                         def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1749                         data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1750                                  SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1751                                  SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1752                                  SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1753                                  SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1754                                  SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1755                         if (def != data)
1756                                 WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1757                 }
1758         }
1759 }
1760
1761 static int sdma_v4_4_2_set_clockgating_state(void *handle,
1762                                           enum amd_clockgating_state state)
1763 {
1764         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1765         uint32_t inst_mask;
1766
1767         if (amdgpu_sriov_vf(adev))
1768                 return 0;
1769
1770         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1771
1772         sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1773                 adev, state == AMD_CG_STATE_GATE, inst_mask);
1774         sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1775                 adev, state == AMD_CG_STATE_GATE, inst_mask);
1776         return 0;
1777 }
1778
1779 static int sdma_v4_4_2_set_powergating_state(void *handle,
1780                                           enum amd_powergating_state state)
1781 {
1782         return 0;
1783 }
1784
1785 static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags)
1786 {
1787         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1788         int data;
1789
1790         if (amdgpu_sriov_vf(adev))
1791                 *flags = 0;
1792
1793         /* AMD_CG_SUPPORT_SDMA_MGCG */
1794         data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL));
1795         if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK))
1796                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1797
1798         /* AMD_CG_SUPPORT_SDMA_LS */
1799         data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL));
1800         if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1801                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1802 }
1803
1804 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = {
1805         .name = "sdma_v4_4_2",
1806         .early_init = sdma_v4_4_2_early_init,
1807         .late_init = sdma_v4_4_2_late_init,
1808         .sw_init = sdma_v4_4_2_sw_init,
1809         .sw_fini = sdma_v4_4_2_sw_fini,
1810         .hw_init = sdma_v4_4_2_hw_init,
1811         .hw_fini = sdma_v4_4_2_hw_fini,
1812         .suspend = sdma_v4_4_2_suspend,
1813         .resume = sdma_v4_4_2_resume,
1814         .is_idle = sdma_v4_4_2_is_idle,
1815         .wait_for_idle = sdma_v4_4_2_wait_for_idle,
1816         .soft_reset = sdma_v4_4_2_soft_reset,
1817         .set_clockgating_state = sdma_v4_4_2_set_clockgating_state,
1818         .set_powergating_state = sdma_v4_4_2_set_powergating_state,
1819         .get_clockgating_state = sdma_v4_4_2_get_clockgating_state,
1820 };
1821
1822 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {
1823         .type = AMDGPU_RING_TYPE_SDMA,
1824         .align_mask = 0xff,
1825         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1826         .support_64bit_ptrs = true,
1827         .get_rptr = sdma_v4_4_2_ring_get_rptr,
1828         .get_wptr = sdma_v4_4_2_ring_get_wptr,
1829         .set_wptr = sdma_v4_4_2_ring_set_wptr,
1830         .emit_frame_size =
1831                 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
1832                 3 + /* hdp invalidate */
1833                 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
1834                 /* sdma_v4_4_2_ring_emit_vm_flush */
1835                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1836                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1837                 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
1838         .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
1839         .emit_ib = sdma_v4_4_2_ring_emit_ib,
1840         .emit_fence = sdma_v4_4_2_ring_emit_fence,
1841         .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
1842         .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
1843         .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
1844         .test_ring = sdma_v4_4_2_ring_test_ring,
1845         .test_ib = sdma_v4_4_2_ring_test_ib,
1846         .insert_nop = sdma_v4_4_2_ring_insert_nop,
1847         .pad_ib = sdma_v4_4_2_ring_pad_ib,
1848         .emit_wreg = sdma_v4_4_2_ring_emit_wreg,
1849         .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
1850         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1851 };
1852
1853 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {
1854         .type = AMDGPU_RING_TYPE_SDMA,
1855         .align_mask = 0xff,
1856         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1857         .support_64bit_ptrs = true,
1858         .get_rptr = sdma_v4_4_2_ring_get_rptr,
1859         .get_wptr = sdma_v4_4_2_page_ring_get_wptr,
1860         .set_wptr = sdma_v4_4_2_page_ring_set_wptr,
1861         .emit_frame_size =
1862                 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
1863                 3 + /* hdp invalidate */
1864                 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
1865                 /* sdma_v4_4_2_ring_emit_vm_flush */
1866                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1867                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1868                 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
1869         .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
1870         .emit_ib = sdma_v4_4_2_ring_emit_ib,
1871         .emit_fence = sdma_v4_4_2_ring_emit_fence,
1872         .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
1873         .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
1874         .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
1875         .test_ring = sdma_v4_4_2_ring_test_ring,
1876         .test_ib = sdma_v4_4_2_ring_test_ib,
1877         .insert_nop = sdma_v4_4_2_ring_insert_nop,
1878         .pad_ib = sdma_v4_4_2_ring_pad_ib,
1879         .emit_wreg = sdma_v4_4_2_ring_emit_wreg,
1880         .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
1881         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1882 };
1883
1884 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev)
1885 {
1886         int i, dev_inst;
1887
1888         for (i = 0; i < adev->sdma.num_instances; i++) {
1889                 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs;
1890                 adev->sdma.instance[i].ring.me = i;
1891                 if (adev->sdma.has_page_queue) {
1892                         adev->sdma.instance[i].page.funcs =
1893                                 &sdma_v4_4_2_page_ring_funcs;
1894                         adev->sdma.instance[i].page.me = i;
1895                 }
1896
1897                 dev_inst = GET_INST(SDMA0, i);
1898                 /* AID to which SDMA belongs depends on physical instance */
1899                 adev->sdma.instance[i].aid_id =
1900                         dev_inst / adev->sdma.num_inst_per_aid;
1901         }
1902 }
1903
1904 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = {
1905         .set = sdma_v4_4_2_set_trap_irq_state,
1906         .process = sdma_v4_4_2_process_trap_irq,
1907 };
1908
1909 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = {
1910         .process = sdma_v4_4_2_process_illegal_inst_irq,
1911 };
1912
1913 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = {
1914         .set = sdma_v4_4_2_set_ecc_irq_state,
1915         .process = amdgpu_sdma_process_ecc_irq,
1916 };
1917
1918 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = {
1919         .process = sdma_v4_4_2_process_vm_hole_irq,
1920 };
1921
1922 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = {
1923         .process = sdma_v4_4_2_process_doorbell_invalid_irq,
1924 };
1925
1926 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = {
1927         .process = sdma_v4_4_2_process_pool_timeout_irq,
1928 };
1929
1930 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = {
1931         .process = sdma_v4_4_2_process_srbm_write_irq,
1932 };
1933
1934 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev)
1935 {
1936         adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
1937         adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
1938         adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
1939         adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
1940         adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
1941         adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
1942
1943         adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs;
1944         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs;
1945         adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs;
1946         adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs;
1947         adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs;
1948         adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs;
1949         adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs;
1950 }
1951
1952 /**
1953  * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine
1954  *
1955  * @ib: indirect buffer to copy to
1956  * @src_offset: src GPU address
1957  * @dst_offset: dst GPU address
1958  * @byte_count: number of bytes to xfer
1959  * @tmz: if a secure copy should be used
1960  *
1961  * Copy GPU buffers using the DMA engine.
1962  * Used by the amdgpu ttm implementation to move pages if
1963  * registered as the asic copy callback.
1964  */
1965 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib,
1966                                        uint64_t src_offset,
1967                                        uint64_t dst_offset,
1968                                        uint32_t byte_count,
1969                                        bool tmz)
1970 {
1971         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1972                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1973                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1974         ib->ptr[ib->length_dw++] = byte_count - 1;
1975         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1976         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1977         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1978         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1979         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1980 }
1981
1982 /**
1983  * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine
1984  *
1985  * @ib: indirect buffer to copy to
1986  * @src_data: value to write to buffer
1987  * @dst_offset: dst GPU address
1988  * @byte_count: number of bytes to xfer
1989  *
1990  * Fill GPU buffers using the DMA engine.
1991  */
1992 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib,
1993                                        uint32_t src_data,
1994                                        uint64_t dst_offset,
1995                                        uint32_t byte_count)
1996 {
1997         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1998         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1999         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2000         ib->ptr[ib->length_dw++] = src_data;
2001         ib->ptr[ib->length_dw++] = byte_count - 1;
2002 }
2003
2004 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = {
2005         .copy_max_bytes = 0x400000,
2006         .copy_num_dw = 7,
2007         .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer,
2008
2009         .fill_max_bytes = 0x400000,
2010         .fill_num_dw = 5,
2011         .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer,
2012 };
2013
2014 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev)
2015 {
2016         adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs;
2017         if (adev->sdma.has_page_queue)
2018                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2019         else
2020                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2021 }
2022
2023 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = {
2024         .copy_pte_num_dw = 7,
2025         .copy_pte = sdma_v4_4_2_vm_copy_pte,
2026
2027         .write_pte = sdma_v4_4_2_vm_write_pte,
2028         .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde,
2029 };
2030
2031 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev)
2032 {
2033         struct drm_gpu_scheduler *sched;
2034         unsigned i;
2035
2036         adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs;
2037         for (i = 0; i < adev->sdma.num_instances; i++) {
2038                 if (adev->sdma.has_page_queue)
2039                         sched = &adev->sdma.instance[i].page.sched;
2040                 else
2041                         sched = &adev->sdma.instance[i].ring.sched;
2042                 adev->vm_manager.vm_pte_scheds[i] = sched;
2043         }
2044         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2045 }
2046
2047 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = {
2048         .type = AMD_IP_BLOCK_TYPE_SDMA,
2049         .major = 4,
2050         .minor = 4,
2051         .rev = 0,
2052         .funcs = &sdma_v4_4_2_ip_funcs,
2053 };
2054
2055 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask)
2056 {
2057         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2058         int r;
2059
2060         if (!amdgpu_sriov_vf(adev))
2061                 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
2062
2063         r = sdma_v4_4_2_inst_start(adev, inst_mask);
2064
2065         return r;
2066 }
2067
2068 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask)
2069 {
2070         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2071         uint32_t tmp_mask = inst_mask;
2072         int i;
2073
2074         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2075                 for_each_inst(i, tmp_mask) {
2076                         amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
2077                                        AMDGPU_SDMA_IRQ_INSTANCE0 + i);
2078                 }
2079         }
2080
2081         sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
2082         sdma_v4_4_2_inst_enable(adev, false, inst_mask);
2083
2084         return 0;
2085 }
2086
2087 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = {
2088         .suspend = &sdma_v4_4_2_xcp_suspend,
2089         .resume = &sdma_v4_4_2_xcp_resume
2090 };
2091
2092 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = {
2093         {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI),
2094         1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"},
2095 };
2096
2097 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = {
2098         {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"},
2099         {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"},
2100         {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"},
2101         {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"},
2102         {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"},
2103         {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"},
2104         {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"},
2105         {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"},
2106         {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"},
2107         {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"},
2108         {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"},
2109         {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"},
2110         {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"},
2111         {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"},
2112         {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"},
2113         {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"},
2114         {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"},
2115         {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"},
2116         {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"},
2117         {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"},
2118         {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"},
2119         {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"},
2120         {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"},
2121         {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"},
2122 };
2123
2124 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev,
2125                                                    uint32_t sdma_inst,
2126                                                    void *ras_err_status)
2127 {
2128         struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;
2129         uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2130         unsigned long ue_count = 0;
2131         struct amdgpu_smuio_mcm_config_info mcm_info = {
2132                 .socket_id = adev->smuio.funcs->get_socket_id(adev),
2133                 .die_id = adev->sdma.instance[sdma_inst].aid_id,
2134         };
2135
2136         /* sdma v4_4_2 doesn't support query ce counts */
2137         amdgpu_ras_inst_query_ras_error_count(adev,
2138                                         sdma_v4_2_2_ue_reg_list,
2139                                         ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2140                                         sdma_v4_4_2_ras_memory_list,
2141                                         ARRAY_SIZE(sdma_v4_4_2_ras_memory_list),
2142                                         sdma_dev_inst,
2143                                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
2144                                         &ue_count);
2145
2146         amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count);
2147 }
2148
2149 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev,
2150                                               void *ras_err_status)
2151 {
2152         uint32_t inst_mask;
2153         int i = 0;
2154
2155         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2156         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2157                 for_each_inst(i, inst_mask)
2158                         sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status);
2159         } else {
2160                 dev_warn(adev->dev, "SDMA RAS is not supported\n");
2161         }
2162 }
2163
2164 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev,
2165                                                    uint32_t sdma_inst)
2166 {
2167         uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2168
2169         amdgpu_ras_inst_reset_ras_error_count(adev,
2170                                         sdma_v4_2_2_ue_reg_list,
2171                                         ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2172                                         sdma_dev_inst);
2173 }
2174
2175 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev)
2176 {
2177         uint32_t inst_mask;
2178         int i = 0;
2179
2180         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2181         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2182                 for_each_inst(i, inst_mask)
2183                         sdma_v4_4_2_inst_reset_ras_error_count(adev, i);
2184         } else {
2185                 dev_warn(adev->dev, "SDMA RAS is not supported\n");
2186         }
2187 }
2188
2189 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = {
2190         .query_ras_error_count = sdma_v4_4_2_query_ras_error_count,
2191         .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count,
2192 };
2193
2194 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = {
2195         .ras_block = {
2196                 .hw_ops = &sdma_v4_4_2_ras_hw_ops,
2197         },
2198 };
2199
2200 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev)
2201 {
2202         adev->sdma.ras = &sdma_v4_4_2_ras;
2203 }