2 * Device Tree Source for AM33XX SoC
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pinctrl/am33xx.h>
14 #include "skeleton.dtsi"
17 compatible = "ti,am33xx";
18 interrupt-parent = <&intc>;
35 compatible = "arm,cortex-a8";
40 * To consider voltage drop between PMIC and SoC,
41 * tolerance value is reduced to 2% from 4% and
42 * voltage value is increased as a precaution.
51 voltage-tolerance = <2>; /* 2 percentage */
52 clock-latency = <300000>; /* From omap-cpufreq driver */
57 * The soc node represents the soc top level view. It is uses for IPs
58 * that are not memory mapped in the MPU view or for the MPU itself.
61 compatible = "ti,omap-infra";
63 compatible = "ti,omap3-mpu";
68 am33xx_pinmux: pinmux@44e10800 {
69 compatible = "pinctrl-single";
70 reg = <0x44e10800 0x0238>;
73 pinctrl-single,register-width = <32>;
74 pinctrl-single,function-mask = <0x7f>;
78 * XXX: Use a flat representation of the AM33XX interconnect.
79 * The real AM33XX interconnect network is quite complex.Since
80 * that will not bring real advantage to represent that in DT
81 * for the moment, just use a fake OCP bus entry to represent
82 * the whole bus hierarchy.
85 compatible = "simple-bus";
89 ti,hwmods = "l3_main";
91 intc: interrupt-controller@48200000 {
92 compatible = "ti,omap2-intc";
94 #interrupt-cells = <1>;
96 reg = <0x48200000 0x1000>;
99 gpio0: gpio@44e07000 {
100 compatible = "ti,omap4-gpio";
104 interrupt-controller;
105 #interrupt-cells = <1>;
106 reg = <0x44e07000 0x1000>;
110 gpio1: gpio@4804c000 {
111 compatible = "ti,omap4-gpio";
115 interrupt-controller;
116 #interrupt-cells = <1>;
117 reg = <0x4804c000 0x1000>;
121 gpio2: gpio@481ac000 {
122 compatible = "ti,omap4-gpio";
126 interrupt-controller;
127 #interrupt-cells = <1>;
128 reg = <0x481ac000 0x1000>;
132 gpio3: gpio@481ae000 {
133 compatible = "ti,omap4-gpio";
137 interrupt-controller;
138 #interrupt-cells = <1>;
139 reg = <0x481ae000 0x1000>;
143 uart0: serial@44e09000 {
144 compatible = "ti,omap3-uart";
146 clock-frequency = <48000000>;
147 reg = <0x44e09000 0x2000>;
152 uart1: serial@48022000 {
153 compatible = "ti,omap3-uart";
155 clock-frequency = <48000000>;
156 reg = <0x48022000 0x2000>;
161 uart2: serial@48024000 {
162 compatible = "ti,omap3-uart";
164 clock-frequency = <48000000>;
165 reg = <0x48024000 0x2000>;
170 uart3: serial@481a6000 {
171 compatible = "ti,omap3-uart";
173 clock-frequency = <48000000>;
174 reg = <0x481a6000 0x2000>;
179 uart4: serial@481a8000 {
180 compatible = "ti,omap3-uart";
182 clock-frequency = <48000000>;
183 reg = <0x481a8000 0x2000>;
188 uart5: serial@481aa000 {
189 compatible = "ti,omap3-uart";
191 clock-frequency = <48000000>;
192 reg = <0x481aa000 0x2000>;
198 compatible = "ti,omap4-i2c";
199 #address-cells = <1>;
202 reg = <0x44e0b000 0x1000>;
208 compatible = "ti,omap4-i2c";
209 #address-cells = <1>;
212 reg = <0x4802a000 0x1000>;
218 compatible = "ti,omap4-i2c";
219 #address-cells = <1>;
222 reg = <0x4819c000 0x1000>;
228 compatible = "ti,omap3-wdt";
229 ti,hwmods = "wd_timer2";
230 reg = <0x44e35000 0x1000>;
234 dcan0: d_can@481cc000 {
235 compatible = "bosch,d_can";
236 ti,hwmods = "d_can0";
237 reg = <0x481cc000 0x2000
243 dcan1: d_can@481d0000 {
244 compatible = "bosch,d_can";
245 ti,hwmods = "d_can1";
246 reg = <0x481d0000 0x2000
252 timer1: timer@44e31000 {
253 compatible = "ti,am335x-timer-1ms";
254 reg = <0x44e31000 0x400>;
256 ti,hwmods = "timer1";
260 timer2: timer@48040000 {
261 compatible = "ti,am335x-timer";
262 reg = <0x48040000 0x400>;
264 ti,hwmods = "timer2";
267 timer3: timer@48042000 {
268 compatible = "ti,am335x-timer";
269 reg = <0x48042000 0x400>;
271 ti,hwmods = "timer3";
274 timer4: timer@48044000 {
275 compatible = "ti,am335x-timer";
276 reg = <0x48044000 0x400>;
278 ti,hwmods = "timer4";
282 timer5: timer@48046000 {
283 compatible = "ti,am335x-timer";
284 reg = <0x48046000 0x400>;
286 ti,hwmods = "timer5";
290 timer6: timer@48048000 {
291 compatible = "ti,am335x-timer";
292 reg = <0x48048000 0x400>;
294 ti,hwmods = "timer6";
298 timer7: timer@4804a000 {
299 compatible = "ti,am335x-timer";
300 reg = <0x4804a000 0x400>;
302 ti,hwmods = "timer7";
307 compatible = "ti,da830-rtc";
308 reg = <0x44e3e000 0x1000>;
315 compatible = "ti,omap4-mcspi";
316 #address-cells = <1>;
318 reg = <0x48030000 0x400>;
326 compatible = "ti,omap4-mcspi";
327 #address-cells = <1>;
329 reg = <0x481a0000 0x400>;
337 compatible = "ti,musb-am33xx";
338 reg = <0x47400000 0x1000 /* usbss */
339 0x47401000 0x800 /* musb instance 0 */
340 0x47401800 0x800>; /* musb instance 1 */
341 interrupts = <17 /* usbss */
342 18 /* musb instance 0 */
343 19>; /* musb instance 1 */
350 ti,hwmods = "usb_otg_hs";
353 epwmss0: epwmss@48300000 {
354 compatible = "ti,am33xx-pwmss";
355 reg = <0x48300000 0x10>;
356 ti,hwmods = "epwmss0";
357 #address-cells = <1>;
360 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
361 0x48300180 0x48300180 0x80 /* EQEP */
362 0x48300200 0x48300200 0x80>; /* EHRPWM */
364 ecap0: ecap@48300100 {
365 compatible = "ti,am33xx-ecap";
367 reg = <0x48300100 0x80>;
372 ehrpwm0: ehrpwm@48300200 {
373 compatible = "ti,am33xx-ehrpwm";
375 reg = <0x48300200 0x80>;
376 ti,hwmods = "ehrpwm0";
381 epwmss1: epwmss@48302000 {
382 compatible = "ti,am33xx-pwmss";
383 reg = <0x48302000 0x10>;
384 ti,hwmods = "epwmss1";
385 #address-cells = <1>;
388 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
389 0x48302180 0x48302180 0x80 /* EQEP */
390 0x48302200 0x48302200 0x80>; /* EHRPWM */
392 ecap1: ecap@48302100 {
393 compatible = "ti,am33xx-ecap";
395 reg = <0x48302100 0x80>;
400 ehrpwm1: ehrpwm@48302200 {
401 compatible = "ti,am33xx-ehrpwm";
403 reg = <0x48302200 0x80>;
404 ti,hwmods = "ehrpwm1";
409 epwmss2: epwmss@48304000 {
410 compatible = "ti,am33xx-pwmss";
411 reg = <0x48304000 0x10>;
412 ti,hwmods = "epwmss2";
413 #address-cells = <1>;
416 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
417 0x48304180 0x48304180 0x80 /* EQEP */
418 0x48304200 0x48304200 0x80>; /* EHRPWM */
420 ecap2: ecap@48304100 {
421 compatible = "ti,am33xx-ecap";
423 reg = <0x48304100 0x80>;
428 ehrpwm2: ehrpwm@48304200 {
429 compatible = "ti,am33xx-ehrpwm";
431 reg = <0x48304200 0x80>;
432 ti,hwmods = "ehrpwm2";
437 mac: ethernet@4a100000 {
438 compatible = "ti,cpsw";
439 ti,hwmods = "cpgmac0";
440 cpdma_channels = <8>;
441 ale_entries = <1024>;
442 bd_ram_size = <0x2000>;
445 mac_control = <0x20>;
448 cpts_clock_mult = <0x80000000>;
449 cpts_clock_shift = <29>;
450 reg = <0x4a100000 0x800
452 #address-cells = <1>;
454 interrupt-parent = <&intc>;
461 interrupts = <40 41 42 43>;
464 davinci_mdio: mdio@4a101000 {
465 compatible = "ti,davinci_mdio";
466 #address-cells = <1>;
468 ti,hwmods = "davinci_mdio";
469 bus_freq = <1000000>;
470 reg = <0x4a101000 0x100>;
473 cpsw_emac0: slave@4a100200 {
474 /* Filled in by U-Boot */
475 mac-address = [ 00 00 00 00 00 00 ];
478 cpsw_emac1: slave@4a100300 {
479 /* Filled in by U-Boot */
480 mac-address = [ 00 00 00 00 00 00 ];
484 ocmcram: ocmcram@40300000 {
485 compatible = "ti,am3352-ocmcram";
486 reg = <0x40300000 0x10000>;
487 ti,hwmods = "ocmcram";
490 wkup_m3: wkup_m3@44d00000 {
491 compatible = "ti,am3353-wkup-m3";
492 reg = <0x44d00000 0x4000 /* M3 UMEM */
493 0x44d80000 0x2000>; /* M3 DMEM */
494 ti,hwmods = "wkup_m3";
498 compatible = "ti,am3352-elm";
499 reg = <0x48080000 0x2000>;
505 gpmc: gpmc@50000000 {
506 compatible = "ti,am3352-gpmc";
508 reg = <0x50000000 0x2000>;
511 gpmc,num-waitpins = <2>;
512 #address-cells = <2>;