1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi SoCs pinctrl driver
6 * License: Dual MIT/GPL
7 * Copyright (c) 2017 Microsemi Corporation
10 #include <linux/gpio/driver.h>
11 #include <linux/interrupt.h>
13 #include <linux/of_device.h>
14 #include <linux/of_platform.h>
15 #include <linux/pinctrl/pinctrl.h>
16 #include <linux/pinctrl/pinmux.h>
17 #include <linux/pinctrl/pinconf.h>
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
21 #include <linux/slab.h>
27 #define OCELOT_GPIO_OUT_SET 0x0
28 #define OCELOT_GPIO_OUT_CLR 0x4
29 #define OCELOT_GPIO_OUT 0x8
30 #define OCELOT_GPIO_IN 0xc
31 #define OCELOT_GPIO_OE 0x10
32 #define OCELOT_GPIO_INTR 0x14
33 #define OCELOT_GPIO_INTR_ENA 0x18
34 #define OCELOT_GPIO_INTR_IDENT 0x1c
35 #define OCELOT_GPIO_ALT0 0x20
36 #define OCELOT_GPIO_ALT1 0x24
37 #define OCELOT_GPIO_SD_MAP 0x28
39 #define OCELOT_PINS 22
40 #define OCELOT_FUNC_PER_PIN 4
74 static const char *const ocelot_function_names[] = {
77 [FUNC_IRQ0_IN] = "irq0_in",
78 [FUNC_IRQ0_OUT] = "irq0_out",
79 [FUNC_IRQ1_IN] = "irq1_in",
80 [FUNC_IRQ1_OUT] = "irq1_out",
81 [FUNC_MIIM1] = "miim1",
82 [FUNC_PCI_WAKE] = "pci_wake",
88 [FUNC_RECO_CLK0] = "reco_clk0",
89 [FUNC_RECO_CLK1] = "reco_clk1",
98 [FUNC_TACHO] = "tacho",
100 [FUNC_TWI_SCL_M] = "twi_scl_m",
101 [FUNC_UART] = "uart",
102 [FUNC_UART2] = "uart2",
105 struct ocelot_pmx_func {
107 unsigned int ngroups;
110 struct ocelot_pin_caps {
112 unsigned char functions[OCELOT_FUNC_PER_PIN];
115 struct ocelot_pinctrl {
117 struct pinctrl_dev *pctl;
118 struct gpio_chip gpio_chip;
120 struct ocelot_pmx_func func[FUNC_MAX];
123 #define OCELOT_P(p, f0, f1, f2) \
124 static struct ocelot_pin_caps ocelot_pin_##p = { \
127 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
131 OCELOT_P(0, SG0, NONE, NONE);
132 OCELOT_P(1, SG0, NONE, NONE);
133 OCELOT_P(2, SG0, NONE, NONE);
134 OCELOT_P(3, SG0, NONE, NONE);
135 OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI);
136 OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
137 OCELOT_P(6, UART, TWI_SCL_M, NONE);
138 OCELOT_P(7, UART, TWI_SCL_M, NONE);
139 OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT);
140 OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT);
141 OCELOT_P(10, PTP2, TWI_SCL_M, SFP0);
142 OCELOT_P(11, PTP3, TWI_SCL_M, SFP1);
143 OCELOT_P(12, UART2, TWI_SCL_M, SFP2);
144 OCELOT_P(13, UART2, TWI_SCL_M, SFP3);
145 OCELOT_P(14, MIIM1, TWI_SCL_M, SFP4);
146 OCELOT_P(15, MIIM1, TWI_SCL_M, SFP5);
147 OCELOT_P(16, TWI, NONE, SI);
148 OCELOT_P(17, TWI, TWI_SCL_M, SI);
149 OCELOT_P(18, PTP0, TWI_SCL_M, NONE);
150 OCELOT_P(19, PTP1, TWI_SCL_M, NONE);
151 OCELOT_P(20, RECO_CLK0, TACHO, NONE);
152 OCELOT_P(21, RECO_CLK1, PWM, NONE);
154 #define OCELOT_PIN(n) { \
157 .drv_data = &ocelot_pin_##n \
160 static const struct pinctrl_pin_desc ocelot_pins[] = {
185 static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
187 return ARRAY_SIZE(ocelot_function_names);
190 static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev,
191 unsigned int function)
193 return ocelot_function_names[function];
196 static int ocelot_get_function_groups(struct pinctrl_dev *pctldev,
197 unsigned int function,
198 const char *const **groups,
199 unsigned *const num_groups)
201 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
203 *groups = info->func[function].groups;
204 *num_groups = info->func[function].ngroups;
209 static int ocelot_pin_function_idx(unsigned int pin, unsigned int function)
211 struct ocelot_pin_caps *p = ocelot_pins[pin].drv_data;
214 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
215 if (function == p->functions[i])
222 static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
223 unsigned int selector, unsigned int group)
225 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
226 struct ocelot_pin_caps *pin = ocelot_pins[group].drv_data;
229 f = ocelot_pin_function_idx(group, selector);
234 * f is encoded on two bits.
235 * bit 0 of f goes in BIT(pin) of ALT0, bit 1 of f goes in BIT(pin) of
237 * This is racy because both registers can't be updated at the same time
238 * but it doesn't matter much for now.
240 regmap_update_bits(info->map, OCELOT_GPIO_ALT0, BIT(pin->pin),
242 regmap_update_bits(info->map, OCELOT_GPIO_ALT1, BIT(pin->pin),
243 f << (pin->pin - 1));
248 static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
249 struct pinctrl_gpio_range *range,
250 unsigned int pin, bool input)
252 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
254 regmap_update_bits(info->map, OCELOT_GPIO_OE, BIT(pin),
255 input ? BIT(pin) : 0);
260 static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
261 struct pinctrl_gpio_range *range,
264 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
266 regmap_update_bits(info->map, OCELOT_GPIO_ALT0, BIT(offset), 0);
267 regmap_update_bits(info->map, OCELOT_GPIO_ALT1, BIT(offset), 0);
272 static const struct pinmux_ops ocelot_pmx_ops = {
273 .get_functions_count = ocelot_get_functions_count,
274 .get_function_name = ocelot_get_function_name,
275 .get_function_groups = ocelot_get_function_groups,
276 .set_mux = ocelot_pinmux_set_mux,
277 .gpio_set_direction = ocelot_gpio_set_direction,
278 .gpio_request_enable = ocelot_gpio_request_enable,
281 static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
283 return ARRAY_SIZE(ocelot_pins);
286 static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,
289 return ocelot_pins[group].name;
292 static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
294 const unsigned int **pins,
295 unsigned int *num_pins)
297 *pins = &ocelot_pins[group].number;
303 static const struct pinctrl_ops ocelot_pctl_ops = {
304 .get_groups_count = ocelot_pctl_get_groups_count,
305 .get_group_name = ocelot_pctl_get_group_name,
306 .get_group_pins = ocelot_pctl_get_group_pins,
307 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
308 .dt_free_map = pinconf_generic_dt_free_map,
311 static struct pinctrl_desc ocelot_desc = {
312 .name = "ocelot-pinctrl",
314 .npins = ARRAY_SIZE(ocelot_pins),
315 .pctlops = &ocelot_pctl_ops,
316 .pmxops = &ocelot_pmx_ops,
317 .owner = THIS_MODULE,
320 static int ocelot_create_group_func_map(struct device *dev,
321 struct ocelot_pinctrl *info)
323 u16 pins[ARRAY_SIZE(ocelot_pins)];
326 for (f = 0; f < FUNC_MAX; f++) {
327 for (npins = 0, i = 0; i < ARRAY_SIZE(ocelot_pins); i++) {
328 if (ocelot_pin_function_idx(i, f) >= 0)
332 info->func[f].ngroups = npins;
333 info->func[f].groups = devm_kzalloc(dev, npins *
336 if (!info->func[f].groups)
339 for (i = 0; i < npins; i++)
340 info->func[f].groups[i] = ocelot_pins[pins[i]].name;
346 static int ocelot_pinctrl_register(struct platform_device *pdev,
347 struct ocelot_pinctrl *info)
351 ret = ocelot_create_group_func_map(&pdev->dev, info);
353 dev_err(&pdev->dev, "Unable to create group func map.\n");
357 info->pctl = devm_pinctrl_register(&pdev->dev, &ocelot_desc, info);
358 if (IS_ERR(info->pctl)) {
359 dev_err(&pdev->dev, "Failed to register pinctrl\n");
360 return PTR_ERR(info->pctl);
366 static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)
368 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
371 regmap_read(info->map, OCELOT_GPIO_IN, &val);
373 return !!(val & BIT(offset));
376 static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
379 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
382 regmap_write(info->map, OCELOT_GPIO_OUT_SET, BIT(offset));
384 regmap_write(info->map, OCELOT_GPIO_OUT_CLR, BIT(offset));
387 static int ocelot_gpio_get_direction(struct gpio_chip *chip,
390 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
393 regmap_read(info->map, OCELOT_GPIO_OE, &val);
395 return !(val & BIT(offset));
398 static int ocelot_gpio_direction_input(struct gpio_chip *chip,
401 return pinctrl_gpio_direction_input(chip->base + offset);
404 static int ocelot_gpio_direction_output(struct gpio_chip *chip,
405 unsigned int offset, int value)
407 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
408 unsigned int pin = BIT(offset);
411 regmap_write(info->map, OCELOT_GPIO_OUT_SET, pin);
413 regmap_write(info->map, OCELOT_GPIO_OUT_CLR, pin);
415 return pinctrl_gpio_direction_output(chip->base + offset);
418 static const struct gpio_chip ocelot_gpiolib_chip = {
419 .request = gpiochip_generic_request,
420 .free = gpiochip_generic_free,
421 .set = ocelot_gpio_set,
422 .get = ocelot_gpio_get,
423 .get_direction = ocelot_gpio_get_direction,
424 .direction_input = ocelot_gpio_direction_input,
425 .direction_output = ocelot_gpio_direction_output,
426 .owner = THIS_MODULE,
429 static int ocelot_gpiochip_register(struct platform_device *pdev,
430 struct ocelot_pinctrl *info)
432 struct gpio_chip *gc;
435 info->gpio_chip = ocelot_gpiolib_chip;
437 gc = &info->gpio_chip;
438 gc->ngpio = OCELOT_PINS;
439 gc->parent = &pdev->dev;
441 gc->of_node = info->dev->of_node;
442 gc->label = "ocelot-gpio";
444 ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
448 /* TODO: this can be used as an irqchip but no board is using that */
453 static const struct regmap_config ocelot_pinctrl_regmap_config = {
457 .max_register = 0x64,
460 static const struct of_device_id ocelot_pinctrl_of_match[] = {
461 { .compatible = "mscc,ocelot-pinctrl" },
465 int ocelot_pinctrl_probe(struct platform_device *pdev)
467 struct device *dev = &pdev->dev;
468 struct ocelot_pinctrl *info;
472 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
476 base = devm_ioremap_resource(dev,
477 platform_get_resource(pdev, IORESOURCE_MEM, 0));
479 dev_err(dev, "Failed to ioremap registers\n");
480 return PTR_ERR(base);
483 info->map = devm_regmap_init_mmio(dev, base,
484 &ocelot_pinctrl_regmap_config);
485 if (IS_ERR(info->map)) {
486 dev_err(dev, "Failed to create regmap\n");
487 return PTR_ERR(info->map);
489 dev_set_drvdata(dev, info->map);
492 ret = ocelot_pinctrl_register(pdev, info);
496 ret = ocelot_gpiochip_register(pdev, info);
503 static struct platform_driver ocelot_pinctrl_driver = {
505 .name = "pinctrl-ocelot",
506 .of_match_table = of_match_ptr(ocelot_pinctrl_of_match),
507 .suppress_bind_attrs = true,
509 .probe = ocelot_pinctrl_probe,
511 builtin_platform_driver(ocelot_pinctrl_driver);