drivers/i2c/busses/i2c-sh_mobile.c

   1 /*
   2  * SuperH Mobile I2C Controller
   3  *
   4  * Copyright (C) 2014 Wolfram Sang <[email protected]>
   5  *
   6  * Copyright (C) 2008 Magnus Damm
   7  *
   8  * Portions of the code based on out-of-tree driver i2c-sh7343.c
   9  * Copyright (c) 2006 Carlos Munoz <[email protected]>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/delay.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/err.h>
  26 #include <linux/i2c.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/io.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/of_device.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/slab.h>
  36
  37 /* Transmit operation:                                                      */
  38 /*                                                                          */
  39 /* 0 byte transmit                                                          */
  40 /* BUS:     S     A8     ACK   P(*)                                         */
  41 /* IRQ:       DTE   WAIT                                                    */
  42 /* ICIC:                                                                    */
  43 /* ICCR: 0x94       0x90                                                    */
  44 /* ICDR:      A8                                                            */
  45 /*                                                                          */
  46 /* 1 byte transmit                                                          */
  47 /* BUS:     S     A8     ACK   D8(1)   ACK   P(*)                           */
  48 /* IRQ:       DTE   WAIT         WAIT                                       */
  49 /* ICIC:      -DTE                                                          */
  50 /* ICCR: 0x94                    0x90                                       */
  51 /* ICDR:      A8    D8(1)                                                   */
  52 /*                                                                          */
  53 /* 2 byte transmit                                                          */
  54 /* BUS:     S     A8     ACK   D8(1)   ACK   D8(2)   ACK   P(*)             */
  55 /* IRQ:       DTE   WAIT         WAIT          WAIT                         */
  56 /* ICIC:      -DTE                                                          */
  57 /* ICCR: 0x94                                  0x90                         */
  58 /* ICDR:      A8    D8(1)        D8(2)                                      */
  59 /*                                                                          */
  60 /* 3 bytes or more, +---------+ gets repeated                               */
  61 /*                                                                          */
  62 /*                                                                          */
  63 /* Receive operation:                                                       */
  64 /*                                                                          */
  65 /* 0 byte receive - not supported since slave may hold SDA low              */
  66 /*                                                                          */
  67 /* 1 byte receive       [TX] | [RX]                                         */
  68 /* BUS:     S     A8     ACK | D8(1)   ACK   P(*)                           */
  69 /* IRQ:       DTE   WAIT     |   WAIT     DTE                               */
  70 /* ICIC:      -DTE           |   +DTE                                       */
  71 /* ICCR: 0x94       0x81     |   0xc0                                       */
  72 /* ICDR:      A8             |            D8(1)                             */
  73 /*                                                                          */
  74 /* 2 byte receive        [TX]| [RX]                                         */
  75 /* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   P(*)             */
  76 /* IRQ:       DTE   WAIT     |   WAIT          WAIT     DTE                 */
  77 /* ICIC:      -DTE           |                 +DTE                         */
  78 /* ICCR: 0x94       0x81     |                 0xc0                         */
  79 /* ICDR:      A8             |                 D8(1)    D8(2)               */
  80 /*                                                                          */
  81 /* 3 byte receive       [TX] | [RX]                                     (*) */
  82 /* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   D8(3)   ACK    P */
  83 /* IRQ:       DTE   WAIT     |   WAIT          WAIT         WAIT      DTE   */
  84 /* ICIC:      -DTE           |                              +DTE            */
  85 /* ICCR: 0x94       0x81     |                              0xc0            */
  86 /* ICDR:      A8             |                 D8(1)        D8(2)     D8(3) */
  87 /*                                                                          */
  88 /* 4 bytes or more, this part is repeated    +---------+                    */
  89 /*                                                                          */
  90 /*                                                                          */
  91 /* Interrupt order and BUSY flag                                            */
  92 /*     ___                                                 _                */
  93 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/                 */
  94 /* SCL      \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/                   */
  95 /*                                                                          */
  96 /*        S   D7  D6  D5  D4  D3  D2  D1  D0              P(*)              */
  97 /*                                           ___                            */
  98 /* WAIT IRQ ________________________________/   \___________                */
  99 /* TACK IRQ ____________________________________/   \_______                */
 100 /* DTE  IRQ __________________________________________/   \_                */
 101 /* AL   IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX                */
 102 /*         _______________________________________________                  */
 103 /* BUSY __/                                               \_                */
 104 /*                                                                          */
 105 /* (*) The STOP condition is only sent by the master at the end of the last */
 106 /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
 107 /* only cleared after the STOP condition, so, between messages we have to   */
 108 /* poll for the DTE bit.                                                    */
 109 /*                                                                          */
 110
 111 enum sh_mobile_i2c_op {
 112         OP_START = 0,
 113         OP_TX_FIRST,
 114         OP_TX,
 115         OP_TX_STOP,
 116         OP_TX_TO_RX,
 117         OP_RX,
 118         OP_RX_STOP,
 119         OP_RX_STOP_DATA,
 120 };
 121
 122 struct sh_mobile_i2c_data {
 123         struct device *dev;
 124         void __iomem *reg;
 125         struct i2c_adapter adap;
 126         unsigned long bus_speed;
 127         unsigned int clks_per_count;
 128         struct clk *clk;
 129         u_int8_t icic;
 130         u_int8_t flags;
 131         u_int16_t iccl;
 132         u_int16_t icch;
 133
 134         spinlock_t lock;
 135         wait_queue_head_t wait;
 136         struct i2c_msg *msg;
 137         int pos;
 138         int sr;
 139         bool send_stop;
 140         bool stop_after_dma;
 141
 142         struct resource *res;
 143         struct dma_chan *dma_tx;
 144         struct dma_chan *dma_rx;
 145         struct scatterlist sg;
 146         enum dma_data_direction dma_direction;
 147         u8 *dma_buf;
 148 };
 149
 150 struct sh_mobile_dt_config {
 151         int clks_per_count;
 152         int (*setup)(struct sh_mobile_i2c_data *pd);
 153 };
 154
 155 #define IIC_FLAG_HAS_ICIC67     (1 << 0)
 156
 157 #define STANDARD_MODE           100000
 158 #define FAST_MODE               400000
 159
 160 /* Register offsets */
 161 #define ICDR                    0x00
 162 #define ICCR                    0x04
 163 #define ICSR                    0x08
 164 #define ICIC                    0x0c
 165 #define ICCL                    0x10
 166 #define ICCH                    0x14
 167 #define ICSTART                 0x70
 168
 169 /* Register bits */
 170 #define ICCR_ICE                0x80
 171 #define ICCR_RACK               0x40
 172 #define ICCR_TRS                0x10
 173 #define ICCR_BBSY               0x04
 174 #define ICCR_SCP                0x01
 175
 176 #define ICSR_SCLM               0x80
 177 #define ICSR_SDAM               0x40
 178 #define SW_DONE                 0x20
 179 #define ICSR_BUSY               0x10
 180 #define ICSR_AL                 0x08
 181 #define ICSR_TACK               0x04
 182 #define ICSR_WAIT               0x02
 183 #define ICSR_DTE                0x01
 184
 185 #define ICIC_ICCLB8             0x80
 186 #define ICIC_ICCHB8             0x40
 187 #define ICIC_TDMAE              0x20
 188 #define ICIC_RDMAE              0x10
 189 #define ICIC_ALE                0x08
 190 #define ICIC_TACKE              0x04
 191 #define ICIC_WAITE              0x02
 192 #define ICIC_DTEE               0x01
 193
 194 #define ICSTART_ICSTART         0x10
 195
 196 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
 197 {
 198         if (offs == ICIC)
 199                 data |= pd->icic;
 200
 201         iowrite8(data, pd->reg + offs);
 202 }
 203
 204 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
 205 {
 206         return ioread8(pd->reg + offs);
 207 }
 208
 209 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
 210                         unsigned char set, unsigned char clr)
 211 {
 212         iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
 213 }
 214
 215 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf)
 216 {
 217         /*
 218          * Conditional expression:
 219          *   ICCL >= COUNT_CLK * (tLOW + tf)
 220          *
 221          * SH-Mobile IIC hardware starts counting the LOW period of
 222          * the SCL signal (tLOW) as soon as it pulls the SCL line.
 223          * In order to meet the tLOW timing spec, we need to take into
 224          * account the fall time of SCL signal (tf).  Default tf value
 225          * should be 0.3 us, for safety.
 226          */
 227         return (((count_khz * (tLOW + tf)) + 5000) / 10000);
 228 }
 229
 230 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
 231 {
 232         /*
 233          * Conditional expression:
 234          *   ICCH >= COUNT_CLK * (tHIGH + tf)
 235          *
 236          * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
 237          * and can ignore it.  SH-Mobile IIC controller starts counting
 238          * the HIGH period of the SCL signal (tHIGH) after the SCL input
 239          * voltage increases at VIH.
 240          *
 241          * Afterward it turned out calculating ICCH using only tHIGH spec
 242          * will result in violation of the tHD;STA timing spec.  We need
 243          * to take into account the fall time of SDA signal (tf) at START
 244          * condition, in order to meet both tHIGH and tHD;STA specs.
 245          */
 246         return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
 247 }
 248
 249 static int sh_mobile_i2c_check_timing(struct sh_mobile_i2c_data *pd)
 250 {
 251         u16 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
 252
 253         if (pd->iccl > max_val || pd->icch > max_val) {
 254                 dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
 255                         pd->iccl, pd->icch);
 256                 return -EINVAL;
 257         }
 258
 259         /* one more bit of ICCL in ICIC */
 260         if (pd->iccl & 0x100)
 261                 pd->icic |= ICIC_ICCLB8;
 262         else
 263                 pd->icic &= ~ICIC_ICCLB8;
 264
 265         /* one more bit of ICCH in ICIC */
 266         if (pd->icch & 0x100)
 267                 pd->icic |= ICIC_ICCHB8;
 268         else
 269                 pd->icic &= ~ICIC_ICCHB8;
 270
 271         dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
 272         return 0;
 273 }
 274
 275 static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
 276 {
 277         unsigned long i2c_clk_khz;
 278         u32 tHIGH, tLOW, tf;
 279
 280         i2c_clk_khz = clk_get_rate(pd->clk) / 1000 / pd->clks_per_count;
 281
 282         if (pd->bus_speed == STANDARD_MODE) {
 283                 tLOW    = 47;   /* tLOW = 4.7 us */
 284                 tHIGH   = 40;   /* tHD;STA = tHIGH = 4.0 us */
 285                 tf      = 3;    /* tf = 0.3 us */
 286         } else if (pd->bus_speed == FAST_MODE) {
 287                 tLOW    = 13;   /* tLOW = 1.3 us */
 288                 tHIGH   = 6;    /* tHD;STA = tHIGH = 0.6 us */
 289                 tf      = 3;    /* tf = 0.3 us */
 290         } else {
 291                 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
 292                         pd->bus_speed);
 293                 return -EINVAL;
 294         }
 295
 296         pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
 297         pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
 298
 299         return sh_mobile_i2c_check_timing(pd);
 300 }
 301
 302 static int sh_mobile_i2c_v2_init(struct sh_mobile_i2c_data *pd)
 303 {
 304         unsigned long clks_per_cycle;
 305
 306         /* L = 5, H = 4, L + H = 9 */
 307         clks_per_cycle = clk_get_rate(pd->clk) / pd->bus_speed;
 308         pd->iccl = DIV_ROUND_UP(clks_per_cycle * 5 / 9 - 1, pd->clks_per_count);
 309         pd->icch = DIV_ROUND_UP(clks_per_cycle * 4 / 9 - 5, pd->clks_per_count);
 310
 311         return sh_mobile_i2c_check_timing(pd);
 312 }
 313
 314 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
 315                             enum sh_mobile_i2c_op op, unsigned char data)
 316 {
 317         unsigned char ret = 0;
 318         unsigned long flags;
 319
 320         dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
 321
 322         spin_lock_irqsave(&pd->lock, flags);
 323
 324         switch (op) {
 325         case OP_START: /* issue start and trigger DTE interrupt */
 326                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
 327                 break;
 328         case OP_TX_FIRST: /* disable DTE interrupt and write data */
 329                 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 330                 iic_wr(pd, ICDR, data);
 331                 break;
 332         case OP_TX: /* write data */
 333                 iic_wr(pd, ICDR, data);
 334                 break;
 335         case OP_TX_STOP: /* issue a stop (or rep_start) */
 336                 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
 337                                                : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
 338                 break;
 339         case OP_TX_TO_RX: /* select read mode */
 340                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
 341                 break;
 342         case OP_RX: /* just read data */
 343                 ret = iic_rd(pd, ICDR);
 344                 break;
 345         case OP_RX_STOP: /* enable DTE interrupt, issue stop */
 346                 iic_wr(pd, ICIC,
 347                        ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 348                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
 349                 break;
 350         case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
 351                 iic_wr(pd, ICIC,
 352                        ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 353                 ret = iic_rd(pd, ICDR);
 354                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
 355                 break;
 356         }
 357
 358         spin_unlock_irqrestore(&pd->lock, flags);
 359
 360         dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
 361         return ret;
 362 }
 363
 364 static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
 365 {
 366         return pd->pos == -1;
 367 }
 368
 369 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
 370                                    unsigned char *buf)
 371 {
 372         switch (pd->pos) {
 373         case -1:
 374                 *buf = i2c_8bit_addr_from_msg(pd->msg);
 375                 break;
 376         default:
 377                 *buf = pd->msg->buf[pd->pos];
 378         }
 379 }
 380
 381 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
 382 {
 383         unsigned char data;
 384
 385         if (pd->pos == pd->msg->len) {
 386                 i2c_op(pd, OP_TX_STOP, 0);
 387                 return 1;
 388         }
 389
 390         sh_mobile_i2c_get_data(pd, &data);
 391         i2c_op(pd, sh_mobile_i2c_is_first_byte(pd) ? OP_TX_FIRST : OP_TX, data);
 392
 393         pd->pos++;
 394         return 0;
 395 }
 396
 397 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
 398 {
 399         unsigned char data;
 400         int real_pos;
 401
 402         do {
 403                 if (pd->pos <= -1) {
 404                         sh_mobile_i2c_get_data(pd, &data);
 405
 406                         if (sh_mobile_i2c_is_first_byte(pd))
 407                                 i2c_op(pd, OP_TX_FIRST, data);
 408                         else
 409                                 i2c_op(pd, OP_TX, data);
 410                         break;
 411                 }
 412
 413                 if (pd->pos == 0) {
 414                         i2c_op(pd, OP_TX_TO_RX, 0);
 415                         break;
 416                 }
 417
 418                 real_pos = pd->pos - 2;
 419
 420                 if (pd->pos == pd->msg->len) {
 421                         if (pd->stop_after_dma) {
 422                                 /* Simulate PIO end condition after DMA transfer */
 423                                 i2c_op(pd, OP_RX_STOP, 0);
 424                                 pd->pos++;
 425                                 break;
 426                         }
 427
 428                         if (real_pos < 0) {
 429                                 i2c_op(pd, OP_RX_STOP, 0);
 430                                 break;
 431                         }
 432                         data = i2c_op(pd, OP_RX_STOP_DATA, 0);
 433                 } else if (real_pos >= 0) {
 434                         data = i2c_op(pd, OP_RX, 0);
 435                 }
 436
 437                 if (real_pos >= 0)
 438                         pd->msg->buf[real_pos] = data;
 439         } while (0);
 440
 441         pd->pos++;
 442         return pd->pos == (pd->msg->len + 2);
 443 }
 444
 445 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
 446 {
 447         struct sh_mobile_i2c_data *pd = dev_id;
 448         unsigned char sr;
 449         int wakeup = 0;
 450
 451         sr = iic_rd(pd, ICSR);
 452         pd->sr |= sr; /* remember state */
 453
 454         dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
 455                (pd->msg->flags & I2C_M_RD) ? "read" : "write",
 456                pd->pos, pd->msg->len);
 457
 458         /* Kick off TxDMA after preface was done */
 459         if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0)
 460                 iic_set_clr(pd, ICIC, ICIC_TDMAE, 0);
 461         else if (sr & (ICSR_AL | ICSR_TACK))
 462                 /* don't interrupt transaction - continue to issue stop */
 463                 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
 464         else if (pd->msg->flags & I2C_M_RD)
 465                 wakeup = sh_mobile_i2c_isr_rx(pd);
 466         else
 467                 wakeup = sh_mobile_i2c_isr_tx(pd);
 468
 469         /* Kick off RxDMA after preface was done */
 470         if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1)
 471                 iic_set_clr(pd, ICIC, ICIC_RDMAE, 0);
 472
 473         if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
 474                 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
 475
 476         if (wakeup) {
 477                 pd->sr |= SW_DONE;
 478                 wake_up(&pd->wait);
 479         }
 480
 481         /* defeat write posting to avoid spurious WAIT interrupts */
 482         iic_rd(pd, ICSR);
 483
 484         return IRQ_HANDLED;
 485 }
 486
 487 static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd)
 488 {
 489         struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE
 490                                 ? pd->dma_rx : pd->dma_tx;
 491
 492         dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg),
 493                          pd->msg->len, pd->dma_direction);
 494
 495         pd->dma_direction = DMA_NONE;
 496 }
 497
 498 static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd)
 499 {
 500         if (pd->dma_direction == DMA_NONE)
 501                 return;
 502         else if (pd->dma_direction == DMA_FROM_DEVICE)
 503                 dmaengine_terminate_all(pd->dma_rx);
 504         else if (pd->dma_direction == DMA_TO_DEVICE)
 505                 dmaengine_terminate_all(pd->dma_tx);
 506
 507         sh_mobile_i2c_dma_unmap(pd);
 508 }
 509
 510 static void sh_mobile_i2c_dma_callback(void *data)
 511 {
 512         struct sh_mobile_i2c_data *pd = data;
 513
 514         sh_mobile_i2c_dma_unmap(pd);
 515         pd->pos = pd->msg->len;
 516         pd->stop_after_dma = true;
 517
 518         i2c_release_dma_safe_msg_buf(pd->msg, pd->dma_buf);
 519
 520         iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
 521 }
 522
 523 static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev,
 524                                 enum dma_transfer_direction dir, dma_addr_t port_addr)
 525 {
 526         struct dma_chan *chan;
 527         struct dma_slave_config cfg;
 528         char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
 529         int ret;
 530
 531         chan = dma_request_slave_channel_reason(dev, chan_name);
 532         if (IS_ERR(chan)) {
 533                 dev_dbg(dev, "request_channel failed for %s (%ld)\n", chan_name,
 534                         PTR_ERR(chan));
 535                 return chan;
 536         }
 537
 538         memset(&cfg, 0, sizeof(cfg));
 539         cfg.direction = dir;
 540         if (dir == DMA_MEM_TO_DEV) {
 541                 cfg.dst_addr = port_addr;
 542                 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 543         } else {
 544                 cfg.src_addr = port_addr;
 545                 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 546         }
 547
 548         ret = dmaengine_slave_config(chan, &cfg);
 549         if (ret) {
 550                 dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
 551                 dma_release_channel(chan);
 552                 return ERR_PTR(ret);
 553         }
 554
 555         dev_dbg(dev, "got DMA channel for %s\n", chan_name);
 556         return chan;
 557 }
 558
 559 static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
 560 {
 561         bool read = pd->msg->flags & I2C_M_RD;
 562         enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 563         struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx;
 564         struct dma_async_tx_descriptor *txdesc;
 565         dma_addr_t dma_addr;
 566         dma_cookie_t cookie;
 567
 568         if (PTR_ERR(chan) == -EPROBE_DEFER) {
 569                 if (read)
 570                         chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
 571                                                                            pd->res->start + ICDR);
 572                 else
 573                         chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
 574                                                                            pd->res->start + ICDR);
 575         }
 576
 577         if (IS_ERR(chan))
 578                 return;
 579
 580         dma_addr = dma_map_single(chan->device->dev, pd->dma_buf, pd->msg->len, dir);
 581         if (dma_mapping_error(chan->device->dev, dma_addr)) {
 582                 dev_dbg(pd->dev, "dma map failed, using PIO\n");
 583                 return;
 584         }
 585
 586         sg_dma_len(&pd->sg) = pd->msg->len;
 587         sg_dma_address(&pd->sg) = dma_addr;
 588
 589         pd->dma_direction = dir;
 590
 591         txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1,
 592                                          read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
 593                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 594         if (!txdesc) {
 595                 dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n");
 596                 sh_mobile_i2c_cleanup_dma(pd);
 597                 return;
 598         }
 599
 600         txdesc->callback = sh_mobile_i2c_dma_callback;
 601         txdesc->callback_param = pd;
 602
 603         cookie = dmaengine_submit(txdesc);
 604         if (dma_submit_error(cookie)) {
 605                 dev_dbg(pd->dev, "submitting dma failed, using PIO\n");
 606                 sh_mobile_i2c_cleanup_dma(pd);
 607                 return;
 608         }
 609
 610         dma_async_issue_pending(chan);
 611 }
 612
 613 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
 614                     bool do_init)
 615 {
 616         if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
 617                 dev_err(pd->dev, "Unsupported zero length i2c read\n");
 618                 return -EOPNOTSUPP;
 619         }
 620
 621         if (do_init) {
 622                 /* Initialize channel registers */
 623                 iic_wr(pd, ICCR, ICCR_SCP);
 624
 625                 /* Enable channel and configure rx ack */
 626                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
 627
 628                 /* Set the clock */
 629                 iic_wr(pd, ICCL, pd->iccl & 0xff);
 630                 iic_wr(pd, ICCH, pd->icch & 0xff);
 631         }
 632
 633         pd->msg = usr_msg;
 634         pd->pos = -1;
 635         pd->sr = 0;
 636
 637         pd->dma_buf = i2c_get_dma_safe_msg_buf(pd->msg, 8);
 638         if (pd->dma_buf)
 639                 sh_mobile_i2c_xfer_dma(pd);
 640
 641         /* Enable all interrupts to begin with */
 642         iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 643         return 0;
 644 }
 645
 646 static int poll_dte(struct sh_mobile_i2c_data *pd)
 647 {
 648         int i;
 649
 650         for (i = 1000; i; i--) {
 651                 u_int8_t val = iic_rd(pd, ICSR);
 652
 653                 if (val & ICSR_DTE)
 654                         break;
 655
 656                 if (val & ICSR_TACK)
 657                         return -ENXIO;
 658
 659                 udelay(10);
 660         }
 661
 662         return i ? 0 : -ETIMEDOUT;
 663 }
 664
 665 static int poll_busy(struct sh_mobile_i2c_data *pd)
 666 {
 667         int i;
 668
 669         for (i = 1000; i; i--) {
 670                 u_int8_t val = iic_rd(pd, ICSR);
 671
 672                 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
 673
 674                 /* the interrupt handler may wake us up before the
 675                  * transfer is finished, so poll the hardware
 676                  * until we're done.
 677                  */
 678                 if (!(val & ICSR_BUSY)) {
 679                         /* handle missing acknowledge and arbitration lost */
 680                         val |= pd->sr;
 681                         if (val & ICSR_TACK)
 682                                 return -ENXIO;
 683                         if (val & ICSR_AL)
 684                                 return -EAGAIN;
 685                         break;
 686                 }
 687
 688                 udelay(10);
 689         }
 690
 691         return i ? 0 : -ETIMEDOUT;
 692 }
 693
 694 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
 695                               struct i2c_msg *msgs,
 696                               int num)
 697 {
 698         struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
 699         struct i2c_msg  *msg;
 700         int err = 0;
 701         int i;
 702         long timeout;
 703
 704         /* Wake up device and enable clock */
 705         pm_runtime_get_sync(pd->dev);
 706
 707         /* Process all messages */
 708         for (i = 0; i < num; i++) {
 709                 bool do_start = pd->send_stop || !i;
 710                 msg = &msgs[i];
 711                 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
 712                 pd->stop_after_dma = false;
 713
 714                 err = start_ch(pd, msg, do_start);
 715                 if (err)
 716                         break;
 717
 718                 if (do_start)
 719                         i2c_op(pd, OP_START, 0);
 720
 721                 /* The interrupt handler takes care of the rest... */
 722                 timeout = wait_event_timeout(pd->wait,
 723                                        pd->sr & (ICSR_TACK | SW_DONE),
 724                                        adapter->timeout);
 725                 if (!timeout) {
 726                         dev_err(pd->dev, "Transfer request timed out\n");
 727                         if (pd->dma_direction != DMA_NONE)
 728                                 sh_mobile_i2c_cleanup_dma(pd);
 729
 730                         err = -ETIMEDOUT;
 731                         break;
 732                 }
 733
 734                 if (pd->send_stop)
 735                         err = poll_busy(pd);
 736                 else
 737                         err = poll_dte(pd);
 738                 if (err < 0)
 739                         break;
 740         }
 741
 742         /* Disable channel */
 743         iic_wr(pd, ICCR, ICCR_SCP);
 744
 745         /* Disable clock and mark device as idle */
 746         pm_runtime_put_sync(pd->dev);
 747
 748         return err ?: num;
 749 }
 750
 751 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
 752 {
 753         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 754 }
 755
 756 static const struct i2c_algorithm sh_mobile_i2c_algorithm = {
 757         .functionality  = sh_mobile_i2c_func,
 758         .master_xfer    = sh_mobile_i2c_xfer,
 759 };
 760
 761 /*
 762  * r8a7740 chip has lasting errata on I2C I/O pad reset.
 763  * this is work-around for it.
 764  */
 765 static int sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd)
 766 {
 767         iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 768         iic_rd(pd, ICCR); /* dummy read */
 769
 770         iic_set_clr(pd, ICSTART, ICSTART_ICSTART, 0);
 771         iic_rd(pd, ICSTART); /* dummy read */
 772
 773         udelay(10);
 774
 775         iic_wr(pd, ICCR, ICCR_SCP);
 776         iic_wr(pd, ICSTART, 0);
 777
 778         udelay(10);
 779
 780         iic_wr(pd, ICCR, ICCR_TRS);
 781         udelay(10);
 782         iic_wr(pd, ICCR, 0);
 783         udelay(10);
 784         iic_wr(pd, ICCR, ICCR_TRS);
 785         udelay(10);
 786
 787         return sh_mobile_i2c_init(pd);
 788 }
 789
 790 static const struct sh_mobile_dt_config default_dt_config = {
 791         .clks_per_count = 1,
 792         .setup = sh_mobile_i2c_init,
 793 };
 794
 795 static const struct sh_mobile_dt_config fast_clock_dt_config = {
 796         .clks_per_count = 2,
 797         .setup = sh_mobile_i2c_init,
 798 };
 799
 800 static const struct sh_mobile_dt_config v2_freq_calc_dt_config = {
 801         .clks_per_count = 2,
 802         .setup = sh_mobile_i2c_v2_init,
 803 };
 804
 805 static const struct sh_mobile_dt_config r8a7740_dt_config = {
 806         .clks_per_count = 1,
 807         .setup = sh_mobile_i2c_r8a7740_workaround,
 808 };
 809
 810 static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
 811         { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
 812         { .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config },
 813         { .compatible = "renesas,iic-r8a7790", .data = &v2_freq_calc_dt_config },
 814         { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
 815         { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
 816         { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config },
 817         { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config },
 818         { .compatible = "renesas,rcar-gen2-iic", .data = &fast_clock_dt_config },
 819         { .compatible = "renesas,iic-r8a7795", .data = &fast_clock_dt_config },
 820         { .compatible = "renesas,rcar-gen3-iic", .data = &fast_clock_dt_config },
 821         { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
 822         { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
 823         {},
 824 };
 825 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
 826
 827 static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd)
 828 {
 829         if (!IS_ERR(pd->dma_tx)) {
 830                 dma_release_channel(pd->dma_tx);
 831                 pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
 832         }
 833
 834         if (!IS_ERR(pd->dma_rx)) {
 835                 dma_release_channel(pd->dma_rx);
 836                 pd->dma_rx = ERR_PTR(-EPROBE_DEFER);
 837         }
 838 }
 839
 840 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd)
 841 {
 842         struct resource *res;
 843         resource_size_t n;
 844         int k = 0, ret;
 845
 846         while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
 847                 for (n = res->start; n <= res->end; n++) {
 848                         ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
 849                                           0, dev_name(&dev->dev), pd);
 850                         if (ret) {
 851                                 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
 852                                 return ret;
 853                         }
 854                 }
 855                 k++;
 856         }
 857
 858         return k > 0 ? 0 : -ENOENT;
 859 }
 860
 861 static int sh_mobile_i2c_probe(struct platform_device *dev)
 862 {
 863         struct sh_mobile_i2c_data *pd;
 864         struct i2c_adapter *adap;
 865         struct resource *res;
 866         const struct sh_mobile_dt_config *config;
 867         int ret;
 868         u32 bus_speed;
 869
 870         pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
 871         if (!pd)
 872                 return -ENOMEM;
 873
 874         pd->clk = devm_clk_get(&dev->dev, NULL);
 875         if (IS_ERR(pd->clk)) {
 876                 dev_err(&dev->dev, "cannot get clock\n");
 877                 return PTR_ERR(pd->clk);
 878         }
 879
 880         ret = sh_mobile_i2c_hook_irqs(dev, pd);
 881         if (ret)
 882                 return ret;
 883
 884         pd->dev = &dev->dev;
 885         platform_set_drvdata(dev, pd);
 886
 887         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 888
 889         pd->res = res;
 890         pd->reg = devm_ioremap_resource(&dev->dev, res);
 891         if (IS_ERR(pd->reg))
 892                 return PTR_ERR(pd->reg);
 893
 894         ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
 895         pd->bus_speed = (ret || !bus_speed) ? STANDARD_MODE : bus_speed;
 896         pd->clks_per_count = 1;
 897
 898         /* Newer variants come with two new bits in ICIC */
 899         if (resource_size(res) > 0x17)
 900                 pd->flags |= IIC_FLAG_HAS_ICIC67;
 901
 902         /* Enable Runtime PM for this device.
 903          *
 904          * Also tell the Runtime PM core to ignore children
 905          * for this device since it is valid for us to suspend
 906          * this I2C master driver even though the slave devices
 907          * on the I2C bus may not be suspended.
 908          *
 909          * The state of the I2C hardware bus is unaffected by
 910          * the Runtime PM state.
 911          */
 912         pm_suspend_ignore_children(&dev->dev, true);
 913         pm_runtime_enable(&dev->dev);
 914         pm_runtime_get_sync(&dev->dev);
 915
 916         config = of_device_get_match_data(&dev->dev);
 917         if (config) {
 918                 pd->clks_per_count = config->clks_per_count;
 919                 ret = config->setup(pd);
 920         } else {
 921                 ret = sh_mobile_i2c_init(pd);
 922         }
 923
 924         pm_runtime_put_sync(&dev->dev);
 925         if (ret)
 926                 return ret;
 927
 928         /* Init DMA */
 929         sg_init_table(&pd->sg, 1);
 930         pd->dma_direction = DMA_NONE;
 931         pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
 932
 933         /* setup the private data */
 934         adap = &pd->adap;
 935         i2c_set_adapdata(adap, pd);
 936
 937         adap->owner = THIS_MODULE;
 938         adap->algo = &sh_mobile_i2c_algorithm;
 939         adap->dev.parent = &dev->dev;
 940         adap->retries = 5;
 941         adap->nr = dev->id;
 942         adap->dev.of_node = dev->dev.of_node;
 943
 944         strlcpy(adap->name, dev->name, sizeof(adap->name));
 945
 946         spin_lock_init(&pd->lock);
 947         init_waitqueue_head(&pd->wait);
 948
 949         ret = i2c_add_numbered_adapter(adap);
 950         if (ret < 0) {
 951                 sh_mobile_i2c_release_dma(pd);
 952                 return ret;
 953         }
 954
 955         dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed);
 956
 957         return 0;
 958 }
 959
 960 static int sh_mobile_i2c_remove(struct platform_device *dev)
 961 {
 962         struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
 963
 964         i2c_del_adapter(&pd->adap);
 965         sh_mobile_i2c_release_dma(pd);
 966         pm_runtime_disable(&dev->dev);
 967         return 0;
 968 }
 969
 970 static int sh_mobile_i2c_runtime_nop(struct device *dev)
 971 {
 972         /* Runtime PM callback shared between ->runtime_suspend()
 973          * and ->runtime_resume(). Simply returns success.
 974          *
 975          * This driver re-initializes all registers after
 976          * pm_runtime_get_sync() anyway so there is no need
 977          * to save and restore registers here.
 978          */
 979         return 0;
 980 }
 981
 982 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
 983         .runtime_suspend = sh_mobile_i2c_runtime_nop,
 984         .runtime_resume = sh_mobile_i2c_runtime_nop,
 985 };
 986
 987 static struct platform_driver sh_mobile_i2c_driver = {
 988         .driver         = {
 989                 .name           = "i2c-sh_mobile",
 990                 .pm             = &sh_mobile_i2c_dev_pm_ops,
 991                 .of_match_table = sh_mobile_i2c_dt_ids,
 992         },
 993         .probe          = sh_mobile_i2c_probe,
 994         .remove         = sh_mobile_i2c_remove,
 995 };
 996
 997 static int __init sh_mobile_i2c_adap_init(void)
 998 {
 999         return platform_driver_register(&sh_mobile_i2c_driver);
1000 }
1001 subsys_initcall(sh_mobile_i2c_adap_init);
1002
1003 static void __exit sh_mobile_i2c_adap_exit(void)
1004 {
1005         platform_driver_unregister(&sh_mobile_i2c_driver);
1006 }
1007 module_exit(sh_mobile_i2c_adap_exit);
1008
1009 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
1010 MODULE_AUTHOR("Magnus Damm and Wolfram Sang");
1011 MODULE_LICENSE("GPL v2");
1012 MODULE_ALIAS("platform:i2c-sh_mobile");