drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27
  28 #include <linux/file.h>
  29 #include <linux/pagemap.h>
  30 #include <linux/sync_file.h>
  31 #include <linux/dma-buf.h>
  32
  33 #include <drm/amdgpu_drm.h>
  34 #include <drm/drm_syncobj.h>
  35 #include <drm/ttm/ttm_tt.h>
  36
  37 #include "amdgpu_cs.h"
  38 #include "amdgpu.h"
  39 #include "amdgpu_trace.h"
  40 #include "amdgpu_gmc.h"
  41 #include "amdgpu_gem.h"
  42 #include "amdgpu_ras.h"
  43
  44 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p,
  45                                  struct amdgpu_device *adev,
  46                                  struct drm_file *filp,
  47                                  union drm_amdgpu_cs *cs)
  48 {
  49         struct amdgpu_fpriv *fpriv = filp->driver_priv;
  50
  51         if (cs->in.num_chunks == 0)
  52                 return -EINVAL;
  53
  54         memset(p, 0, sizeof(*p));
  55         p->adev = adev;
  56         p->filp = filp;
  57
  58         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
  59         if (!p->ctx)
  60                 return -EINVAL;
  61
  62         if (atomic_read(&p->ctx->guilty)) {
  63                 amdgpu_ctx_put(p->ctx);
  64                 return -ECANCELED;
  65         }
  66         return 0;
  67 }
  68
  69 static int amdgpu_cs_job_idx(struct amdgpu_cs_parser *p,
  70                              struct drm_amdgpu_cs_chunk_ib *chunk_ib)
  71 {
  72         struct drm_sched_entity *entity;
  73         unsigned int i;
  74         int r;
  75
  76         r = amdgpu_ctx_get_entity(p->ctx, chunk_ib->ip_type,
  77                                   chunk_ib->ip_instance,
  78                                   chunk_ib->ring, &entity);
  79         if (r)
  80                 return r;
  81
  82         /*
  83          * Abort if there is no run queue associated with this entity.
  84          * Possibly because of disabled HW IP.
  85          */
  86         if (entity->rq == NULL)
  87                 return -EINVAL;
  88
  89         /* Check if we can add this IB to some existing job */
  90         for (i = 0; i < p->gang_size; ++i)
  91                 if (p->entities[i] == entity)
  92                         return i;
  93
  94         /* If not increase the gang size if possible */
  95         if (i == AMDGPU_CS_GANG_SIZE)
  96                 return -EINVAL;
  97
  98         p->entities[i] = entity;
  99         p->gang_size = i + 1;
 100         return i;
 101 }
 102
 103 static int amdgpu_cs_p1_ib(struct amdgpu_cs_parser *p,
 104                            struct drm_amdgpu_cs_chunk_ib *chunk_ib,
 105                            unsigned int *num_ibs)
 106 {
 107         int r;
 108
 109         r = amdgpu_cs_job_idx(p, chunk_ib);
 110         if (r < 0)
 111                 return r;
 112
 113         ++(num_ibs[r]);
 114         p->gang_leader_idx = r;
 115         return 0;
 116 }
 117
 118 static int amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser *p,
 119                                    struct drm_amdgpu_cs_chunk_fence *data,
 120                                    uint32_t *offset)
 121 {
 122         struct drm_gem_object *gobj;
 123         struct amdgpu_bo *bo;
 124         unsigned long size;
 125         int r;
 126
 127         gobj = drm_gem_object_lookup(p->filp, data->handle);
 128         if (gobj == NULL)
 129                 return -EINVAL;
 130
 131         bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
 132         p->uf_entry.priority = 0;
 133         p->uf_entry.tv.bo = &bo->tbo;
 134         /* One for TTM and two for the CS job */
 135         p->uf_entry.tv.num_shared = 3;
 136
 137         drm_gem_object_put(gobj);
 138
 139         size = amdgpu_bo_size(bo);
 140         if (size != PAGE_SIZE || (data->offset + 8) > size) {
 141                 r = -EINVAL;
 142                 goto error_unref;
 143         }
 144
 145         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
 146                 r = -EINVAL;
 147                 goto error_unref;
 148         }
 149
 150         *offset = data->offset;
 151
 152         return 0;
 153
 154 error_unref:
 155         amdgpu_bo_unref(&bo);
 156         return r;
 157 }
 158
 159 static int amdgpu_cs_p1_bo_handles(struct amdgpu_cs_parser *p,
 160                                    struct drm_amdgpu_bo_list_in *data)
 161 {
 162         struct drm_amdgpu_bo_list_entry *info;
 163         int r;
 164
 165         r = amdgpu_bo_create_list_entry_array(data, &info);
 166         if (r)
 167                 return r;
 168
 169         r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
 170                                   &p->bo_list);
 171         if (r)
 172                 goto error_free;
 173
 174         kvfree(info);
 175         return 0;
 176
 177 error_free:
 178         kvfree(info);
 179
 180         return r;
 181 }
 182
 183 /* Copy the data from userspace and go over it the first time */
 184 static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,
 185                            union drm_amdgpu_cs *cs)
 186 {
 187         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 188         unsigned int num_ibs[AMDGPU_CS_GANG_SIZE] = { };
 189         struct amdgpu_vm *vm = &fpriv->vm;
 190         uint64_t *chunk_array_user;
 191         uint64_t *chunk_array;
 192         uint32_t uf_offset = 0;
 193         unsigned int size;
 194         int ret;
 195         int i;
 196
 197         chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t),
 198                                      GFP_KERNEL);
 199         if (!chunk_array)
 200                 return -ENOMEM;
 201
 202         /* get chunks */
 203         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
 204         if (copy_from_user(chunk_array, chunk_array_user,
 205                            sizeof(uint64_t)*cs->in.num_chunks)) {
 206                 ret = -EFAULT;
 207                 goto free_chunk;
 208         }
 209
 210         p->nchunks = cs->in.num_chunks;
 211         p->chunks = kvmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 212                             GFP_KERNEL);
 213         if (!p->chunks) {
 214                 ret = -ENOMEM;
 215                 goto free_chunk;
 216         }
 217
 218         for (i = 0; i < p->nchunks; i++) {
 219                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 220                 struct drm_amdgpu_cs_chunk user_chunk;
 221                 uint32_t __user *cdata;
 222
 223                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 224                 if (copy_from_user(&user_chunk, chunk_ptr,
 225                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 226                         ret = -EFAULT;
 227                         i--;
 228                         goto free_partial_kdata;
 229                 }
 230                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 231                 p->chunks[i].length_dw = user_chunk.length_dw;
 232
 233                 size = p->chunks[i].length_dw;
 234                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 235
 236                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t),
 237                                                     GFP_KERNEL);
 238                 if (p->chunks[i].kdata == NULL) {
 239                         ret = -ENOMEM;
 240                         i--;
 241                         goto free_partial_kdata;
 242                 }
 243                 size *= sizeof(uint32_t);
 244                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 245                         ret = -EFAULT;
 246                         goto free_partial_kdata;
 247                 }
 248
 249                 /* Assume the worst on the following checks */
 250                 ret = -EINVAL;
 251                 switch (p->chunks[i].chunk_id) {
 252                 case AMDGPU_CHUNK_ID_IB:
 253                         if (size < sizeof(struct drm_amdgpu_cs_chunk_ib))
 254                                 goto free_partial_kdata;
 255
 256                         ret = amdgpu_cs_p1_ib(p, p->chunks[i].kdata, num_ibs);
 257                         if (ret)
 258                                 goto free_partial_kdata;
 259                         break;
 260
 261                 case AMDGPU_CHUNK_ID_FENCE:
 262                         if (size < sizeof(struct drm_amdgpu_cs_chunk_fence))
 263                                 goto free_partial_kdata;
 264
 265                         ret = amdgpu_cs_p1_user_fence(p, p->chunks[i].kdata,
 266                                                       &uf_offset);
 267                         if (ret)
 268                                 goto free_partial_kdata;
 269                         break;
 270
 271                 case AMDGPU_CHUNK_ID_BO_HANDLES:
 272                         if (size < sizeof(struct drm_amdgpu_bo_list_in))
 273                                 goto free_partial_kdata;
 274
 275                         ret = amdgpu_cs_p1_bo_handles(p, p->chunks[i].kdata);
 276                         if (ret)
 277                                 goto free_partial_kdata;
 278                         break;
 279
 280                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 281                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 282                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 283                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
 284                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
 285                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
 286                         break;
 287
 288                 default:
 289                         goto free_partial_kdata;
 290                 }
 291         }
 292
 293         if (!p->gang_size) {
 294                 ret = -EINVAL;
 295                 goto free_partial_kdata;
 296         }
 297
 298         for (i = 0; i < p->gang_size; ++i) {
 299                 ret = amdgpu_job_alloc(p->adev, vm, p->entities[i], vm,
 300                                        num_ibs[i], &p->jobs[i]);
 301                 if (ret)
 302                         goto free_all_kdata;
 303         }
 304         p->gang_leader = p->jobs[p->gang_leader_idx];
 305
 306         if (p->ctx->vram_lost_counter != p->gang_leader->vram_lost_counter) {
 307                 ret = -ECANCELED;
 308                 goto free_all_kdata;
 309         }
 310
 311         if (p->uf_entry.tv.bo)
 312                 p->gang_leader->uf_addr = uf_offset;
 313         kvfree(chunk_array);
 314
 315         /* Use this opportunity to fill in task info for the vm */
 316         amdgpu_vm_set_task_info(vm);
 317
 318         return 0;
 319
 320 free_all_kdata:
 321         i = p->nchunks - 1;
 322 free_partial_kdata:
 323         for (; i >= 0; i--)
 324                 kvfree(p->chunks[i].kdata);
 325         kvfree(p->chunks);
 326         p->chunks = NULL;
 327         p->nchunks = 0;
 328 free_chunk:
 329         kvfree(chunk_array);
 330
 331         return ret;
 332 }
 333
 334 static int amdgpu_cs_p2_ib(struct amdgpu_cs_parser *p,
 335                            struct amdgpu_cs_chunk *chunk,
 336                            unsigned int *ce_preempt,
 337                            unsigned int *de_preempt)
 338 {
 339         struct drm_amdgpu_cs_chunk_ib *chunk_ib = chunk->kdata;
 340         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 341         struct amdgpu_vm *vm = &fpriv->vm;
 342         struct amdgpu_ring *ring;
 343         struct amdgpu_job *job;
 344         struct amdgpu_ib *ib;
 345         int r;
 346
 347         r = amdgpu_cs_job_idx(p, chunk_ib);
 348         if (r < 0)
 349                 return r;
 350
 351         job = p->jobs[r];
 352         ring = amdgpu_job_ring(job);
 353         ib = &job->ibs[job->num_ibs++];
 354
 355         /* MM engine doesn't support user fences */
 356         if (p->uf_entry.tv.bo && ring->funcs->no_user_fence)
 357                 return -EINVAL;
 358
 359         if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
 360             chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 361                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 362                         (*ce_preempt)++;
 363                 else
 364                         (*de_preempt)++;
 365
 366                 /* Each GFX command submit allows only 1 IB max
 367                  * preemptible for CE & DE */
 368                 if (*ce_preempt > 1 || *de_preempt > 1)
 369                         return -EINVAL;
 370         }
 371
 372         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
 373                 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
 374
 375         r =  amdgpu_ib_get(p->adev, vm, ring->funcs->parse_cs ?
 376                            chunk_ib->ib_bytes : 0,
 377                            AMDGPU_IB_POOL_DELAYED, ib);
 378         if (r) {
 379                 DRM_ERROR("Failed to get ib !\n");
 380                 return r;
 381         }
 382
 383         ib->gpu_addr = chunk_ib->va_start;
 384         ib->length_dw = chunk_ib->ib_bytes / 4;
 385         ib->flags = chunk_ib->flags;
 386         return 0;
 387 }
 388
 389 static int amdgpu_cs_p2_dependencies(struct amdgpu_cs_parser *p,
 390                                      struct amdgpu_cs_chunk *chunk)
 391 {
 392         struct drm_amdgpu_cs_chunk_dep *deps = chunk->kdata;
 393         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 394         unsigned num_deps;
 395         int i, r;
 396
 397         num_deps = chunk->length_dw * 4 /
 398                 sizeof(struct drm_amdgpu_cs_chunk_dep);
 399
 400         for (i = 0; i < num_deps; ++i) {
 401                 struct amdgpu_ctx *ctx;
 402                 struct drm_sched_entity *entity;
 403                 struct dma_fence *fence;
 404
 405                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
 406                 if (ctx == NULL)
 407                         return -EINVAL;
 408
 409                 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
 410                                           deps[i].ip_instance,
 411                                           deps[i].ring, &entity);
 412                 if (r) {
 413                         amdgpu_ctx_put(ctx);
 414                         return r;
 415                 }
 416
 417                 fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
 418                 amdgpu_ctx_put(ctx);
 419
 420                 if (IS_ERR(fence))
 421                         return PTR_ERR(fence);
 422                 else if (!fence)
 423                         continue;
 424
 425                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
 426                         struct drm_sched_fence *s_fence;
 427                         struct dma_fence *old = fence;
 428
 429                         s_fence = to_drm_sched_fence(fence);
 430                         fence = dma_fence_get(&s_fence->scheduled);
 431                         dma_fence_put(old);
 432                 }
 433
 434                 r = amdgpu_sync_fence(&p->sync, fence);
 435                 dma_fence_put(fence);
 436                 if (r)
 437                         return r;
 438         }
 439         return 0;
 440 }
 441
 442 static int amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser *p,
 443                                          uint32_t handle, u64 point,
 444                                          u64 flags)
 445 {
 446         struct dma_fence *fence;
 447         int r;
 448
 449         r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
 450         if (r) {
 451                 DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
 452                           handle, point, r);
 453                 return r;
 454         }
 455
 456         r = amdgpu_sync_fence(&p->sync, fence);
 457         if (r)
 458                 goto error;
 459
 460         /*
 461          * When we have an explicit dependency it might be necessary to insert a
 462          * pipeline sync to make sure that all caches etc are flushed and the
 463          * next job actually sees the results from the previous one.
 464          */
 465         if (fence->context == p->gang_leader->base.entity->fence_context)
 466                 r = amdgpu_sync_fence(&p->gang_leader->explicit_sync, fence);
 467
 468 error:
 469         dma_fence_put(fence);
 470         return r;
 471 }
 472
 473 static int amdgpu_cs_p2_syncobj_in(struct amdgpu_cs_parser *p,
 474                                    struct amdgpu_cs_chunk *chunk)
 475 {
 476         struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata;
 477         unsigned num_deps;
 478         int i, r;
 479
 480         num_deps = chunk->length_dw * 4 /
 481                 sizeof(struct drm_amdgpu_cs_chunk_sem);
 482         for (i = 0; i < num_deps; ++i) {
 483                 r = amdgpu_syncobj_lookup_and_add(p, deps[i].handle, 0, 0);
 484                 if (r)
 485                         return r;
 486         }
 487
 488         return 0;
 489 }
 490
 491 static int amdgpu_cs_p2_syncobj_timeline_wait(struct amdgpu_cs_parser *p,
 492                                               struct amdgpu_cs_chunk *chunk)
 493 {
 494         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata;
 495         unsigned num_deps;
 496         int i, r;
 497
 498         num_deps = chunk->length_dw * 4 /
 499                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
 500         for (i = 0; i < num_deps; ++i) {
 501                 r = amdgpu_syncobj_lookup_and_add(p, syncobj_deps[i].handle,
 502                                                   syncobj_deps[i].point,
 503                                                   syncobj_deps[i].flags);
 504                 if (r)
 505                         return r;
 506         }
 507
 508         return 0;
 509 }
 510
 511 static int amdgpu_cs_p2_syncobj_out(struct amdgpu_cs_parser *p,
 512                                     struct amdgpu_cs_chunk *chunk)
 513 {
 514         struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata;
 515         unsigned num_deps;
 516         int i;
 517
 518         num_deps = chunk->length_dw * 4 /
 519                 sizeof(struct drm_amdgpu_cs_chunk_sem);
 520
 521         if (p->post_deps)
 522                 return -EINVAL;
 523
 524         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
 525                                      GFP_KERNEL);
 526         p->num_post_deps = 0;
 527
 528         if (!p->post_deps)
 529                 return -ENOMEM;
 530
 531
 532         for (i = 0; i < num_deps; ++i) {
 533                 p->post_deps[i].syncobj =
 534                         drm_syncobj_find(p->filp, deps[i].handle);
 535                 if (!p->post_deps[i].syncobj)
 536                         return -EINVAL;
 537                 p->post_deps[i].chain = NULL;
 538                 p->post_deps[i].point = 0;
 539                 p->num_post_deps++;
 540         }
 541
 542         return 0;
 543 }
 544
 545 static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p,
 546                                                 struct amdgpu_cs_chunk *chunk)
 547 {
 548         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata;
 549         unsigned num_deps;
 550         int i;
 551
 552         num_deps = chunk->length_dw * 4 /
 553                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
 554
 555         if (p->post_deps)
 556                 return -EINVAL;
 557
 558         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
 559                                      GFP_KERNEL);
 560         p->num_post_deps = 0;
 561
 562         if (!p->post_deps)
 563                 return -ENOMEM;
 564
 565         for (i = 0; i < num_deps; ++i) {
 566                 struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
 567
 568                 dep->chain = NULL;
 569                 if (syncobj_deps[i].point) {
 570                         dep->chain = dma_fence_chain_alloc();
 571                         if (!dep->chain)
 572                                 return -ENOMEM;
 573                 }
 574
 575                 dep->syncobj = drm_syncobj_find(p->filp,
 576                                                 syncobj_deps[i].handle);
 577                 if (!dep->syncobj) {
 578                         dma_fence_chain_free(dep->chain);
 579                         return -EINVAL;
 580                 }
 581                 dep->point = syncobj_deps[i].point;
 582                 p->num_post_deps++;
 583         }
 584
 585         return 0;
 586 }
 587
 588 static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p)
 589 {
 590         unsigned int ce_preempt = 0, de_preempt = 0;
 591         int i, r;
 592
 593         for (i = 0; i < p->nchunks; ++i) {
 594                 struct amdgpu_cs_chunk *chunk;
 595
 596                 chunk = &p->chunks[i];
 597
 598                 switch (chunk->chunk_id) {
 599                 case AMDGPU_CHUNK_ID_IB:
 600                         r = amdgpu_cs_p2_ib(p, chunk, &ce_preempt, &de_preempt);
 601                         if (r)
 602                                 return r;
 603                         break;
 604                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 605                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
 606                         r = amdgpu_cs_p2_dependencies(p, chunk);
 607                         if (r)
 608                                 return r;
 609                         break;
 610                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 611                         r = amdgpu_cs_p2_syncobj_in(p, chunk);
 612                         if (r)
 613                                 return r;
 614                         break;
 615                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 616                         r = amdgpu_cs_p2_syncobj_out(p, chunk);
 617                         if (r)
 618                                 return r;
 619                         break;
 620                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
 621                         r = amdgpu_cs_p2_syncobj_timeline_wait(p, chunk);
 622                         if (r)
 623                                 return r;
 624                         break;
 625                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
 626                         r = amdgpu_cs_p2_syncobj_timeline_signal(p, chunk);
 627                         if (r)
 628                                 return r;
 629                         break;
 630                 }
 631         }
 632
 633         return 0;
 634 }
 635
 636 /* Convert microseconds to bytes. */
 637 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 638 {
 639         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 640                 return 0;
 641
 642         /* Since accum_us is incremented by a million per second, just
 643          * multiply it by the number of MB/s to get the number of bytes.
 644          */
 645         return us << adev->mm_stats.log2_max_MBps;
 646 }
 647
 648 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 649 {
 650         if (!adev->mm_stats.log2_max_MBps)
 651                 return 0;
 652
 653         return bytes >> adev->mm_stats.log2_max_MBps;
 654 }
 655
 656 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 657  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 658  * which means it can go over the threshold once. If that happens, the driver
 659  * will be in debt and no other buffer migrations can be done until that debt
 660  * is repaid.
 661  *
 662  * This approach allows moving a buffer of any size (it's important to allow
 663  * that).
 664  *
 665  * The currency is simply time in microseconds and it increases as the clock
 666  * ticks. The accumulated microseconds (us) are converted to bytes and
 667  * returned.
 668  */
 669 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 670                                               u64 *max_bytes,
 671                                               u64 *max_vis_bytes)
 672 {
 673         s64 time_us, increment_us;
 674         u64 free_vram, total_vram, used_vram;
 675         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 676          * throttling.
 677          *
 678          * It means that in order to get full max MBps, at least 5 IBs per
 679          * second must be submitted and not more than 200ms apart from each
 680          * other.
 681          */
 682         const s64 us_upper_bound = 200000;
 683
 684         if (!adev->mm_stats.log2_max_MBps) {
 685                 *max_bytes = 0;
 686                 *max_vis_bytes = 0;
 687                 return;
 688         }
 689
 690         total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
 691         used_vram = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
 692         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 693
 694         spin_lock(&adev->mm_stats.lock);
 695
 696         /* Increase the amount of accumulated us. */
 697         time_us = ktime_to_us(ktime_get());
 698         increment_us = time_us - adev->mm_stats.last_update_us;
 699         adev->mm_stats.last_update_us = time_us;
 700         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 701                                       us_upper_bound);
 702
 703         /* This prevents the short period of low performance when the VRAM
 704          * usage is low and the driver is in debt or doesn't have enough
 705          * accumulated us to fill VRAM quickly.
 706          *
 707          * The situation can occur in these cases:
 708          * - a lot of VRAM is freed by userspace
 709          * - the presence of a big buffer causes a lot of evictions
 710          *   (solution: split buffers into smaller ones)
 711          *
 712          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 713          * accum_us to a positive number.
 714          */
 715         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 716                 s64 min_us;
 717
 718                 /* Be more aggressive on dGPUs. Try to fill a portion of free
 719                  * VRAM now.
 720                  */
 721                 if (!(adev->flags & AMD_IS_APU))
 722                         min_us = bytes_to_us(adev, free_vram / 4);
 723                 else
 724                         min_us = 0; /* Reset accum_us on APUs. */
 725
 726                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 727         }
 728
 729         /* This is set to 0 if the driver is in debt to disallow (optional)
 730          * buffer moves.
 731          */
 732         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 733
 734         /* Do the same for visible VRAM if half of it is free */
 735         if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
 736                 u64 total_vis_vram = adev->gmc.visible_vram_size;
 737                 u64 used_vis_vram =
 738                   amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 739
 740                 if (used_vis_vram < total_vis_vram) {
 741                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 742                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 743                                                           increment_us, us_upper_bound);
 744
 745                         if (free_vis_vram >= total_vis_vram / 2)
 746                                 adev->mm_stats.accum_us_vis =
 747                                         max(bytes_to_us(adev, free_vis_vram / 2),
 748                                             adev->mm_stats.accum_us_vis);
 749                 }
 750
 751                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 752         } else {
 753                 *max_vis_bytes = 0;
 754         }
 755
 756         spin_unlock(&adev->mm_stats.lock);
 757 }
 758
 759 /* Report how many bytes have really been moved for the last command
 760  * submission. This can result in a debt that can stop buffer migrations
 761  * temporarily.
 762  */
 763 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 764                                   u64 num_vis_bytes)
 765 {
 766         spin_lock(&adev->mm_stats.lock);
 767         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 768         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 769         spin_unlock(&adev->mm_stats.lock);
 770 }
 771
 772 static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
 773 {
 774         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 775         struct amdgpu_cs_parser *p = param;
 776         struct ttm_operation_ctx ctx = {
 777                 .interruptible = true,
 778                 .no_wait_gpu = false,
 779                 .resv = bo->tbo.base.resv
 780         };
 781         uint32_t domain;
 782         int r;
 783
 784         if (bo->tbo.pin_count)
 785                 return 0;
 786
 787         /* Don't move this buffer if we have depleted our allowance
 788          * to move it. Don't move anything if the threshold is zero.
 789          */
 790         if (p->bytes_moved < p->bytes_moved_threshold &&
 791             (!bo->tbo.base.dma_buf ||
 792             list_empty(&bo->tbo.base.dma_buf->attachments))) {
 793                 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 794                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 795                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 796                          * visible VRAM if we've depleted our allowance to do
 797                          * that.
 798                          */
 799                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 800                                 domain = bo->preferred_domains;
 801                         else
 802                                 domain = bo->allowed_domains;
 803                 } else {
 804                         domain = bo->preferred_domains;
 805                 }
 806         } else {
 807                 domain = bo->allowed_domains;
 808         }
 809
 810 retry:
 811         amdgpu_bo_placement_from_domain(bo, domain);
 812         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 813
 814         p->bytes_moved += ctx.bytes_moved;
 815         if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 816             amdgpu_bo_in_cpu_visible_vram(bo))
 817                 p->bytes_moved_vis += ctx.bytes_moved;
 818
 819         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 820                 domain = bo->allowed_domains;
 821                 goto retry;
 822         }
 823
 824         return r;
 825 }
 826
 827 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 828                             struct list_head *validated)
 829 {
 830         struct ttm_operation_ctx ctx = { true, false };
 831         struct amdgpu_bo_list_entry *lobj;
 832         int r;
 833
 834         list_for_each_entry(lobj, validated, tv.head) {
 835                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
 836                 struct mm_struct *usermm;
 837
 838                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 839                 if (usermm && usermm != current->mm)
 840                         return -EPERM;
 841
 842                 if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) &&
 843                     lobj->user_invalidated && lobj->user_pages) {
 844                         amdgpu_bo_placement_from_domain(bo,
 845                                                         AMDGPU_GEM_DOMAIN_CPU);
 846                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 847                         if (r)
 848                                 return r;
 849
 850                         amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 851                                                      lobj->user_pages);
 852                 }
 853
 854                 r = amdgpu_cs_bo_validate(p, bo);
 855                 if (r)
 856                         return r;
 857
 858                 kvfree(lobj->user_pages);
 859                 lobj->user_pages = NULL;
 860         }
 861         return 0;
 862 }
 863
 864 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 865                                 union drm_amdgpu_cs *cs)
 866 {
 867         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 868         struct amdgpu_vm *vm = &fpriv->vm;
 869         struct amdgpu_bo_list_entry *e;
 870         struct list_head duplicates;
 871         unsigned int i;
 872         int r;
 873
 874         INIT_LIST_HEAD(&p->validated);
 875
 876         /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
 877         if (cs->in.bo_list_handle) {
 878                 if (p->bo_list)
 879                         return -EINVAL;
 880
 881                 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
 882                                        &p->bo_list);
 883                 if (r)
 884                         return r;
 885         } else if (!p->bo_list) {
 886                 /* Create a empty bo_list when no handle is provided */
 887                 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
 888                                           &p->bo_list);
 889                 if (r)
 890                         return r;
 891         }
 892
 893         mutex_lock(&p->bo_list->bo_list_mutex);
 894
 895         /* One for TTM and one for the CS job */
 896         amdgpu_bo_list_for_each_entry(e, p->bo_list)
 897                 e->tv.num_shared = 2;
 898
 899         amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 900
 901         INIT_LIST_HEAD(&duplicates);
 902         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 903
 904         if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
 905                 list_add(&p->uf_entry.tv.head, &p->validated);
 906
 907         /* Get userptr backing pages. If pages are updated after registered
 908          * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
 909          * amdgpu_ttm_backend_bind() to flush and invalidate new pages
 910          */
 911         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
 912                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 913                 bool userpage_invalidated = false;
 914                 int i;
 915
 916                 e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,
 917                                         sizeof(struct page *),
 918                                         GFP_KERNEL | __GFP_ZERO);
 919                 if (!e->user_pages) {
 920                         DRM_ERROR("kvmalloc_array failure\n");
 921                         r = -ENOMEM;
 922                         goto out_free_user_pages;
 923                 }
 924
 925                 r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages, &e->range);
 926                 if (r) {
 927                         kvfree(e->user_pages);
 928                         e->user_pages = NULL;
 929                         goto out_free_user_pages;
 930                 }
 931
 932                 for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
 933                         if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
 934                                 userpage_invalidated = true;
 935                                 break;
 936                         }
 937                 }
 938                 e->user_invalidated = userpage_invalidated;
 939         }
 940
 941         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 942                                    &duplicates);
 943         if (unlikely(r != 0)) {
 944                 if (r != -ERESTARTSYS)
 945                         DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 946                 goto out_free_user_pages;
 947         }
 948
 949         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 950                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 951
 952                 e->bo_va = amdgpu_vm_bo_find(vm, bo);
 953         }
 954
 955         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 956                                           &p->bytes_moved_vis_threshold);
 957         p->bytes_moved = 0;
 958         p->bytes_moved_vis = 0;
 959
 960         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 961                                       amdgpu_cs_bo_validate, p);
 962         if (r) {
 963                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 964                 goto error_validate;
 965         }
 966
 967         r = amdgpu_cs_list_validate(p, &duplicates);
 968         if (r)
 969                 goto error_validate;
 970
 971         r = amdgpu_cs_list_validate(p, &p->validated);
 972         if (r)
 973                 goto error_validate;
 974
 975         if (p->uf_entry.tv.bo) {
 976                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo);
 977
 978                 r = amdgpu_ttm_alloc_gart(&uf->tbo);
 979                 if (r)
 980                         goto error_validate;
 981
 982                 p->gang_leader->uf_addr += amdgpu_bo_gpu_offset(uf);
 983         }
 984
 985         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 986                                      p->bytes_moved_vis);
 987
 988         for (i = 0; i < p->gang_size; ++i)
 989                 amdgpu_job_set_resources(p->jobs[i], p->bo_list->gds_obj,
 990                                          p->bo_list->gws_obj,
 991                                          p->bo_list->oa_obj);
 992         return 0;
 993
 994 error_validate:
 995         ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 996
 997 out_free_user_pages:
 998         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
 999                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1000
1001                 if (!e->user_pages)
1002                         continue;
1003                 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, e->range);
1004                 kvfree(e->user_pages);
1005                 e->user_pages = NULL;
1006                 e->range = NULL;
1007         }
1008         mutex_unlock(&p->bo_list->bo_list_mutex);
1009         return r;
1010 }
1011
1012 static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *p)
1013 {
1014         int i, j;
1015
1016         if (!trace_amdgpu_cs_enabled())
1017                 return;
1018
1019         for (i = 0; i < p->gang_size; ++i) {
1020                 struct amdgpu_job *job = p->jobs[i];
1021
1022                 for (j = 0; j < job->num_ibs; ++j)
1023                         trace_amdgpu_cs(p, job, &job->ibs[j]);
1024         }
1025 }
1026
1027 static int amdgpu_cs_patch_ibs(struct amdgpu_cs_parser *p,
1028                                struct amdgpu_job *job)
1029 {
1030         struct amdgpu_ring *ring = amdgpu_job_ring(job);
1031         unsigned int i;
1032         int r;
1033
1034         /* Only for UVD/VCE VM emulation */
1035         if (!ring->funcs->parse_cs && !ring->funcs->patch_cs_in_place)
1036                 return 0;
1037
1038         for (i = 0; i < job->num_ibs; ++i) {
1039                 struct amdgpu_ib *ib = &job->ibs[i];
1040                 struct amdgpu_bo_va_mapping *m;
1041                 struct amdgpu_bo *aobj;
1042                 uint64_t va_start;
1043                 uint8_t *kptr;
1044
1045                 va_start = ib->gpu_addr & AMDGPU_GMC_HOLE_MASK;
1046                 r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
1047                 if (r) {
1048                         DRM_ERROR("IB va_start is invalid\n");
1049                         return r;
1050                 }
1051
1052                 if ((va_start + ib->length_dw * 4) >
1053                     (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
1054                         DRM_ERROR("IB va_start+ib_bytes is invalid\n");
1055                         return -EINVAL;
1056                 }
1057
1058                 /* the IB should be reserved at this point */
1059                 r = amdgpu_bo_kmap(aobj, (void **)&kptr);
1060                 if (r) {
1061                         return r;
1062                 }
1063
1064                 kptr += va_start - (m->start * AMDGPU_GPU_PAGE_SIZE);
1065
1066                 if (ring->funcs->parse_cs) {
1067                         memcpy(ib->ptr, kptr, ib->length_dw * 4);
1068                         amdgpu_bo_kunmap(aobj);
1069
1070                         r = amdgpu_ring_parse_cs(ring, p, job, ib);
1071                         if (r)
1072                                 return r;
1073                 } else {
1074                         ib->ptr = (uint32_t *)kptr;
1075                         r = amdgpu_ring_patch_cs_in_place(ring, p, job, ib);
1076                         amdgpu_bo_kunmap(aobj);
1077                         if (r)
1078                                 return r;
1079                 }
1080         }
1081
1082         return 0;
1083 }
1084
1085 static int amdgpu_cs_patch_jobs(struct amdgpu_cs_parser *p)
1086 {
1087         unsigned int i;
1088         int r;
1089
1090         for (i = 0; i < p->gang_size; ++i) {
1091                 r = amdgpu_cs_patch_ibs(p, p->jobs[i]);
1092                 if (r)
1093                         return r;
1094         }
1095         return 0;
1096 }
1097
1098 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
1099 {
1100         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1101         struct amdgpu_job *job = p->gang_leader;
1102         struct amdgpu_device *adev = p->adev;
1103         struct amdgpu_vm *vm = &fpriv->vm;
1104         struct amdgpu_bo_list_entry *e;
1105         struct amdgpu_bo_va *bo_va;
1106         struct amdgpu_bo *bo;
1107         unsigned int i;
1108         int r;
1109
1110         r = amdgpu_vm_clear_freed(adev, vm, NULL);
1111         if (r)
1112                 return r;
1113
1114         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
1115         if (r)
1116                 return r;
1117
1118         r = amdgpu_sync_fence(&p->sync, fpriv->prt_va->last_pt_update);
1119         if (r)
1120                 return r;
1121
1122         if (fpriv->csa_va) {
1123                 bo_va = fpriv->csa_va;
1124                 BUG_ON(!bo_va);
1125                 r = amdgpu_vm_bo_update(adev, bo_va, false);
1126                 if (r)
1127                         return r;
1128
1129                 r = amdgpu_sync_fence(&p->sync, bo_va->last_pt_update);
1130                 if (r)
1131                         return r;
1132         }
1133
1134         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1135                 /* ignore duplicates */
1136                 bo = ttm_to_amdgpu_bo(e->tv.bo);
1137                 if (!bo)
1138                         continue;
1139
1140                 bo_va = e->bo_va;
1141                 if (bo_va == NULL)
1142                         continue;
1143
1144                 r = amdgpu_vm_bo_update(adev, bo_va, false);
1145                 if (r)
1146                         return r;
1147
1148                 r = amdgpu_sync_fence(&p->sync, bo_va->last_pt_update);
1149                 if (r)
1150                         return r;
1151         }
1152
1153         r = amdgpu_vm_handle_moved(adev, vm);
1154         if (r)
1155                 return r;
1156
1157         r = amdgpu_vm_update_pdes(adev, vm, false);
1158         if (r)
1159                 return r;
1160
1161         r = amdgpu_sync_fence(&p->sync, vm->last_update);
1162         if (r)
1163                 return r;
1164
1165         for (i = 0; i < p->gang_size; ++i) {
1166                 job = p->jobs[i];
1167
1168                 if (!job->vm)
1169                         continue;
1170
1171                 job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);
1172         }
1173
1174         if (amdgpu_vm_debug) {
1175                 /* Invalidate all BOs to test for userspace bugs */
1176                 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1177                         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1178
1179                         /* ignore duplicates */
1180                         if (!bo)
1181                                 continue;
1182
1183                         amdgpu_vm_bo_invalidate(adev, bo, false);
1184                 }
1185         }
1186
1187         return 0;
1188 }
1189
1190 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
1191 {
1192         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1193         struct amdgpu_bo_list_entry *e;
1194         unsigned int i;
1195         int r;
1196
1197         list_for_each_entry(e, &p->validated, tv.head) {
1198                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1199                 struct dma_resv *resv = bo->tbo.base.resv;
1200                 enum amdgpu_sync_mode sync_mode;
1201
1202                 sync_mode = amdgpu_bo_explicit_sync(bo) ?
1203                         AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
1204                 r = amdgpu_sync_resv(p->adev, &p->sync, resv, sync_mode,
1205                                      &fpriv->vm);
1206                 if (r)
1207                         return r;
1208         }
1209
1210         for (i = 0; i < p->gang_size; ++i) {
1211                 r = amdgpu_sync_push_to_job(&p->sync, p->jobs[i]);
1212                 if (r)
1213                         return r;
1214         }
1215
1216         r = amdgpu_ctx_wait_prev_fence(p->ctx, p->entities[p->gang_leader_idx]);
1217         if (r && r != -ERESTARTSYS)
1218                 DRM_ERROR("amdgpu_ctx_wait_prev_fence failed.\n");
1219         return r;
1220 }
1221
1222 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1223 {
1224         int i;
1225
1226         for (i = 0; i < p->num_post_deps; ++i) {
1227                 if (p->post_deps[i].chain && p->post_deps[i].point) {
1228                         drm_syncobj_add_point(p->post_deps[i].syncobj,
1229                                               p->post_deps[i].chain,
1230                                               p->fence, p->post_deps[i].point);
1231                         p->post_deps[i].chain = NULL;
1232                 } else {
1233                         drm_syncobj_replace_fence(p->post_deps[i].syncobj,
1234                                                   p->fence);
1235                 }
1236         }
1237 }
1238
1239 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1240                             union drm_amdgpu_cs *cs)
1241 {
1242         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1243         struct amdgpu_job *leader = p->gang_leader;
1244         struct amdgpu_bo_list_entry *e;
1245         unsigned int i;
1246         uint64_t seq;
1247         int r;
1248
1249         for (i = 0; i < p->gang_size; ++i)
1250                 drm_sched_job_arm(&p->jobs[i]->base);
1251
1252         for (i = 0; i < p->gang_size; ++i) {
1253                 struct dma_fence *fence;
1254
1255                 if (p->jobs[i] == leader)
1256                         continue;
1257
1258                 fence = &p->jobs[i]->base.s_fence->scheduled;
1259                 r = drm_sched_job_add_dependency(&leader->base, fence);
1260                 if (r)
1261                         goto error_cleanup;
1262         }
1263
1264         if (p->gang_size > 1) {
1265                 for (i = 0; i < p->gang_size; ++i)
1266                         amdgpu_job_set_gang_leader(p->jobs[i], leader);
1267         }
1268
1269         /* No memory allocation is allowed while holding the notifier lock.
1270          * The lock is held until amdgpu_cs_submit is finished and fence is
1271          * added to BOs.
1272          */
1273         mutex_lock(&p->adev->notifier_lock);
1274
1275         /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1276          * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1277          */
1278         r = 0;
1279         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1280                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1281
1282                 r |= !amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, e->range);
1283                 e->range = NULL;
1284         }
1285         if (r) {
1286                 r = -EAGAIN;
1287                 goto error_unlock;
1288         }
1289
1290         p->fence = dma_fence_get(&leader->base.s_fence->finished);
1291         list_for_each_entry(e, &p->validated, tv.head) {
1292
1293                 /* Everybody except for the gang leader uses READ */
1294                 for (i = 0; i < p->gang_size; ++i) {
1295                         if (p->jobs[i] == leader)
1296                                 continue;
1297
1298                         dma_resv_add_fence(e->tv.bo->base.resv,
1299                                            &p->jobs[i]->base.s_fence->finished,
1300                                            DMA_RESV_USAGE_READ);
1301                 }
1302
1303                 /* The gang leader is remembered as writer */
1304                 e->tv.num_shared = 0;
1305         }
1306
1307         seq = amdgpu_ctx_add_fence(p->ctx, p->entities[p->gang_leader_idx],
1308                                    p->fence);
1309         amdgpu_cs_post_dependencies(p);
1310
1311         if ((leader->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1312             !p->ctx->preamble_presented) {
1313                 leader->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1314                 p->ctx->preamble_presented = true;
1315         }
1316
1317         cs->out.handle = seq;
1318         leader->uf_sequence = seq;
1319
1320         amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
1321         for (i = 0; i < p->gang_size; ++i) {
1322                 amdgpu_job_free_resources(p->jobs[i]);
1323                 trace_amdgpu_cs_ioctl(p->jobs[i]);
1324                 drm_sched_entity_push_job(&p->jobs[i]->base);
1325                 p->jobs[i] = NULL;
1326         }
1327
1328         amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1329         ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1330
1331         mutex_unlock(&p->adev->notifier_lock);
1332         mutex_unlock(&p->bo_list->bo_list_mutex);
1333         return 0;
1334
1335 error_unlock:
1336         mutex_unlock(&p->adev->notifier_lock);
1337
1338 error_cleanup:
1339         for (i = 0; i < p->gang_size; ++i)
1340                 drm_sched_job_cleanup(&p->jobs[i]->base);
1341         return r;
1342 }
1343
1344 /* Cleanup the parser structure */
1345 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser)
1346 {
1347         unsigned i;
1348
1349         for (i = 0; i < parser->num_post_deps; i++) {
1350                 drm_syncobj_put(parser->post_deps[i].syncobj);
1351                 kfree(parser->post_deps[i].chain);
1352         }
1353         kfree(parser->post_deps);
1354
1355         dma_fence_put(parser->fence);
1356
1357         if (parser->ctx)
1358                 amdgpu_ctx_put(parser->ctx);
1359         if (parser->bo_list)
1360                 amdgpu_bo_list_put(parser->bo_list);
1361
1362         for (i = 0; i < parser->nchunks; i++)
1363                 kvfree(parser->chunks[i].kdata);
1364         kvfree(parser->chunks);
1365         for (i = 0; i < parser->gang_size; ++i) {
1366                 if (parser->jobs[i])
1367                         amdgpu_job_free(parser->jobs[i]);
1368         }
1369         if (parser->uf_entry.tv.bo) {
1370                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo);
1371
1372                 amdgpu_bo_unref(&uf);
1373         }
1374 }
1375
1376 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1377 {
1378         struct amdgpu_device *adev = drm_to_adev(dev);
1379         struct amdgpu_cs_parser parser;
1380         int r;
1381
1382         if (amdgpu_ras_intr_triggered())
1383                 return -EHWPOISON;
1384
1385         if (!adev->accel_working)
1386                 return -EBUSY;
1387
1388         r = amdgpu_cs_parser_init(&parser, adev, filp, data);
1389         if (r) {
1390                 if (printk_ratelimit())
1391                         DRM_ERROR("Failed to initialize parser %d!\n", r);
1392                 return r;
1393         }
1394
1395         r = amdgpu_cs_pass1(&parser, data);
1396         if (r)
1397                 goto error_fini;
1398
1399         r = amdgpu_cs_pass2(&parser);
1400         if (r)
1401                 goto error_fini;
1402
1403         r = amdgpu_cs_parser_bos(&parser, data);
1404         if (r) {
1405                 if (r == -ENOMEM)
1406                         DRM_ERROR("Not enough memory for command submission!\n");
1407                 else if (r != -ERESTARTSYS && r != -EAGAIN)
1408                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1409                 goto error_fini;
1410         }
1411
1412         r = amdgpu_cs_patch_jobs(&parser);
1413         if (r)
1414                 goto error_backoff;
1415
1416         r = amdgpu_cs_vm_handling(&parser);
1417         if (r)
1418                 goto error_backoff;
1419
1420         r = amdgpu_cs_sync_rings(&parser);
1421         if (r)
1422                 goto error_backoff;
1423
1424         trace_amdgpu_cs_ibs(&parser);
1425
1426         r = amdgpu_cs_submit(&parser, data);
1427         if (r)
1428                 goto error_backoff;
1429
1430         amdgpu_cs_parser_fini(&parser);
1431         return 0;
1432
1433 error_backoff:
1434         ttm_eu_backoff_reservation(&parser.ticket, &parser.validated);
1435         mutex_unlock(&parser.bo_list->bo_list_mutex);
1436
1437 error_fini:
1438         amdgpu_cs_parser_fini(&parser);
1439         return r;
1440 }
1441
1442 /**
1443  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1444  *
1445  * @dev: drm device
1446  * @data: data from userspace
1447  * @filp: file private
1448  *
1449  * Wait for the command submission identified by handle to finish.
1450  */
1451 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1452                          struct drm_file *filp)
1453 {
1454         union drm_amdgpu_wait_cs *wait = data;
1455         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1456         struct drm_sched_entity *entity;
1457         struct amdgpu_ctx *ctx;
1458         struct dma_fence *fence;
1459         long r;
1460
1461         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1462         if (ctx == NULL)
1463                 return -EINVAL;
1464
1465         r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1466                                   wait->in.ring, &entity);
1467         if (r) {
1468                 amdgpu_ctx_put(ctx);
1469                 return r;
1470         }
1471
1472         fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1473         if (IS_ERR(fence))
1474                 r = PTR_ERR(fence);
1475         else if (fence) {
1476                 r = dma_fence_wait_timeout(fence, true, timeout);
1477                 if (r > 0 && fence->error)
1478                         r = fence->error;
1479                 dma_fence_put(fence);
1480         } else
1481                 r = 1;
1482
1483         amdgpu_ctx_put(ctx);
1484         if (r < 0)
1485                 return r;
1486
1487         memset(wait, 0, sizeof(*wait));
1488         wait->out.status = (r == 0);
1489
1490         return 0;
1491 }
1492
1493 /**
1494  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1495  *
1496  * @adev: amdgpu device
1497  * @filp: file private
1498  * @user: drm_amdgpu_fence copied from user space
1499  */
1500 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1501                                              struct drm_file *filp,
1502                                              struct drm_amdgpu_fence *user)
1503 {
1504         struct drm_sched_entity *entity;
1505         struct amdgpu_ctx *ctx;
1506         struct dma_fence *fence;
1507         int r;
1508
1509         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1510         if (ctx == NULL)
1511                 return ERR_PTR(-EINVAL);
1512
1513         r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1514                                   user->ring, &entity);
1515         if (r) {
1516                 amdgpu_ctx_put(ctx);
1517                 return ERR_PTR(r);
1518         }
1519
1520         fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1521         amdgpu_ctx_put(ctx);
1522
1523         return fence;
1524 }
1525
1526 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1527                                     struct drm_file *filp)
1528 {
1529         struct amdgpu_device *adev = drm_to_adev(dev);
1530         union drm_amdgpu_fence_to_handle *info = data;
1531         struct dma_fence *fence;
1532         struct drm_syncobj *syncobj;
1533         struct sync_file *sync_file;
1534         int fd, r;
1535
1536         fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1537         if (IS_ERR(fence))
1538                 return PTR_ERR(fence);
1539
1540         if (!fence)
1541                 fence = dma_fence_get_stub();
1542
1543         switch (info->in.what) {
1544         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1545                 r = drm_syncobj_create(&syncobj, 0, fence);
1546                 dma_fence_put(fence);
1547                 if (r)
1548                         return r;
1549                 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1550                 drm_syncobj_put(syncobj);
1551                 return r;
1552
1553         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1554                 r = drm_syncobj_create(&syncobj, 0, fence);
1555                 dma_fence_put(fence);
1556                 if (r)
1557                         return r;
1558                 r = drm_syncobj_get_fd(syncobj, (int *)&info->out.handle);
1559                 drm_syncobj_put(syncobj);
1560                 return r;
1561
1562         case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1563                 fd = get_unused_fd_flags(O_CLOEXEC);
1564                 if (fd < 0) {
1565                         dma_fence_put(fence);
1566                         return fd;
1567                 }
1568
1569                 sync_file = sync_file_create(fence);
1570                 dma_fence_put(fence);
1571                 if (!sync_file) {
1572                         put_unused_fd(fd);
1573                         return -ENOMEM;
1574                 }
1575
1576                 fd_install(fd, sync_file->file);
1577                 info->out.handle = fd;
1578                 return 0;
1579
1580         default:
1581                 dma_fence_put(fence);
1582                 return -EINVAL;
1583         }
1584 }
1585
1586 /**
1587  * amdgpu_cs_wait_all_fences - wait on all fences to signal
1588  *
1589  * @adev: amdgpu device
1590  * @filp: file private
1591  * @wait: wait parameters
1592  * @fences: array of drm_amdgpu_fence
1593  */
1594 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1595                                      struct drm_file *filp,
1596                                      union drm_amdgpu_wait_fences *wait,
1597                                      struct drm_amdgpu_fence *fences)
1598 {
1599         uint32_t fence_count = wait->in.fence_count;
1600         unsigned int i;
1601         long r = 1;
1602
1603         for (i = 0; i < fence_count; i++) {
1604                 struct dma_fence *fence;
1605                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1606
1607                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1608                 if (IS_ERR(fence))
1609                         return PTR_ERR(fence);
1610                 else if (!fence)
1611                         continue;
1612
1613                 r = dma_fence_wait_timeout(fence, true, timeout);
1614                 dma_fence_put(fence);
1615                 if (r < 0)
1616                         return r;
1617
1618                 if (r == 0)
1619                         break;
1620
1621                 if (fence->error)
1622                         return fence->error;
1623         }
1624
1625         memset(wait, 0, sizeof(*wait));
1626         wait->out.status = (r > 0);
1627
1628         return 0;
1629 }
1630
1631 /**
1632  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1633  *
1634  * @adev: amdgpu device
1635  * @filp: file private
1636  * @wait: wait parameters
1637  * @fences: array of drm_amdgpu_fence
1638  */
1639 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1640                                     struct drm_file *filp,
1641                                     union drm_amdgpu_wait_fences *wait,
1642                                     struct drm_amdgpu_fence *fences)
1643 {
1644         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1645         uint32_t fence_count = wait->in.fence_count;
1646         uint32_t first = ~0;
1647         struct dma_fence **array;
1648         unsigned int i;
1649         long r;
1650
1651         /* Prepare the fence array */
1652         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1653
1654         if (array == NULL)
1655                 return -ENOMEM;
1656
1657         for (i = 0; i < fence_count; i++) {
1658                 struct dma_fence *fence;
1659
1660                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1661                 if (IS_ERR(fence)) {
1662                         r = PTR_ERR(fence);
1663                         goto err_free_fence_array;
1664                 } else if (fence) {
1665                         array[i] = fence;
1666                 } else { /* NULL, the fence has been already signaled */
1667                         r = 1;
1668                         first = i;
1669                         goto out;
1670                 }
1671         }
1672
1673         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1674                                        &first);
1675         if (r < 0)
1676                 goto err_free_fence_array;
1677
1678 out:
1679         memset(wait, 0, sizeof(*wait));
1680         wait->out.status = (r > 0);
1681         wait->out.first_signaled = first;
1682
1683         if (first < fence_count && array[first])
1684                 r = array[first]->error;
1685         else
1686                 r = 0;
1687
1688 err_free_fence_array:
1689         for (i = 0; i < fence_count; i++)
1690                 dma_fence_put(array[i]);
1691         kfree(array);
1692
1693         return r;
1694 }
1695
1696 /**
1697  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1698  *
1699  * @dev: drm device
1700  * @data: data from userspace
1701  * @filp: file private
1702  */
1703 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1704                                 struct drm_file *filp)
1705 {
1706         struct amdgpu_device *adev = drm_to_adev(dev);
1707         union drm_amdgpu_wait_fences *wait = data;
1708         uint32_t fence_count = wait->in.fence_count;
1709         struct drm_amdgpu_fence *fences_user;
1710         struct drm_amdgpu_fence *fences;
1711         int r;
1712
1713         /* Get the fences from userspace */
1714         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1715                         GFP_KERNEL);
1716         if (fences == NULL)
1717                 return -ENOMEM;
1718
1719         fences_user = u64_to_user_ptr(wait->in.fences);
1720         if (copy_from_user(fences, fences_user,
1721                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1722                 r = -EFAULT;
1723                 goto err_free_fences;
1724         }
1725
1726         if (wait->in.wait_all)
1727                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1728         else
1729                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1730
1731 err_free_fences:
1732         kfree(fences);
1733
1734         return r;
1735 }
1736
1737 /**
1738  * amdgpu_cs_find_mapping - find bo_va for VM address
1739  *
1740  * @parser: command submission parser context
1741  * @addr: VM address
1742  * @bo: resulting BO of the mapping found
1743  * @map: Placeholder to return found BO mapping
1744  *
1745  * Search the buffer objects in the command submission context for a certain
1746  * virtual memory address. Returns allocation structure when found, NULL
1747  * otherwise.
1748  */
1749 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1750                            uint64_t addr, struct amdgpu_bo **bo,
1751                            struct amdgpu_bo_va_mapping **map)
1752 {
1753         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1754         struct ttm_operation_ctx ctx = { false, false };
1755         struct amdgpu_vm *vm = &fpriv->vm;
1756         struct amdgpu_bo_va_mapping *mapping;
1757         int r;
1758
1759         addr /= AMDGPU_GPU_PAGE_SIZE;
1760
1761         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1762         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1763                 return -EINVAL;
1764
1765         *bo = mapping->bo_va->base.bo;
1766         *map = mapping;
1767
1768         /* Double check that the BO is reserved by this CS */
1769         if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->ticket)
1770                 return -EINVAL;
1771
1772         if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1773                 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1774                 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1775                 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1776                 if (r)
1777                         return r;
1778         }
1779
1780         return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1781 }